MAX5188_01 [MAXIM]
Dual, 8-Bit, 40MHz, Current/Voltage,Alternate-Phase Output DACs; 双路，8位， 40MHz的，电流/电压，交替相输出DAC
| 型号： | MAX5188_01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual, 8-Bit, 40MHz, Current/Voltage,Alternate-Phase Output DACs |
| 文件： | 总15页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1580; Rev 2; 12/01
Dual, 8-Bit, 40MHz, Current/Voltage,
Alternate-Phase Output DACs
General Description
Features
The MAX5188 is a dual 8-bit, alternate-phase-update,
current-output digital-to-analog converter (DAC)
designed for superior performance in systems requiring
analog signal reconstruction with low distortion and
low-power operation. The MAX5191 provides equal
specifications, with on-chip output resistors for voltage-
output operation. Both devices are designed for 10pVs
glitch operation to reduce distortion and minimize
unwanted spurious signal components at the output. An
on-board +1.2V bandgap circuit provides a well-regu-
lated, low-noise reference that may be disabled for
external reference operation.
o +2.7V to +3.3V Single-Supply Operation
o Wide Spurious-Free Dynamic Range: 70dB
at f = 2.2MHz
OUT
o Fully Differential Outputs for Each DAC
0.ꢀ5 FSR ꢁain Mismatch Betꢂeen DAC Outputs
o
o Loꢂ-Current Standby or Full Shutdoꢂn Modes
o Internal +1.2V Loꢂ-Noise Bandgap Reference
o Small 28-Pin QSOP Package
The MAX5188/MAX5191 are designed to provide a high
level of signal integrity for the least amount of power
dissipation. Both DACs operate from a +2.7V to +3.3V
single supply. Additionally, these DACs have three
modes of operation: normal, low-power standby, and
full shutdown. A full shutdown provides the lowest pos-
sible power dissipation with a maximum shutdown cur-
rent of 1µA. A fast wake-up time (0.5µs) from standby
mode to full DAC operation allows for power conserva-
tion by activating the DACs only when required.
Ordering Information
PART
TEMP. RANꢁE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAꢁE
28 QSOP
MAXꢀ188BEEI
MAXꢀ191BEEI
28 QSOP
The MAX5188/MAX5191 are available in a 28-pin QSOP
package and are specified for the extended (-40°C to
+85°C) temperature range. For pin-compatible 10-bit
versions, refer to the MAX5182/MAX5185 data sheet.
Pin Configuration
TOP VIEW
Applications
CREF1
OUT1P
OUT1N
AGND
1
2
3
4
5
6
7
8
9
28 CREF2
27 OUT2P
26 OUT2N
25 REFO
24 REFR
Signal Reconstruction Applications
Digital Signal Processing
Arbitrary Waveform Generators
Imaging Applications
AV
DD
MAX5188
MAX5191
DACEN
PD
23 DGND
22 DV
21 D7
20 D6
19 D5
18 D4
17 D3
16 D2
15 D1
DD
CS
CLK
N.C. 10
REN 11
DGND 12
DGND 13
D0 14
QSOP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual, 8-Bit, 40MHz, Current/Voltage,
Alternate-Phase Output DACs
ABSOLUTE MAXIMUM RATINꢁS
AV , DV
to AGꢁD, DGꢁD .................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
DD
DD
Digital Inputs to DGꢁD.............................................-0.3V to +6V
OUT1P, OUT1ꢁ, OUT2P, OUT2ꢁ, CREF1,
28-Pin QSOP (derate 9.00mW/°C above +70°C)..........725mW
Operating Temperature Ranges
MAX5188/MAX5191BEEI..................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
CREF2 to AGꢁD....................................................-0.3V to +6V
V
to AGꢁD ..........................................................-0.3V to +6V
REF
AV
to DV ..................................................................... 3.3V
DD
DD
AGꢁD to DGꢁD.....................................................-0.3V to +0.3V
Maximum Current into Any Pin............................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= DV
= +3V 10ꢀ, AGꢁD = DGꢁD = 0, f
= 40MHz, I = 1mA, 400Ω differential output, C = 5pF, T = T
to T
,
MAX
DD
DD
CLK
FS
L
A
MIꢁ
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ꢁ
8
-1
Bits
LSB
LSB
LSB
LSB
LSB
Integral ꢁonlinearity
Differential ꢁonlinearity
IꢁL
DꢁL
0.25
0.25
+1
+1
Guaranteed monotonic
-1
MAX5188
MAX5191
(ꢁote 1)
-1
+1
Zero-Scale Error
-4
+4
Full-Scale Error
-20
4
+20
DYNAMIC PERFORMANCE
Output Settling Time
Glitch Impulse
To 0.5LSB error band
25
10
72
70
-70
-68
52
52
-60
50
10
ns
pVs
f
f
f
f
f
f
= 500kHz
OUT
OUT
OUT
OUT
OUT
OUT
Spurious-Free Dynamic Range
to ꢁyquist
SFDR
THD
SꢁR
f
f
= 40MHz
= 40MHz
dBc
dB
CLK
= 2.2MHz, T = +25°C
A
57
46
= 500kHz
Total Harmonic Distortion
to ꢁyquist
CLK
= 2.2MHz, T = +25°C
A
-63
= 500kHz
Signal-to-ꢁoise Ratio
to ꢁyquist
f
f
= 40MHz
= 2.2MHz
dB
CLK
= 2.2MHz, T = +25°C
A
DAC-to-DAC Output Isolation
Clock and Data Feedthrough
Output ꢁoise
dB
nVs
OUT
All 0s to all 1s
pA/√Hz
Gain Mismatch Between DAC
Outputs
f
= 2.2MHz, T = +25°C
LSB
0.5
1
OUT
A
ANALOꢁ OUTPUT
Full-Scale Output Voltage
Voltage Compliance of Output
Output Leakage Current
Full-Scale Output Current
V
400
mV
V
FS
-0.3
-1
0.8
1
DACEꢁ = 0, MAX5188 only
MAX5188 only
µA
mA
I
FS
0.5
1
1.5
DAC External Output Resistor
Load
MAX5188 only
400
Ω
2
________________________________________________________________________________________
Dual, 8-Bit, 40MHz, Current/Voltage,
Alternate-Phase Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +3V 10ꢀ, AGꢁD = DGꢁD = 0, f
= 40MHz, I = 1mA, 400Ω differential output, C = 5pF, T = T
to T
,
MAX
DD
DD
CLK
FS
L
A
MIꢁ
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
REFERENCE
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage Range
V
1.12
1.2
50
1.28
V
REF
Output Voltage Temperature
Drift
TCV
ppm/°C
REF
Reference Output Drive
Capability
I
10
µA
REFOUT
Reference Supply Rejection
0.5
8
mV/V
Current Gain (I / I
)
mA/mA
FS REF
POWER REQUIREMENTS
Analog Power-Supply Voltage
Analog Supply Current
Digital Power-Supply Voltage
Digital Supply Current
AV
2.7
2.7
3.3
5
V
DD
I
PD = 0, DACEꢁ = 1, digital inputs at 0 or DV
2.7
mA
V
AVDD
DD
DV
3.3
5
DD
I
PD = 0, DACEꢁ = 1, digital inputs at 0 or DV
PD = 0, DACEꢁ = 0, digital inputs at 0 or DV
4.2
1
mA
mA
DVDD
DD
Standby Current
I
1.5
STAꢁDBY
DD
PD = 1, DACEꢁ = X, digital inputs at 0 or DV
(X = don’t care)
DD
Shutdown Current
I
0.5
1
µA
SHDꢁ
LOꢁIC INPUTS AND OUTPUTS
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Current
V
2
V
V
IH
V
0.8
1
IL
I
Iꢁ
V
Iꢁ
= 0 or DV
DD
µA
pF
Digital Input Capacitance
TIMINꢁ CHARACTERISTICS
C
Iꢁ
10
DAC1 DATA to CLK Rise Setup
Time
t
10
10
0
ns
ns
ns
ns
DS1
DS2
DH1
DH2
DAC2 DATA to CLK Fall Setup
Time
t
DAC1 CLK Rise to DATA Hold
Time
t
t
DAC2 CLK Fall to DATA Hold
Time
0
5
5
ns
ns
µs
µs
ns
ns
ns
CS Fall to CLK Rise Time
CS Fall to CLK Fall Time
DACEꢁ Rise Time to V
0.5
50
OUT
PD Fall Time to V
Clock Period
OUT
t
25
10
10
CLK
Clock High Time
Clock Low Time
t
CH
t
CL
Note 1: Excludes reference and reference resistor (MAX5191) tolerance.
_______________________________________________________________________________________
3
Dual, 8-Bit, 40MHz, Current/Voltage,
Alternate-Phase Output DACs
Typical Operating Characteristics
(AV
= DV
= +3V, AGꢁD = DGꢁD = 0, 400Ω differential output, I = 1mA, C = 5pF, T = +25°C, unless otherwise noted.)
DD FS L
A
DD
INTEGRAL NONLINEARITY
vs. INPUT CODE
DIFFERENTIAL NONLINEARITY
vs. INPUT CODE
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
0.150
0.125
0.100
0.075
0.050
0.025
0.100
0.075
0.050
0.025
0
3.00
2.75
2.50
2.25
2.00
MAX5191
MAX5188
-0.025
-0.050
-0.075
0
-0.025
-0.050
0
32 64 96 128 160 192 224 256
INPUT CODE
0
32 64 96 128 160 192 224 256
INPUT CODE
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
10
3.00
2.75
2.50
4.00
3.75
3.50
MAX5188
MAX5191
8
6
MAX5191
MAX5188
MAX5188
MAX5191
4
2
2.25
2.00
3.25
3.00
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-15
10
35
60
85
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
STANDBY CURRENT
vs. SUPPLY VOLTAGE
STANDBY CURRENT
vs. TEMPERATURE
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
3.8
3.7
3.6
3.5
3.4
620
610
600
590
580
570
560
600
590
580
570
560
550
MAX5191
MAX5191
MAX5188
MAX5188
MAX5188
MAX5191
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-15
10
35
60
85
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
4
_______________________________________________________________________________________
Dual, 8-Bit, 40MHz, Current/Voltage,
Alternate-Phase Output DACs
Typical Operating Characteristics (continued)
(AV
= DV
= +3V, AGꢁD = DGꢁD = 0, 400Ω differential output, I = 1mA, C = 5pF, T = +25°C, unless otherwise noted.)
DD FS L
A
DD
OUTPUT CURRENT
vs. REFERENCE CURRENT
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
4
3
2
1.28
1.27
1.26
1.25
1.24
1.23
1.28
1.27
1.26
1.25
1.24
1.23
MAX5188
MAX5191
MAX5188
MAX5191
1
0
0
100
200
300
400
500
-40
-15
10
35
60
85
2.5
3.0
3.5
4.0
4.5
5.0
5.5
REFERENCE CURRENT (µA)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
DYNAMIC RESPONSE RISE TIME
DYNAMIC RESPONSE FALL TIME
OUT_P
150mV/div
OUT_P
150mV/div
OUT_N
150mV/div
OUT_N
150mV/div
50ns/div
50ns/div
FFT PLOT, DAC2
FFT PLOT, DAC1
SETTLING TIME
0
0
-10
f
f
= 40MHz
= 2.2MHz
f
f
= 40MHz
-10
CLK
OUT
CLK
OUT
= 2.2MHz
-20
-20
-30
-30
-40
OUT_N
-40
100mV/div
-50
-50
-60
-60
-70
-70
-80
-80
OUT_P
100mV/div
-90
-90
-100
-110
-120
-100
-110
-120
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
12.5ns/div
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
_______________________________________________________________________________________
ꢀ
Dual, 8-Bit, 40MHz, Current/Voltage,
Alternate-Phase Output DACs
Typical Operating Characteristics (continued)
(AV
= DV
= +3V, AGꢁD = DGꢁD = 0, 400Ω differential output, I = 1mA, C = 5pF, T = +25°C, unless otherwise noted.)
DD
DD
FS
L
A
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT
FREQUENCY AND CLOCK FREQUENCY, DAC1
100
90
80
70
60
50
40
78
f
= 40MHz
CLK
76
74
72
70
68
66
f
= 60MHz
CLK
f
= 20MHz
= 10MHz
CLK
DAC2
DAC1
f
= 50MHz
CLK
f
CLK
f
= 30MHz
CLK
10 15 20 25 30 35 40 45 50 55 60
CLOCK FREQUENCY (MHz)
500 700 900 1100 1300 1500 1700 1900 2100 2300
OUTPUT FREQUENCY (kHz)
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT
FREQUENCY AND CLOCK FREQUENCY, DAC2
78
SIGNAL-TO-NOISE PLUS DISTORTION
vs. OUTPUT FREQUENCY
62.5
62.0
61.5
61.0
60.5
60.0
f
= 50MHz
f
= 20MHz
f
= 40MHz
CLK
CLK
CLK
76
74
72
70
68
66
DAC2
f
= 10MHz
DAC1
CLK
f
= 60MHz
CLK
f
= 30MHz
CLK
500 700 900 1100 1300 1500 1700 1900 2100 2300
OUTPUT FREQUENCY (kHz)
0
500
1000
1500
2000
2500
OUPUT FREQUENCY (kHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. FULL-SCALE OUTPUT CURRENT
MULTITONE SPURIOUS-FREE DYNAMIC
RANGE vs. OUTPUT FREQUENCY
74
72
70
68
0
-10
-20
-30
-40
-50
66
64
-60
-70
62
60
-80
-120
0.50
0.75
1.00
1.25
1.50
0
2
4
6
8
10 12 14 16 18 20
FULL-SCALE OUTPUT CURRENT (mA)
OUTPUT FREQUENCY (MHz)
6
_______________________________________________________________________________________
Dual, 8-Bit, 40MHz, Current/Voltage,
Alternate-Phase Output DACs
Pin Description
PIN
1
NAME
CREF1
OUT1P
OUT1ꢁ
AGꢁD
FUNCTION
Reference Bias Bypass, DAC1
2
Positive Analog Output, DAC1. Current output for the MAX5188; voltage output for the MAX5191.
ꢁegative Analog Output, DAC1. Current output for the MAX5188; voltage output for the MAX5191.
Analog Ground
3
4
5
AV
Analog Positive Supply, +2.7V to +3.3V
DD
DAC Enable, Digital Input
0: Enter DAC standby mode with PD = DGꢁD
1: Power-up DAC with PD = DGꢁD
6
7
DACEꢁ
PD
X: Enter shutdown mode with PD = DV (X = don’t care)
DD
Power-Down Select
0: Enter DAC standby mode (DACEꢁ = DGꢁD) or power-up DAC (DACEꢁ = DV
1: Enter shutdown mode
)
DD
8
9
Active-Low Chip Select
CS
CLK
ꢁ.C.
REN
Clock Input
10
11
ꢁot Connected. Do not connect to this pin.
Active-Low Reference Enable. Connect to DGꢁD to activate on-chip +1.2V reference.
12, 13, 23 DGꢁD
Digital Ground
14
15–20
21
D0
D1–D6
D7
Data Bit D0 (LSB)
Data Bits D1–D6
Data Bit D7 (MSB)
22
DV
Digital Supply, +2.7V to +3.3V
DD
24
REFR
REFO
Reference Input
25
Reference Output
26
OUT2ꢁ
OUT2P
CREF2
ꢁegative Analog Output, DAC2. Current output for the MAX5188; voltage output for the MAX5191.
Positive Analog Output, DAC2. Current output for the MAX5188; voltage output for the MAX5191.
Reference Bias Bypass, DAC2
27
28
_______________________________________________________________________________________
7
Dual, 8-Bit, 40MHz, Current/Voltage,
Alternate-Phase Output DACs
REN
1.2V REF
AV
AGND
CS
DACEN
PD
DD
REFO
REFR
CREF1
CREF2
CURRENT-
SOURCE ARRAY
OUT1P
OUT1N
OUT2P
OUT2N
9.6k*
DAC 1 SWITCHES
DAC 2 SWITCHES
OUTPUT
LATCHES
OUTPUT
LATCHES
MSB DECODE
MSB DECODE
MAX5188
MAX5191
CLK
INPUT
LATCHES
INPUT
LATCHES
DV
DGND
DD
*INTERNAL 400Ω AND 9.6kΩ RESISTORS FOR MAX5191 ONLY.
D7–D0
Figure 1. Functional Diagram
Due to its limited 10µA output drive capability, the
REFO pin must be buffered with an external amplifier if
heavier loading is required.
Detailed Description
The MAX5188/MAX5191 are dual 8-bit digital-to-analog
converters (DACs) capable of operating with clock
speeds up to 40MHz. Each of these dual converters
consists of separate input and DAC registers, followed
by a current-source array capable of generating up to
1.5mA full-scale output current (Figure 1). An integrat-
ed +1.2V voltage reference and control amplifier deter-
mine the data converters’ full-scale output currents/
voltages. Careful reference design ensures close gain
matching and excellent drift characteristics. The
MAX5191’s voltage output operation features matched
400Ω on-chip resistors that convert the current from the
current array into a voltage.
The MAX5188/MAX5191 also employ a control amplifi-
er, designed to simultaneously regulate the full-scale
output current I for both MAX5188/MAX5191 outputs.
FS
The output current is calculated as follows:
I
FS
= 8 ✕ I
REF
where I
is the reference output current (I
SET FS
=
REF
REF
/ R
V
) and I is the full-scale output current.
REFO
R
is the reference resistor that determines the
SET
amplifier’s output current (Figure 2) on the MAX5188.
This current is mirrored into the current-source array,
where it is equally distributed between matched current
segments and summed to valid output current readings
for the DACs.
Internal Reference
and Control Amplifier
The MAX5188/MAX5191 provide an integrated
50ppm/°C, +1.2V, low-noise bandgap reference that
can be disabled and overridden by an external refer-
ence voltage. REFO serves either as an input for an
external reference or as an output for the integrated ref-
erence. If REN is connected to DGꢁD, the internal ref-
erence is selected and REFO provides a +1.2V output.
Inside the MAX5191, each output current (DAC1 and
DAC2) is converted to an output voltage (V
, V
)
OUT1 OUT2
with two internal, ground-referenced, 400Ω load resis-
tors. Using the internal +1.2V reference voltage, the inte-
grated reference output current resistor of the MAX5191
(R
SET
= 9.6kΩ) sets I to 125µA and I to 1mA.
REF FS
8
_______________________________________________________________________________________
Dual, 8-Bit, 40MHz, Current/Voltage,
Alternate-Phase Output DACs
OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS
DGND
REN
+1.2V
MAX4040
BANDGAP
REFERENCE
REFO
REFR
I
FS
C
*
CURRENT-
SOURCE ARRAY
COMP
I
REF
AGND
V
R
REF
SET
R
I
=
SET
REF
R
**
SET
9.6k
MAX5188
MAX5191
AGND
*COMPENSATION CAPACITOR (C
= 100nF)
**9.6kΩ REFERENCE CURRENT SET RESISTOR
COMP
INTERNAL TO MAX5191 ONLY. USE EXTERNAL
R
FOR MAX5188.
SET
Figure 2. Setting I with the Internal +1.2V Reference and Control Amplifier
FS
must be pulled high with PD held at DGꢁD. The
MAX5188/MAX5191 typically require 50µs to wake up
and allow both the outputs and the reference to settle.
External Reference
To disable the MAX5188/MAX5191’s internal reference,
connect REN to DV . A temperature-stable external
DD
reference may now be applied to drive the REFO pin
(Figure 3) to set the full-scale output. Choose a refer-
ence that can supply at least 150µA to drive the bias
circuit that generates the cascode current for the cur-
rent array. For improved accuracy and drift perfor-
mance, choose a fixed output voltage reference such
as the +1.2V, 25ppm/°C MAX6520 bandgap reference.
Shutdown Mode
For lowest power consumption, the MAX5188/MAX5191
provide a power-down mode in which the reference,
control amplifier, and current array are inactive and the
DAC’s supply current is reduced to 1µA. To enter this
mode, connect PD to DV . To return to active mode,
DD
connect PD to DGꢁD and DACEꢁ to DV . About 50µs
DD
are required for the devices to leave shutdown mode
and settle their outputs to the values prior to shutdown.
Table 1 lists the power-down mode selection.
Standby Mode
To enter the lower-power standby mode, connect digi-
tal inputs PD and DACEꢁ to DGꢁD. In standby, both
the reference and the control amplifier are active with
the current array inactive. To exit this condition, DACEꢁ
Table 1. Poꢂer-Doꢂn Mode Selection
PD
DACEN
(DAC ENABLE)
POWER-DOWN
OUTPUT STATE
(POWER-DOWN SELECT)
MODE
MAX5188
MAX5191
High-Z
AGꢁD
0
0
1
X
Standby
Wake-Up
Shutdown
0
1
Last state prior to standby mode
MAX5188
High-Z
MAX5191 AGꢁD
X = Don’t care
_______________________________________________________________________________________
9
Dual, 8-Bit, 40MHz, Current/Voltage,
Alternate-Phase Output DACs
DV
DD
10µF
0.1µF
DGND
REN
+1.2V
AV
DD
BANDGAP
REFERENCE
EXTERNAL
+1.2V
REFERENCE
REFO
REFR
I
FS
CURRENT-
SOURCE ARRAY
MAX6520
I
REF
AGND
9.6k*
R
SET
MAX5188
MAX5191
AGND
*9.6kΩ REFERENCE CURRENT SET RESISTOR
INTERNAL TO MAX5191 ONLY. USE EXTERNAL
R
FOR MAX5188.
SET
Figure 3. MAX5188/MAX5191 Using an External Reference
t
t
t
CH
CLK
CL
CLK
N
N - 1
N + 1
N + 1
N - 1
N
D0–D7
DAC1
DAC2
DAC1
DAC2
DAC1
DAC2
t
t
t
t
DH2
DS1
DS2
DH1
OUT1
N - 2
N - 1
N
OUT2
N - 2
N - 1
N
Figure 4. Timing Diagram
10 ______________________________________________________________________________________
Dual, 8-Bit, 40MHz, Current/Voltage,
Alternate-Phase Output DACs
ed 400Ω resistors that restore the array currents into
proportional, differential voltages of 400mV. These dif-
ferential output voltages can then be used to drive a
balun transformer or a low-distortion, high-speed oper-
ational amplifier to convert the differential voltage into a
single-ended voltage.
Timing Information
Both internal DAC cells write to their outputs in alternate
phase (Figure 4). The input latch of the first DAC
(DAC1) is loaded after the clock signal transitions high.
When the clock signal transitions low, the input latch of
the second DAC (DAC2) is loaded. The contents of the
first input latch are shifted into the DAC1 register on the
rising edge of the clock; the contents of the second
input latch are shifted into the input register of DAC2 on
the falling edge of the clock. Both outputs are updated
on alternate phases of the clock.
Applications Information
Static and Dynamic
Performance Definitions
Integral Nonlinearity
Integral nonlinearity (IꢁL) (Figure 5a) is the deviation of
the values on an actual transfer function from either a
best-straight-line fit (closest approximation to the actual
transfer curve) or a line drawn between the endpoints
Outputs
The MAX5188 outputs are designed to supply 1mA full-
scale output currents into 400Ω loads in parallel with a
capacitive load of 5pF. The MAX5191 features integrat-
7
6
6
1 LSB
5
4
5
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
4
AT STEP
3
2
3
2
1
0
011 (1/2 LSB )
1 LSB
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
AT STEP
1
0
001 (1/4 LSB )
000 001 010 011 100 101 110 111
DIGITAL INPUT CODE
000
001
010
011
100
101
DIGITAL INPUT CODE
Figure 5b. Differential Nonlinearity
Figure 5a. Integral Nonlinearity
IDEAL FULL-SCALE OUTPUT
7
6
5
ACTUAL
3
2
1
0
GAIN ERROR
(-1 1/4 LSB)
DIAGRAM
IDEAL DIAGRAM
IDEAL DIAGRAM
ACTUAL
FULL-SCALE
OUTPUT
ACTUAL
OFFSET
POINT
OFFSET ERROR
(+1 1/4 LSB)
4
0
IDEAL OFFSET
POINT
000 100
101
110
111
000
001
010
011
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 5d. Gain Error
Figure 5c. Offset Error
______________________________________________________________________________________ 11
Dual, 8-Bit, 40MHz, Current/Voltage,
Alternate-Phase Output DACs
of the transfer function once offset and gain errors have
been nullified. For a DAC, the deviations are measured
at every single step.
Differential to Single-Ended Conversion
The MAX4108 low-distortion, high input-bandwidth
amplifier may be used to generate a voltage from the
MAX5188’s current-array output. The differential volt-
age across OUT1P (or OUT2P) and OUT1ꢁ (or OUT2ꢁ)
is converted into a single-ended voltage by designing
an appropriate operational amplifier configuration as
shown in Figure 6.
Differential Nonlinearity
Differential nonlinearity (DꢁL) (Figure 5b) is the differ-
ence between an actual step height and the ideal value
of 1LSB. A DꢁL error specification of less than 1LSB
guarantees no missing codes and a monotonic transfer
function.
Grounding and Power-Supply Decoupling
Grounding and power-supply decoupling strongly influ-
ence the performance of the MAX5188/MAX5191.
Unwanted digital crosstalk may couple through the
input, reference, power-supply, and ground connec-
tions, which may affect dynamic specifications like SꢁR
or SFDR. In addition, electromagnetic interference
(EMI) can either couple into or be generated by the
MAX5188/MAX5191. Therefore, grounding and power-
supply decoupling guidelines for high-speed, high-fre-
quency applications should be closely followed.
Offset Error
Offset error (Figure 5c) is the difference between the
ideal and the actual offset point. For a DAC, the offset
point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated by trimming.
Gain Error
Gain error (Figure 5d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
alters the slope of the transfer function and corre-
sponds to the same percentage error in each step.
First, a multilayer PC board with separate ground and
power-supply planes is recommended. High-speed
signals should run on controlled impedance lines
directly above the ground plane. Since the MAX5188/
MAX5191 have separate analog and digital ground
buses (AGꢁD and DGꢁD, respectively), the PC board
should also have separate analog and digital ground
sections with only one point connecting the two. Digital
signals should run above the digital ground plane, and
analog signals should run above the analog ground
plane.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the noise generated on a DAC’s
output when any digital input transitions. Proper board
layout and grounding will significantly reduce this
noise, but there will always be some feedthrough
caused by the DAC itself.
Both devices have two power-supply inputs: analog
V
DD
(AV ) and digital V
(DV ). Each AV
input
DD
DD
DD
DD
should be decoupled with parallel 10µF and 0.1µF
ceramic-chip capacitors as close to the pin as possi-
ble. Their opposite ends should have the shortest pos-
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first four harmonics to the fun-
damental itself. This is expressed as:
sible connection to the ground plane. The DV
pins
DD
should also have separate 10µF and 0.1µF capacitors,
again adjacent to their respective pins. Try to minimize
the analog load capacitance for proper operation. For
best performance, bypass CREF1 and CREF2 with low-
2
2
2
2
V
+ V + V + V
3 4 5
(
)
2
THD = 20 × log
ESR, 0.1µF capacitors to AV
.
DD
V
1
The power-supply voltages should also be decoupled
with large tantalum or electrolytic capacitors at the
point they enter the PC board. Ferrite beads with addi-
tional decoupling capacitors forming a pi network could
also improve performance.
where V is the fundamental amplitude, and V through
1
2
V
are the amplitudes of the 2nd- through 5th-order
harmonics.
5
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion
component.
12 ______________________________________________________________________________________
Dual, 8-Bit, 40MHz, Current/Voltage,
Alternate-Phase Output DACs
AV
AV
DD
DD
+3V
+3V
10µF
0.1µF
0.1µF
0.1µF
10µF
0.1µF
402Ω
DV
AV
DD CREF1
CREF2
DD
+5V
-5V
402Ω
CLK
OUT1P
OUTPUT1
400Ω*
400Ω*
MAX5188
MAX5191
MAX4108
D0–D7
OUT1N
402Ω
402Ω
402Ω
REFO
REFR
+5V
402Ω
0.1µF
OUT2P
OUTPUT2
400Ω*
400Ω*
MAX4108
-5V
R
**
SET
OUT2N
AGND
402Ω
402Ω
DGND
REN
**MAX5188 ONLY
*400Ω RESISTORS INTERNAL TO MAX5191 ONLY.
Figure 6. Differential to Single-Ended Conversion Using the MAX4108 Low-Distortion Amplifier
Chip Information
TRAꢁSISTOR COUꢁT: 9464
SUBSTRATE COꢁꢁECTED TO GꢁD
______________________________________________________________________________________ 13
Dual, 8-Bit, 40MHz, Current/Voltage,
Alternate-Phase Output DACs
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.
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