MAX5195EGM-T [MAXIM]
D/A Converter, 1 Func, Parallel, Word Input Loading, 7 X 7 MM, 0.90 MM HEIGHT, QFN-48;
| 型号： | MAX5195EGM-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Parallel, Word Input Loading, 7 X 7 MM, 0.90 MM HEIGHT, QFN-48 转换器 |
| 文件： | 总18页 (文件大小：652K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2557; Rev 0; 7/02
14-Bit, 260Msps High-Dynamic
Performance DAC
General Description
Features
The MAX5195 is an advanced, 14-bit, 260Msps digital-
to-analog converter (DAC) designed to meet the
demanding performance requirements of signal synthe-
sis applications found in wireless base stations and
other communication systems. Operating from a single
5V supply, this DAC offers exceptional dynamic perfor-
mance such as 77dBc spurious-free dynamic range
o 260Msps Output Update Rate
o Excellent SFDR Performance
To Nyquist (-12dBFS)
At 19.4MHz Output = 77dBc
At 51.6MHz Output = 76dBc
o Industry-Leading IMD Performance
For 4 Tones (-15dBFS)
(SFDR) at f
= 19.4MHz, while supporting update
OUT
rates beyond 260Msps.
At 18MHz Output = 86dBc
At 31MHz Output = 84dBc
The MAX5195 current-source array architecture sup-
ports a full-scale current range of 10mA to 20mA, which
allows a differential output voltage swing between
o Low Noise Performance
0.5V
and 1V
.
P-P
SNR = 160dB/Hz at f
= 19.4MHz
P-P
OUT
The MAX5195 features an integrated 1.2V bandgap ref-
erence and control amplifier to ensure high accuracy
and low-noise performance. Additionally, a separate
reference input pin allows the user to apply an external
reference source for optimum flexibility.
o On-Chip 1.2V Bandgap Reference
o 20mA Full-Scale Current
o Single 5V Supply
o Differential LVPECL-Compatible Digital Inputs
o 48-Lead QFN-EP Package
The digital and clock inputs of the MAX5195 are
designed for differential LVPECL-compatible voltage
levels.
The MAX5195 is available in a 48-lead QFN package
with exposed paddle and is specified for the extended
industrial temperature range (-40°C to +85°C).
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX5195EGM
-40°C to +85°C
48 QFN-EP*
Applications
*EP = Exposed paddle.
Base Stations:
Single-/Multi-Carrier UMTS, GSM
Pin Configuration
LMDS, MMDS, Point-to-Point Microwave
Direct IF Synthesis
TOP VIEW
Digital-Signal Synthesis
Broadband Cable Systems
Automated Test Equipment
Instrumentation
36
35
34
33
32
31
30
29
28
27
26
25
D9P
D8N
D8P
1
2
3
4
5
6
7
8
9
RSET
AV
CC
AMPOUT
D7N
D7P
CLKP
CLKN
D6N
D6P
AV
AV
CC
CC
OUTP
OUTN
AV
CC
MAX5195
AGND
D5N 10
D5P 11
D4N 12
AGND
REFOUT
AV
CC
QFN
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
14-Bit, 260Msps High-Dynamic
Performance DAC
ABSOLUTE MAXIMUM RATINGS
AV , DV
to AGND..............................................-0.3V to +6V
to DGND..............................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
CC
CC
CC
AV , DV
48-Pin QFN-EP (thermal resistance θ = +37°C/W)....2162W
CC
JA
AGND to DGND.....................................................-0.3V to +0.3V
D0N–D013, D0P–D13P, T.P. to DGND .................-0.3V to +3.6V
OUTP, OUTN, AMPOUT, REFOUT, CLKP,
CLKN, RSET to AGND..........................................-0.3V to +6V
REFIN Voltage Range...............................................-0.3V to +6V
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= DV
= 5V, AGND = DGND = 0, external reference V
= 1.196V, R = 27.4Ω referenced to AV , V
= 1V
,
P-P
CC
CC
REFIN
T
CC
OUT
R
= 3.83kΩ, f
= 156MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
SET
CLK
A
MIN
MAX A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
14
2
LSB
LSB
LSB
%FS
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
Best-straight-line fit
= +25°C
DNL
T
-3.3
1.5
0.05
2.5
1.6
+3.0
0.1
6
A
V
(Note 1)
OS
Internal reference
External reference
Full-Scale Gain Error
(Note 2)
GE
%FS
4
DYNAMIC PERFORMANCE
Maximum Throughput Rate
f
260
MHz
CLK
Full-scale output, within Nyquist window,
Signal-to-Noise Ratio
SNR
160
dB/Hz
f
= 260MHz, f = 19.4MHz
OUT
CLK
f
= 1MHz, -2dBFS
89
77
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
f
= 156MHz
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
= 19.42MHz
= 51.67MHz
= 19.4MHz
= 51.61MHz
= 19.42MHz
= 51.67MHz
= 19.42MHz
= 51.61MHz
= 1.27MHz
= 9.53MHz
= 19.42MHz
= 28.82MHz
= 38.42MHz
= 51.67MHz
= 70.05MHz
CLK
Spurious-Free Dynamic Range
to Nyquist, -12dBFS
SFDR
76
dBc
dBc
74
f
f
f
= 260MHz
= 156MHz
= 260MHz
CLK
CLK
CLK
72
82
75
Spurious-Free Dynamic Range
10MHz Window, -12dBFS
SFDR
HD2
82
76
-88
-86
-82
-79
-77
-79
-72
f
f
= 156MHz
= 260MHz
CLK
CLK
2nd-Order Harmonic Distortion,
-12dBFS
dBc
2
_______________________________________________________________________________________
14-Bit, 260Msps High-Dynamic
Performance DAC
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= 5V, AGND = DGND = 0, external reference V
= 1.196V, R = 27.4Ω referenced to AV , V
= 1V
,
P-P
CC
CC
REFIN
T
CC
OUT
R
= 3.83kΩ, f
= 156MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
SET
CLK
A
MIN
MAX A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
-90
-85
-81
-78
-78
-79
-80
92
90
91
89
89
87
88
87
86
84
86
84
81
79
81
78
80
77
79
76
75
73
76
74
MAX
UNITS
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
= 1.27MHz
= 9.53MHz
= 19.42MHz
= 28.82MHz
= 38.42MHz
= 51.64MHz
= 70.05MHz
= 18MHz
= 31MHz
= 18MHz
= 31MHz
= 18MHz
= 31MHz
= 18MHz
= 31MHz
= 18MHz
= 31MHz
= 18MHz
= 31MHz
= 18MHz
= 31MHz
= 18MHz
= 31MHz
= 18MHz
= 31MHz
= 18MHz
= 31MHz
= 18MHz
= 31MHz
= 18MHz
= 31MHz
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
f
= 156MHz
CLK
3rd-Order Harmonic Distortion,
-12dBFS
HD3
dBc
f
f
= 260MHz
= 156MHz
CLK
CLK
2-Tone IMD,
-9dBFS, 200kHz
Frequency Spacing
IM3
dBc
dBc
dBc
dBc
dBc
dBc
f
f
f
f
f
f
f
f
f
f
f
= 260MHz
= 156MHz
= 260MHz
= 156MHz
= 260MHz
= 156MHz
= 260MHz
= 156MHz
= 260MHz
= 156MHz
= 260MHz
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
2-Tone IMD,
-12dBFS, 200kHz
Frequency Spacing
IM3
4-Tone Power Ratio,
-15dBFS, 200kHz
Frequency Spacing
MTPR
MTPR
MTPR
MTPR
4-Tone Power Ratio,
-18dBFS, 200kHz
Frequency Spacing
8-Tone Power Ratio,
-21dBFS, 200kHz
Frequency Spacing
8-Tone Power Ratio,
-24dBFS, 200kHz
Frequency Spacing
REFERENCE AND CONTROL AMPLIFIER
Internal Reference Voltage Range
V
1.136
1.196
1.255
V
V
REFOUT
1.196
8%
Reference Input Voltage Range
V
REFIN
Internal Reference Voltage Drift
Internal Reference
TCO
30
200
1.5
1
µV/°C
µA
REF
I
SINK
Sink/Source Current
I
mA
SOURCE
Amplifier Input Impedance
R
MΩ
IN
_______________________________________________________________________________________
3
14-Bit, 260Msps High-Dynamic
Performance DAC
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= 5V, AGND = DGND = 0, external reference V
= 1.196V, R = 27.4Ω referenced to AV , V
= 1V
,
P-P
CC
CC
REFIN
T
CC
OUT
R
= 3.83kΩ, f
= 156MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
SET
CLK
A
MIN
MAX A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG OUTPUT TIMING
Output Fall Time
t
90% to 10%
10% to 90%
0.8
0.8
0.5
ns
ns
FALL
Output Rise Time
t
RISE
Glitch Energy
pV-s
TIMING CHARACTERISTICS
Data-to-Clock Setup Time
(D0N–D13N, D0P–D13P)
t
Referenced to the rising edge, Figure 4
Referenced to the rising edge, Figure 4
0.5
1
ns
ns
SETUP
Data-to-Clock Hold Time
(D0N–D13N, D0P–D13P)
t
0.5
0.5
1.1
HOLD
Propagation Delay Time
t
(Note 3)
ns
ns
ns
PD
Minimum Clock Pulse Width High
Minimum Clock Pulse Width Low
t
CLKP, CLKN
CLKP, CLKN
1.6
1.6
CH
t
CL
LOGIC INPUTS (D0N–D13N, D0P–D13P, CLKP, CLKN)
Input Logic High
V
2.4
V
IH
Input Logic Low
V
1.6
V
IL
Input Logic Current, Logic High
Input Logic Current, Logic Low
Digital Input Capacitance
POWER SUPPLIES
I
V
V
= 2.4V
= 1.6V
-300
-300
50
10
2
+300
+300
µA
µA
pF
IH
IH
IL
I
IL
C
IN
Analog Supply Voltage Range
Digital Supply Voltage Range
Analog Supply Current
Digital Supply Current
AV
DV
4.75
4.75
5
5
5.25
5.25
58
V
V
CC
CC
I
AV
AV
AV
AV
= DV
= DV
= DV
= DV
= 5V
48
mA
AVCC
DVCC
CC
CC
CC
CC
CC
CC
CC
CC
I
= 5V
190
1190
0.2
230
1440
mA
Power Dissipation
P
= 5V
mW
%FS/V
DISS
Power-Supply Rejection Ratio
PSRR
= 5V 5% (Note 4)
Note 1: Offset error is the deviation of the output voltage from its ideal value at midscale.
Note 2: Full-scale gain error is the deviation of the output voltage from the ideal full-scale value. The actual full-scale voltage is
determined by V - V , when D0P–D13P are set high and D0N–D13N are set low.
OUTP
OUTN
Note 3: Propagation delay is the time difference between the active edge of the clock and the active edge of the output.
Note 4: Power-supply rejection ratio is the full-scale output change as the supply voltage varies over its specified range.
4
_______________________________________________________________________________________
14-Bit, 260Msps High-Dynamic
Performance DAC
Typical Operating Characteristics
(AV
1V , R
P-P SET
= DV
= 5V, external reference V
= 1.196V, f
= 156.072MHz, R = 27.4Ω referenced to AV , C = 15pF, V
=
REFIN
CC
CC
CLK
T
CC
L
OUT
= 3.83kΩ, T = +25°C, unless otherwise noted.)
A
REFERENCE VOLTAGE
vs. TEMPERATURE
INTEGRAL NONLINEARITY
DIFFERENTIAL NONLINEARITY
2.0
1.5
1.0
0.5
0
3
2
1.20
1.19
1.18
1.17
1.16
1
0
-0.5
-1.0
-1.5
-2.0
-1
-2
-3
0
2048 4096 6144 8192 10240122881433616384
DIGITAL INPUT CODE
0
2048 4096 6144 8192 10240122881433616384
DIGITAL INPUT CODE
-40
-15
10
35
60
85
TEMPERATURE (°C)
REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
OFFSET ERROR vs. TEMPERATURE
GAIN ERROR vs. TEMPERATURE
1.1904
1.1900
1.1896
1.1892
1.1888
1.1884
0
-0.02
-0.04
-0.06
-0.08
-0.10
1.75
1.70
1.65
1.60
1.55
1.50
4.750
4.875
5.000
5.125
5.250
-40
-15
10
35
60
85
-40
-15
10
35
60
85
ANALOG SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
SPURIOUS-FREE DYNAMIC RANGE vs.
OUTPUT FREQUENCY (f
= 156.072MHz)
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
CLK
100
90
80
70
60
50
40
250
200
150
100
50
250
200
150
100
50
-6dBFS
-12dBFS
DIGITAL SUPPLY CURRENT
ANALOG SUPPLY CURRENT
DIGITAL SUPPLY CURRENT
ANALOG SUPPLY CURRENT
-18dBFS
0
0
0
10 20 30 40 50 60 70 80
(MHz)
-40
-15
10
35
60
85
4.750
4.875
5.000
5.125
5.250
f
TEMPERATURE (°C)
ANALOG SUPPLY VOLTAGE (V)
OUT
_______________________________________________________________________________________
5
14-Bit, 260Msps High-Dynamic
Performance DAC
Typical Operating Characteristics (continued)
(AV
1V , R
P-P SET
= DV
= 5V, external reference V
= 1.196V, f
= 156.072MHz, R = 27.4Ω referenced to AV , C = 15pF, V
=
REFIN
CC
CC
CLK
T
CC
L
OUT
= 3.83kΩ, T = +25°C, unless otherwise noted.)
A
SPURIOUS-FREE DYNAMIC RANGE vs.
OUTPUT FREQUENCY (f = 208.096MHz)
SPURIOUS-FREE DYNAMIC RANGE vs.
SPURIOUS-FREE DYNAMIC RANGE vs.
OUTPUT FREQUENCY (f
= 260.12MHz)
OUTPUT FREQUENCY (f
= 312.144MHz)
CLK
CLK
CLK
100
90
80
70
60
50
40
100
90
80
70
60
50
40
100
90
80
70
60
50
40
-6dBFS
-6dBFS
-6dBFS
-12dBFS
-12dBFS
-12dBFS
-18dBFS
-18dBFS
-18dBFS
0
20
40
60
80
100
120
0
20
40
60
80 100 120 140
(MHz)
0
20 40 60 80 100 120 140 160
(MHz)
f
(MHz)
f
OUT
f
OUT
OUT
SPECTRAL PLOT, SINGLE-TONE SFDR
FOR A 10MHz WINDOW
SPURIOUS-FREE DYNAMIC RANGE vs.
TEMPERATURE (f = 16MHz AT -12dBFS)
SPECTRAL PLOT, SINGLE-TONE SFDR
FOR A 10MHz WINDOW
OUT
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
83
82
81
80
79
78
77
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
f
f
= 260.12MHz
f
= 160MHz
f
f
= 156.072MHz
CENTER
CLK
CENTER
CLK
CLK
= 19.3975MHz
= 19.416 MHz
OUTPUT AMPLITUDE:
-12dBFS
OUTPUT AMPLITUDE:
-12dBFS
f
f
CENTER
CENTER
10 12 14 16 18 20 22 24 26 28
OUTPUT FREQUENCY (MHz)
-40
-15
10
35
60
85
10 12 14 16 18 20 22 24 26 28
OUTPUT FREQUENCY (MHz)
TEMPERATURE (°C)
SPURIOUS-FREE DYNAMIC RANGE vs.
MULTITONE (4 TONES) POWER RATIO vs.
CLOCK FREQUENCY
CLOCK FREQUENCY (f
= 19MHz)
OUT
85
81
77
73
69
65
-70
-75
-80
-85
-90
-95
-6dBFS
32MHz/-18dBFS
18MHz/-18dBFS
32MHz/-15dBFS
-12dBFS
18MHz/-15dBFS
-18dBFS
150
180
210
240
(MHz)
270
300
330
150
180
210
240
(MHz)
270
300
330
f
f
CLK
CLK
6
_______________________________________________________________________________________
14-Bit, 260Msps High-Dynamic
Performance DAC
Typical Operating Characteristics (continued)
(AV
1V , R
P-P SET
= DV
= 5V, external reference V
= 1.196V, f
= 156.072MHz, R = 27.4Ω referenced to AV , C = 15pF, V
=
REFIN
CC
CC
CLK
T
CC
L
OUT
= 3.83kΩ, T = +25°C, unless otherwise noted.)
A
MULTITONE (8 TONES) POWER RATIO
vs. CLOCK FREQUENCY
OUTPUT RISE/FALL TIMES
-70.0
32MHz/-24dBFS
-73.0
90%
10%
18MHz/-24dBFS
-76.0
200mV/div
32MHz/-21dBFS
-79.0
18MHz/-21dBFS
-82.0
-85.0
150
180
210
240
(MHz)
270
300
330
1ns/div
f
CLK
Pin Description
PIN
1
NAME
D9P
FUNCTION
Data Bit 9
2
D8N
D8P
Complementary Data Bit 8
Data Bit 8
3
4
D7N
D7P
Complementary Data Bit 7
Data Bit 7
5
6
CLKP
Converter Clock Input. Positive input terminal for LVPECL-compatible differential converter clock.
Complementary Converter Clock Input. Negative input terminal for LVPECL-compatible differential
converter clock.
7
CLKN
8
D6N
D6P
D5N
D5P
D4N
D4P
D3N
D3P
Complementary Data Bit 6
Data Bit 6
9
10
11
12
13
14
15
Complementary Data Bit 5
Data Bit 5
Complementary Data Bit 4
Data Bit 4
Complementary Data Bit 3
Data Bit 3
Digital Supply Voltage. Accepts a 4.75V to 5.25V supply voltage range. Bypass to DGND with a capacitor
combination of 10µF in parallel with 0.1µF and 47pF.
16, 47
DV
CC
17, 46
18
19
DGND
D2N
D2P
Digital Ground
Complementary Data Bit 2
Data Bit 2
20
21
D1N
D1P
Complementary Data Bit 1
Data Bit 1
22
D0N
Complementary Data Bit 0 (LSB)
_______________________________________________________________________________________
7
14-Bit, 260Msps High-Dynamic
Performance DAC
Pin Description (continued)
PIN
23
NAME
D0P
FUNCTION
Data Bit 0 (LSB)
24
T.P.
Test Point. Must be connected to LVPECL high level (2.4V) for optimum dynamic performance.
25, 29, 32,
33, 35
Analog Supply Voltage. Accepts a 4.75V to 5.25V supply voltage range. Bypass to AGND with a capacitor
combination of 10µF in parallel with 0.1µF and 47pF.
AV
CC
Reference Output. Output of the internal 1.2V precision bandgap reference. Bypass with a 1µF capacitor to
AGND, if an external reference source is used.
26
REFOUT
27, 28
30
AGND
OUTN
OUTP
Analog Ground
Complementary DAC Output. Negative terminal for differential voltage output.
DAC Output. Positive terminal for differential voltage output.
31
Control Amplifier Output. For stable operation, bypass to AGND with a combination of a 3kΩ resistor in
parallel with a 1.5µF tantalum capacitor.
34
36
37
AMPOUT
RSET
Output Current Set Resistor. External resistor (3.83kΩ to 7.66kΩ) sets the full-scale current of the DAC.
Reference Input. Accepts an input voltage range of 1.196V 8%. Bypass to AGND with a 0.1µF capacitor,
when used with the internal bandgap reference.
REFIN
38
39
40
41
42
43
44
45
48
D13N
D13P
D12N
D12P
D11N
D11P
D10N
D10P
D9N
Complementary Data Bit 13 (MSB)
Data Bit 13 (MSB)
Complementary Data Bit 12
Data Bit 12
Complementary Data Bit 11
Data Bit 11
Complementary Data Bit 10
Data Bit 10
Complementary Data Bit 9
8
_______________________________________________________________________________________
14-Bit, 260Msps High-Dynamic
Performance DAC
Internal Reference and Control Amplifier
Detailed Description
The MAX5195 supports operation with the on-chip 1.2V
bandgap reference or an external reference voltage
source. REFIN serves as the input for an external refer-
ence source, and REFOUT provides a 1.2V output volt-
age, if the internal reference is used. For internal
reference operation, REFIN and REFOUT must be con-
nected together and decoupled to AGND with a 1µF
capacitor in parallel with a 0.1µF capacitor for stable
operation.
Architecture
The MAX5195 is a high-performance, 14-bit, segmented
current-source array DAC (Figure 1) capable of operat-
ing with clock speeds up to 260MHz. The converter
consists of separate input and DAC registers, followed
by a current-source array. This current-source array is
capable of generating differential full-scale currents in
the range of 10mA to 20mA. An internal R2R resistor
network, in combination with external 27.4Ω termination
resistors, convert these differential output currents into a
differential output voltage with a peak-to-peak output
voltage range of 0.5V to 1V. An integrated 1.2V
bandgap reference, control amplifier, and user-selec-
table, external resistor determine the data converter’s
full-scale output range.
The MAX5195 reference circuit also employs a control
amplifier, designed to regulate the full-scale current I
FS
for the differential current outputs of the MAX5195. For
stable operation, the output AMPOUT of this amplifier
must be bypassed with a 3kΩ resistor in parallel with a
1.5µF tantalum capacitor to AGND. Configured as a
voltage-to-current amplifier, the output current can be
calculated as follows:
I
FS
= 64 ✕ I
- 1LSB
REF
DV
DGND
CC
AGND
AV
1.2V
REFERENCE
R2R
NETWORK
CC
BIAS
REFOUT
REFIN
OUTP
OUTN
CURRENT-SOURCE
ARRAY
RSET
CLKN
CLKP
INPUT REGISTER
DECODER
INPUT LATCH
MAX5195
14
D0N/D0P–D13N/D13P
Figure 1. Simplified MAX5195 Block Diagram
_______________________________________________________________________________________
9
14-Bit, 260Msps High-Dynamic
Performance DAC
Table 1. I and R
FS
Selection Matrix Based on a Typical 1.2V Reference Voltage
SET
R
(kΩ)
SET
FULL-SCALE CURRENT
REFERENCE CURRENT
(µA)
OUTPUT VOLTAGE
I
FS
(mA)
I
V
* (mV
OUTP/N P-P
)
REF
CALCULATED
7.68
1% EIA STD
7.50
10
12
14
16
18
20
156.26
187.50
218.80
250.00
281.30
312.50
500
6.40
6.34
600
700
800
900
1000
5.49
5.49
4.80
4.75
4.27
4.22
3.84
3.83
*Terminated into a 27.4Ω load (see Analog Outputs section for details) referenced to AV
.
CC
I
FS
= 64 ✕ I
- (I / 214)
REF FS
where I
V
is the reference output current (I
=
is
REF
/R
REF
3kΩ
1.5µF
AV
CC
) and I is the full-scale current. R
REFOUT SET
FS
SET
MAX5195
the reference resistor that determines the amplifier’s
output current (Figure 2) on the MAX5195. See Table 1
for a matrix of different I and R
selections.
FS
SET
1.2V
REFERENCE
External Reference Operation
Figure 3 illustrates a low-impedance reference source
applied to the data converter for external reference
operation. REFIN allows an input voltage range of
1.196V 8%. Use a fixed output voltage reference
source such as the 1.2V, 25ppm/°C (typ) MAX6520
bandgap reference for improved accuracy and drift
performance. Bypass the unused REFOUT pin of the
MAX5195 with a 1µF capacitor to AGND.
REFOUT
0.1µF
1µF
OUTP
OUTN
REFIN
RSET
CURRENT-SOURCE
ARRAY
I
= V
/R
I
REF
REF
REFOUT SET
NOTE: CONNECT REFIN AND REFOUT TOGETHER FOR INTERNAL REFERENCE OPERATION.
Figure 2. Internal Reference Configuration
3kΩ
1.5µF
AV
CC
MAX5195
AMPOUT
1.2V
REFERENCE
REFOUT
1µF
REFIN
MAX6520
OUTP
OUTN
CURRENT-SOURCE
ARRAY
RSET
I
= V
/R
REF
REFOUT SET
I
REF
Figure 3. External Reference Configuration Using the MAX6520
10 ______________________________________________________________________________________
14-Bit, 260Msps High-Dynamic
Performance DAC
Table 2. LVPECL Voltage Levels
PARAMETER
Input Voltage High
MINIMUM LVPECL SPECIFICATION
MAXIMUM LVPECL SPECIFICATION
V
V
** - 1.16V
CC
** - 1.81V
CC
V
V
** - 0.88V
CC
** - 1.48V
CC
Input Voltage Low
Common-Mode Level
V
** - 1.3V
CC
**V
is the supply voltage associated with the LVPECL source. A typical V
level associated with LVPECL is 3.3V, which sets the
CC
CC
common-mode level to 2V, allowing a typical peak-to-peak signal swing of 0.8V.
provides for minimum setup and hold times (<2ns), allow-
ing for noncritical external interface timing (Figure 4).
LVPECL-Compatible Digital Inputs
(D0P–D13P, D0N–D13N)
The MAX5195 digital interface consists of 14 differen-
tial, LVPECL-compatible digital input pins. These inputs
follow standard positive binary coding where D0P and
D0N represent the differential inputs to the least signifi-
cant bit (LSB), and D13P and D13N represent the dif-
ferential pair associated with the most significant bit
(MSB). D0P/N through D13P/N accept LVPECL input
For best AC performance, a differential, DC-coupled
clock signal with LVPECL-compatible voltage levels
(Table 2) should be used. The MAX5195 operates
properly with a clock duty cycle set within the limits list-
ed in the Electrical Characteristics table. However, a
50% duty cycle should be utilized for optimum dynamic
performance. To maintain the DAC’s excellent dynamic
performance, clock and data signals should originate
from separate signal sources.
levels of 0.8V
(Table 2).
P-P
Each of the digital input terminals can be terminated
with a separate 50Ω resistor; however, to achieve the
lowest noise performance, it is recommended to termi-
nate each differential pair with a 100Ω resistor located
between the positive and negative input terminals.
Analog Outputs (OUTP, OUTN)
The MAX5195’s current array is designed to drive full-
scale currents of 10mA to 20mA into an internal R2R
resistor network (R
). To achieve the desired differ-
R2R
ential output voltage range of 0.5V
to 1V , both
P-P
Clock Inputs (CLKP, CLKN) and Data
Timing Relationship
P-P
OUTP and OUTN should be externally terminated into
27.4Ω (R ), resulting in a combined load of R
=
LOAD
T
The MAX5195 features differential, LVPECL-compatible
clock inputs. Internal edge-triggered flip-flops latch the
input word on the rising edge of the clock-input pair
CLKP/CLKN. The DAC is updated with the data word
on the next rising edge of the clock input. This results in
a conversion latency of one clock cycle. The MAX5195
25Ω (Figure 5):
R
LOAD
R
LOAD
R
LOAD
= R
|| R
R2R T
= (285Ω ✕ 27.4Ω) / (285Ω + 27.4Ω)
= 25Ω
t
t
CL
CH
CLKP
CLKN
t
SETUP
t
HOLD
D13–D0
OUTP
OUTN
90% POINT
t
PD
MAX5195
10% POINT
t
, t
RISE FALL
Figure 4. Input/Output Timing Information
______________________________________________________________________________________ 11
14-Bit, 260Msps High-Dynamic
Performance DAC
The proportional, differential output voltages can then
AV
CC
be used to drive a wideband RF transformer or a fast,
low-noise, low-distortion operational amplifier to convert
the differential voltage into a single-ended output.
AV
CC
R
T
R
R
R2R
285Ω
R2R
285Ω
R
R
= 25Ω
27.4Ω
LOAD
The MAX5195 analog outputs can also be configured in
single-ended mode. For more details on different output
configurations, see the Applications Information section.
OUTN
OUTP
= 25Ω
R
T
27.4Ω
LOAD
Applications Information
AV
Differential Coupling Using a
Wideband RF Transformer
CC
A wideband RF transformer such as the TTWB1010 (1:1
turns ratio) from Coilcraft can be used to convert the
MAX5195 differential output signal to a single-ended
signal (Figure 6). As long as the generated output
spectrum is within the passband of the transformer, a
differentially coupled transformer provides the best dis-
tortion performance. Additionally, the transformer helps
to reject noise and even-order harmonics, provides
electrical isolation, and is capable of delivering more
power to the load.
AMPOUT
AGND
R
IS THE COMBINED LOAD OF
LOAD
THE INTERNAL R2R RESISTOR
MAX5195
NETWORK IN PARALLEL WITH THE
EXTERNAL TERMINATION RESISTOR.
Figure 5. Simplified Output Architecture
With a full-scale current of 10mA (20mA), both outputs
OUTP and OUTN achieve a 0.25V (0.5V) voltage swing
Single-Ended Unbuffered Output
Configuration
each, resulting in a 0.5V
(1V ) differential output
P-P
P-P
Figure 7a shows an unbuffered single-ended output,
which is suitable for applications requiring a unipolar
voltage output. The nominal termination resistor load of
signal. For applications that require an even smaller
output voltage swing, the termination resistor value R
T
can be as low as 0Ω.
27.4Ω (referred to AV ) results in a differential output
CC
AV , DV
CC
CC
AV
CC
R
T
27.4Ω
V
, SINGLE ENDED
AGND
OUT
OUTP
1 : 1
D0–D13
14
OUTN
TTWB1010
R
T
AGND
27.4Ω
WIDEBAND RF TRANSFORMER
PERFORMS DIFFERENTIAL-TO-
SINGLE-ENDED CONVERSION.
AV
CC
MAX5195
Figure 6. Differential Coupling Using a Wideband RF Transformer
AGND, DGND
12 ______________________________________________________________________________________
14-Bit, 260Msps High-Dynamic
Performance DAC
AV , DV
CC
CC
AV
CC
R
T
27.4Ω
OUTP
V
OUTP
AGND
D0–D13
V
= I × R
OUT_ FS LOAD
14
V
OUTN
OUTN
R
T
27.4Ω
AGND
: RESISTOR COMBINATION OF
R
LOAD
AV
CC
INTERNAL R2R NETWORK AND EXTERNAL
TERMINATION RESISTOR
MAX5195
AGND, DGND
Figure 7a. Single-Ended Unbuffered Output Configuration
AV , DV
CC
CC
R
LOOP
OUTP
C
LOOP
D0–D13
V
OUT
14
AGND
OUTN
AV
CC
MAX5195
AGND, DGND
Figure 7b. Single-Ended Buffered Output Configuration
swing of 1V
(0.5V
single ended) when applying a
P-P
amplifier’s maximum output swing and the MAX5195
full-scale current determine the value of R . An
P-P
full-scale current of 20mA.
LOOP
optional roll-off capacitor (C
) in the feedback loop
LOOP
Alternatively, an external unity-gain amplifier can be
used to buffer the outputs. This circuit works as an I-V
amplifier (Figure 7b), in which OUTP is held at AV
the inverting terminal of the buffer amplifier. OUTN
should then be connected to AV to provide a DC-
current path for the current switched to OUTP. The
helps to ease dV/dt requirements at the input of the
operational amplifier. It is recommended that the ampli-
fier’s power-supply rails be higher than the resistor’s
by
CC
output reference voltage AV
due to its positive and
CC
CC
CC
negative output swing around AV
.
______________________________________________________________________________________ 13
14-Bit, 260Msps High-Dynamic
Performance DAC
point connecting the two planes. Digital signals should
Grounding, Bypassing, and Power-Supply
Considerations
run above the digital ground plane and analog signals
above the analog ground plane. Digital signals should
be kept as far away from sensitive analog inputs, refer-
ence input lines, and clock inputs. Digital signal paths
should be kept short and run lengths matched to avoid
propagation delay mismatch.
Grounding and power-supply decoupling can strongly
influence the performance of the MAX5195. Unwanted
digital crosstalk can couple through the input, refer-
ence, power supply, and ground connections, thus
affecting dynamic performance. Proper grounding and
power-supply decoupling guidelines for high-speed,
high-frequency applications should be closely followed.
This reduces EMI and internal crosstalk, which can also
affect the dynamic performance of the MAX5195.
The MAX5195 has two separate power-supply inputs
for analog (AV ) and digital (DV ). Each AV input
CC
CC
CC
should be decoupled with parallel ceramic chip capac-
itors of 10µF in parallel with 0.1µF and 47pF with these
capacitors as close to the supply pins as possible and
their opposite ends with the shortest possible connec-
Use of a multilayer printed circuit (PC) board with sepa-
rate ground and power-supply planes is recommend-
ed. High-speed signals should be run on lines directly
above the ground plane. Since the MAX5195 has sepa-
rate analog and digital ground buses (AGND and
DGND, respectively), the PC board should have sepa-
rate analog and digital ground sections with only one
tion to the ground plane (Figure 8). The DV
pins
CC
should also have separate 10µF in parallel with 0.1µF
and 47pF capacitors adjacent to their respective pins.
Try to minimize the analog and digital load capaci-
tances for proper operation.
5V
10µF
0.1µF
47pF
1.5µF
3kΩ
AMPOUT
DGND DV
CC
5V
AV
CC
1.2V
REFERENCE
R2R
NETWORK
47pF
0.1µF
10µF
BIAS
AGND
OUTP
REFOUT
REFIN
27.4Ω
27.4Ω
AGND
V
OUT
RSET
CURRENT-SOURCE
ARRAY
AGND
1µF
OUTN
3.83kΩ
AGND
0.1µF
INPUT REGISTER
DECODER
CLKP
CLKN
2.4V
1.6V
2V
MAX5195
260MHz,
LVPECL
INPUT LATCH
14
D0N/D0P–D13N/D13P
Figure 8. Decoupling and Bypassing Techniques for MAX5195—Typical Operating Circuit
14 ______________________________________________________________________________________
14-Bit, 260Msps High-Dynamic
Performance DAC
The power-supply voltages should also be decoupled
greater) vias (≤0.3mm diameter per via hole and 1.2mm
pitch between via holes) is recommended. A smaller via
array can be used as well, but results in an increased θja.
at the point where they enter the PC board with tanta-
lum or electrolytic capacitors. Ferrite beads with addi-
tional decoupling capacitors forming a π network can
also improve performance.
Note that efficient thermal management for the MAX5195
is strongly dependent on PC board and circuit design,
component placement, and installation; therefore, exact
performance figures cannot be provided. For more infor-
mation on proper design techniques and recommenda-
tions to enhance the thermal performance of parts such
as the MAX5195, refer to Amkor Technology’s website at
www.amkor.com.
The analog and digital power-supply inputs AV
and
CC
DV
of the MAX5195 allow a 4.75V to 5.25V supply
CC
voltage range.
Enhanced Thermal Dissipation QFN-EP Package
The MAX5195 is packaged in a thermally enhanced 48-
pin QFN-EP package, providing greater design flexibili-
ty, increased thermal efficiency, and a low thermal
junction-case (θjc) resistance of ≈2°C/W. In this pack-
age, the data converter die is attached to an EP lead
frame. The back of the lead frame is exposed at the
package bottom surface (the PC board side of the
package, Figure 9. This allows the package to be
attached to the PC board with standard infrared (IR)
flow soldering techniques. A specially created land pat-
tern on the PC board, matching the size of the EP
(5.5mm ✕ 5.5mm), guarantees proper attachment of the
chip, and can also be used for heat-sinking purposes.
Designing thermal vias* into the land area and imple-
menting large ground planes in the PC board design
further enhance the thermal conductivity between
board and package. To remove heat from a 48-pin
QFN-EP package effectively, an array of 3 ✕ 3 (or
Static Performance Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best-straight-line
fit (closest approximation to the actual transfer curve)
or a line drawn between the endpoints of the transfer
function, once offset and gain errors have been nulli-
fied. For a DAC, the deviations are measured every
individual step.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step height and the ideal value of 1LSB. A DNL
error specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function.
*Connect the land pattern to internal or external copper
planes.
48-LEAD QFN PACKAGE
WITH EXPOSED PAD
DIE
BONDING WIRE
EPOXY
EXPOSED PAD
COPPER
TRACE, 1oz
COPPER TRACE, 1oz
PC BOARD
TOP LAYER
GROUND PLANE
AGND, DGND
POWER PLANE
GROUND PLANE (AGND)
3 x 3 ARRAY OF THERMAL VIAS
THERMAL LAND
COPPER PLANE, 1oz
MAX5195
Figure 9. MAX5195 Exposed Paddle/PC Board Cross Section
______________________________________________________________________________________ 15
14-Bit, 260Msps High-Dynamic
Performance DAC
Offset Error
Spurious-Free Dynamic Range
The offset error is the difference between the ideal and
the actual offset point. For a DAC, the offset point is the
step value when the digital input is at midscale. This
error affects all codes by the same amount.
SFDR is the ratio of RMS amplitude of the carrier fre-
quency (maximum signal components) to the RMS
value of the next largest distortion component. SFDR is
measured in dBc, with respect to the carrier frequency
amplitude.
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Multitone Power Ratio (MTPR)
A series of equally spaced ones is applied to the DAC
with one tone removed from the center of the range.
MTPR is defined as the worst-case distortion (usually a
3rd-order harmonic product of the fundamental frequen-
cies), which appears as the largest spur at the frequency
of the missing tone in the sequence. This test can be
performed with any number of input tones; however, four
and eight tones are among the most common test condi-
tions for CDMA- and GSM/EDGE-type applications.
Glitch Energy
Glitch impulses are caused by asymmetrical switching
times in the DAC architecture, which generates unde-
sired output transients. The amount of energy that
appears at DAC’s output is measured over time and is
usually specified in the pV-s range.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc of either
input tone to the worst 3rd-order (or higher) IMD prod-
ucts. Note that 2nd-order IMD products usually fall at
frequencies, which can be easily removed by digital fil-
tering. Therefore, they are not as critical as 3rd-order
IMDs. The two-tone IMD performance of the MAX5195
was tested with the two individual input tone levels set
to -9dBFS and -12dBFS.
Dynamic Performance Parameter
Definitions
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of the
full-scale analog output (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum can be derived from the DAC’s resolution (N bits):
Chip Information
TRANSISTOR COUNT: 15,000
SNR = 6.02 ✕ N + 1.76
dB
dB
dB
However, noise sources such as thermal noise, refer-
ence noise, clock jitter, etc., affect the ideal reading.
SNR is therefore computed by taking the ratio of the
RMS signal to the RMS noise, which includes all spec-
tral components minus the fundamental, the first four
harmonics, and the DC offset.
PROCESS: SiGe
16 ______________________________________________________________________________________
14-Bit, 260Msps High-Dynamic
Performance DAC
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
ENG LIS H • ? ? ? ? • ? ? ? • ? ? ?
WH AT' S N EW
PRO DU CT S
S OL UT IO NS
D ESIGN
A PPNOTES
SU PPORT
B U Y
CO MPA N Y
M EMB ERS
M a x i m > P r o d u c t s > D i g i t a l - t o - A n a l o g C o n v e r t e r s H i g h - S p e e d D a t a C o n v e r t e r s
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D i a g r a m
D o c u m e n t R e f . : 1 9 - 2 5 5 7 ; R e v 0 ; 2 0 0 2 - 0 8 - 0 5
T h i s p a g e l a s t m o d i f i e d : 2 0 0 7 - 0 7 - 3 0
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