MAX521_技术文档

19-0378; Rev 3; 9/96

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

0/MAX521

_______________Ge n e ra l De s c rip t io n

____________________________Fe a t u re s

♦ Single +5V Supply

The MAX520/MAX521 are quad/octal, 8-bit voltage-output

digital-to-analog converters (DACs) with simple 2-wire ser-

ial interfaces that allow communication between multiple

devices. They operate from a single +5V supply and their

reference input range includes both supply rails.

♦ Simple 2-Wire Serial Interface

♦ I²C Compatible

♦ Outputs Swing Rail to Rail:

Unbuffered Outputs (MAX520)

Buffered Outputs (MAX521)

The MAX521 includes rail-to-rail output buffer amplifiers for

reduced system size and component count when driving

loads. The MAX520’s unbuffered voltage outputs reduce

the device’s total supply current to 4µA and provide

increased accuracy at low output currents.

♦ 1%-Accurate Trimmed Output Resistance (MAX520A)

♦ Ultra-Low 4µA Supply Current (MAX520)

♦ Individual DACs Have Separate Reference Inputs

♦ Power-On Reset Clears All Latches

The MAX520/MAX521 feature a serial interface and internal

software protocol, allowing communication at data rates up

to 400kbps. The interface, combined with the double-

buffered input configuration, allows the DAC registers to be

updated individually or simultaneously. In addition, the

devices can be put into a low-power shutdown mode that

reduces supply current to 4µA. Power-on reset ensures the

DAC outputs are at 0V when power is initially applied.

♦ 4µA Power-Down Mode

______________Ord e rin g In fo rm a t io n

TUE

(LSB)

PART^†

TEMP. RANGE PIN-PACKAGE

The MAX520 is available in 16-pin DIP and wide SO pack-

a ge s, a s we ll a s a spa c e -sa ving 20-p in SSOP. The

MAX521 comes in 20-pin DIP and 24-pin SO packages, as

well as a space-saving 24-pin SSOP.

MAX520ACPE

MAX520BCPE

MAX520ACWE

MAX520BCWE

0°C to +70°C

16 Plastic DIP

16 Wide SO

1

________________________Ap p lic a t io n s

Minimum Component Analog Systems

Digital Offset/Gain Adjustment

Ordering Information continued at end of data sheet.

MAX520 “A” grade parts include a 1%-accurate, factory-trimmed

output resistance.

†

Industrial Process Control

Automatic Test Equipment

_______________Fu n c t io n a l Dia g ra m s

Programmable Attenuators

SDA SCL

REF1

REF0

_________________P in Co n fig u ra t io n s

OUTPUT

LATCH 0

INPUT

LATCH 0

OUT0

OUT1

DAC0

MAX520

1

TOP VIEW

8

8-BIT

SHIFT REGISTER

ADDRESS

COMPARATOR

OUT1

OUT0

REF1

REF0

AGND

DGND

SCL

1

2

3

4

5

6

7

8

16 OUT2

15 OUT3

14 REF2

INPUT

LATCH 1

OUTPUT

LATCH 1

DAC1

START/STOP

DETECTOR

1

REF3

13

MAX520

OUTPUT

LATCH 2

INPUT

LATCH 2

OUT2

OUT3

DAC2

DAC3

V

12

11

10

9

DD

DECODE

1

AD2

AD1

AD0

4

INPUT

LATCH 3

OUTPUT

LATCH 3

SDA

1

AD0

AD2

REF2

REF3

DIP/SO

AD1

Functional Diagrams continued at end of data sheet.

Pin Configurations continued at end of data sheet.

________________________________________________________________ Maxim Integrated Products

1

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

ABSOLUTE MAXIMUM RATINGS

V

to DGND ...........................................................-0.3V to +6V

to AGND............................................................-0.3V to +6V

16-Pin Wide SO (derate 9.52mW/°C above +70°C) ......762mW

24-Pin Wide SO (derate 11.76mW/°C above +70°C) ....941mW

20-Pin SSOP (derate 8.00mW/°C above +70°C) .........640mW

24-Pin SSOP (derate 8.00mW/°C above +70°C) .........640mW

16-Pin CERDIP (derate 10.00mW/°C above +70°C)....800mW

20-Pin CERDIP (derate 11.11mW/°C above +70°C)....889mW

Operating Temperature Ranges

MAX520_C_ _/MAX521_C_ _..............................0°C to +70°C

MAX520_E_ _/MAX521_E_ _ ...........................-40°C to +85°C

MAX520_MJE/MAX521BMJP ........................-55°C to +125°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10sec) .............................+300°C

DD

V

DD

OUT_ ..........................................................-0.3V to (V + 0.3V)

REF_ ...........................................................-0.3V to (V + 0.3V)

AD0, AD1, AD2...........................................-0.3V to (V + 0.3V)

SCL, SDA to DGND..................................................-0.3V to +6V

AGND to DGND.....................................................-0.3V to +0.3V

Maximum Current into Any Pin............................................50mA

DD

Continuous Power Dissipation (T = +70°C)

A

16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)....842mW

20-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

0/MAX521

ELECTRICAL CHARACTERISTICS

(V = 5V ±10%, V

= 4V, R = ∞ (MAX520), R = 10kΩ (MAX521), C = 0pF (MAX520), C = 100pF (MAX521), T = T

to T

MIN MAX,

L

DD

REF_

A

unless otherwise noted. Typical values are at T = +25°C)

A

PARAMETER

STATIC ACCURACY

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Bits

Resolution

8

MAX520_

±1

±1.5

±2

Total Unadjusted Error

Differential Nonlinearity

TUE

DNL

MAX521A

MAX521B

LSB

Guaranteed monotonic

±1.0

8

LSB

MAX520_

MAX521_C

MAX521_E

MAX521BM

18

Zero-Code Error

ZCE

Code = 00 hex

mV

20

Zero-Code-Error Supply Rejection

Code = 00 hex

±1

mV

Zero-Code-Error Temperature Coefficient

±10

µV/°C

MAX520_

8

MAX521_C

MAX521_E

MAX521BM

18

20

Full-Scale Error

Code = FF hex

mV

Full-Scale-Error Supply Rejection

Code = FF hex, V = 5V ±10%

±1

mV

DD

Full-Scale-Error Temperature Coefficient

±10

µV/°C

2

_______________________________________________________________________________________

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

0/MAX521

ELECTRICAL CHARACTERISTICS (continued)

(V = 5V ±10%, V

= 4V, R = ∞ (MAX520), R = 10kΩ (MAX521), C = 0pF (MAX520), C = 100pF (MAX521), T = T

to T

,

L

A

MIN

MAX

DD

REF_

unless otherwise noted. Typical values are at T = +25°C)

A

PARAMETER

REFERENCE INPUTS

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input Voltage Range

Input Resistance

Input Current

0

8

V

DD

MAX520_

MAX521_

12

6

Code =

55 hex

(Note 1)

R

REF4

4

kΩ

µA

pF

IN

REF0–REF3

16

24

PD = 1

±10

MAX520_

MAX521_

30

120

30

Code =

FF hex

(Note 2)

Input Capacitance

REF4

REF0–REF3

MAX520_

MAX521_

-70

-60

-70

Channel-to-Channel Isolation

(Note 3)

(Note 4)

dB

AC Feedthrough

DAC OUTPUTS

Full-Scale Output Voltage

0

V

DD

V

T

= +25°C

15.8

15.6

8.4

16

16.2

16.4

A

MAX520A

MAX520B

Output Resistance (Note 5)

T

A

= T

to T

MAX

kΩ

MIN

MAX521_, OUT_ = 4V,

0mA to 2.5mA

0.25

1.5

MAX521_C/E, V

= V

,

REF_

DD

Output Load Regulation

Output Leakage Current

LSB

µA

code = FF hex, 0µA to 500µA

MAX521BM, V = V

code = FF hex, 0µA to 500µA

,

DD

REF_

2.0

MAX521_, OUT_ = 0V to V

PD = 1

,

DD

±10

DIGITAL INPUTS SCL, SDA

Input High Voltage

V

0.7V

V

IH

DD

Input Low Voltage

V

IL

0.3V

DD

Input Current

I

0V ≤ V ≤ V

±10

µA

V

IN

(Note 5)

DD

Input Hysteresis

V

0.05V

DD

HYST

Input Capacitance

C

10

pF

IN

DIGITAL INPUTS AD0, AD1

Input High Voltage

V

2.4

V

IH

Input Low Voltage

V

IL

0.8

Input Leakage

I

IN

V

IN

= 0V to V

DD

±10

µA

DIGITAL OUTPUT SDA (Note 6)

I

= 3mA

= 6mA

0.4

0.6

±10

10

SINK

Output Low Voltage

V

OL

I

SINK

Three-State Leakage Current

I

V

= 0V to V

DD

µA

pF

L

IN

Three-State Output Capacitance

C

(Note 5)

OUT

_______________________________________________________________________________________

3

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

ELECTRICAL CHARACTERISTICS (continued)

(V = 5V ±10%, V

= 4V, R = ∞ (MAX520), R = 10kΩ (MAX521), C = 0pF (MAX520), C = 100pF (MAX521), T = T

to T

,

L

A

MIN

MAX

DD

REF_

unless otherwise noted. Typical values are at T = +25°C)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DYNAMIC PERFORMANCE

MAX521_C

1.0

0.7

0.5

Voltage Output Slew Rate

Output Settling Time

Positive and negative MAX521_E

MAX521BM

V/µs

MAX520_, to 1/2LSB, no load

2

6

µs

MAX521_, to 1/2LSB, 10kΩ and

100pF load (Note 7)

Code = 00 hex, all digital inputs from

0V to V

Digital Feedthrough

5

nV-s

dB

DD

0/MAX521

Digital-Analog Glitch Impulse

Signal to Noise + Distortion Ratio

Code 128 to 127

= 4Vp-p at 1kHz, V = 5V,

12

87

V

REF_

DD

SINAD

code = FF hex

Multiplying Bandwidth

Wideband Amplifier Noise

POWER REQUIREMENTS

Supply Voltage

V

= 4Vp-p, 3dB bandwidth

1

MHz

REF_

MAX521_

60

µV

RMS

V

4.5

5.5

20

24

20

V

DD

MAX520_

4

10

4

µA

Operating mode, out-

put unloaded, all dig- MAX521_C

ital inputs 0V or V

Supply Current

I

DD

mA

µA

DD

MAX521_E/BM

Power-down mode (PD = 1)

Note 1: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.

Note 2: Input capacitance is code dependent. The highest input capacitance occurs at code = FF hex.

Note 3:

V

REF_

= 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the

code of all other DACs to 00 hex.

= 4Vp-p, 10kHz, DAC code = 00 hex.

Note 4:

V

REF_

Note 5: Guaranteed by design.

Note 6: I²C-compatible mode.

Note 7: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.

4

_______________________________________________________________________________________

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

0/MAX521

TIMING CHARACTERISTICS

(V = 5V ±10%, T = T

to T , unless otherwise noted. Typical values are at T = +25°C.)

MAX A

A

MIN

DD

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Serial Clock Frequency

f

0

400

kHz

SCL

Bus Free Time Between a STOP and a

START Condition

t

1.3

µs

BUF

Hold Time, (Repeated) Start Condition

Low Period of the SCL Clock

t

0.6

µs

ns

µs

pF

ns

HD, STA

t

1.3

LOW

High Period of the SCL Clock

t

0.6

HIGH

Setup Time for a Repeated START Condition

Data Hold Time

0.6

SU, STA

HD, DAT

t

(Note 8)

0

0.9

Data Setup Time

t

100

SU, DAT

Rise Time of Both SDA and SCL Signals, Receiving

Fall Time of Both SDA and SCL Signals, Receiving

Fall Time of SDA Transmitting (Note 6)

Setup Time for STOP Condition

t

(Note 9)

20 + 0.1Cb

0.6

300

250

R

t

F

I

≤ 6mA (Note 9)

SINK

t

SU, STO

Cb

Capacitive Load for Each Bus Line

Pulse Width of Spike Suppressed

400

50

t

SP

(Notes 10, 11)

0

Note 8: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V of the SCL signal) in order to

IL

bridge the undefined region of SCL’s falling edge.

Note 9: Cb = total capacitance of one bus line in pF. t and t measured between 0.3V and 0.7V .

DD

R

f

DD

Note 10: An input filter on the SDA and SCL input suppresses noise spikes less than 50ns.

Note 11: Guaranteed by design.

__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s

(V = 5V, DAC outputs unloaded, T = +25°C, unless otherwise noted.)

DD

A

MAX520

REFERENCE INPUT CURRENT vs.

TEMPERATURE (SHUTDOWN MODE)

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

SUPPLY CURRENT vs. TEMPERATURE

10

9

40

35

2

0

V

= 4V

REF

OPERATING MODE OR

SHUTDOWN MODE

ONE REF INPUT DRIVEN

8

V

DD

= 5V

-2

-4

30

25

20

15

10

5

V

REF

= 4Vp-p SINE WAVE

7

CENTERED AT 2.5V

6

-6

5

-8

4

-10

-12

-14

-16

-18

3

2

1

0

-60 -30

0

30

60

90 120 150

-60 -30

0

30

60

90 120 150

1k

10k

100k

FREQUENCY (Hz)

1M

10M

TEMPERATURE (°C)

_______________________________________________________________________________________

5

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

______________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )

(V = 5V, DAC outputs unloaded, T = +25°C, unless otherwise noted.)

DD

A

MAX520

NEGATIVE SETTLING TIME

POSITIVE SETTLING TIME

OUT2

1V/div

0/MAX521

1µs/div

OUT2 = NO LOAD, REF2 = 4V,

DAC CODE = FF HEX to 00 HEX

OUT2 = NO LOAD, REF2 = 4V,

DAC CODE = 00 HEX to FF HEX

MAX520

WORST-CASE 1LSB DIGITAL STEP CHANGE

(CAPACITIVE LOAD = 25pF)

WORST-CASE 1LSB DIGITAL STEP CHANGE

(CAPACITIVE LOAD < 5pF)

OUT2

20mV/div

AC COUPLED

OUT2

20mV/div

AC COUPLED

500ns/div

REF2 = 4V, DAC CODE = 7F HEX to 80 HEX

6

_______________________________________________________________________________________

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

0/MAX521

__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s

(V = 5V, DAC outputs unloaded, T = +25°C, unless otherwise noted.)

DD

A

MAX521

SUPPLY CURRENT vs. TEMPERATURE

SUPPLY CURRENT

vs. REFERENCE VOLTAGE

SHUTDOWN SUPPLY CURRENT

vs. TEMPERATURE

12

10

8

10

8

6

5

4

3

2

1

0

V

= 5.5V

V

= 5.5V

DD

ALL REFERENCE

INPUTS DRIVEN

ALL REF INPUTS = 0.6V

ALL DIGITAL INPUTS to V

ALL REF INPUTS = 0.6V

ALL DIGITAL INPUTS to V

DD

ALL DAC CODES FF HEX

6

ALL DAC CODES = FF HEX

4

ALL DAC CODES 00 HEX

2

ALL DAC CODES = 00 HEX

2

0

-60

-20

20

60

100

140

0

1

2

3

4

5

-60

-20

20

60

100

140

TEMPERATURE (°C)

REFERENCE VOLTAGE (V)

TEMPERATURE (°C)

MAX521

DAC OUTPUT LOW VOLTAGE

vs. OUTPUT SINK CURRENT

DAC OUTPUT HIGH VOLTAGE

vs. OUTPUT SOURCE CURRENT

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

1.0

2

1.0

V

= 5V

V

= 5V

REF

0

DAC CODE = FF HEX

LOAD to AGND

DAC CODE = 00 HEX

LOAD to V

DD

0.8

0.6

0.4

0.2

0

0.8

0.6

0.4

0.2

0

-2

-4

-6

4V SINE

p-p

-8

2V SINE

p-p

1V SINE

p-p

-10

-12

-14

-16

-18

0.5V SINE

p-p

V

REF

= SINE WAVE

CENTERED AT 2.5V

V

OUT

= V x (255/256)

REF

0

2

4

6

8

10 12 14 16

0

2

4

6

8

10

1k

10k

100k

FREQUENCY (Hz)

1M

10M

OUTPUT SOURCE CURRENT (mA)

OUTPUT SINK CURRENT (mA)

MAX521

POSITIVE SETTLING TIME

NEGATIVE SETTLING TIME

OUT1

1V/div

1µs/div

OUT1 LOADED WITH 10kΩ II 100pF, REF1 = 4V,

DAC CODE = 00 HEX to FF HEX

1µs/div

OUT1 LOADED WITH 10kΩ II 100pF, REF1 = 4V,

DAC CODE = FF HEX to 00 HEX

_______________________________________________________________________________________

7

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

______________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )

(V = 5V, DAC outputs unloaded, T = +25°C, unless otherwise noted.)

DD

A

MAX521

WORST-CASE 1LSB DIGITAL STEP CHANGE

OUT1

20mV/div

AC COUPLED

0/MAX521

500ns/div

REF1 = 5V, DAC CODE = 80 HEX to 7F HEX

REFERENCE FEEDTHROUGH AT 1kHz

CLOCK FEEDTHROUGH

A

B

A

B

A = REF1, 1V/div (4V

)

P-P

A = SCL, 400kHz, 5V/div

B = OUT1, 50µV/div, UNLOADED

B = OUT1, 5mV/div

FILTER PASSBAND = 100Hz to 10kHz, DAC CODE = 00 HEX

REF1 = 5V, DAC CODE = 7F HEX

REFERENCE FEEDTHROUGH AT 10kHz

REFERENCE FEEDTHROUGH AT 100kHz

A

B

A

B

A = REF1, 1V/div (4V

)

P-P

A = REF1, 1V/div (4V )

P-P

B = OUT1, 50µV/div, UNLOADED

FILTER PASSBAND = 1kHz to 100kHz, DAC CODE = 00 HEX

FILTER PASSBAND = 10kHz to 1MHz, DAC CODE = 00 HEX

8

_______________________________________________________________________________________

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

0/MAX521

______________________________________________________________P in De s c rip t io n

MAX520

MAX521

SO/SSOP

NAME

FUNCTION

DIP/SO

SSOP

DIP

1

2

1

2

3

5

1

2

1

OUT1

OUT0

REF1

REF0

N.C.

DAC1 Voltage Output

2

DAC0 Voltage Output

3

Reference Voltage Input for DAC1

Reference Voltage Input for DAC0

No Connect—not internally connected

Digital Ground

4

—

6

4, 7, 14, 17

—

5

7, 9, 16, 20

8

5

DGND

AGND

SCL

5

6

Analog Ground

7

9

7

8

Serial Clock Input

8

10

—

11

12

13

15

—

16

18

19

20

8

10

11

12

13

14

15

17

—

18

19

21

22

23

24

SDA

Serial Data Input

—

9

OUT4

OUT5

OUT6

OUT7

AD0

DAC4 Voltage Output

10

11

12

13

14

—

15

16

17

18

19

20

DAC5 Voltage Output

DAC6 Voltage Output

DAC7 Voltage Output

Address Input 0; sets IC’s slave address

Address Input 1; sets IC’s slave address

Address Input 2; sets IC’s slave address

Power Supply, +5V

10

11

12

—

13

14

15

16

AD1

AD2

V

DD

REF4

REF3

REF2

OUT3

OUT2

Reference Voltage Input for DACs 4, 5, 6, and 7

Reference Voltage Input for DAC3

Reference Voltage Input for DAC2

DAC3 Voltage Output

DAC2 Voltage Output

SDA

t

BUF

t

,

t ,

SU STA

SU DAT

t

,

HD STA

t

,

SU STO

t

t ,

HD DAT

LOW

SCL

t

HIGH

t

,

HD STA

t

R

t

F

START CONDITION

REPEATED START CONDITION

STOP CONDITION START CONDITION

Figure 1. 2-Wire Serial-Interface Timing Diagram

_______________________________________________________________________________________

9

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

_______________De t a ile d De s c rip t io n

S e ria l In t e rfa c e

The MAX520/MAX521 use a simple 2-wire serial interface

requiring only two I/O lines (2-wire bus) of a standard

microprocessor (µP) port. Figure 1 shows the timing dia-

gram for signals on the 2-wire bus. Figure 2 shows the

typical application of the MAX520/MAX521. The 2-wire

b us c a n ha ve s e ve ra l d e vic e s (in a d d ition to the

REF0

REF1

REF2

REF3

+1V

+4V

+5V

µC

SDA SCL

QUAD

DAC

OUT0

OFFSET ADJUSTMENT

GAIN ADJUSTMENT

R

1k

C

OUT1

OUT2

OUT3

MAX520

MAX520/MAX521) attached. The two bus lines (SDA and

SCL) must be high when the bus is not in use. When in

use, the port bits are toggled to generate the appropriate

signals for SDA and SCL. External pull-up resistors are

not required on these lines. The MAX520/MAX521 can

be used in applications where pull-up resistors are

SCL

SDA

AD0

AD1

AD2

+5V

2

required (such as in I C systems) to maintain compatibil-

ity with the existing circuitry.

0/MAX521

REF0

.

The MAX520/MAX521 are receive-only devices and

must be controlled by a bus master device. They oper-

ate at SCL rates up to 400kHz. A master device sends

information to the devices by transmitting their address

over the bus and then transmitting the desired informa-

tion. Each transmission consists of a START condition,

the MAX520/MAX521’s programmable slave-address,

one or more command-byte/output-byte pairs (or a

command byte alone, if it is the last byte in the trans-

mission), and finally, a STOP condition (Figure 3).

.

OCTAL

DAC

REF4

OUT0

OUT1

BRIGHTNESS ADJUSTMENT

CONTRAST ADJUSTMENT

MAX521

OUT2

.

THRESHOLD

ADJUSTMENTS

SCL

SDA

AD0

AD1

+5V

OUT6

OUT7

+5V

The address byte and pairs of command and output

bytes are transmitted between the START and STOP con-

ditions. The SDA state is allowed to change only while

SCL is low. SDA’s state is sampled, and therefore must

remain stable while SCL is high. The only exceptions to

this are the START and STOP conditions. Data is transmit-

ted in 8-bit bytes. Nine clock cycles are required to trans-

fer the data bits to the MAX520/MAX521. Set SDA low

during the 9th clock cycle as the MAX520/MAX521 pull

MOTOR

+12V

SDA low during this time. R (Figure 2) limits the current

C

that flows during this time if SDA stays high for short peri-

ods of time.

Figure 2. Typical Application Circuit

SLAVE ADDRESS BYTE

COMMAND BYTE

OUTPUT BYTE

SDA

SCL

MSB

LSB

ACK

MSB

LSB ACK

MSB

LSB

ACK

STOP CONDITION

START CONDITION

Figure 3. A Complete Serial Transmission

10 ______________________________________________________________________________________

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

0/MAX521

START and STOP Conditions

When the bus is not in use, both SCL and SDA must be

SDA

SCL

high. A bus master signals the beginning of a transmis-

sion with a START condition by transitioning SDA from

high to low while SCL is high (Figure 4). When the mas-

ter has finished communicating with the slave, it issues

a STOP condition by transitioning SDA from low to high

while SCL is high. The bus is then free for another

transmission.

START CONDITION

STOP CONDITION

Figure 4. All communications begin with a START condition and

end with a STOP condition, both generated by a bus master.

Slave Address

The MAX520/MAX521 each have a 7-bit-long slave

address (Figure 5). The first four bits (MSBs) of the slave

address have been factory programmed and are always

0101. In addition, the MAX521 has the next bit factory

programmed to 0. The logic state of the address input

pins (AD0, AD1, and AD2 of the MAX520; AD0 and AD1

of the MAX521) determine the least significant bits of the

7-bit slave address. These input pins may be connected

SLAVE ADDRESS

0

1

0

1

0 or AD2 AD1 AD0

0

ACK

SDA

SCL

LSB

SLAVE ADDRESS BITS AD2, AD1, AND AD0 CORRESPOND TO THE LOGIC STATE

OF THE ADDRESS INPUT PINS AD2, AD1, AND AD0.

to V or DGND, or they may be actively driven by TTL

DD

or CMOS logic levels. There are four possible slave

addresses for the MAX521, and therefore a maximum of

four such devices may be on the bus at one time. The

MAX520 has eight possible slave addresses. The eighth

bit (LSB) in the slave address byte should be low when

writing to the MAX520/MAX521.

Figure 5. Address Byte

R2

R1

R0 RST

PD

A2

A1

A0

ACK

SDA

SCL

MSB

LSB

The MAX520/MAX521 monitor the bus continuously,

waiting for a START condition followed by its slave

address. When a device recognizes its slave address, it

is ready to accept data.

R2, R1, R0:

RST:

RESERVED BITS. SET TO 0.

RESET BIT, SET TO 1 TO RESET ALL DAC REGISTERS.

Command Byte and Output Byte

A command byte follows the slave address. Figure 6

shows the format for the command byte. A command

byte is usually followed by an output byte unless it is

the last byte in the transmission. If it is the last byte, all

bits except PD and RST are ignored. If an output byte

follows the command byte, A0–A2 of the command

byte indicate the digital address of the DAC whose

input data latch receives the digital output data. The

data is transferred to the DAC’s output latch during the

STOP condition following the transmission. This allows

all DACs to be updated and the new outputs to appear

simultaneously (Figure 7).

PD:

POWER-DOWN BIT. SET TO 1 TO PLACE THE DEVICE IN THE 4µA

SHUTDOWN MODE. SET TO 0 TO RETURN TO THE NORMAL

OPERATIONAL STATE.

A2, A1, A0:

ACK:

ADDRESS BITS. DIGITAL ADDRESS FOR DAC0 TO DAC7. DETERMINES

WHICH DAC'S INPUT LATCH RECEIVES THE 8 BITS OF DATA IN

THE NEXT BYTE. A2 IS IGNORED BY THE MAX520.

ACKNOWLEDGE BIT. THE MAX520/MAX521 PULL SDA LOW DURING THE

9TH CLOCK PULSE.

Figure 6. Command Byte

the STOP condition is detected. When in power-down,

the MAX521’s DAC outputs float, and the MAX520’s

unbuffered outputs look like a 16kΩ resistor to AGND.

In this mode, the supply current is a maximum of 20µA.

A c omma nd b yte with the PD b it low re turns the

MAX520/MAX521 to normal operation following a STOP

condition, and the voltage outputs reflect the current

output-latch contents (Figures 9a and 9b). Because

each subsequent command byte overwrites the previ-

ous PD bit, only the last command byte of a transmis-

sion affects the power-down state.

Se tting the PD b it hig h p owe rs d own the MAX520/

MAX521 following a STOP condition (Figure 8a). If a

command byte with PD set high is followed by an out-

p ut b yte , the a d d re s s e d DAC’s inp ut la tc h will b e

updated and the data will be transferred to the DAC’s

output latch following the STOP condition (Figure 8b). If

the transmission’s last command byte has PD high, the

voltage outputs will not reflect the newly entered data

because the DAC will enter power-down mode when

______________________________________________________________________________________ 11

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

0 OR AD2

0

1

0

1

AD1 AD0 0

0

1

0

0 0

0

SDA

ACK

ADDRESS BYTE

ACK

COMMAND BYTE

(ADDRESSING DAC0)

OUTPUT BYTE

(FULL SCALE)

COMMAND BYTE

(ADDRESSING DAC1)

DAC0 INPUT LATCH

ACK

START

CONDITION

(

)

SET TO FULL SCALE

1

0

1

0

1

0

SDA

OUTPUT BYTE

(FULL SCALE)

ACK

COMMAND BYTE

(ADDRESSING DAC2)

DAC1 INPUT LATCH

OUTPUT BYTE

(HALF SCALE)

ACK

STOP

CONDITION

DAC2 INPUT LATCH

SET TO HALF SCALE

(

)

(

)

SET TO FULL SCALE

DAC OUTPUTS CHANGE HERE:

DACS 0 AND 1 GO TO FULL SCALE,

DAC 2 GOES TO HALF SCALE.

(

)

0/MAX521

Figure 7. Setting DAC Outputs

0 OR AD2

(PD)

1

(a)

0

1

0

1

AD1 AD0 0

0

X

0

X

SDA

ADDRESS BYTE

ACK

COMMAND BYTE

ACK

STOP

START

CONDITION

DEVICE ENTERS

CONDITION POWER-DOWN STATE

(

)

0 OR AD2

AD1 AD0 0

(b)

SDA

(PD)

1

0

1

0

1

0

1

ACK

ADDRESS BYTE

ACK

COMMAND BYTE

(ADDRESSING DAC0)

OUTPUT BYTE

(FULL SCALE)

ACK

STOP

START

CONDITION

DAC 0 INPUT LATCH

SET TO FULL SCALE

(

)

DEVICE ENTERS POWER-DOWN STATE.

DAC 0 OUTPUT LATCH SET TO FULL SCALE.

NOTE: X = DON'T CARE

(

)

Figure 8. Entering the Power-Down State

0 OR AD2

(PD)

0

(a)

0

1

0

1

AD1 AD0 0

0

X

SDA

ADDRESS BYTE

ACK

COMMAND BYTE

ACK

START

CONDITION

STOP

DEVICE RETURNS TO

CONDITION NORMAL OPERATION

(

)

0 OR AD2

AD1 AD0 0

(b)

SDA

(PD)

0

1

0

1

0

1

0

ACK

ADDRESS BYTE

ACK

COMMAND BYTE

(ADDRESSING DAC3)

OUTPUT BYTE

(SET TO 0)

ACK

STOP

CONDITION

START

CONDITION

DAC3 OUTPUT

(

)

LATCH SET TO 0

DEVICE RETURNS TO NORMAL OPERATION.

DAC 3 SET TO 0.

NOTE: X = DON'T CARE

(

)

Figure 9. Returning to Normal Operation from Power-Down

12 ______________________________________________________________________________________

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

0/MAX521

0 OR AD2

AD1 AD0 0

(RST)

1

(a)

SDA

0

1

0

1

0

X

X X

ADDRESS BYTE

ACK

COMMAND BYTE

ACK

STOP

START

CONDITION

ALL INPUT LATCHES

SET TO 0

(

)

ALL OUTPUTS

SET TO 0

(

)

0 OR AD2

AD1 AD0 0

(b)

SDA

(RST)

1

0

1

0

1

0

X

ACK

ADDITIONAL

COMMAND BYTE/

"DUMMY"

OUTPUT BYTE

ADDRESS BYTE

ACK

COMMAND BYTE

ACK

STOP

CONDITION

START

CONDITION

OUTPUT BYTE PAIRS

ALL INPUT LATCHES

SET TO 0

ALL DAC OUTPUTS SET TO 0 UNLESS

CHANGED BY ADDITIONAL COMMAND

BYTE/OUTPUT BYTE PAIRS

(

)

NOTE: X = DON'T CARE

(

)

Figure 10. Resetting DAC Outputs

Setting the RST bit high clears all DAC input latches.

The DAC outputs remain unchanged until a STOP con-

dition is detected (Figure 10a). If a reset is issued, the

following output byte is ignored. Subsequent pairs of

c omma nd /outp ut b yte s ove rwrite the inp ut la tc he s

(Figure 10b).

2

µC

E PROM

XICOR

X24C04

SDA SCL

All changes made during a transmission affect the

MAX520/MAX521’s outputs only when the transmission

ends and a STOP has been recognized. The R0, R1,

and R2 bits are reserved bits that must be set to zero.

SCL

SDA

QUAD

DAC

2

I C Co m p a t ib ilit y

The MAX520/MAX521 are fully compatible with existing

I C systems. SCL and SDA are high-impedance inputs;

MAX520

2

SCL

SDA has an open drain which pulls the data line low

during the 9th clock pulse. Figure 11 shows a typical

I C application.

SDA

AD0

AD1

AD2

2

Additional START Conditions

It is possible to interrupt a transmission to a MAX520/

MAX521 with a new START (repeated start) condition

(perhaps addressing another device), which leaves the

input latches with data that has not been transferred to

the outp ut la tc he s (Fig ure 12). Only the c urre ntly

addressed device will recognize a STOP condition and

transfer data to its output latches. If the device is left

with data in its input latches, the data can be trans-

ferred to the output latches the next time the device is

addressed, as long as it receives at least one com-

mand byte and a STOP condition.

OCTAL

DAC

+5V

MAX521

SCL

SDA

AD0

AD1

Figure 11. Typical I²C Application Circuit

______________________________________________________________________________________ 13

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

SDA

START

ADDRESS BYTE

(DEVICE 0)

ACK

COMMAND BYTE

ADDRESSING DAC1

ACK

OUTPUT BYTE

(FULL SCALE)

ACK

ADDRESS BYTE

(DEVICE 1)

ACK

CONDITION

DEVICE 0's

DAC1 INPUT LATCH

SET TO FULL SCALE

REPEATED START

CONDITION

(

)

0

1

0

1

0

SDA

ACK

OUTPUT BYTE

(FULL SCALE)

ACK

COMMAND BYTE

(ADDRESSING DAC2)

STOP

CONDITION

DEVICE 1's

DAC2 INPUT LATCH ONLY DEVICE 1's DAC2 OUTPUT LATCH SET TO FULL

(

)

SET TO FULL SCALE

(

SCALE. DEVICE 0's OUTPUT LATCHES UNCHANGED.

)

0/MAX521

Figure 12. Repeated START Conditions

0 OR AD2

(RST) (PD)

0 1 1 0

(a)

SDA

0

1

AD1 AD0 0

0

INTERRUPTED

COMMAND BYTE

ADDRESS BYTE

ACK

EARLY

MAX520/MAX521's STATES

START

STOP CONDITION REMAIN UNCHANGED

(

CONDITION

)

0 OR AD2

AD1 AD0 0

(b)

SDA

(PD)

0 RST 1

0

1

0

1

0

1

0

INTERRUPTED

OUTPUT BYTE

ADDRESS BYTE

ACK

COMMAND BYTE

(POWER DOWN)

ACK

MAX520/MAX521 POWER DOWN;

INPUT LATCHES UNCHANGED IF

RST = 0, DAC OUTPUTS RESET IF

RST = 1.

START

CONDITION

EARLY

STOP CONDITION

(

)

Figure 13. Early STOP Conditions

Early Stop Conditions

words into equivalent analog output voltages in propor-

tion to the a p p lie d re fe re nc e volta g e s . For b oth

devices, DAC0–DAC3 each have separate reference

inputs, while the MAX521’s DAC4–DAC7 all share a

common reference input. Figure 14 shows a simplified

diagram of one DAC.

The addressed device recognizes a STOP condition at

any point in a transmission. If the STOP occurs during a

command byte, all previous uninterrupted command

and output byte pairs are accepted, the interrupted

command byte is ignored, and the transmission ends

(Figure 13a). If the STOP occurs during an output byte,

all previous uninterrupted command and output byte

pairs are accepted, the final command byte’s PD and

RST bits are accepted, the interrupted output byte is

ignored, and the transmission ends (Figure 13b).

Reference Inputs

The MAX520/MAX521 can be used for multiplying appli-

cations. The reference accepts a 0V to V

voltage,

DD

both DC and AC signals. The voltage at each REF input

s e ts the full-s c a le outp ut volta g e for its re s p e c tive

DAC(s). The reference voltage must be positive. The

DAC’s input impedance is code dependent, with the

lowest value occurring when the input code is 55 hex or

0101 0101, and the maximum value occurring when the

input code is 00 hex. Since the REF input resistance

An a lo g S e c t io n

DAC Operation

The MAX520 contains four matched voltage-output

DACs, and the MAX521 contains eight. The DACs are

inverted R-2R ladder networks that convert 8-bit digital

14 ______________________________________________________________________________________

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

0/MAX521

MAX5 2 0 Un b u ffe re d DAC Ou t p u t s

The unbuffered DAC outputs (OUT0–OUT3) connect

directly to the internal 16kΩ R-2R network. The outputs

swing from 0V to V

.

DD

The MAX520 has no output buffer amplifiers, giving it

very low supply current. The output-offset voltage is

lower without the output buffer, and the output can also

slew and settle faster if capacitive loading is minimized.

Resistive loading should be very light for highest accu-

racy. Any output loading generates some gain error,

increasing full-scale error. The R-2R ladder’s output

resistance is 16kΩ, so a 1µA output current creates a

16mV error. Linearity is not affected because the ladder

output resistance does not change with DAC code.

Ladder-resistance changes with temperature are also

very small.

OUT_

(MAX521)

R

OUT_

(MAX520)

2R

D0

2R

D5

2R

D6

2R

D7

REF_

AGND

DACs a re ofte n us e d in trimming a p p lic a tions to

replace hardware potentiometers. Figure 15a shows a

typical application, which requires a buffered output so

that a precise current can be injected into the summing

SHOWN FOR ALL 1s ON DAC

Figure 14. DAC Simplified Circuit Diagram

node through precision resistor R . For this application,

the MAX520A features a precise ±1% (T = +25°C,

A

(R ) is code dependent, it must be driven by a circuit

IN

T

with low output impedance (no more than R ÷ 2000) to

IN

±2.5% over temperature) factory-trimmed output resis-

tance. Because the MAX520A’s output resistance is

p re c is e ly trimme d , the re is no ne e d for a n inte rna l

buffer or external precision resistor (Figure 15b). For

applications where the output resistance value is not

critical, use the MAX520B.

maintain output linearity. The REF input capacitance is

also code dependent, with the maximum value occur-

ring at code FF hex (typically 30pF for the MAX520/

MAX521’s REF0–REF3, and 120pF for the MAX521’s

REF4). The output voltage for any DAC can be repre-

sented by a digitally programmable voltage source as:

V

= (N x V ) / 256, where N is the numerical value

OUT

REF

All DACs exhibit output glitches during code transitions.

An output filter is sometimes used to reduce these

glitches in sensitive applications. The MAX520 simpli-

fies output filtering because its internal resistive ladder

network serves as the “R” in an RC filter. Simply con-

nect a small capacitor from the DAC output to ground.

See the Typical Operating Characteristics for oscillo-

scope photos of the worst-case 1LSB step change both

without and with 25pF of capacitance on the MAX520’s

output.

of the DAC’s binary input code. Table 1 shows the

unipolar code.

Table 1. Unipolar Code Table

DAC CONTENTS

ANALOG OUTPUT

255

+ V_REF(———)

256

11111111

129

+ V_REF(———)

256

10000001

10000000

01111111

MAX5 2 1 Ou t p u t Bu ffe r Am p lifie rs

The MAX521 voltage outputs (OUT0–OUT7) are inter-

nally buffered precision unity-gain followers that slew

128

+ V_REF(———) = ——

256

V

REF

2

up to 1V/µs. The outputs can swing from 0V to V

.

DD

127

With a 0V to 4V (or 4V to 0V) output transition, the

amplifier outputs typically settle to 1/2LSB in 6µs when

loaded with 10kΩ in parallel with 100pF. The buffer

amplifiers are stable with any combination of resistive

loads ≥2kΩ and capacitive loads ≤300pF.

+ V_REF(———)

256

1

+ V_REF(———)

256

00000001

00000000

0V

______________________________________________________________________________________ 15

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

R

F

R

F

R

IN

R

IN

R

T

16kΩ

DAC

(1%)

MAX520A

0/MAX521

Figure 15a. Typical Trimming Circuit

Figure 15b. MAX520A Trimming Circuit

__________Ap p lic a t io n s In fo rm a t io n

SYSTEM GND

S h u t d o w n Mo d e

In shutdown mode, the MAX520/MAX521 reference

inputs are disconnected from the R-2R ladder inputs,

which saves power when the reference is not powered

down. In addition, the MAX521’s output buffers are dis-

a b le d , g re a tly re d uc ing the s up p ly c urre nt. The

MAX520’s operating supply current does not change in

shutdown mode. The Command Byte and Output Byte

s e c tion d e s c rib e s how to e nte r a nd e xit s hutd own

mode.

PIN1

OUT2

OUT1

OUT0

REF1

REF0

OUT3

REF2

REF3

P o w e r-S u p p ly Byp a s s in g a n d

Gro u n d Ma n a g e m e n t

Bypass V with a 0.1µF capacitor, located as close to

DD

V

DD

a nd DGND a s p os s ib le . The a na log g round

(AGND) and digital ground (DGND) pins should be

connected in a “star” configuration to the highest quali-

ty ground available, which should be located as close

to the MAX521 as possible.

Figure 16. PC Board Layout for Minimizing Crosstalk (MAX521

bottom view, DIP package)

Careful PC board layout minimizes crosstalk among

DAC outp uts , re fe re nc e inp uts , a nd d ig ita l inp uts .

Figure 16 shows the suggested PC board layout to mini-

mize crosstalk.

16 ______________________________________________________________________________________

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

0/MAX521

___________________________________________________P in Co n fig u ra t io n s (c o n t in u e d )

TOP VIEW

OUT1

OUT0

REF1

REF0

DGND

AGND

N.C.

OUT2

OUT3

REF2

REF3

N.C.

OUT1

OUT0

REF1

N.C.

1

2

OUT2

OUT3

REF2

REF3

REF4

24

23

22

21

20

19

18

17

16

15

14

OUT2

OUT3

REF2

N.C.

OUT1

OUT0

REF1

REF0

1

2

1

2

20

19

18

17

16

15

14

13

12

11

20

19

18

17

16

15

14

13

12

11

3

4

MAX521

MAX520

REF0

AGND

N.C.

5

DGND

AGND

SCL

REF3

5

REF4

6

V

DD

V

DD

6

V

DD

7

AD1

N.C.

AD2

AD1

AD0

7

SCL

AD1

N.C.

AD0

OUT7

DGND

8

SDA

AD0

8

N.C.

SDA

SCL

SDA

OUT4

OUT5

9

OUT7

OUT6

9

10

11

12

10

OUT4

OUT5

DIP

SSOP

13 OUT6

SO/SSOP

________________________________________________Fu n c t io n a l Dia g ra m s (c o n t in u e d )

SDA SCL

REF2 REF1 REF0

OUT0

OUT1

OUT2

8

INPUT

LATCH 0

OUTPUT

LATCH 0

DAC0

DAC1

DAC2

MAX521

1

INPUT

LATCH 1

OUTPUT

LATCH 1

8-BIT

SHIFT REGISTER

1

INPUT

LATCH 2

OUTPUT

LATCH 2

ADDRESS

COMPARATOR

1

START/STOP

DETECTOR

OUT3

8

INPUT

LATCH 3

OUTPUT

LATCH 3

DAC3

1

OUT4

OUT5

OUT6

OUT7

8

INPUT

OUTPUT

LATCH 4

DAC4

DAC5

DAC6

DAC7

DECODE

8

LATCH 4

1

8

INPUT

OUTPUT

LATCH 5

1

INPUT

OUTPUT

LATCH 6

1

INPUT

OUTPUT

LATCH 7

AD0

AD1

REF3 REF4

______________________________________________________________________________________ 17

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

__Ord e rin g In fo rm a t io n (c o n t in u e d )

_________________Ch ip To p o g ra p h ie s

TUE

(LSB)

MAX520

PART^†

TEMP. RANGE PIN-PACKAGE

AGND

REF0

DGND

MAX520ACAP

MAX520BCAP

MAX520AC/D

MAX520BC/D

MAX520AEPE

MAX520BEPE

0°C to +70°C

-40°C to +85°C

20 SSOP

1

2

1

2

1

2

1

2

1

2

1

2

20 SSOP

REF1

OUT0

Dice*

SCLK

Dice*

SDATA

16 Plastic DIP

16 Wide SO

20 SSOP

MAX520AEWE -40°C to +85°C

MAX520BEWE -40°C to +85°C

OUT1

0. 121"

(3. 073mm)

OUT2

MAX520AEAP

MAX520BEAP

MAX520AMJE

MAX520BMJE

MAX521ACPP

MAX521BCPP

MAX521ACWG

MAX521BCWG

MAX521ACAG

MAX521BCAG

MAX521BC/D

MAX521AEPP

MAX521BEPP

-40°C to +85°C

AD0

20 SSOP

0/MAX521

-55°C to +125°C 16 CERDIP

AD1

AD2

OUT3

REF2

0°C to +70°C

-40°C to +85°C

20 Plastic DIP

24 Wide SO

24 SSOP

REF3

OUT3

V

DD

0. 098"

(2. 489mm)

24 SSOP

MAX521

Dice*

OUT0

OUT2

REF2

REF1

OUT1

20 Plastic DIP

24 Wide SO

24 SSOP

REF0

REF3

MAX521AEWG -40°C to +85°C

MAX521BEWG -40°C to +85°C

MAX521AEAG

MAX521BEAG

MAX521BMJP

-40°C to +85°C

DGND

AGND

24 SSOP

-55°C to +125°C 20 CERDIP

* Dice are specified at T = +25°C, DC parameters only.

A

†

MAX520 “A” grade parts include a 1%-accurate, factory-trimmed

output resistance.

0. 212"

(5. 385mm)

REF4

AGND

SCL

V

DD

AD1

SDA

AD0

OUT4 OUT5 OUT6 OUT7

0. 125"

(3. 175mm)

TRANSISTOR COUNT: 4518

SUBSTRATE CONNECTED TO V

DD

18 ______________________________________________________________________________________

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

0/MAX521

________________________________________________________P a c k a g e In fo rm a t io n

INCHES

MILLIMETERS

DIM

E

MIN

MAX

0.200

–

MIN

–

MAX

5.08

–

A

–

E1

D

A1 0.015

A2 0.125

A3 0.055

0.38

3.18

1.40

0.41

1.14

0.20

0.13

7.62

6.10

2.54

7.62

–

0.175

0.080

0.022

0.065

0.012

0.080

0.325

0.310

–

4.45

2.03

0.56

1.65

0.30

2.03

8.26

7.87

–

A3

A2

A1

A

L

B

0.016

B1 0.045

0.008

D1 0.005

0.300

E1 0.240

0.100

eA 0.300

C

0° - 15°

E

C

e

B1

eA

eB

–

B

eB

L

–

0.400

0.150

10.16

3.81

0.115

2.92

D1

INCHES

MILLIMETERS

PKG. DIM

PINS

Plastic DIP

PLASTIC

DUAL-IN-LINE

PACKAGE

(0.300 in.)

MIN

MAX MIN

MAX

8

P

N

D

0.348 0.390 8.84

9.91

14

16

18

20

24

0.735 0.765 18.67 19.43

0.745 0.765 18.92 19.43

0.885 0.915 22.48 23.24

1.015 1.045 25.78 26.54

1.14 1.265 28.96 32.13

21-0043A

INCHES

MILLIMETERS

DIM

MIN

0.093

MAX

0.104

0.012

0.019

0.013

0.299

MIN

2.35

0.10

0.35

0.23

7.40

MAX

2.65

0.30

0.49

0.32

7.60

D

A

A1 0.004

0°- 8°

B

C

E

e

0.014

0.009

0.291

A

0.101mm

0.004in.

1.27

0.050

e

B

A1

H

L

0.394

0.016

0.419

0.050

10.00

0.40

10.65

1.27

C

L

INCHES

MILLIMETERS

MAX

PINS

DIM

MIN MAX MIN

E

H

Wide SO

SMALL-OUTLINE

PACKAGE

0.398 0.413 10.10 10.50

0.447 0.463 11.35 11.75

0.496 0.512 12.60 13.00

0.598 0.614 15.20 15.60

D

16

18

20

24

28

(0.300 in.)

0.697 0.713 17.70 18.10

21-0042A

______________________________________________________________________________________ 19

Qu a d /Oc t a l, 2 -Wire S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

___________________________________________P a c k a g e In fo rm a t io n (c o n t in u e d )

INCHES

MILLIMETERS

DIM

MIN

0.068

MAX

0.078

0.008

0.015

0.008

MIN

1.73

0.05

0.25

0.09

MAX

1.99

0.21

0.38

0.20

A

A1 0.002

B

C

D

E

e

0.010

0.004

SEE VARIATIONS

α

0.205

0.209

5.20

5.38

E

H

0.0256 BSC

0.65 BSC

H

L

0.301

0.311

0.037

8˚

7.65

0.63

0˚

7.90

0.95

8˚

0.025

0˚

C

α

L

INCHES

MILLIMETERS

0/MAX521

DIM PINS

MAX

6.33

MIN MAX MIN

0.239 0.249 6.07

0.278 0.289 7.07

0.317 0.328 8.07

0.397 0.407 10.07

e

D

14

16

20

24

28

6.33

SSOP

SHRINK

SMALL-OUTLINE

PACKAGE

7.33

A

8.33

10.33

21-0056A

B

A1

D

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

20 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX521
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs 四/八通道， 2线串行8位DAC，具有轨至轨输出
文件：	总20页 (文件大小：275K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX521 [MAXIM]

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