MAX532AMJE/883B [MAXIM]
D/A Converter, 2 Func, Serial Input Loading, 2.5us Settling Time, CDIP16, 0.300 INCH, CERDIP-16;
| 型号： | MAX532AMJE/883B |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 2 Func, Serial Input Loading, 2.5us Settling Time, CDIP16, 0.300 INCH, CERDIP-16 CD 转换器 |
| 文件： | 总16页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0046; Rev. 1; 3/94
Du a l, S e ria l-In p u t ,
Vo lt a g e -Ou t p u t , 1 2 -Bit MDAC
MAX532
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
The MAX532 is a complete, dual, serial-input, 12-bit
multiplying digital-to-analog converter (MDAC) with out-
put amplifiers. No external user trims are required to
achieve full specified performance. The MAX532’s 3-
wire serial interface minimizes the number of package
pins, so it uses less board space than parallel-interface
parts. The interface is SPI™, QSPI™ and Microwire™
compatible. A serial output, DOUT, allows cascading
of two or more MAX532s and read-back of the data
written to the device.
♦ Two 12-Bit MDACs with Output Amplifiers
♦ Fast, 6MHz 3-Wire Interface
♦ SPI, QSPI, and Microwire Compatible
♦ ±12V Output Swing
♦ ±10mA Output Current
♦ 2.5µs Settling Time to ±1/2LSB
♦ Guaranteed Monotonic Over Temperature
♦ Low Integral Nonlinearity: ±1/2LSB Max
♦ Low Gain Tempco: 2ppm/°C
♦ Operates from ±12V to ±15V Supplies
♦ Power-On Reset
The device’s serial interface minimizes digital-noise
feedthrough from its logic pins to its analog outputs.
Serial interfacing also simplifies opto-coupler-isolated
or transformer-isolated applications.
The MAX532 is specified with ±12V to ±15V power sup-
plies. All logic inputs are TTL and CMOS compatible. It
comes in space-saving 16-pin DIP and wide SO packages.
♦ Available in 16-Pin DIP and Wide SO Packages
________________________Ap p lic a t io n s
Automatic Test Equipment
______________Ord e rin g In fo rm a t io n
Arbitrary Waveform Generators
Programmable-Gain Amplifiers
Motion Control Systems
ERROR
PART
TEMP. RANGE PIN-PACKAGE
(LSBs)
±1/2
±1
MAX532ACPE
MAX532BCPE
MAX532ACWE
MAX532BCWE
MAX532BC/D
0°C to +70°C 16 Plastic DIP
0°C to +70°C 16 Plastic DIP
0°C to +70°C 16 Wide SO
0°C to +70°C 16 Wide SO
0°C to +70°C Dice*
Servo Controls
±1/2
±1
±1
________________Fu n c t io n a l Dia g ra m
Ordering Information continued on last page.
* Contact factory for dice specifications.
V
DD
__________________P in Co n fig u ra t io n
MAX532
DACA
LATCH
RFBA
TOP VIEW
VREFA
DIN
DACA
VOUTA
AGNDA
RFBA
VREFA
VOUTA
AGNDA
V
1
2
3
4
5
6
7
8
DD
16
15
14
13
12
11
10
9
LDAC
CS
24-BIT SHIFT
REGISTER
DOUT
SCLK
MAX532
DIN
RFBB
CS
AGNDB
VOUTB
VREFB
RFBB
DOUT
SCLK
DGND
DACB
VOUTB
AGNDB
LDAC
DACB
LATCH
VREFB
V
SS
V
DGND
DIP/Wide SO
SS
™Microwire is a trademark of National Semiconductor Corp. SPI and QSPI are trademarks of Motorola, Inc.
________________________________________________________________ Maxim Integrated Products
1
Ca ll t o ll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 fo r fre e s a m p le s o r lit e ra t u re .
Du a l, S e ria l-In p u t ,
Vo lt a g e -Ou t p u t , 1 2 -Bit MDAC
ABSOLUTE MAXIMUM RATINGS
Pin Voltages
Operating Temperature Ranges:
V
to DGND, AGNDA, AGNDB........................-0.3V to +17V
to DGND, AGNDA, AGNDB (Note 1) ..........+0.3V to -17V
MAX532_C__ ......................................................0°C to +70°C
MAX532_E__....................................................-40°C to +85°C
MAX532_MJE ................................................-55°C to +125°C
Junction Temperatures:
DD
V
SS
VREFA, VREFB.............................(V - 0.3V) to (V + 0.3V)
AGNDA, AGNDB.....................(DGND - 0.3V) to (V + 0.3V)
SS
DD
DD
VOUTA, VOUTB ...........................(V - 0.3V) to (V + 0.3V)
MAX532_C__, E__........................................................+150°C
MAX532_MJE...............................................................+175°C
Storage Temperature Range ........................... -65°C to +160°C
Lead Temperature (soldering, 10sec) ........................... +300°C
SS
DD
RFBA, RFBB.................................(V - 0.3V) to (V + 0.3V)
SS
DD
MAX532
SCLK, DIN, DOUT, LDAC, CS ..(DGND - 0.3V) to (V + 0.3V)
DD
DOUT Sink Current .............................................................20mA
Continuous Power Dissipation (T = +70°C)
A
Plastic DIP (derate 10.53mW/°C above +70°C) ..........842mW
Wide SO (derate 9.52mW/°C above +70°C)................762mW
CERDIP (derate 10.00mW/°C above +70°C)...............800mW
Note 1: If V is open-circuited with V and either AGND applied, the V pin will float positive, exceeding the Absolute Maximum Ratings.
SS
DD
SS
A Schottky diode connected between V and GND ensures the maximum ratings will not be exceeded.
SS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 11.4V to 16.5V, V = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, R = 2kΩ,
SS
L
C
= 100pF, VOUT_ connected to RFB_, TA = TMIN to TMAX, unless otherwise noted.)
L
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE (Note 1)
Resolution
12
Bits
LSB
LSB
MAX532A
MAX532B
±1/2
±1
Relative Accuracy
INL
Differential Nonlinearity
Guaranteed monotonic
±1
T
= +25°C, MAX532_
±2
A
DAC latch loaded
with all 0s
T
A
= T
to T
, MAX532A
, MAX532B
Zero-Code Offset Error
±3
mV
MIN
MAX
T
A
= T
to T
±4
MIN MAX
Zero-Code Offset
Temperature Coefficient
DAC latch loaded with all 0s
±5
µV/°C
MAX532A
MAX532B
MAX532A
MAX532B
±2
±5
±4
±7
T
= +25°C, DAC latch
A
loaded with all 1s
= T to T , DAC
MAX
Gain Error
LSB
T
A
MIN
latch loaded with all 1s
Gain-Error Temperature
Coefficient
ppm/°C
of FSR
±2
REFERENCE INPUTS (VREFA, VREFB)
VREFA, VREFB Input
Resistance
8
10
13
kΩ
VREFA, VREFB Input
Resistance Matching
±0.5
±3.0
%
2
_______________________________________________________________________________________
Du a l, S e ria l-In p u t ,
Vo lt a g e -Ou t p u t , 1 2 -Bit MDAC
MAX532
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 11.4V to 16.5V, V = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, R = 2kΩ, C = 100pF,
SS
L
L
VOUT_ connected to RFB_, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SCLK, DIN, LDAC, CS)
V
Input High Voltage
Input Low Voltage
Input Current
2.4
V
V
INH
V
INL
0.8
±1
8
Digital inputs at 0V or V
µA
pF
DD
Input Capacitance (Note 2)
DIGITAL OUTPUT (DOUT) (Note 3)
I
= 5mA
0.08
0.2
0.4
±10
15
SINK
V
Output Voltage Low
Output High Leakage
V
OL
I
= 16mA
= 0V to V
DD
SINK
I
V
DOUT
µA
LKG
Output High Capacitance
(Note 2)
C
pF
OUT
ANALOG OUTPUTS (VOUTA, VOUTB)
DC Output Impedance
0.2
20
Ω
Short-Circuit Current
VOUTA, VOUTB connected to AGNDA, AGNDB
mA
(V - 2.5)
DD
to
Output Voltage Swing
V
(V + 2.5)
SS
POWER REQUIREMENTS
V
Positive Supply Voltage
Negative Supply Voltage
11.4
16.5
V
V
DD
V
SS
-11.4
-16.5
∆Full scale/∆V , V = 11.4V to 16.5V, VREF = -8.9V,
DAC latches loaded with all 1s
DD DD
±0.035
±0.035
Power-Supply Rejection
PSR
LSB/%
∆Full scale/∆V , V = -11.4V to -16.5V, VREF = 8.9V,
SS SS
DAC latches loaded with all 1s
I
Positive Supply Current
Negative Supply Current
AC CHARACTERISTICS
Output unloaded
Output unloaded
5
4
10
6
mA
mA
DD
I
SS
Voltage-Output
Settling Time
Settling time to within 1/2 LSB of final DAC value; DAC
latch alternately loaded with all 0s and all 1s
2.5
8
µs
Slew Rate
V/µs
nV-s
Digital-to-Analog
Glitch Impulse
DAC latch alternately loaded with 011...11 and 100...00
60
VREFA = 20V 10kHz
p-p
VREFA to VOUTB
VREFB to VOUTA
sine wave; DAC latches
loaded with all 0s
-100
-100
Channel-to-Channel
Isolation
dB
VREFB = 20V 10kHz
p-p
sine wave; DAC latches
loaded with all 0s
_______________________________________________________________________________________
3
Du a l, S e ria l-In p u t ,
Vo lt a g e -Ou t p u t , 1 2 -Bit MDAC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 11.4V to 16.5V, V = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, R = 2kΩ, C = 100pF,
SS
L
L
VOUT_ connected to RFB_, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Multiplying Feedthrough
Error
VREF = 20V 10kHz sine wave;
p-p
DAC latch loaded with all 0s
-77
1.0
125
-90
dB
MAX532
Unity-Gain Small-Signal
Bandwidth
VREF = 100mV sine wave;
p-p
DAC latch loaded with all 1s
MHz
kHz
dB
VREF = 20V sine wave;
p-p
DAC latch loaded with all 1s
Full-Power Bandwidth
VREF = 6V
, 1kHz sine wave;
RMS
Total Harmonic Distortion
THD
DAC latch loaded with all 1s
Digital Feedthrough
Digital Crosstalk
CS = 1; transitions on SCLK, LDAC, DIN
DACA code all 1s, DACB code transition from all 0s to all 1s
0.1Hz to 10Hz
1.1
10
2
nV-s
nV-s
µV
RMS
Output Noise Voltage
Note 1: Static performance tested at V = +15V, V = -15V. Performance over supplies guaranteed by PSR test.
DD
SS
Note 2: Guaranteed by design. Not subject to production testing.
Note 3: Open-drain output.
TIMING CHARACTERISTICS
(VDD = 11.4V to 16.5V, V = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V) (Notes 4, 5)
SS
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
SCLK Clock Frequency
6.25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
t
SCLK Pulse Width High
80
80
50
0
CH
t
SCLK Pulse Width Low
CL
t
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
CS Fall to SCLK Rise Setup Time
CS Rise to SCLK Rise Setup Time
SCLK Fall to CS Fall Hold Time
SCLK Rise to CS Rise Hold Time
CS Pulse Width High
DS
t
DH
t
50
50
5
CSS0
t
CSS1
t
CSH0
t
80
120
0
CSH1
t
CSW
t
C
C
C
= 20pF, R
= 20pF, R
= 20pF, R
= 1kΩ to 5V
SCLK Fall to DOUT Valid (Note 6)
CS Fall to DOUT Enable (Note 7)
CS Rise to DOUT Disable (Note 7)
LDAC Pulse Width Low
200
100
60
DO
L
L
L
PULL-UP
PULL-UP
PULL-UP
t
= 1kΩ to 5V
= 1kΩ to 5V
DV
t
TR
t
60
LDAC
t
CS Rise to LDAC Fall Setup Time
100
LDACS
Note 4: All input signals are specified with t = t ≤ 5ns. Logic input swing is 0V to 5V.
R
F
Note 5: See Figure 1.
Note 6: Timing is for SCLK fall to DOUT fall to 0.8V, or for SCLK fall to DOUT rise to 2.4V. Additional time must be added for any
larger passive RC pull-up delay.
Note 7: DOUT enable: DOUT falls to 4.5V from 5.0V. DOUT disable: DOUT rises to 0.5V from 0V.
4
_______________________________________________________________________________________
Du a l, S e ria l-In p u t ,
Vo lt a g e -Ou t p u t , 1 2 -Bit MDAC
MAX532
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = 15V, V = -15V, R = 2kΩ, C = 100pF, unless otherwise noted.)
DD
SS
L
L
OUTPUT VOLTAGE SWING
vs. RESISTIVE LOAD
NOISE SPECTRAL DENSITY
LARGE-SIGNAL FREQUENCY RESPONSE
25
5
0
VREF = 20V at 1kHz
VREF = 0V
DAC CODE = 11...111
GAIN = -1
p-p
300
200
100
20
15
10
5
-5
-10
-15
VREF = 20Vp-p
DAC CODE = 11...111
GAIN = -1
-20
-25
-30
-35
-40
0
0
10
100
1k
10k
100k
10
100
1k
10k
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
LOAD RESISTANCE (Ω)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (BANDWIDTH = 80kHz)
SMALL-SIGNAL FREQUENCY RESPONSE
MULTIPLYING FEEDTHROUGH ERROR
5
-94
-35
-40
-45
-50
-55
VREF = 6V
RMS
DAC CODE = 111...111
VREFA = 20V
p-p
VREFB = AGNDB
DAC CODE = 00...00
-96
-98
0
-5
VREF = 100mV
p-p
DAC CODE = 11...111
-100
-102
-104
-106
-10
-15
-60
-65
-70
-75
-80
-85
-20
-25
100
1k
10k
100k
1M
10M
100
1k
10k
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (BANDWIDTH > 500kHz)
-60
-65
-70
-75
-80
-85
-90
-95
-100
VREF = 6V
RMS
DAC CODE = 111...111
100
1k
10k
100k
FREQUENCY (Hz)
_________________________________________________________________________________________________
5
Du a l, S e ria l-In p u t ,
Vo lt a g e -Ou t p u t , 1 2 -Bit MDAC
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = 15V, V = -15V, R = 2kΩ, C = 100pF, unless otherwise noted.)
DD
SS
L
L
SMALL-SIGNAL PULSE RESPONSE
LARGE-SIGNAL PULSE RESPONSE
MAX532
AGNDA
A
AGNDA
A
A = V , 50mV/div
OUTA
A = VOUTA, 5V/div
TIMEBASE = 2µs/div
= ±100mV SQUARE WAVE
TIMEBASE = 2µs/div
VREFA = ±10V SQUARE WAVE
V
REFA
______________________________________________________________P in De s c rip t io n
PIN
1
NAME
RFBA
FUNCTION
Feedback Resistor for DACA
Reference Input for DACA
Voltage Output for DACA
Analog Ground for DACA
Analog Ground for DACB
Voltage Output for DACB
Reference Input for DACB
Feedback Resistor for DACB
Negative Supply Voltage
Digital Ground
2
VREFA
VOUTA
AGNDA
AGNDB
VOUTB
VREFB
RFBB
3
4
5
6
7
8
V
SS
9
10
11
DGND
SCLK
Serial Clock Input
Serial Data Output. Open-drain N-channel MOSFET output: requires external pull-up resis-
tor. Data on DOUT changes on the falling edge of SCLK. Serial output data is delayed 24
clock cycles from DIN.
12
DOUT
Serial Data Input. CMOS- and TTL-compatible input. Data is clocked into DIN on the rising
edge of SCLK. CS must be low for data to be clocked in.
13
14
DIN
CS
Chip-Select Input, active low. Data is shifted in and out when CS is low. DAC latches are
updated when CS is high and LDAC is low.
Asynchronous Load DAC Input, active low. DAC latches are updated when CS is high and
LDAC is low.
15
16
LDAC
V
DD
Positive Supply Voltage
6
_______________________________________________________________________________________
Du a l, S e ria l-In p u t ,
Vo lt a g e -Ou t p u t , 1 2 -Bit MDAC
MAX532
____________________________________________________________Tim in g Dia g ra m s
t
CSW
t
t
CSH1
LDACS
CS
t
CSHO
t
CSS1
t
t
CH
t
CL
CSSO
SCLK
t
DS
t
DH
D0
D1
Q1
D23
DIN
t
DV
t
D0
t
TR
Q0
Q23
D0
DOUT
LDAC
t
LDAC
DACS
UPDATED
Figure 1. Timing Diagram
_______________________________________________________________________________________
7
Du a l, S e ria l-In p u t ,
Vo lt a g e -Ou t p u t , 1 2 -Bit MDAC
_______________________________________________Tim in g Dia g ra m s (c o n t in u e d )
CS
DACS
MAX532
UPDATED
SCLK
DIN
D23
D16
D15 D14 D13 D12 D11..........
LSB DACB MSB DACA
............................................
D1 D0
Q1 Q0
MSB DACB
LSB DACA
D23
DOUT
Q23 Q22
Q16 Q15 Q14 Q13 Q12 Q11..........
D23
.....................................
MSB DACA FROM
PREVIOUS WRITE
MSB DACB FROM
PREVIOUS WRITE
Figure 2. 3-Wire Interface Timing Diagram (LDAC = DGND)
CS
SCLK
DIN
D23
D16
Q16
D15 D14 D13 D12 D11..........
LSB DACB MSB DACA
............................................
D1 D0
MSB DACB
LSB DACA
DOUT
LDAC
Q23 Q22
Q15 Q14 Q13 Q12 Q11..........
MSB DACA FROM
PREVIOUS WRITE
Q1 Q0
D23
D23
...................................
MSB DACB FROM
PREVIOUS WRITE
DACS
UPDATED
Figure 3. 4-Wire Inferface Timing Diagam
8
_______________________________________________________________________________________
Du a l, S e ria l-In p u t ,
Vo lt a g e -Ou t p u t , 1 2 -Bit MDAC
MAX532
5V
5V
1k
1k
SS
SCLK
SK
DOUT
MISO
DIN
SO
SI
DIN
MOSI
SCK
MAX532
MAX532
MICROWIRE
PORT
SPI
PORT
DOUT
SCLK
CS
I/O
I/O
CS
I/O
I/O
LDAC
LDAC
CPOL = 0, CPHA = 0
THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE
MAX532, BUT MAY BE USED FOR READ-BACK PURPOSES.
THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX532,
BUT MAY BE USED FOR READ-BACK PURPOSES.
Figure 4. Connections for Microwire
Figure 5. Connections for SPI
the device’s 24-bit shift register. The data at DOUT is
delayed 24 clock cycles from the data at DIN (see
Figures 2 and 3, and the Functional Diagram). DOUT
is an open-drain N-channel MOSFET that requires an
external pull-up resistor (typically 1kΩ if pulled up to
+5V, and 3kΩ if pulled up to +12V or +15V). Logic lev-
els are guaranteed with sink currents up to 5mA (see
Electrical Characteristics). Output data changes on the
falling edge of SCLK when CS is low. If CS is high,
DOUT is three-state (high-impedance).
_______________De t a ile d De s c rip t io n
Dig it a l In t e rfa c e
The MAX532 is Microwire and SPI compatible (Figures
4 and 5). Both DACs are programmed by writing three
8-bit words (see Figures 2 and 3, and the Functional
Diagram). Serial data is clocked into the data registers
MSB first, with DACB information preceding DACA
information. Data is clocked in on the rising edge of
SCLK while CS is low. With CS high, data can not be
clocked into DIN, and DOUT is high impedance. SCLK
can be driven at rates up to 6.25MHz.
Da is y-Ch a in in g De vic e s
Any number of MAX532s can be daisy-chained by con-
necting the DOUT pin of one device (with a pull-up
resistor) to the DIN pin of the following device in the
chain (Figure 6).
The MAX532 uses either a 3-wire or a 4-wire serial
interface. Three wires may be used (CS, DIN, SCLK)
b y tying LDAC low. With LDAC low, the DACs a re
up d a te d s imulta ne ous ly whe n CS g oe s hig h (s e e
Figure 2 and the Functional Diagram). The 3-wire inter-
face may be used if the MAX532 is used alone, or if two
or more MAX532s are cascaded (DOUT of one device
tied to DIN of the other) (Figure 6).
When daisy-chaining devices, t
(CS low to SCLK
CSS0
high), must be the greater of t + t or t + (t + t
DV
DS
DS
RC
TR
- t ), where t
is the CS pulse width used in the sys-
CS
CSW
tem and the term (t + t - t
) accounts for the time
RC
TR CSW
spent charging the DOUT capacitance with the external
pull-up resistor. So, for t < 250ns, t is simply t
The 4-wire interface (LDAC, CS, DIN, SCLK) is required
if several serial devices are tied to the same data line,
a nd it is d e s ira b le to up d a te the m s imulta ne ous ly
(Figure 7). With the 4-wire interface, the DACs are
updated when LDAC goes low (see Figure 3 and the
Functional Diagram).
RC
CSS0
DV
+ t . Calculate t using the following equation:
DS
RC
t
= R x C x ln (V
/(V
- 2.4V))
RC
P
PULL-UP PULL-UP
where V
is the voltage that the pull-up resistor
PULL-UP
is connected to, R is the value of the pull-up resistor,
P
A serial output, DOUT, allows cascading of two or more
MAX532s and allows read-back of the data written to
and C is the capacitance at DOUT. Values of t
given in Table 1.
are
RC
_______________________________________________________________________________________
9
Du a l, S e ria l-In p u t ,
Vo lt a g e -Ou t p u t , 1 2 -Bit MDAC
+5V
+5V
+5V
R
1k
R
R
P
P
P
1k
1k
MAX532
MAX532
MAX532
LDAC
SCLK
DIN
CS
SCLK
DIN
CS
SCLK
DIN
CS
SCLK
DIN
CS
MAX532
DOUT
DOUT
DOUT
LDAC
LDAC
TO OTHER
SERIAL DEVICES
MAX532
LDAC
SCLK
DIN
CS
SCLK
DIN
CS
Figure 6. Daisy-chained or individual MAX532s are simultaneously updated by bringing CS high when using the 3-wire interface
(LDAC = DGND).
DIN
SCLK
LDAC
CS1
CS2
CS3
TO OTHER
SERIAL DEVICES
CS
CS
CS
LDAC
SCLK
DIN
LDAC
LDAC
MAX532
MAX532
SCLK
MAX532
SCLK
DIN
DIN
Figure 7. Multiple devices sharing a common DIN line may be simultaneously updated by bringing LDAC low. CS1, CS2, CS3, . . .,
are driven separately, thus controlling which data are written to devices 1, 2, 3, . . . .
10 ______________________________________________________________________________________
Du a l, S e ria l-In p u t ,
Vo lt a g e -Ou t p u t , 1 2 -Bit MDAC
MAX532
Dig it a l-t o -An a lo g S e c t io n
Table 1. t Delay Times
RC
Figure 8 shows a simplified circuit diagram for one of
the DACs and the output amplifier.
V
(V)
C (pF)
20
R
P
(kΩ)
1
t
RC
(ns)
PULL-UP
4.5
15
A s e g me nte d s c he me is us e d to imp rove line a rity,
whereby the two MSBs of the 12-bit data word are
decoded to drive the three switches, SA, SB, and SC.
The remaining ten bits drive the switches S0 through S9
in a standard R-2R ladder configuration.
4.5
35
1
27
38
76
114
14
25
35
71
106
12
21
29
59
88
4.5
50
1
4.5
100
150
20
1
4.5
1
Each of the switches, SA, SB, and SC, steers 1/4 of the
total reference current with the remaining 1/4 passing
through the R-2R section.
11.4
11.4
11.4
11.4
11.4
13.5
13.5
13.5
13.5
13.5
3
35
3
50
3
The output amplifier and feedback resistor perform the
current-to-voltage conversion, giving the following:
100
150
20
3
3
VOUT_ = -D x VREF_,
3
where _ denotes A or B, and D is the fractional representa-
tion of the digital word. (D can be set from 0 to 4095/4096.)
35
3
50
3
100
150
3
+12V to +15V
3
V
DD
RFBA
With the values of t
given in Table 1, t
is always
RC
CSS0
given by t + t
. For different values of R or C, t
DV
DS
RC
must be calculated to determine t
.
CSS0
VREFA
VOUTA
V
IN
DACA
V
OUT
Additionally, the maximum clock frequency is limited to
1
MAX532
DGND
V
SS
AGNDA
f
(max) = ————————————— .
CLK
2 x (t
+ t -15ns + t
)
DO
RC
DS
-12V to -15V
For example, with t
= 15ns (5V ±10% supply with
RC
1kΩ pull-up), the maximum clock frequency is 2MHz.
Figure 9. Unipolar Binary Operation
VREF_
R
R
R
2R
SC
2R
SB
2R
2R
S9
2R
S8
2R
S0
2R
SA
R/2
RFB_
VOUT_
AGND_
SHOWN FOR ALL 1s ON DAC
Figure 8. Simplified D/A Circuit Diagram
______________________________________________________________________________________ 11
Du a l, S e ria l-In p u t ,
Vo lt a g e -Ou t p u t , 1 2 -Bit MDAC
Ou t p u t Am p lifie rs
__________Ap p lic a t io n s In fo rm a t io n
The output amplifiers are stable with any combination
of resistive loads ≥ 2kΩ and capacitive loads ≤ 100pF.
They are internally compensated, and settle to ±0.01%
FSR (1/2LSB) in 2.5µs.
La yo u t , Gro u n d in g , a n d Byp a s s in g
For best system performance, use printed circuit boards
with separate analog and digital ground planes. Wire-
wrap boards are not recommended. The two ground
planes should be tied together at the low-impedance
power-supply source, as shown in Figure 11.
Un ip o la r Co n fig u ra t io n
Figure 9 shows DACA connected for unipolar binary
operation. Similar connections apply for DACB. When
MAX532
The board layout should ensure that digital and analog
signal lines are kept separate from each other as much
as possible. Do not run analog and digital lines parallel
to one another.
V
IN
is an AC signal, the circuit performs two-quadrant
multiplication. Table 2 shows the codes for this circuit.
Bip o la r Op e ra t io n
The output amplifiers are sensitive to high-frequency
Figure 10 shows the MAX532 connected for bipolar
operation. The coding is offset binary, as shown in
noise in the V
and V power supplies. Bypass
DD
SS
these supplies to the analog ground plane with 0.1µF
and 10µF bypass capacitors. Minimize capacitor lead
lengths for best noise rejection.
Table 3. When V is an AC signal, the circuit performs
IN
four-quadrant multiplication. To maintain gain error
specifications, resistors R1, R2, and R3 should be ratio-
matched to 0.01%.
Table 2. Unipolar Code Table
Table 3. Bipolar Code Table
DAC Latch Contents
DAC Latch Contents
Analog Output, V
Analog Output, V
OUT
OUT
MSB
LSB
MSB
LSB
-V x (4095/4096)
+V x (2047/2048)
IN
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0000
IN
-V x (2048/4096) = -1/2V
IN
+V x (1/2048)
IN
IN
-V x (1/4096)
IN
0V
-V x (1/2048)
IN
0V
-V + (2048/2048) = -V
IN
1LSB = V /4096
IN
IN
1LSB = V /2048
IN
R2
20k
ANALOG
SUPPLY
DIGITAL
SUPPLY
R1
20k
V
OUT
+12V to +15V
+15V
-15V
AGND
+5V
DGND
R3
10k
V
DD
RFB_
V
IN
VREF_
VOUT_
DAC_
MAX532
SS
V
V
AGNDA
AGNDB
DGND
+5V
DGND
DD
SS
V
AGND_
DGND
DIGITAL
CIRCUITRY
-12V to -15V
MAX532
Figure 10. Bipolar Operation
Figure 11. Power-Supply Grounding
12 ______________________________________________________________________________________
Du a l, S e ria l-In p u t ,
Vo lt a g e -Ou t p u t , 1 2 -Bit MDAC
MAX532
P ro g ra m m a b le -Ga in Am p lifie r (P GA)
The DAC/amplifier combination, along with access to
the feedback resistors, makes the MAX532 ideal as a
programmable-gain amplifier. In this application, the
DAC functions as a programmable resistor in the feed-
back loop. This type of configuration is shown in Figure
12, and is suitable for AC gain control. The DAC code
controls the gain for the PGA. As the code decreases,
the effective DAC resistance increases, and so the gain
also increases. The transfer function is given by:
MAX532
R/2
VREFA
VOUTA
2
3
DACA
4096
CODE
R
2
RFBA
1
V
IN
V
OUT
V
/V = -REQA/RFBA,
OUT IN
where RFBA is the value of the feedback resistor (R/2),
and REQA is the effective DAC resistance controlled
by the digital input code:
AGNDA
4
V
-4096
CODE
OUT
=
V
IN
R
4096
REQA = —— (————) ,
CODE
2
Figure 12. Programmable-Gain Amplifer
where CODE is the DAC code in decimal.
The transfer function is thus:
V
-4096
——— = ———
CODE
OUT
V
IN
12
The code may be programmed between 1 and (2 -1).
The zero code is not allowed, as it results in an open-
loop amplifier response.
P o w e r-On Re s e t
On p owe r-up , the inte rna l DAC la tc he s a re s e t to
00 . . . . .00.
______________________________________________________________________________________ 13
Du a l, S e ria l-In p u t ,
Vo lt a g e -Ou t p u t , 1 2 -Bit MDAC
__Ord e rin g In fo rm a t io n (c o n t in u e d )
___________________Ch ip To p o g ra p h y
ERROR
PART
TEMP. RANGE PIN-PACKAGE
(LSBs)
±1/2
±1
RFBA
V
DD
VREFA
LDAC
MAX532AEPE
MAX532BEPE
MAX532AEWE
MAX532BEWE
MAX532AMJE
MAX532BMJE
-40°C to +85°C 16 Plastic DIP
-40°C to +85°C 16 Plastic DIP
-40°C to +85°C 16 Wide SO
-40°C to +85°C 16 Wide SO
-55°C to +125°C 16 CERDIP**
-55°C to +125°C 16 CERDIP**
CS
±1/2
±1
MAX532
VOUTA
AGNDA
±1/2
±1
DIN
**Contact factory for availability and processing to MIL-STD-883B.
0. 250"
(6. 35mm)
AGNDB
VOUTB
DOUT
SCLK
RFBB
V
SS
DGND
VREFB
V
SS
0. 140"
(3. 56mm)
TRANSISTOR COUNT: 1324;
SUBSTRATE CONNECTED TO V
.
DD
14 ______________________________________________________________________________________
Du a l, S e ria l-In p u t ,
Vo lt a g e -Ou t p u t , 1 2 -Bit MDAC
MAX532
________________________________________________________P a c k a g e In fo rm a t io n
INCHES
MILLIMETERS
DIM
D1
MIN
MAX
0.200
–
MIN
–
MAX
5.08
–
A
–
A1 0.015
A2 0.125
A3 0.055
0.38
3.18
1.40
0.41
1.27
0.20
18.92
0.13
7.62
6.10
0.150
0.080
0.022
0.065
0.012
0.765
0.030
0.325
0.280
3.81
2.03
0.56
1.65
0.30
19.43
0.76
8.26
7.11
B
0.016
B1 0.050
C
D
0.008
0.745
E
D1 0.005
0.300
E1 0.240
E
E1
D
e
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
A3
e
A
B
A2
A1
A
L
e
–
0.115
0˚
0.400
0.150
15˚
–
10.16
3.81
L
2.92
0˚
α
15˚
21-587A
α
16-PIN PLASTIC
DUAL-IN-LINE
PACKAGE
C
e
B1
e
e
A
B
B
INCHES
MILLIMETERS
DIM
MIN
0.093
MAX
0.104
0.012
0.019
0.013
0.413
0.299
MIN
2.35
0.10
0.35
0.23
10.10
7.40
MAX
2.65
0.30
0.49
0.32
10.50
7.60
A
A1 0.004
B
C
D
E
e
0.014
0.009
0.398
0.291
E
H
0.050 BSC
1.27 BSC
H
h
0.394
0.010
0.016
0˚
0.419
0.030
0.050
8˚
10.00
0.25
0.40
0˚
10.65
0.75
1.27
L
α
8˚
21-589B
h x 45˚
D
α
A
0.127mm
0.004in.
16-PIN PLASTIC
SMALL-OUTLINE
(WIDE)
e
A1
C
B
L
PACKAGE
______________________________________________________________________________________ 15
Du a l, S e ria l-In p u t ,
Vo lt a g e -Ou t p u t , 1 2 -Bit MDAC
MAX532
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1994 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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