MAX533BEEE+T [MAXIM]
D/A Converter, 4 Func, Serial Input Loading, 6us Settling Time, PDSO16, 0.150 INCH, 0.025 INCH PITCH, QSOP-16;型号: | MAX533BEEE+T |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | D/A Converter, 4 Func, Serial Input Loading, 6us Settling Time, PDSO16, 0.150 INCH, 0.025 INCH PITCH, QSOP-16 |
文件: | 总16页 (文件大小:147K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
19-1080; Rev 0; 6/96
2 .7 V, Lo w -P o w e r, 8 -Bit Qu a d DAC
w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs
MAX53
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
The MAX533 serial-input, voltage-output, 8-bit quad
digital-to-analog converter (DAC) operates from a sin-
gle +2.7V to +3.6V supply. Internal precision buffers
swing rail to rail, and the reference input range includes
both ground and the positive rail. The MAX533 features
a 1µA shutdown mode.
♦ +2.7V to +3.6V Single-Supply Operation
♦ Ultra-Low Supply Current:
0.7mA while Operating
1µA in Shutdown Mode
♦ Ultra-Small 16-Pin QSOP Package
The serial interface is double buffered: a 12-bit input
shift register is followed by four 8-bit buffer registers
and four 8-bit DAC registers. The 12-bit serial word
consists of eight data bits and four control bits (for DAC
selection and special programming commands). Both
the input and DAC registers can be updated indepen-
dently or simultaneously with a single software com-
mand. Two additional asynchronous control pins, LDAC
and CLR, provide simultaneous updating or clearing of
the input and DAC registers.
♦ Ground to V
Reference Input Range
DD
♦ Output Buffer Amplifiers Swing Rail to Rail
♦ 10MHz Serial Interface, Compatible with SPI, QSPI
(CPOL = CPHA = 0 or CPOL = CPHA = 1), and
Microwire
♦ Double-Buffered Registers for Synchronous
Updating
♦ Serial Data Output for Daisy Chaining
The interface is compatible with SPI™, QSPI™ (CPOL =
CPHA = 0 or CPOL = CPHA = 1), and Microwire™. A
buffered data output allows daisy chaining of serial
devices.
♦ Power-On Reset Clears Serial Interface and Sets
All Registers to Zero
♦ Software Shutdown
In addition to 16-pin DIP and CERDIP packages, the
MAX533 is available in a 16-pin QSOP that occupies
the same area as an 8-pin SO.
♦ Software-Programmable Logic Output
♦ Asynchronous Hardware Clear Resets All Internal
Registers to Zero
________________________Ap p lic a t io n s
Digital Gain and Offset Adjustments
Programmable Attenuators
______________Ord e rin g In fo rm a t io n
Programmable Current Sources
Portable Instruments
INL
(LSB)
PART
TEMP. RANGE PIN-PACKAGE
MAX533ACPE
MAX533BCPE
MAX533ACEE
MAX533BCEE
MAX533BC/D
MAX533AEPE
MAX533BEPE
MAX533AEEE
MAX533BEEE
MAX533AMJE
MAX533BMJE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
16 Plastic DIP
16 Plastic DIP
16 QSOP
±1
±2
±1
±2
±2
±1
±2
±1
±2
±1
±2
__________________P in Co n fig u ra t io n
16 QSOP
TOP VIEW
Dice*
OUTB
OUTA
REF
1
2
3
4
5
6
7
8
16
15
14
13
OUTC
OUTD
AGND
-40°C to +85°C 16 Plastic DIP
-40°C to +85°C 16 Plastic DIP
-40°C to +85°C 16 QSOP
-40°C to +85°C 16 QSOP
UPO
PDE
MAX533
V
DD
-55°C to +125°C 16 CERDIP**
-55°C to +125°C 16 CERDIP**
12 DGND
11 DIN
LDAC
CLR
*Dice are tested at T = +25°C.
A
10
9
SCLK
CS
**Contact factory for availability and processing to MIL-STD-883.
DOUT
Functional Diagram appears at end of data sheet.
DIP/QSOP
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
2 .7 V, Lo w -P o w e r, 8 -Bit Qu a d DAC
w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs
ABSOLUTE MAXIMUM RATINGS
V
DD
to DGND ..............................................................-0.3V, +6V
Continuous Power Dissipation (T = +70°C)
A
V
to AGND...............................................................-0.3V, +6V
Plastic DIP (derate 10.53mW/°C above +70°C) .........842mW
QSOP (derate 8.3mW/°C above +70°C).....................667mW
CERDIP (derate 10.00mW/°C above +70°C)..............800mW
Operating Temperature Ranges
DD
Digital Input Voltage to DGND ....................................-0.3V, +6V
Digital Output Voltage to DGND....................-0.3V, (V + 0.3V)
AGND to DGND..................................................................±0.3V
DD
REF................................................................-0.3V, (V + 0.3V)
MAX533 _ C_ E ..................................................0°C to +70°C
MAX533 _ E_ E ...............................................-40°C to +85°C
MAX533 _ MJE .............................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
DD
OUT_ ...........................................................................-0.3V, V
DD
MAX53
Maximum Current into Any Pin............................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +2.7V to +3.6V, V
= 2.5V, AGND = DGND = 0V, R = 10kΩ, C = 100pF, T = T
to T , unless otherwise noted.
MAX
DD
REF
L
L
A
MIN
Typical values are at V = +3V and T = +25°C.)
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC ACCURACY
Resolution
8
Bits
MAX533A
MAX533B
±1
Integral Nonlinearity
(Note 1)
INL
LSB
±2
Differential Nonlinearity (Note 1)
Zero-Code Error
DNL
ZCE
Guaranteed monotonic (all codes)
Code = 00 hex
±1.0
±20
LSB
mV
Zero-Code-Error Supply
Rejection
Code = 00 hex, V = 2.7V to 3.6V
DD
1
LSB
Zero-Code Temperature
Coefficient
Code = 00 hex
Code = FF hex
±10
±10
µV/°C
mV
Full-Scale Error
±30
1
Full-Scale Error Supply
Rejection
Code = FF hex, V = 2.7V to 3.6V
DD
LSB
Full-Scale Temperature
Coefficient
Code = FF hex
µV/°C
REFERENCE INPUTS
Input Voltage Range
Input Resistance
0
V
V
DD
322
460
10
598
kΩ
pF
dB
dB
Input Capacitance
Channel-to-Channel Isolation
AC Feedthrough
(Note 2)
(Note 3)
-60
-70
DAC OUTPUTS
Output Voltage Range
Load Regulation
R
= open
0
V
V
L
REF
Code = FF hex, R from 10kΩ to ∞
0.25
LSB
L
2
_______________________________________________________________________________________
2 .7 V, Lo w -P o w e r, 8 -Bit Qu a d DAC
w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs
MAX53
ELECTRICAL CHARACTERISTICS (continued)
(V = +2.7V to +3.6V, V
= 2.5V, AGND = DGND = 0V, R = 10kΩ, C = 100pF, T = T
to T , unless otherwise noted.
MAX
DD
REF
L
L
A
MIN
Typical values are at V = +3V and T = +25°C.)
DD
A
PARAMETER
DIGITAL INPUTS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
Input Low Voltage
Input Current
V
0.7V
V
V
IH
DD
V
IL
0.3V
DD
I
IN
V
= 0V or V
DD
±1.0
10
µA
pF
IN
Input Capacitance
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
C
(Note 4)
IN
V
OH
I
= TBDmA
V - 0.5
DD
V
V
SOURCE
V
OL
I
= 1.6mA
0.4
SINK
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
CODE = FF hex
0.6
6
V/µs
µs
To 1/2LSB, from code 00 to code FF hex
(Note 5)
Output Settling Time
Digital Feedthrough and
Crosstalk
VREF = 0V, code 00 to code FF hex (Note 6)
Code 80 hex to code 7F hex
5
nV-s
nV-s
Digital-to-Analog Glitch Impulse
50
-70
V
REF
= 2.5Vp-p at 1kHz, V = 3V,
DD
Signal-to-Noise Plus
Distortion Ratio
code = FF hex
SINAD
dB
V
REF
= 2.5Vp-p at 10kHz
-62
380
60
Multiplying Bandwidth
Wideband Amplifier Noise
POWER SUPPLIES
V
REF
= 0.5Vp-p, 3dB bandwidth
kHz
µV
RMS
Power-Supply Voltage
V
2.7
3.6
1.3
1.5
10
V
DD
MAX533C/E
MAX533M
0.68
0.68
1
Supply Current
I
DD
mA
µA
Shutdown Current
TIMING CHARACTERISTICS
(V = +2.7V to +3.6V, V
= 2.5V, AGND = DGND = 0V, C
= 100pF, T = T
to T , unless otherwise noted.
MAX
DD
REF
DOUT
A
MIN
Typical values are at V = +3V and T = +25°C.)
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
50
UNITS
MAX533C/E
MAX533M
MAX533C/E
MAX533M
MAX533C/E
MAX533M
MAX533C/E
MAX533M
MAX533C/E
MAX533M
V
Rise to CS Fall Setup Time
DD
t
µs
VDCS
LDAC
(Note 4)
60
40
50
40
50
40
50
90
100
20
25
t
ns
ns
ns
ns
LDAC Pulse Width Low
CS Rise to LDAC Fall Setup
Time (Note 7)
t
CLL
20
25
t
CLR Pulse Width Low
CS Pulse Width High
CLW
t
CSW
_______________________________________________________________________________________
3
2 .7 V, Lo w -P o w e r, 8 -Bit Qu a d DAC
w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs
TIMING CHARACTERISTICS (continued)
(V = +2.7V to +3.6V, V
= 2.5V, AGND = DGND = 0V, C
= 100pF, T = T
to T , unless otherwise noted.
MAX
DD
REF
DOUT
A
MIN
Typical values are at V = +3V and T = +25°C.)
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SERIAL-INTERFACE TIMING
MAX533C/E
MAX533M
MAX533C/E
MAX533M
MAX533C/E
MAX533M
MAX533C/E
MAX533M
10
SCLK Clock Frequency (Note 8)
f
MHz
ns
CLK
MAX53
8.3
40
50
40
50
40
50
SCLK Pulse Width High
SCLK Pulse Width Low
t
CH
t
ns
CL
CS Fall to SCLK Rise Setup
Time
t
ns
CSS
t
0
ns
SCLK Rise to CS Rise Hold Time
CSH
MAX533C/E
MAX533M
40
50
0
DIN to SCLK Rise to Setup Time
DIN to SCLK Rise to Hold Time
t
DS
t
ns
ns
DH
MAX533C/E
MAX533M
MAX533C/E
MAX533M
MAX533C/E
MAX533M
MAX533C/E
MAX533M
200
230
210
250
SCLK Rise to DOUT Valid
Propagation Delay (Note 9)
t
t
DO1
DO2
SCLK Fall to DOUT Valid
Propagation Delay (Note 10)
ns
ns
ns
40
50
40
50
t
SCLK Rise to CS Fall Delay
CS0
CS1
CS Rise to SCLK Rise Setup
Time
t
Note 1: INL and DNL are measured with R referenced to ground. Nonlinearity is measured from the first code that is greater than
L
or equal to the maximum offset specification to code FF hex (full scale). See DAC Linearity and Voltage Offset section.
Note 2:
Note 3:
V
= 2.5Vp-p, 10kHz. Channel-to-channel isolation is measured by setting one DAC’s code to FF hex and setting all
REF
other DAC’s codes to 00 hex.
= 2.5Vp-p, 10kHz. DAC code = 00 hex.
V
REF
Note 4: Guaranteed by design, not production tested.
Note 5: Output settling time is measured from the 50% point of the rising edge of CS to 1/2LSB of V
’s final value.
OUT
Note 6: Digital crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other
DAC.
Note 7: If LDAC is activated prior to CS’s rising edge, it must stay low for t
or longer after CS goes high.
LDAC
Note 8: When DOUT is not used. If DOUT is used, f
max is 4MHz, due to the SCLK to DOUT propagation delay.
CLK
Note 9: Serial data clocked out at SCLK’s rising edge (measured from 50% of the clock edge to 20% or 80% of V ).
DD
Note 10: Serial data clocked out at SCLK’s falling edge (measured from 50% of the clock edge to 20% or 80% of V ).
DD
4
_______________________________________________________________________________________
2 .7 V, Lo w -P o w e r, 8 -Bit Qu a d DAC
w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs
MAX53
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +3V, T = +25°C, unless otherwise noted.)
DD
A
DAC ZERO-CODE OUTPUT VOLTAGE vs.
OUTPUT SINK CURRENT
DAC FULL-SCALE OUTPUT VOLTAGE vs.
OUTPUT SOURCE CURRENT
SUPPLY CURRENT vs.
TEMPERATURE
1.50
5.0
4.5
4.0
3.5
1000
800
600
400
DAC CODE = FF HEX
DAC CODE = 00 HEX
V
= V = 5.0V
DD REF
1.25
1.00
0.75
LOAD TO V
DD
V
DD
= +5.0V
V = +3.0V
DD
V
REF
= +4.5V
V
REF
= +2.5V
DAC CODE = FF HEX
LOAD TO GND
V
= V = 3.0V
DD REF
DAC CODE = 00 HEX
0.50
0.25
0
3.0
2.5
2.0
V
= V = 5.0V
DD REF
200
0
V
= V = 3.0V
DD REF
0
1
2
3
4
5
6
7
8
0
2
4
6
8
10
12
-55 -35 -15
5
25 45 65 85 105 125
DAC OUTPUT SINK CURRENT (mA)
DAC OUTPUT SOURCE CODE (mA)
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT vs.
TEMPERATURE
SUPPLY CURRENT vs.
REFERENCE VOLTAGE (V = +3.0V)
DD
SUPPLY CURRENT vs.
REFERENCE VOLTAGE (V = +5.0V)
DD
5
3
3
2
1000
800
600
400
1000
800
600
400
ALL DAC CODES = FF HEX
ALL DAC CODES = 00 HEX
ALL DAC CODES = FF HEX
ALL DAC CODES = 00 HEX
V
DD
= +5.0V
V
DD
= +3.0V
1
0
200
0
200
0
-55 -35 -15
5
25 45 65 85 105 125
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
THD + NOISE AT DAC OUTPUT vs.
REFERENCE AMPLITUDE
THD + NOISE AT DAC OUTPUT vs.
REFERENCE FREQUENCY
-20
-30
-40
V
= +3.0V
= SINE WAVE
DD
V
DD
= +3.0V
V
REF
V
REF
= SINE WAVE
CENTERED AT 1.2V
DAC C0DE = FF HEX
80kHz LOWPASS FILTER
-30
-40
-50
-60
-70
CENTERED AT 1.2V
DAC CODE = FF HEX
500kHz LOWPASS FILTER
V
= 20kHz
-50
REF
V
REF
= 2V
p-p
V
REF
= 1V
P-P
-60
-70
V
REF
= 1kHz
V
REF
= 0.5V
p-p
0
0.5
1.0
1.5
2.0
1
0.1
1
10
100
REFERENCE AMPLITUDE (V
)
p-p
FREQUENCY (kHz)
_______________________________________________________________________________________
5
2 .7 V, Lo w -P o w e r, 8 -Bit Qu a d DAC
w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +3V, T = +25°C, unless otherwise noted.)
DD
A
REFERENCE INPUT FREQUENCY RESPONSE
REFERENCE FEEDTHROUGH vs. FREQUENCY
5
0
-20
-30
-40
-50
-60
-70
-80
V
= +3.0V
= 3V SINE WAVE
p-p
DD
V
REF
DAC CODE = 00 HEX
MAX53
-5
-10
-15
-20
-25
-30
V
= 0.1V SINE WAVE
p-p
REF
CENTERED AT 2.5V
DAC CODE = FF HEX
V
DD
= +3.0V
0.01
0.1
1
10
0.01
0.1
1
10
FREQUENCY (MHz)
FREQUENCY (MHz)
WORST-CASE 1LSB DIGITAL
STEP CHANGE (NEGATIVE)
WORST-CASE 1LSB DIGITAL
STEP CHANGE (POSITIVE)
MAX533-TOC11
MAX533-TOC10
CS
CS
2V/div
2V/div
OUTA
50mV/div
OUTA
50mV/div
2µs/div
DAC CODE = 80 TO 7F hex
2µs/div
V
V
REF
= 3.0V
= 2.5V
DD
V
V
REF
= 3.0V
= 2.5V
DAC CODE = 7F TO 80 hex
NO LOAD
DD
NO LOAD
CLOCK FEEDTHROUGH
POSITIVE SETTLING TIME
MAX533-TOC13
MAX533-TOC14
SCLK
2V/div
CS
2V/div
OUTA
1V/div
OUTA
10mV/div
2µs/div
5µs/div
V
= 2.5V
SCLK = 333kHz
REF
V
V
REF
= 3.0V
= 2.5V
DD
DAC CODE = 00 TO FF hex
NO LOAD
DAC CODE = 80 hex
NO LOAD
SCLK t = t = 25ns
R
F
V
DD
= 3.0V
6
_______________________________________________________________________________________
2 .7 V, Lo w -P o w e r, 8 -Bit Qu a d DAC
w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs
MAX53
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +3V, T = +25°C, unless otherwise noted.)
DD
A
POSITIVE SETTLING TIME
NEGATIVE SETTLING TIME
MAX533-TOC15
MAX533-TOC16
CS
CS
2V/div
2V/div
OUTA
1V/div
OUTA
1V/div
5µs/div
5µs/div
DAC CODE = FF TO 00 hex
NO LOAD
V
V
REF
= 3.0V
= 2.5V
V
V
REF
= 3.0V
= 2.5V
DAC CODE = 01 TO FF hex
NO LOAD
DD
DD
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
1
2
3
4
5
OUTB
OUTA
REF
DAC B Voltage Output
DAC A Voltage Output
Reference-Voltage Input
UPO
Software-Programmable Logic Output
PDE
Power-Down Enable. Must be high to enter software shutdown mode.
Load DAC Input (active low). Driving this asynchronous input low (level sensitive) transfers the contents
of each input latch to its respective DAC latch.
6
7
LDAC
CLR
Clear DAC Input (active low). Driving CLR low asynchronously clears the input and DAC registers, and
sets all DAC outputs to zero.
Serial Data Output. Sinks and sources current. Data at DOUT can be clocked out on the rising or falling
edge of SCLK (Table 1).
8
DOUT
CS
Chip-Select Input (active low). Data is shifted in and out when CS is low. Programming commands are
executed when CS returns high.
9
Serial Clock Input. Data is clocked in on the rising edge and clocked out on the falling (default) or rising
edge (A0 = A1 = 1, see Table 1).
10
SCLK
11
12
13
14
15
16
DIN
Serial Data Input. Data is clocked in on the rising edge of SCLK.
Digital Ground
DGND
V
DD
Power Supply, +2.7V to +3.6V
Analog Ground
AGND
OUTD
OUTC
DAC D Voltage Output
DAC C Voltage Output
_______________________________________________________________________________________
7
2 .7 V, Lo w -P o w e r, 8 -Bit Qu a d DAC
w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs
INSTRUCTION
EXECUTED
CS
• • •
• • •
SCLK
MAX53
DIN
• • •
C1
A1
C0
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
A1 A0 C1 C0
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
A0
DACA
DACD
DOUT
MODE 1
• • •
A1
A1
A0 C1 C0 D7
D0
D6 D5 D4 D3 D2 D1
A1 A0 C1 C0 D7
D6 D5 D4 D3 D2 D1 D0
A1
A1
DATA FROM PREVIOUS DATA INPUT
DATA FROM PREVIOUS DATA INPUT
DOUT
MODE 0
(DEFAULT)
• • •
D0
A1 A0 C1 C0 D7
D6 D5 D4 D3 D2 D1 D0
A1 A0 C1 C0 D7
D6 D5 D4 D3 D2 D1
A1
Figure 1. 3-Wire Interface Timing
CS
t
CSW
t
CSH
t
t
t
CH
t
CP
CS0
CSS
t
CS1
t
CL
SCLK
DIN
t
DS
t
DH
t
D02
t
D01
DOUT
LDAC
t
CLL
t
LDAC
Figure 2. Detailed Serial-Interface Timing Diagram
_______________________________________________________________________________________
8
2 .7 V, Lo w -P o w e r, 8 -Bit Qu a d DAC
w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs
MAX53
Serial Input Data Format and Control Codes
_______________De t a ile d De s c rip t io n
The 12-bit serial input format shown in Figure 3 com-
prises two DAC address bits (A1, A0), two control bits
(C1, C0), and eight bits of data (D7...D0).
S e ria l In t e rfa c e
At p owe r-on, the s e ria l inte rfa c e a nd a ll d ig ita l-to-
analog converters (DACs) are cleared and set to code
zero. The serial data output (DOUT) is set to transition
on SCLK's falling edge.
The 4-bit address/control code configures the DAC as
shown in Table 1.
Load Input Register, DAC Registers Unchanged
(Single Update Operation)
The MAX533 c ommunic a te s with mic rop roc e s s ors
through a synchronous, full-duplex, 3-wire interface
(Figure 1). Data is sent MSB first and can be transmit-
ted in one 4-bit and one 8-bit (byte) packet or in one
12-bit word. If a 16-bit word is used, the first four bits
are ignored. A 4-wire interface adds a line for LDAC
and allows asynchronous updating. The serial clock
(SCLK) synchronizes the data transfer. Data is transmit-
ted and received simultaneously.
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
Address
0
1
8-Bit Data
(LDAC = H)
When performing a single update operation, A1 and A0
select the respective input register. At the rising edge
of CS, the selected input register is loaded with the cur-
re nt s hift-re g is te r d a ta . All DAC outp uts re ma in
unchanged. This preloads individual data in the input
register without changing the DAC outputs.
Figure 2 shows the detailed serial-interface timing.
Please note that the clock should be low if it is stopped
b e twe e n up d a te s . DOUT d oe s not g o into a hig h-
impedance state if the clock idles or CS is high.
Load Input and DAC Registers
Serial data is clocked into the data registers in MSB-first
format, with the address and configuration information
preceding the actual DAC data. Data is clocked in on
SCLK’s rising edge while CS is low. Data at DOUT is
clocked out 12 clock cycles later, either at SCLK’s falling
edge (default or mode 0) or rising edge (mode 1).
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
Address
1
1
8-Bit Data
(LDAC = H)
This command directly loads the selected DAC register at
CS’s rising edge. A1 and A0 set the DAC address. Current
shift-register data is placed in the selected input and DAC
registers.
Chip select (CS) must be low to enable the DAC. If CS
is high, the interface is disabled and DOUT remains
unchanged. CS must go low at least 40ns before the
first rising edge of the clock pulse to properly clock in
the firs t b it. With CS low, d a ta is c loc ke d into the
MAX533’s internal shift register on the rising edge of
the external serial clock. Always clock in the full 12 bits
because each time CS goes high the bits currently in
the input shift register are interpreted as a command.
SCLK can be driven at rates up to 10MHz.
For example, to load all four DAC registers simultaneously
with individual settings (DAC A = 0.5V, DAC B = 1V,
DAC C = 1.5V, and DAC D = 2V), four commands are
re q uire d . Firs t, p e rform thre e s ing le inp ut re g is te r
update operations for DACs A, B, and C (C1 = 0). The
final command loads input register D and updates all
four DAC registers from their respective input registers.
Software “LDAC ” Command
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
x
x
x
x
x
x
x
x
THIS IS THE FIRST BIT SHIFTED IN
MSB
LSB
(LDAC = 1)
A1
A0
C1 C0 ..
D
.
7
D1 D6 D0
DOUT
DIN
All DAC registers are updated with the contents of their
respective input registers at CS’s rising edge. With the
exception of using CS to execute, this performs the
same function as the asynchronous LDAC.
8-BIT DAC DATA
CONTROL AND
ADDRESS BITS
Figure 3. Serial Input Format
_______________________________________________________________________________________
9
2 .7 V, Lo w -P o w e r, 8 -Bit Qu a d DAC
w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs
12-BIT SERIAL WORD
LDAC
FUNCTION
A1
A0
C1
C0
D7 . . . . . . . . D0
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
8-bit DAC data
8-bit DAC data
8-bit DAC data
8-bit DAC data
1
1
1
1
Load input register A; all DAC outputs unchanged.
Load input register B; all DAC outputs unchanged.
Load input register C; all DAC outputs unchanged.
Load input register D; all DAC outputs unchanged.
MAX53
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
8-bit DAC data
8-bit DAC data
8-bit DAC data
8-bit DAC data
1
1
1
1
Load input register A; all DAC outputs updated
Load input register B; all DAC outputs updated
Load input register C; all DAC outputs updated
Load input register D; all DAC outputs updated.
Software LDAC commands. Update all DACs from
their respective input registers. Also bring the part out
of shutdown mode.
0
1
0
0
X X X X X X X X
1
Load all DACs with shift-register data. Also bring the
part out of shutdown mode.
1
0
0
0
8-bit DAC data
X
1
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X
X
X
X
Software shutdown (provided PDE is high)
UPO goes low.
UPO goes high.
No operation (NOP); shift data in shift registers.
Set DOUT phase—SCLK rising (mode 1). DOUT
clocked out on rising edge of SCLK. All DACs updated
from their respective input registers.
1
1
1
0
1
1
0
0
X X X X X X X X
X X X X X X X X
X
X
Set DOUT phase—SCLK falling (mode 0). DOUT
clocked out on falling edge of SCLK. All DACs up-
dated from their respective registers (default).
Load All DACs with Shift-Register Data
User-Programmable Output (UPO)
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
8-Bit Data
UPO
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
Output
1
0
0
0
0
0
0
1
1
1
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Low
(LDAC = X)
High
All four DAC registers are updated with shift-register
data. This command allows all DACs to be set to any
analog value within the reference range. This command
can be used to substitute CLR if code 00 hex is pro-
grammed, which clears all DACs.
(LDAC = X)
User-programmable logic output for controlling another
device across an isolated interface. Example devices
are gain control of an amplifier, a 4mA to 20mA amplifi-
er, and a polarity output for a motor speed control.
Software Shutdown
No Operation (NOP)
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
1
1
0
0
x
x
x
x
x
x
x
x
0
0
0
0
x
x
x
x
x
x
x
x
(LDAC = X, PDE = H)
(LDAC = X)
Shuts down all output buffer amplifiers, reducing sup-
ply current to 10µA max.
The NOP command (no operation) allows data to be
shifted through the MAX533 shift register without affect-
ing the input or DAC registers. This is useful in daisy
chaining (also see the Daisy Chaining Devices section).
10 ______________________________________________________________________________________
2 .7 V, Lo w -P o w e r, 8 -Bit Qu a d DAC
w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs
MAX53
For this command, the data bits are “Don't Cares.” As
Serial Data Output
DOUT is the internal shift register’s output. DOUT can
be programmed to clock out data on SCLK’s falling
edge (mode 0) or rising edge (mode 1). In mode 0, out-
put data lags input data by 12.5 clock cycles, maintain-
ing compatibility with Microwire and SPI. In mode 1,
output data lags input data by 12 clock cycles. On
power-up, DOUT defaults to mode 0 timing. DOUT
never three-states; it always actively drives either high
or low and remains unchanged when CS is high.
an example, three MAX533s are daisy chained (A, B,
and C), and devices A and C need to be updated. The
36-bit-wide command would consist of one 12-bit word
for device C, followed by an NOP instruction for device
B and a third 12-bit word with data for device A. At CS’s
rising edge, device B will not change state.
Set DOUT Phase—SCLK Rising (Mode 1)
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
1
1
1
0
x
x
x
x
x
x
x
x
(LDAC = x)
Mode 1 resets the serial-output DOUT to transition at
SCLK’s rising edge. Once this command is issued,
DOUT’s phase is latched and will not change except on
power-up or if the specific command to set the phase
to falling edge is issued.
SCLK
DIN
SK
SO
MAX533
MICROWIRE
PORT
This command also loads all DAC registers with the con-
tents of their respective input registers, and is identical to
the “LDAC” command.
I/0
CS
Set DOUT Phase—SCLK Falling (Mode 0, Default)
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
0
x
x
x
x
x
x
x
x
(LDAC = x)
Figure 4. Connections for Microwire
This command resets DOUT to transition at SCLK’s falling
edge. The same command also updates all DAC registers
with the contents of their respective input registers, identical
to the “LDAC” command.
LDAC Operation (Hardware)
LDAC is typically used in 4-wire interfaces (Figure 7). This
command is level sensitive, and it allows asynchronous
hardware control of the DAC outputs. With LDAC low, the
DAC registers are transparent, and any time an input regis-
ter is updated, the DAC output immediately follows.
MAX533
DIN
SCLK
CS
MOSI
SPI/QSPI
PORT
SCK
I/0
Clear DACs with CLR
Strobing the CLR pin low causes an asynchronous
clear of input and DAC registers and sets all DAC out-
puts to zero. Similar to the LDAC pin, CLR can be
invoked at any time, typically when the device is not
selected (CS = H). When the DAC data is all zeros, this
function is equivalent to the “Update all DACs from Shift
Registers” command.
CPOL = 0, CPHA = 0
Figure 5. Connections for SPI/QSPI
______________________________________________________________________________________ 11
2 .7 V, Lo w -P o w e r, 8 -Bit Qu a d DAC
w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs
Interfacing to the Microprocessor
The MAX533 is Microwire™ and SPI™/QSPI™ compati-
ble. For SPI and QSPI, clear the CPOL and CPHA con-
figuration bits (CPOL = CPHA = 0). The SPI/QSPI CPOL
= CPHA = 1 c onfig ura tion c a n a ls o b e us e d if the
DOUT output is ignored.
An a lo g S e c t io n
DAC Operation
The MAX533 uses a matrix decoding architecture for
the DACs, which saves power in the overall system.
The external reference voltage is divided down by a
resistor string placed in a matrix fashion. Row and col-
umn d e c od e rs s e le c t the a p p rop ria te ta b from the
resistor string to provide the needed analog voltages.
The resistor string presents a code-independent input
impedance to the reference and guarantees a mono-
tonic output. Figure 8 shows a simplified diagram of the
four DACs.
The MAX533 can interface with Intel’s 80C5X/80C3X
family in mode 0 if the SCLK clock polarity is inverted.
More universally, if a serial port is not available, three
lines from one of the parallel ports can be used for bit
manipulation.
MAX53
Digital feedthrough at the voltage outputs is greatly
minimized by operating the serial clock only to update
the registers. Also see the Clock Feedthrough photo in
the Typ ic a l Op e ra ting Cha ra c te ris tic s s e c tion. The
clock idle state is low.
Reference Input
The voltage at REF sets the full-scale output voltage for
all four DACs. The 460kΩ typical input impedance at
REF is code independent. The output voltage for any
DAC can be represented by a digitally programmable
voltage source as follows:
Daisy-Chaining Devices
Any number of MAX533s can be daisy-chained by con-
necting DOUT of one device to DIN of the following
de vic e in the c ha in. The NOP instruc tion (Ta ble 1)
allows data to be passed from DIN to DOUT without
changing the input or DAC registers of the passing
device. A 3-wire interface updates daisy-chained or
individual MAX533s simultaneously by bringing CS
high (Figure 6).
V
OUT
= (NB x V ) / 256
REF
where NB is the numerical value of the DAC’s binary
input code.
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
MAX533
MAX533
MAX533
SCLK
DIN
CS
SCLK
DIN
CS
SCLK
DIN
CS
SCLK
DIN
CS
DOUT
DOUT
DOUT
TO OTHER
SERIAL DEVICES
DEVICE B
DEVICE A
MAX533
DEVICE C
SCLK
DIN
CS
SCLK
DIN
CS
Figure 6. Daisy-chained or individual MAX533s are simultaneously updated by bringing CS high. Only three wires are required.
12 ______________________________________________________________________________________
2 .7 V, Lo w -P o w e r, 8 -Bit Qu a d DAC
w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs
MAX53
DIN
SCLK
LDAC
CS1
CS2
CS3
TO OTHER
SERIAL
DEVICES
CS
CS
CS
MAX533
MAX533
MAX533
LDAC
LDAC
LDAC
SCLK
DIN
SCLK
DIN
SCLK
DIN
Figure 7. Multiple MAX533s sharing one DIN line. Simultaneously update by strobing LDAC, or specifically update by enabling an
individual CS.
Output Buffer Amplifiers
All MAX533 voltage outputs are internally buffered by
__________Ap p lic a t io n s In fo rm a t io n
DAC Lin e a rit y a n d Vo lt a g e Offs e t
The output buffer can have a negative input offset volt-
age that would normally drive the output negative, but
since there is no negative supply the output stays at 0V
(Figure 9). When linearity is determined using the end-
point method, it is measured between zero code (all
inputs 0) and full-scale code (all inputs 1) after offset
and gain error are calibrated out. However, in single-
s up p ly op e ra tion the ne xt c od e a fte r ze ro ma y not
change the output (Figure 9), so the lowest code that
produces a positive output is the lower endpoint.
p re c is ion unity-g a in followe rs tha t s le w a t a b out
0.6V/µs. The outputs can swing from GND to V . With
DD
a 0V to +2.5V (or +2.5V to 0V) output transition, the
amplifier outputs will typically settle to 1/2LSB in 6µs
when loaded with 10kΩ in parallel with 100pF.
The buffer amplifiers are stable with any combination of
resistive (≥10kΩ) or capacitive loads.
______________________________________________________________________________________ 13
2 .7 V, Lo w -P o w e r, 8 -Bit Qu a d DAC
w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs
REF
R1
R15
R0
D7
R16
MAX53
D6
D5
D4
OUTPUT
VOLTAGE
R255
0V
DAC CODE
NEGATIVE
OFFSET
LSB DECODER
D2 D1
D3
D0
DAC A
Figure 8. DAC Simplified Circuit Diagram
Figure 9. Effect of Negative Offset (Single Supply)
P o w e r S e q u e n c in g
The voltage applied to REF should not exceed V at
Table 2. Unipolar Code Table
DD
any time. If proper power sequencing is not possible,
connect an external Schottky diode between REF and
DAC CONTENTS
ANALOG
OUTPUT
MSB
LSB
V
to ensure compliance with the absolute maximum
DD
ratings. Do not apply signals to the digital inputs before
the device is fully powered up.
255
256
1 1 1 1
1 1 1 1
+V
(
––––
)
)
REF
P o w e r-S u p p ly Byp a s s in g
a n d Gro u n d Ma n a g e m e n t
Connect AGND and DGND together at the IC. This
ground should then return to the highest-quality ground
129
1 0 0 0
1 0 0 0
0 1 1 1
0 0 0 1
0 0 0 0
1 1 1 1
+V
(
––––
REF
256
V
REF
128
––––
2
+V
(
––––
)
= +
available. Bypass V
with a 0.1µF capacitor, located
DD
REF
256
as close to V and DGND as possible.
DD
127
Careful PC board layout minimizes crosstalk among
DAC outputs and digital inputs. Figure 10 shows sug-
gested circuit board layout to minimize crosstalk.
+V
(
––––
)
)
REF
256
1
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 0
+V
(
––––
REF
Un ip o la r-Ou t p u t ,
Tw o -Qu a d ra n t Mu lt ip lic a t io n
In unipolar operation, the output voltages and the refer-
ence input are the same polarity. Figure 11 shows the
MAX533 unipolar configuration, and Table 2 shows the
unipolar code.
256
0V
1
-8
Note: 1LSB = (V ) (2 ) = +VREF (––––)
REF
256
14 ______________________________________________________________________________________
2 .7 V, Lo w -P o w e r, 8 -Bit Qu a d DAC
w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs
MAX53
REFERENCE INPUT
3
+3V
13
V
DD
REFAB
MAX533
2
OUTA
DAC A
SYSTEM GND
OUTC
OUTB
1
OUTB
OUTC
OUTD
DAC B
DAC C
DAC D
OUTD
AGND
OUTA
REF
SERIAL
INTERFACE
NOT SHOWN
16
15
DGND
12
AGND
14
Figure 10. Suggested PC Board Layout for Minimizing
Crosstalk (Bottom View)
Figure 11. Unipolar Output Circuit
_________________________________________________________Fu n c t io n a l Dia g ra m
V
DD
DOUT
REF
CLR LDAC
PDE
DGND
AGND
UPO
DECODE
CONTROL
MAX533
OUTA
INPUT
REGISTER A
DAC
REGISTER A
DAC A
DAC B
DAC C
DAC D
OUTB
OUTC
OUTD
12-BIT
SHIFT
REGISTER
INPUT
REGISTER B
DAC
REGISTER B
INPUT
REGISTER C
DAC
REGISTER C
SR
INPUT
REGISTER D
DAC
REGISTER D
CONTROL
SCLK
CS
DIN
______________________________________________________________________________________ 15
2 .7 V, Lo w -P o w e r, 8 -Bit Qu a d DAC
w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs
___________________Ch ip In fo rm a t io n
TRANSISTOR COUNT: 6821
MAX53
________________________________________________________P a c k a g e In fo rm a t io n
INCHES
MILLIMETERS
INCHES
MILLIMETERS
DIM
DIM PINS
MIN
0.061
MAX
MIN
MAX
1.73
0.25
1.55
0.31
0.25
MIN MAX MIN
MAX
4.98
0.18
8.74
1.40
8.74
0.76
9.98
A
0.068
1.55
16 0.189 0.196 4.80
16 0.0020 0.0070 0.05
20 0.337 0.344 8.56
20 0.0500 0.0550 1.27
24 0.337 0.344 8.56
24 0.0250 0.0300 0.64
28 0.386 0.393 9.80
28 0.0250 0.0300 0.64
D
S
D
S
D
S
D
S
D
A1 0.004 0.0098 0.127
A2 0.055
0.061
0.012
1.40
0.20
0.19
B
C
D
E
e
0.008
A
0.0075 0.0098
SEE VARIATIONS
e
0.150
0.157
3.81
3.99
A1
B
0.25 BSC
0.635 BSC
0.76
21-0055A
H
h
0.230
0.010
0.016
0.244
0.016
0.035
5.84
0.25
0.41
6.20
0.41
0.89
S
L
N
S
α
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
E
H
QSOP
QUARTER
SMALL-OUTLINE
PACKAGE
h x 45°
α
A2
N
E
L
C
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1996 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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