MAX536BC/D [MAXIM]
Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface; 校准，四通道，12位电压输出DAC，串行接口
| 型号： | MAX536BC/D |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface |
| 文件： | 总24页 (文件大小：361K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0230; Rev 2a; 1/97
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
6/MAX537
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ Four 12-Bit DACs with Output Buffers
The MAX536/MAX537 combine four 12-bit, voltage-output
digital-to-analog converters (DACs) and four precision
output amplifiers in a space-saving 16-pin package.
Offset, gain, and linearity are factory calibrated to provide
the MAX536’s ±1LSB total unadjusted error. The MAX537
operates with ±5V supplies, while the MAX536 uses -5V
and +12V to +15V supplies.
♦ Simultaneous or Independent Control of Four
DACs via a 3-Wire Serial Interface
♦ Power-On Reset
♦ SPI/QSPI and Microwire Compatible
♦ ±1LSB Total Unadjusted Error (MAX536)
♦ Full 12-Bit Performance without Adjustments
♦ ±5V Supply Operation (MAX537)
♦ Double-Buffered Digital Inputs
♦ Buffered Voltage Output
Each DAC has a double-buffered input, organized as
an input register followed by a DAC register. A 16-bit
serial word is used to load data into each input/DAC
register. The serial interface is compatible with either
SPI/QSPI™ or Microwire™, and allows the input and
DAC registers to be updated independently or simulta-
neously with a single software command. The DAC reg-
isters can be simultaneously updated with a hardware
LDAC pin. All logic inputs are TTL/CMOS compatible.
♦ 16-Pin DIP/SO Packages
______________Ord e rin g In fo rm a t io n
INL
(LSB)
PART
TEMP. RANGE PIN-PACKAGE
1
MAX536ACPE
MAX536BCPE
MAX536ACWE
MAX536BCWE
MAX536BC/D
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
16 Plastic DIP
16 Plastic DIP
16 Wide SO
16 Wide SO
Dice*
± ⁄
2
________________________Ap p lic a t io n s
±1
1
Industrial Process Controls
Automatic Test Equipment
Digital Offset and Gain Adjustment
Motion Control Devices
± ⁄
2
±1
±1
1
MAX536AEPE -40°C to +85°C
MAX536BEPE -40°C to +85°C
MAX536AEWE -40°C to +85°C
MAX536BEWE -40°C to +85°C
16 Plastic DIP
16 Plastic DIP
16 Wide SO
16 Wide SO
± ⁄
2
±1
1
Remote Industrial Controls
Microprocessor-Controlled Systems
± ⁄
2
±1
1
MAX536AMDE -55°C to +125°C 16 Ceramic SB** ± ⁄
2
MAX536BMDE -55°C to +125°C 16 Ceramic SB**
±1
________________Fu n c t io n a l Dia g ra m
Ordering Information continued at end of data sheet.
* Contact factory for dice specifications.
** Contact factory for availability and processing to MIL-STD-883.
__________________P in Co n fig u ra t io n
TOP VIEW
V
DGND
AGND
DD
TP
V
SS
SDO LDAC
REFAB
DECODE
CONTROL
MAX536/MAX537
OUTA
OUTB
OUTC
OUTD
INPUT
REG A
DAC
REG A
DAC A
OUTB
OUTA
OUTC
OUTD
V
1
2
3
4
5
6
7
8
16
15
INPUT
REG B
DAC
REG B
DAC B
DAC C
DAC D
16-BIT
SHIFT
REGISTER
V
SS
14 DD
INPUT
REG C
DAC
REG C
MAX536
MAX537
AGND
TP
13
REFAB
DGND
LDAC
SDI
REFCD
12
11
10
9
INPUT
REG D
DAC
REG D
SDO
SCK
CS
SR
CONTROL
SCK
REFCD
CS
SDI
DIP/SO
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
ABSOLUTE MAXIMUM RATINGS
V
DD
to AGND or DGND
Continuous Power Dissipation (T = +70°C)
A
MAX536 ..................................................................-0.3V, +17V
MAX537 ....................................................................-0.3V, +7V
Plastic DIP (derate 10.53mW/°C above +70°C) .................842mW
Wide SO (derate 9.52mW/°C above +70°C).................762mW
Ceramic SB (derate 10.53mW/°C above +70°C)..................842mW
Operating Temperature Ranges
V
to AGND or DGND ...............................................-7V, +0.3V
SS
SDI, SCK, CS, LDAC, TP, SDO
to AGND or DGND.....................................-0.3V, (V
+ 0.3V)
+ 0.3V)
DD SS
MAX53_AC_E/BC_E.............................................0°C to +70°C
MAX53_AE_E/BE_E ..........................................-40°C to +85°C
MAX53_AMDE/BMDE .....................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
DD
REFAB, REFCD to AGND or DGND .............-0.3V, (V
DD
OUT_ to AGND or DGND .............................................V , V
Maximum Current into Any Pin............................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX536
6/MAX537
(V = +15V, V = -5V, REFAB/REFCD = 10V, AGND = DGND = 0V, R = 5kΩ, C = 100pF, T = T
to T , unless
MAX
DD
SS
L
L
A
MIN
otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
12
TYP
MAX
UNITS
STATIC PERFORMANCE—ANALOG SECTION
Resolution
N
Bits
MAX536A
±1.0
±2.0
±2.0
±3.0
±2.5
±3.5
±3.0
±4.0
T
= +25°C
A
MAX536B
MAX536AC
MAX536BC
MAX536AE
MAX536BE
MAX536AM
MAX536BM
Total Unadjusted Error
(Note 1)
TUE
LSB
T
A
= T to T
MIN MAX
MAX536A
MAX536B
±0.15 ±0.50
±1
Integral Nonlinearity
INL
LSB
LSB
Differential Nonlinearity
DNL
Guaranteed monotonic
±1
MAX536A
±2.5
T
A
= +25°C
MAX536B
±5.0
MAX536AC
MAX536BC
MAX536AE
MAX536BE
MAX536AM
MAX536BM
±5.0
±7.5
Offset Error
mV
±6.1
T
A
= T to T
MIN MAX
±8.5
±7.5
±10.0
R = ∞
-0.1
-0.6
±1.0
±1.5
±2.0
L
Gain Error
LSB
MAX536_C/E
MAX536_M
R = 5kΩ
L
V
Power-Supply
DD
PSRR
PSRR
T
±0.02 ±0.125
±0.03 ±0.30
LSB/V
LSB/V
A
= +25°C, 10.8V < V < 16.5V
DD
Rejection Ratio
V
Power-Supply
SS
T
= +25°C, -5.5V < V < -4.5V
SS
A
Rejection Ratio
2
_______________________________________________________________________________________
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
6/MAX537
ELECTRICAL CHARACTERISTICS—MAX536 (continued)
(V = +15V, V = -5V, REFAB/REFCD = 10V, AGND = DGND = 0V, R = 5kΩ, C = 100pF, T = T
to T , unless
MAX
DD
SS
L
L
A
MIN
otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MATCHING PERFORMANCE (T = +25°C)
A
MAX536A
MAX536B
±1.0
±2.0
±1.0
±2.5
±5.0
±1.0
Total Unadjusted Error
Gain Error
TUE
INL
LSB
LSB
mV
±0.1
±1.2
±1.2
±0.2
MAX536A
MAX536B
Offset Error
Integral Nonlinearity
LSB
REFERENCE INPUT
Reference Input Range
Reference Input Resistance
REF
0.0
5
V
DD
– 4
V
kΩ
RREF
Code dependent, minimum at code 555 hex
MULTIPLYING-MODE PERFORMANCE
Reference 3dB Bandwidth
Reference Feedthrough
V
= 2Vp-p
700
kHz
dB
REF
V
= 10Vp-p
REF
-100
at 400Hz
Input code = all 0s
V
= 10Vp-p
REF
-82
at 4kHz
Total Harmonic Distortion
Plus Noise
THD + N
V
REF
= 2.0Vp-p at 50kHz
0.012
%
DIGITAL INPUTS (SDI, SCK, CS, LDAC)
Input High Voltage
V
2.4
V
V
IH
Input Low Voltage
V
IL
0.8
1.0
10
µA
pF
Input Leakage Current
Input Capacitance (Note 2)
V
= 0V or V
IN DD
DIGITAL OUTPUT (SDO)
Output Low Voltage
V
OL
SDO sinking 5mA
SDO = 0V to V
0.18
0.40
±10
V
µA
Output Leakage Current
DD
DYNAMIC PERFORMANCE (R = 5kΩ, C = 100pF)
L
L
V/µs
µs
Voltage-Output Slew Rate
Output Settling Time
5
3
5
8
1
To ± ⁄ LSB of full scale
2
Digital Feedthrough
nV-s
nV-s
Digital Crosstalk (Note 3)
V
= 5V
REF
POWER SUPPLIES
Positive Supply Range
Negative Supply Range
V
10.8
-4.5
16.5
-5.5
18
V
V
DD
V
SS
T
= +25°C
8
A
Positive Supply Current
(Note 4)
I
DD
mA
mA
T
A
= T
to T
25
MIN
MAX
T
A
= +25°C
-6
-16
-23
Negative Supply Current
(Note 4)
I
SS
T
A
= T
to T
MIN
MAX
_______________________________________________________________________________________
3
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
ELECTRICAL CHARACTERISTICS—MAX536 (continued)
(V = +15V, V = -5V, REFAB/REFCD = 10V, AGND = DGND = 0V, R = 5kΩ, C = 100pF, T = T
to T , unless
MAX
DD
SS
L
L
A
MIN
otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (Note 5)
Internal Power-On Reset
Pulse Width (Note 2)
µs
t
20
POR
SCK Clock Period
t
100
30
ns
ns
ns
CP
SCK Pulse Width High
SCK Pulse Width Low
t
CH
t
30
CL
CS Fall to SCK Rise
Setup Time
t
20
10
ns
ns
CSS
SCK Rise to CS Rise
Hold Time
t
CSH
6/MAX537
SDI Setup Time
SDI Hold Time
t
40
0
26
ns
ns
DS
t
DH
SDO high
78
50
81
53
105
80
1kΩ pull-up on SDO
to V
SCK Rise to SDO Valid
Propagation Delay (Note 6)
t
ns
DO1
DO2
=
DD,
C
50pF
1kΩ pull-up on SDO
to V
SDO low
SDO high
SDO low
LOAD
110
85
SCK Fall to SDO Valid
Propagation Delay (Note 7)
t
ns
ns
ns
=
DD,
C
50pF
OAD
L
CS Fall to SDO Enable
(Note 8)
t
27
40
45
60
DV
CS Rise to SDO Disable
(Note 9)
t
TR
t
Continuous SCK, SCK edge ignored
SCK edge ignored
20
20
ns
ns
SCK Rise to CS Fall Delay
CS0
CS1
CS Rise to SCK Rise
Hold Time
t
t
30
40
ns
ns
LDAC Pulse Width Low
CS Pulse Width High
LDAC
t
CSW
Note 1: TUE is specified with no resistive load.
Note 2: Guaranteed by design.
Note 3: Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC
.
Note 4: Digital inputs at 2.4V; with digital inputs at CMOS levels, I
DD decreases slightly.
Note 5: All input signals are specified with t
= t ≤ 5ns. Logic input swing is 0V to 5V.
R
F
Note 6: Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO
pin has an internal active pull-up.)
Note 7: Serial data clocked out of SDO on SCK’s rising edge.
Note 8: SDO changes from High-Z state to 90% of final value.
Note 9: SDO rises 10% toward High-Z state.
4
_______________________________________________________________________________________
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
6/MAX537
ELECTRICAL CHARACTERISTICS—MAX537
(V = +5V, V = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, R = 5kΩ, C = 100pF, T = T
to T , unless
MAX
DD
SS
L
L
A
MIN
otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE—ANALOG SECTION
Resolution
N
12
Bits
LSB
LSB
MAX537A
MAX537B
±0.15
±0.50
±1
Integral Nonlinearity
Differential Nonlinearity
INL
DNL
Guaranteed monotonic
±1
MAX537A
±3.0
±6.0
±6.0
±9.0
±7.0
±11.0
±9.0
±15.0
±1.5
±3.0
T
= +25°C
A
MAX537B
MAX537AC
MAX537BC
MAX537AE
MAX537BE
MAX537AM
MAX537BM
Offset Error
mV
T
A
= T to T
MIN MAX
R = ∞
-0.3
-0.8
L
Gain Error
LSB
R = 5kΩ
L
V
Power-Supply
DD
T
= +25°C, 4.5V ≤ V ≤ 5.5V
PSRR
PSRR
A
±0.01
±0.02
±0.5
±0.7
LSB/V
LSB/V
DD
Rejection Ratio
V
Power-Supply
SS
T
A
= +25°C, -5.5V ≤ V ≤ -4.5V
SS
Rejection Ratio
MATCHING PERFORMANCE (T = +25°C)
A
Gain Error
±0.1
±0.3
±1.25
±3.0
±6.0
±1.0
LSB
mV
MAX537A
MAX537B
Offset Error
±0.3
Integral Nonlinearity
INL
±0.35
LSB
REFERENCE INPUT
Reference Input Range
Reference Input Resistance
REF
0.0
5
V
DD
- 2.2
V
kΩ
RREF
Code dependent, minimum at code 555 hex
MULTIPLYING-MODE PERFORMANCE
Reference 3dB Bandwidth
V
= 2Vp-p
700
-100
-82
kHz
dB
REF
V
= 10V
p-p
REF
at 400Hz
Reference Feedthrough
Input code = all 0s
V
REF
= 10Vp-p at 4kHz
Total Harmonic Distortion
Plus Noise
THD + N
V
REF
= 850mVp-p at 100kHz
0.024
%
DIGITAL INPUTS (SDI, SCK, CS, LDAC)
Input High Voltage
V
2.4
V
V
IH
Input Low Voltage
V
IL
0.8
µA
pF
Input Leakage Current
Input Capacitance (Note 2)
V
IN
= 0V or V
1.0
10
DD
_______________________________________________________________________________________
5
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
ELECTRICAL CHARACTERISTICS—MAX537 (continued)
(V = +5V, V = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, R = 5kΩ, C = 100pF, T = T
to T , unless
MAX
DD
SS
L
L
A
MIN
otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
DIGITAL OUTPUT (SDO)
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
OH
SDO sourcing 2mA
SDO sinking 2mA
V
– 0.5
V – 0.25
DD
V
V
DD
V
OL
0.13
0.40
DYNAMIC PERFORMANCE (R = 5kΩ, C = 100pF)
L
L
V/µs
µs
Voltage-Output Slew Rate
Output Settling Time
5
5
5
5
1
To ± ⁄ LSB of full scale
2
Digital Feedthrough
nV-s
nV-s
Digital Crosstalk (Note 3)
POWER SUPPLIES
6/MAX537
Positive Supply Range
Negative Supply Range
V
4.5
5.5
-5.5
12
V
V
DD
V
SS
-4.5
T
= +25°C
5.5
A
Positive Supply Current
(Note 4)
I
DD
mA
mA
T
A
= T
to T
16
MIN
MAX
T
A
= +25°C
-4.7
-10
-14
Negative Supply Current
(Note 4)
I
SS
T
A
= T
to T
MIN
MAX
TIMING CHARACTERISTICS (Note 5)
Internal Power-On Reset
Pulse Width (Note 2)
µs
ns
ns
t
50
POR
SCK Clock Period
t
CP
100
35
40
35
40
40
50
MAX537_C/E
MAX537_M
MAX537_C/E
MAX537_M
MAX537_C/E
MAX537_M
SCK Pulse Width High
SCK Pulse Width Low
t
CH
t
ns
CL
CS Fall to SCK Rise
Setup Time
t
ns
ns
CSS
CSH
SCK Rise to CS Rise
Hold Time
t
0
MAX537_C/E
MAX537_M
40
50
0
24
SDI Setup Time
SDI Hold Time
t
ns
ns
ns
DS
t
DH
MAX537_C/E
MAX537_M
MAX537_C/E
MAX537_M
116
123
200
230
210
250
SCK Rise to SDO Valid
Propagation Delay (Note 6)
t
t
C
C
= 50pF
DO1
DO2
LOAD
LOAD
SCK Fall to SDO Valid
Propagation Delay (Note 7)
= 50pF
ns
6
_______________________________________________________________________________________
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
6/MAX537
ELECTRICAL CHARACTERISTICS—MAX537 (continued)
(V = +5V, V = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, R = 5kΩ, C = 100pF, T = T
to T , unless
MAX
DD
SS
L
L
A
MIN
otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX537_C/E
MAX537_M
MAX537_C/E
MAX537_M
MAX537_C/E
MAX537_M
MAX537_C/E
MAX537_M
75
140
170
130
165
t
C
C
= 50pF
= 50pF
ns
CS Fall to SDO Enable
DV
LOAD
LOAD
70
CS Rise to SDO Disable
(Note 10)
t
ns
ns
ns
ns
ns
TR
35
40
Continuous SCK,
SCK edge ignored
t
t
SCK Rise to CS Fall Delay
CS0
CS1
35
CS Rise to SCK Rise
Hold Time
SCK edge ignored
40
MAX537_C/E
MAX537_M
MAX537_C/E
MAX537_M
50
t
LDAC Pulse Width High
CS Pulse Width High
LDAC
70
100
125
t
CSW
Note 2: Guaranteed by design.
Note 3: Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC
.
Note 4: Digital inputs at 2.4V; with digital inputs at CMOS levels, I
DD decreases slightly.
Note 5: All input signals are specified with t
= t ≤ 5ns. Logic input swing is 0V to 5V.
R
F
Note 6: Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO
pin has an internal active pull-up.)
Note 7: Serial data clocked out of SDO on SCK’s rising edge.
Note 10: When disabled, SDO is internally pulled high.
_______________________________________________________________________________________
7
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(T = +25°C, unless otherwise noted.)
A
MAX5 3 6
MAX536
MAX536
MAX536
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. REFERENCE FREQUENCY
INTEGRAL NONLINEARITY
ERROR vs. REFERENCE VOLTAGE
1.0
20
10
0.200
REFAB SWEPT 2Vp-p
MONITORED
V
= -5V
DAC CODE = ALL 1s
REFAB = 10Vp-p
SS
V
OUTA
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
0.6
0.2
0
R = 10kΩ, C = 100pF
L
L
V
= +15V
DD
-10
R = NO LOAD, C = 0pF
L
-20
-30
L
-0.2
V
= +12V
DD
--0.6
-40
-50
6/MAX537
-1.0
1k
10k
100k
1M
10M
0
4
8
12
16
10
100
200
FREQUENCY (Hz)
REFERENCE VOLTAGE (V)
FREQUENCY (kHz)
MAX536
MAX536
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. REFERENCE FREQUENCY
MAX536
FULL-SCALE ERROR vs. LOAD
SUPPLY CURRENT vs. TEMPERATURE
10
6
0.200
1
0
DAC CODE = ALL 1s
REFAB = 5Vp-p
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
I
DD
V
V
SS
= +15V
= -5V
DD
-1
-2
-3
2
R = 10kΩ, C = 100pF
L
L
-2
R = NO LOAD, C = 0pF
L
L
I
SS
-6
-4
-5
-10
100
10
100
200
0.1
1
10
100
1000
60
20
TEMPERATURE (°C)
140
-60
-20
FREQUENCY (kHz)
LOAD (kΩ)
MAX536
MAX536
REFERENCE FEEDTHROUGH AT 400Hz
REFERENCE FEEDTHROUGH AT 4kHz
REFAB,
5V/div
REFAB,
5V/div
0V
0V
OUTA,
100µV/div
OUTA,
200µV/div
500µs/div
50µs/div
INPUT CODE = ALL 0s
INPUT CODE = ALL 0s
8
_______________________________________________________________________________________
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
6/MAX537
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(T = +25°C, unless otherwise noted.)
A
MAX5 3 6
MAX536
MAX536
NEGATIVE FULL-SCALE SETTLING TIME
(ALL BITS ON TO ALL BITS OFF)
DYNAMIC RESPONSE (ALL BITS ON, OFF, ON)
CS,
5V/div
CS,
5V/div
OUTA,
5V/div
OUTA,
2V/div
OUTA,
5mV/div
5µs/div
1µs/div
V
= +15V, V = -5V, REFAB = 5V, C = 100pF, R = 10kΩ
V
= +15V, V = -5V, REFAB = 10V, C = 100pF, R = 10kΩ
DD
SS
L
L
DD
SS
L
L
MAX536
MAX536
DIGITAL FEEDTHROUGH
POSITIVE FULL-SCALE SETTLING TIME
(ALL BITS OFF TO ALL BITS ON)
CS,
5V/div
SCK,
5V/div
OUTA,
5V/div
OUTA,
-10V OFFSET
5mV/div
OUTA,
AC-COUPLED,
10mV/div
1µs/div
V
= +15V, V = -5V, REFAB = 10V, CS = HIGH,
SS
V
= +15V, V = -5V, REFAB = 10V, C = 100pF, R = 10kΩ
DD
DD
SS
L
L
1
DIN TOGGLING AT ⁄ THE CLOCK RATE,
2
OUTA = 5V
_______________________________________________________________________________________
9
Ca lib ra t e d , Qu a d , 1 2 -Bit
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____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(T = +25°C, unless otherwise noted.)
A
MAX5 3 7
MAX537
INTEGRAL NONLINEARITY
ERROR vs. REFERENCE VOLTAGE
2.0
MAX537
MAX537
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
20
10
0.200
REFAB SWEPT 2Vp-p
REFAB = 2.5Vp-p
V
= +5V
= -5V
DD
V
OUTA
MONITORED
1.5
1.0
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
V
SS
0
0.5
0
-10
R = 10kΩ, C = 100pF
L
L
-20
-30
-0.5
-1.0
-1.5
-2.0
R = NO LOAD, C = 0pF
L
L
-40
-50
6/MAX537
1k
10k
100k
1M
10M
10
100
200
0
1
2
3
4
5
FREQUENCY (Hz)
FREQUENCY (kHz)
V
REF
(V)
MAX537
MAX537
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
MAX537
FULL-SCALE ERROR vs. LOAD
SUPPLY CURRENT vs. TEMPERATURE
2
1
5
3
0.200
REFAB = 1Vp-p
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
I
DD
V
V
SS
= +5V
= -5V
DD
0
1
-1
R = 10kΩ, C = 100pF
L
L
-1
-2
-3
-4
I
SS
-3
-5
R = NO LOAD, C = 0pF
L
L
100
60
20
TEMPERATURE (°C)
140
10
100
200
0.1
1
10
100
1000
-60
-20
FREQUENCY (kHz)
LOAD (kΩ)
MAX537
MAX537
REFERENCE FEEDTHROUGH AT 4kHz
REFERENCE FEEDTHROUGH AT 400Hz
REFAB,
1V/div
REFAB,
1V/div
0V
0V
OUTA,
OUTA,
AC-COUPLED,
100µV/div
AC-COUPLED,
100µV/div
50µs/div
500µs/div
INPUT CODE = ALL 0s
INPUT CODE = ALL 0s
10 ______________________________________________________________________________________
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
6/MAX537
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(T = +25°C, unless otherwise noted.)
A
MAX5 3 7
MAX537
NEGATIVE FULL-SCALE SETTLING TIME
(ALL BITS ON TO ALL BITS OFF)
MAX537
DYNAMIC RESPONSE (ALL BITS ON, OFF, ON)
CS,
5V/div
CS,
5V/div
OUTA,
5mV/div
OUTA,
1V/div
1µs/div
5µs/div
V
= +5V, V = -5V, REFAB = 2.5V, C = 100pF, R = 10kΩ
V
= +5V, V = -5V, REFAB = 2.5V, C = 100pF, R = 10kΩ
DD
SS
L
L
DD
SS
L
L
MAX537
MAX537
DIGITAL FEEDTHROUGH
POSITIVE FULL-SCALE SETTLING TIME
(ALL BITS OFF TO ALL BITS ON)
CS,
5V/div
SCK,
5V/div
OUTA,
OUTA,
AC-COUPLED,
20mV/div
5mV/div
100ns/div
1µs/div
V
= +5V, V = -5V, REFAB = 2.5V, CS = HIGH,
SS
V
= +5V, V = -5V, REFAB = 2.5V, C = 100pF, R = 10kΩ
DD
DD
SS
L
L
1
DIN TOGGLING AT ⁄ THE CLOCK RATE,
2
OUTA = 1.25V
______________________________________________________________________________________ 11
Ca lib ra t e d , Qu a d , 1 2 -Bit
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______________________________________________________________P in De s c rip t io n
PIN
1
NAME
OUTB
OUTA
FUNCTION
DAC B Output Voltage
DAC A Output Voltage
Negative Power Supply
Analog Ground
2
3
V
SS
4
AGND
REFAB
DGND
5
Reference Voltage Input for DAC A and DAC B
Digital Ground
6
Load DAC Input (active low). Driving this asynchronous input low transfers the contents of all input
registers to their respective DAC registers.
7
8
LDAC
SDI
Serial Data Input. Data is shifted into an internal 16-bit shift register on SCK's rising edge.
Chip-Select Input (active low). A low level on CS enables the input shift register and SDO.
On CS’s rising edge, data is latched into the appropriate register(s).
6/MAX537
9
CS
10
11
SCK
SDO
Shift Register Clock Input
Serial Data Output. SDO is the output of the internal shift register. SDO is enabled when CS is low.
For the MAX536, SDO is an open-drain output. For the MAX537, SDO has an active pull-up to V
.
DD
12
13
14
15
16
REFCD
TP
Reference Voltage Input for DAC C and DAC D
Test Pin. Connect to V for proper operation.
DD
V
DD
Positive Power Supply
DAC D Output Voltage
DAC C Output Voltage
OUTD
OUTC
_______________De t a ile d De s c rip t io n
The MAX536/MAX537 contain four 12-bit voltage-output
DACs that are easily addressed using a simple 3-wire
serial interface. They include a 16-bit data-in/data-out
shift register, and each DAC has a double-buffered
input composed of an input register and a DAC register
(see the Functional Diagram on the front page).
R
R
R
V
OUT
2R
2R
2R
D9
2R
2R
D11
D0
D10
The DACs are “inverted” R-2R ladder networks that
convert 12-bit digital inputs into equivalent analog out-
put voltages in proportion to the applied reference-volt-
age inputs. DAC A and DAC B share the REFAB refer-
ence input, while DAC C and DAC D share the REFCD
reference input. The two reference inputs allow different
full-scale output voltage ranges for each pair of DACs.
Figure 1 shows a simplified circuit diagram of one of
the four DACs.
REF
AGND
SHOWN FOR ALL 1s ON DAC
Figure 1. Simplified DAC Circuit Diagram
Re fe re n c e In p u t s
The two reference inputs accept positive DC and AC
s ig na ls . The volta g e a t e a c h re fe re nc e inp ut s e ts
the full-scale output voltage for its two correspond-
ing DACs. The REFAB/REFCD voltage range is 0V to
a digitally programmable voltage source as:
= N (V / 4096
V
OUT_
B
REF)
where N is the numeric value of the DAC’s binary input
B
(V - 4V) for the MAX536 and 0V to (V - 2.2V) for the
DD
DD
code (0 to 4095) and V
is the reference voltage.
REF
MAX537. The output voltages V _ are represented by
OUT
12 ______________________________________________________________________________________
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6/MAX537
The input impedance at each reference input is code
dependent, ranging from a low value of typically 6kΩ
(with an input code of 0101 0101 0101) to a high value
of 60kΩ (with an input code of 0000 0000 0000). Since
the input impe d a nc e a t the re fe re nc e p ins is c ode
dependent, load regulation of the reference source is
important.
Ou t p u t Bu ffe r Am p lifie rs
All MAX536/MAX537 volta g e outp uts a re inte rna lly
buffered by precision unity-gain followers with a typical
slew rate of 5V/µs for the MAX536 and 3V/µs for the
MAX537.
With a full-scale transition at the MAX536 output (0V to
10V or 10V to 0V), the typical settling time to ±1/2LSB is
3µs when loaded with 5kΩ in parallel with 100pF (loads
less than 5kΩ degrade performance).
The REFAB and REFCD reference inputs have a 5kΩ
guaranteed minimum input impedance. When the two
reference inputs are driven from the same source, the
effective minimum impedance becomes 2.5kΩ. A volt-
age reference with a load regulation of 0.001%/mA,
s uc h a s the MAX674, would typ ic a lly d e via te b y
0.164LSB (0.328LSB worst case) when simultaneously
driving both MAX536 reference inputs at 10V.
With a full-scale transition at the MAX537 output (0V to
2.5V or 2.5V to 0V), the typical settling time to ±1/2LSB
is 5µs when loaded with 5kΩ in parallel with 100pF
(loads less than 5kΩ degrade performance).
Output dynamic responses and settling performances
of the MAX536/MAX537 output amplifier are shown in
the Typical Operating Characteristics.
An op amp, such as the MAX400 or OP07, can be used
to buffer the reference to increase reference accuracy.
The op amp’s closed-loop output impedance should be
ke p t b e low 0.05Ω to e ns ure a n e rror of le s s tha n
0.08LSB. Reference accuracy is also improved by driv-
ing the REFAB and REFCD pins separately, or by using
a reference with excellent accuracy and superior load
regulation, such as the MAX676/MAX677/MAX678.
Se ria l-Inte rfa c e Configura tions
The MAX536/MAX537’s 3-wire or 4-wire serial interface is
compatible with both Microwire (Figure 2) and SPI/QSPI
(Figure 3). In Figures 2 and 3, LDAC can be tied either
high or low for a 3-wire interface, or used as the fourth
input with a 4-wire interface. The connection between
SDO and the serial-interface port is not necessary, but
may be used for data echo. (Data held in the shift register
The reference input capacitance is also code depen-
dent and typically ranges from 125pF to 300pF.
5V
5V
†
†
R
P
1k
R
P
1k
SS
SDO*
MISO*
SCK
SK
SDI
MOSI
SCK
SDI
SO
SI*
SPI/QSPI
PORT
MAX536
MAX537
SCK
MAX536
MAX537
MICROWIRE
PORT
SDO*
CS
I/O
I/O
CS
I/O
I/O
LDAC**
LDAC**
CPOL = 0, CPHA = 0
*THE SDO-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX536,
BUT MAY BE USED FOR READBACK PURPOSES.
*THE SDO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX536,
BUT MAY BE USED FOR READBACK PURPOSES.
**THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE.
**THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE.
†
†
THE MAX537 HAS AN INTERNAL ACTIVE PULL-UP TO V
DD,
THE MAX537 HAS AN INTERNAL ACTIVE PULL-UP TO V
DD,
SO R IS NOT NECESSARY.
P
SO R IS NOT NECESSARY.
P
Figure 2. Connections for Microwire
Figure 3. Connections for SPI/QSPI
_______________________________________________________________________________________ 13
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
CS
COMMAND
EXECUTED
SCK
1
8
9
16
SDI
D2 D1 D0
..........
..........
D15 D14 D13
MSB
LSB
SDO
...........
Q15
..........
Q0
MSB FROM
PREVIOUS WRITE
LSB FROM
PREVIOUS WRITE
Figure 4. 3-Wire Serial-Interface Timing Diagram (LDAC = GND or V
)
DD
6/MAX537
CS
SCK
SDI
INPUT REGISTER(S)
UPDATED
1
8
9
16
..........D2 D1 D0
D15 D14 D13..........
MSB
LSB
SDO
..........
Q15
Q0
..........
MSB FROM
PREVIOUS WRITE
LSB FROM
PREVIOUS WRITE
LDAC
DACs
UPDATED
Figure 5. 4-Wire Serial-Interface Timing Diagram for Asynchronous DAC Updating Using LDAC
t
CSW
CS
t
CP
t
t
t
CH
CSH
CSS
t
t
CL
CSO
t
CSI
SCK
t
DS
t
DH
SDI
t
DO2
t
DV
t
TR
t
DO1
SDO
LDAC*
*USE OF LDAC IS OPTIONAL
t
LDAC
Figure 6. Detailed Serial-Interface Timing Diagram
14 ______________________________________________________________________________________
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
6/MAX537
of the MAX536/MAX537 can be shifted out of SDO and
returned to the microprocessor for data verification; data
in the MAX536/MAX537 input/DAC registers cannot be
read.)
clocked into the internal shift register via the serial data input
pin (SDI) on SCK’s rising edge. The maximum guaranteed
clock frequency is 10MHz. Data is latched into the appropri-
ate MAX536/MAX537 input/DAC registers on CS’s rising
edge.
With a 3-wire interface (CS, SCK, SDI) and LDAC tied
hig h, the DACs a re d oub le -b uffe re d . In this mod e ,
depending on the command issued through the serial
inte rfa c e , the inp ut re g is te r(s ) ma y b e loa d e d
without affecting the DAC register(s), the DAC register(s)
can be loaded directly, or all four DAC registers may be
simultaneously updated from the input registers. With a 3-
wire interface (CS, SCK, SDI) and LDAC tied low (Figure
4), the DAC registers remain transparent. Any time an
input register is updated, the change appears at the DAC
output with the rising edge of CS.
Interface timing is optimized when serial data is clocked out
of the microcontroller/microprocessor on one clock edge
and clocked into the MAX536/MAX537 on the other edge.
Table 1 lists the serial-interface programming commands.
For certain commands, the 12 data bits are “don’t cares”.
The programming command Load-All-DACs-From-Shift-
Register allows all input and DAC registers to be simultane-
ously loaded with the same digital code from the input shift
register. The NOP (no operation) command allows the regis-
te r c onte nts to b e una ffe c te d a nd is us e ful whe n the
MAX536/MAX537 are configured in a daisy-chain (see the
Daisy-Chaining Devices section). The command to change
the clock edge on which serial data is shifted out of the
MAX536/MAX537 SDO pin also loads data from all input reg-
isters to their respective DAC registers.
The 4-wire interface (CS, SCK, SDI, LDAC) is similar to
the 3-wire interface with LDAC tied high, except LDAC is
a hardware input that simultaneously and asynchronously
loads all DAC registers from their respective input regis-
ters when driven low (Figure 5).
Se ria l-Inte rfa c e De s c ription
The MAX536/MAX537 require 16 bits of serial data. Data is
sent MSB first and can be sent in two 8-bit packets or one
16-bit word (CS must remain low until 16 bits are trans-
ferred). The serial data is composed of two DAC address
bits (A1, A0), two control bits (C1, C0), and the 12 data bits
D11…D0 (Figure 7). The 4-bit address/control code deter-
mines the following: 1) the register(s) to be updated and/or
the status of the input and DAC registers (i.e., whether they
are in transparent or latch mode), and 2) the edge on which
data is clocked out of SDO.
Se ria l-Da ta Output
The serial-data output, SDO, is the internal shift register’s
output. The MAX536/MAX537 can be programmed so that
data is clocked out of SDO on SCK’s rising (Mode 1) or
falling (Mode 0) edge . In Mode 0, output data at SDO lags
input data at SDI by 16.5 clock cycles, maintaining compati-
bility with Microwire, SPI/QSPI, and other serial interfaces. In
Mode 1, output data lags input data by 16 clock cycles. On
power-up, SDO defaults to Mode 1 timing.
For the MAX536, SDO is an open-drain output that should be
pulled up to +5V. The data sheet timing specifications for
SDO use a 1kΩ pull-up resistor. For the MAX537, SDO is a
complementary output and does not require an external
pull-up.
MSB ..................................................................................LSB
16 Bits of Serial Data
Address
Bits
Control
Bits
Data Bits
Te s t Pin
MSB.............................................LSB
The test pin (TP) is used for pre-production analysis of the IC.
A1 A0 C1 C0 D11................................................D0
Connect TP to V for proper MAX536/MAX537 operation.
DD
Failure to do so affects DAC operation.
4 Address/
12 Data Bits
Control Bits
Da is y-Cha ining De vic e s
Any number of MAX536/MAX537s can be daisy-chained by
connecting the SDO pin of one device (with a pull-up resis-
tor, if appropriate) to the SDI pin of the following device in the
chain (Figure 8).
Figure 7. Serial-Data Format (MSB Sent First)
Figure 6 shows the serial-interface timing requirements. The
chip-select pin (CS) must be low to enable the DAC’s serial
interface. When CS is high, the interface control circuitry is
disabled and the serial data output pin (SDO) is driven high
(MAX537) or is a high-impedance open drain (MAX536). CS
must go low at least tCSS before the rising serial clock (SCK)
edge to properly clock in the first bit. When CS is low, data is
Since the MAX537’s SDO pin has an internal active pull-up,
the SDO sink/source capability determines the time required
to discharge/charge a capacitive load. Refer to the serial
data out V
and V
specifications in the Electrical
OH
OL
Characteristics.
______________________________________________________________________________________ 15
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD
LDAC
FUNCTION
A1
0
A0
0
C1
0
C0
1
D11…D0
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
XXXXXXXXXXXX
XXXXXXXXXXXX
1
1
1
1
1
1
1
1
X
X
1
Load DAC A input register; DAC output unchanged.
Load DAC B input register; DAC output unchanged.
Load DAC C input register; DAC output unchanged.
Load DAC D input register; DAC output unchanged.
Load input register A; all DAC registers updated.
Load input register B; all DAC registers updated.
Load input register C; all DAC registers updated.
Load input register D; all DAC registers updated.
Load all DACs from shift register.
0
1
0
1
1
0
0
1
1
1
0
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
1
6/MAX537
X
X
0
0
0
0
1
0
0
No operation (NOP)
X
1
0
Update all DACs from their respective input registers.
Mode 1 (default condition at power-up), DOUT clocked out on
SCK’s rising edge. All DACs updated from their respective
input registers.
1
1
1
0
1
1
0
0
XXXXXXXXXXXX
XXXXXXXXXXXX
X
X
Mode 0, DOUT clocked out on SCK’s falling edge. All DACs
updated from their respective input registers.
0
0
1
1
0
1
0
1
X
X
X
X
1
1
1
1
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
0
0
0
0
Load DAC A input register; DAC A is immediately updated.
Load DAC B input register; DAC B is immediately updated.
Load DAC C input register; DAC C is immediately updated.
Load DAC D input register; DAC D is immediately updated.
“X” = Don’t Care. LDAC provides true latch control: when LDAC is low, the DAC registers are transparent; when LDAC is high,
the DAC registers are latched.
Additionally, when daisy-chaining devices, the maximum
clock frequency is limited to:
Whe n d a is y-c ha ining MAX536s , the d e la y from CS
low to SCK high (t ) must be the greater of:
CSS
t
+ t
DV DS
1
f
(max) = ——————————————
SCK
or
2 (t
+ t - 38ns + t
)
DO
RC
DS
t
+ t + t - t
RC DS CSW
TR
For e xa mp le , with t
= 23ns (5V ± 10% s up p ly with
RC
where t is the time constant of the external pull-up resistor
(R ) and the load capacitance (C) at SDO. For t < 20ns,
RC
R = 1kΩ and C = 30pF), the maximum clock frequency is
p
p
CSS
RC
8.7MHz.
t
is simply t + t . Calculate t from the following
DV DS RC
Figure 9 shows an alternate method of connecting several
MAX536/MAX537s. In this configuration, the data bus is
common to all devices; data is not shifted through a
daisy-chain. More I/O lines are required in this configu-
ration because a dedicated chip-select input (CS) is
required for each IC.
equation:
V
PULL-UP
t
= R (C) ln
RC
p
(
)
]
[
V
- 2.4V
PULL-UP
where V
is the voltage to which the pull-up resistor is
PULL-UP
connected.
16 ______________________________________________________________________________________
Ca lib ra t e d , Qu a d , 1 2 -Bit
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6/MAX537
+5V
+5V
+5V
R *
P
1k
R *
P
1k
R *
P
1k
MAX536
MAX537
MAX536
MAX537
MAX536
MAX537
SCK
SDI
CS
SCK
SDI
CS
SCK
SDI
CS
SCK
DIN
SDO
SDO
SDO
CS
TO OTHER
SERIAL DEVICES
* THE MAX537 HAS AN ACTIVE INTERNAL PULL-UP, SO R IS NOT NECESSARY.
P
Figure 8. Daisy-Chaining MAX536/MAX537s with a 3-Wire Serial Interface
DIN
SCK
LDAC
CS1
CS2
TO OTHER
SERIAL DEVICES
CS3
CS
CS
CS
LDAC
LDAC
LDAC
MAX536
MAX537
MAX536
MAX537
MAX536
MAX537
SCK
SDI
SCK
SDI
SCK
SDI
Figure 9. Multiple devices sharing a common DIN line may be simultaneously updated by bringing LDAC low. CS1, CS2, CS3… are
driven separately, thus controlling which data are written to devices 1, 2, 3…
______________________________________________________________________________________ 17
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
Bits 6 and 7 are not used. Writes to these bits are ignored.
__________Ap p lic a t io n s In fo rm a t io n
The PORT D Data Direction Register (DDRD) deter-
mines whether the port bits are inputs or outputs. Its
configuration is shown below:
In t e rfa c in g t o t h e M6 8 HC1 1 *
PORT D of the 68HC11 supports SPI. The four registers
used for SPI operation are the Serial Peripheral Control
Register, the Serial Peripheral Status Register, the Serial
Peripheral Data I/O Register, and PORT D’s Data Direction
Register. These registers have a default starting location of
$1000.
BIT
7
6
5
4
3
2
1
0
NAME
–
–
DDD5 DDD4 DDD3 DDD2 DDD1 DDD0
On reset, the PORT D register (memory location $1008) is
cleared and bits 5-0 are configured as general-purpose
inputs. Setting bit 6 (SPE) of the Serial Peripheral Control
Register (SPCR) configures PORT D for SPI as follows:
Setting DDD_ = 0 configures the port bit as an input, while
setting DDD_ = 1 configures the port bit as an output. Writes
to bits 6 and 7 have no effect.
In SPI mode with MSTR = 1, when a PORT D bit is expected
to be an input (SS, MISO, RXD), the corresponding DDRD bit
(DDD_) is ignored. If the bit is expected to be an output
(SCK, MOSI, TXD), the corresponding DDRD bit must be
set for the bit to be an output.
BIT
7
NAME
–
6
5
4
3
2
1
0
6/MAX537
–
SS
SCK MOSI MISO TXD RXD
Table 2. Serial Peripheral Control-Register Definitions
NAME
DEFINITION
Serial Peripheral Interrupt Enable. Clearing SPIE disables the SPI hardware-interrupt request; the SPSR is polled to
determine when an SPI data transfer is complete. Setting SPIE requests a hardware interrupt when the Serial Peripheral
Status Register’s SPIF bit or MODF bit is set.
SPIE
Setting SPE (Serial Peripheral System Enable) configures PORT D for SPI. Clearing SPE configures the port as a general-
purpose I/O port.
SPE
DWOM
MSTR
When DWOM is set, the six PORT D outputs are open drain. When DWOM is cleared, the outputs are complementary.
Master/Slave select option
Determines clock polarity. When set, the serial clock idles high while data is not being transferred; when cleared, the
clock idles low.
CPOL
CPHA
Determines the clock phase.
SPI Clock-Rate Select
SPR1
SPR0
0
0
1
1
0
1
0
1
µP clock divided by 2
µP clock divided by 4
µP clock divided by 16
µP clock divided by 32
SPR1/0
Table 3. Serial Peripheral Status-Register Definitions
NAME
DEFINITION
SPIF
SPIF is set when an SPI data transfer is complete. It is cleared by reading the SPSR and then accessing the SPDR.
The Write Collision flag is set when a write to the SPDR occurs while a data transfer is in progress. It is cleared by read-
ing the SPSR and then accessing the SPDR.
WCOL
MODF
The Mode Fault flag detects master/slave conflicts in a multimaster environment. It is set when the “master” controller
has its SS line (PORT D) pulled low, and cleared by reading the SPSR followed by a write to the SPCR.
*M68HC11 is a Motorola microcontroller. General information about the device was obtained from M68HC11 technical manuals.
18 ______________________________________________________________________________________
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
6/MAX537
Table 4. M68HC11 Programming Code
______________________________________________________________________________________ 19
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
Un ip o la r Ou t p u t
SS is an input intended for use in a multimaster environ-
ment. However, SS or unused PORT D bit RXD, TXD, or
possibly MISO (if DAC readback is not used) should be
configured as a general-purpose output and used as CS by
setting the appropriate Data Direction Register bit.
For a unipolar output, the output voltages and the reference
inputs are the same polarity. Figure 10 shows the
MAX536/MAX537 unipolar output circuit, which is also the typ-
ical operating circuit. Table 5 lists the unipolar output codes.
The SPCR configuration (memory location $1028) is shown
below:
Bip o la r Ou t p u t
The MAX536/MAX537 outputs can be configured for
bipolar operation using Figure 11’s circuit. One op amp
and two resistors are required per DAC. With R1 = R2:
BIT
7
6
5
4
3
2
1
0
V
OUT
= V
[(2N / 4096) - 1]
REF B
NAME
SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0
where N is the numeric value of the DAC’s binary
B
input code. Table 6 shows digital codes and corre -
sponding output voltages for Figure 11’s circuit.
SETTING AFTER RESET
0
0
0
0
0
1
U*
SETTING FOR TYPICAL SPI COMMUNICATION
0** 1**
U*
Table 5. Unipolar Code Table
6/MAX537
0
1
0
1
0
0
DAC CONTENTS
ANALOG OUTPUT
*U = Unknown
**Depends on µP clock frequency.
MSB
LSB
4095
( ——— )
4096
1 1 1 1
1 1 1 1 1 1 1 1
+V
REF
Always configure the 68HC11 as the “master” controller
and the MAX536/MAX537 as the “slave” device.
2049
( ——— )
4096
1000
1 0 0 0
0 1 1 1
0000
0001
+V
REF
Whe n MSTR = 1 in the SPCR, a write to the Se ria l
Peripheral Data I/O Register (SPDR), located at memory
location $102A, initiates the transmission/reception of
data. The data transfer is monitored and the appropri-
a te fla g s a re s e t in the Se ria l Pe rip he ra l Sta tus
Register (SPSR).
2048
+VREF
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
+V
REF
( ——— ) = ————
4096
2
2047
+V
( ——— )
4096
REF
The SPSR configuration is shown below:
1
BIT
7
0 0 0 0
0 0 0 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
+V
( ——— )
4096
REF
6
5
4
3
–
0
2
–
0
1
–
0
0
–
0
0V
NAME
SPIF WCOL
–
MODF
RESET CONDITIONS
0
Table 6. Bipolar Code Table
0
0
0
DAC CONTENTS
ANALOG OUTPUT
MSB
LSB
An e xa mp le of 68HC11 p rog ra mming c od e for a
two-byte SPI transfer to the MAX536/MAX537 is given in
Table 4. SS is used for CS, the high byte of MAX536/
MAX537 digital data is stored in memory location $0100,
and the low byte is stored in memory location $0101.
2047
1 1 1 1
1 1 1 1 1 1 1 1
+V
( ——— )
2048
REF
1
1000
1 0 0 0
0 1 1 1
0000
0001
+V
( ——— )
2048
REF
In t e rfa c in g t o Ot h e r Co n t ro lle rs
When using Microwire, refer to the section on Inter-
facing to the M68HC11 for guidance, since Microwire
can be considered similar to SPI when CPOL = 0 and
CPHA = 0. When interfacing to Intel’s 80C51/80C31
microcontroller family, use bit-pushing to configure a
desired port as the MAX536/MAX537 interface port. Bit-
pushing involves arbitrarily assigning I/O port bits as
interface control lines, and then writing to the port each
time a signal transition is required.
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0V
1
-V
REF
( ——— )
2048
2047
( ——— )
2048
0 0 0 0
0 0 0 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
1
-V
REF
2048
( ——— ) = -V
-V
REF
REF
2048
NOTE: 1LSB = (V ) (
)
REF
4096
20 ______________________________________________________________________________________
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
6/MAX537
+15V (+5V)
REFERENCE INPUTS
MAX536
MAX537
MAX536
MAX537
13
TP
5
12
REFCD
14
V
REFAB
DD
R1
R2
V
REF
2
DAC A
DAC B
OUTA
OUTB
+15V (+5V)
1
V
OUT
DAC
OUTPUT
16
15
DAC C
DAC D
OUTC
OUTD
–5V
R1 = R2 = 10kΩ 0.1%
V
AGND
4
DGND
6
SS
NOTES: ( ) ARE FOR MAX537.
IS THE SELECTED REFERENCE INPUT FOR THE MAX536/MAX537.
3
V
REF
-5V
NOTE: ( ) ARE FOR MAX537.
Figure 10. Unipolar Output Circuit
Figure 11. Bipolar Output Circuit
+15V
(+5V)
+15V (+5V)
14
AC
REFERENCE
INPUT
15k
5
13
TP
+4V (+750mV)
REFAB
V
DD
5
14
13
TP
10k
REFAB
V
DD
+
-4V
V
(-750mV)
IN
2
DAC A
OUTA
-
1
DAC B
OUTB
AGND
4
MAX536/MAX537
MAX536/MAX537
+
V
DGND
6
SS
V
SS
AGND
DGND
V
BIAS
3
3
4
6
-
-5V
-5V
NOTES: ( ) ARE FOR MAX537.
DIGITAL INPUTS NOT SHOWN.
NOTES: ( ) ARE FOR MAX537.
DIGITAL INPUTS NOT SHOWN.
Figure 12. AC Reference Input Circuit
Figure 13. AGND Bias Circuit
______________________________________________________________________________________ 21
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
Offs e t t in g AGND
AGND can be biased from DGND to the reference voltage
to provide an arbitrary nonzero output voltage for a zero
input code (Figure 13). The output voltage V
is:
OUTA
V
= V
+ N (V
OUTA
BIAS B IN)
3
4
V
SS
where V
is the positive offset voltage (with respect
to DGND) applied to AGND, and N is the numeric
value of the DAC’s binary input code. Since AGND is
common to all four DACs, all outputs will be offset by
BIAS
B
MAX536
MAX537
1N5817
V
BIAS
in the same manner. As the voltage at AGND
increases, the DAC’s resolution decreases because its
full-scale voltage swing is effectively reduced. AGND
should not be biased more negative than DGND.
AGND
P o w e r-S u p p ly Co n s id e ra t io n s
On power-up, V should come up first, V next, then
SS
DD
6/MAX537
REFAB or REFCD. If supply sequencing is not possible,
tie an external Schottky diode between V and AGND
SS
Figure 14. When V and V cannot be sequenced, tie a
SS
DD
as shown in Figure 14. On power-up, all input and DAC
registers are cleared (set to zero code) and SDO is in
Mode 0 (serial data is shifted out of SDO on the clock’s
rising edge).
Schottky diode between V and AGND.
SS
Us in g a n AC Re fe re n c e
In applications where the reference has AC signal compo-
nents, the MAX536/MAX537 have multiplying capability
within the reference input range specifications. Figure 12
shows a technique for applying a sine-wave signal to the
reference input where the AC signal is offset before being
applied to REFAB/REFCD. The reference voltage must
never be more negative than DGND.
For rated MAX536 performance, V
higher than REFAB/REFCD and should be between
10.8V and 16.5V. When using the MAX537, V should
be at least 2.2V higher than REFAB/REFCD and should
should be 4V
DD
DD
be between 4.75V and 5.5V. Bypass both V and V
DD
SS
with a 4.7µF capacitor in parallel with a 0.1µF capacitor
to AGND. Use short lead lengths and place the bypass
capacitors as close to the supply pins as possible.
The MAX536’s tota l ha rmonic d is tortion p lus nois e
(THD + N) is typically less than 0.012%, given a 5Vp-p sig-
nal swing and input frequencies up to 35kHz, or given a
2Vp-p swing and input frequencies up to 50kHz. The typi-
cal -3dB frequency is 700kHz as shown in the Typical
Operating Characteristics graphs.
Gro u n d in g a n d La yo u t Co n s id e ra t io n s
Digital or AC transient signals between AGND and
DGND c a n c re a te nois e a t the a na log outp uts . Tie
AGND and DGND together at the DAC, then tie this
point to the highest quality ground available.
For the MAX537, with a n inp ut s ig na l a mp litud e of
0.85mVp-p, THD + N is typically less than 0.024% with a
5kΩ load in parallel with 100pF and input frequencies up to
100kHz, or with a 2kΩ load in parallel with 100pF and input
frequencies up to 95kHz.
Good printed circuit board ground layout minimizes
crosstalk between DAC outputs, reference inputs, and
digital inputs. Reduce crosstalk by keeping analog
lines away from digital lines. Wire-wrapped boards are
not recommended.
22 ______________________________________________________________________________________
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
6/MAX537
_Ord e rin g In fo rm a t io n (c o n t in u e d )
___________________Ch ip To p o g ra p h y
INL
(LSB)
V
DD
OUTA OUTB OUTC OUTD
PART
TEMP. RANGE PIN-PACKAGE
1
MAX537ACPE
MAX537BCPE
MAX537ACWE
MAX537BCWE
MAX537BC/D
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
16 Plastic DIP
16 Plastic DIP
16 Wide SO
16 Wide SO
Dice*
± ⁄
2
VSS
AGND
REFAB
±1
1
± ⁄
2
±1
±1
1
TP
MAX537AEPE -40°C to +85°C
MAX537BEPE -40°C to +85°C
MAX537AEWE -40°C to +85°C
MAX537BEWE -40°C to +85°C
16 Plastic DIP
16 Plastic DIP
16 Wide SO
16 Wide SO
± ⁄
2
±1
1
± ⁄
2
±1
1
REFCD
MAX537AMDE -55°C to +125°C 16 Ceramic SB**
MAX537BMDE -55°C to +125°C 16 Ceramic SB**
± ⁄
2
±1
* Contact factory for dice specifications.
** Contact factory for availability and processing to MIL-STD-883.
0. 309"
(7. 848mm)
DGND
SDO
LDAC
SDI
SCK
CS
0. 139"
(3. 5306mm)
TRANSISTOR COUNT: 5034
SUBSTRATE CONNECTED TO V
DD
______________________________________________________________________________________ 23
Ca lib ra t e d , Qu a d , 1 2 -Bit
Vo lt a g e -Ou t p u t DACs w it h S e ria l In t e rfa c e
________________________________________________________P a c k a g e In fo rm a t io n
6/MAX537
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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