MAX545BEPD_技术文档

19-1088; Rev 3; 12/99

+5V, Serial-Input, Voltage-Output, 14-Bit DACs

General Description

Features

The MAX544/MAX545 are serial-input, voltage-output,

14-bit digital-to-analog converters (DACs) that operate

from a single +5V supply. They provide 14-bit perfor-

mance (±±.5ꢀLS ꢁIꢀ and ±±.0ꢀLS DIꢀ) over tempera-

ture without any adjustments. The DAC output is

unbuffered, resulting in a low supply current of ±.3mA

and a low offset error of ±.6mV.

ꢀ Full 14-Bit Performance Without Adjustments

ꢀ +5V Single-Supply Operation

ꢀ Low Power: 1.5mW

ꢀ 1µs Settling Time

ꢀ Unbuffered Voltage Output Directly Drives 60kΩ

Loads

The DAC output range is ±V to V

For bipolar opera-

REF.

ꢀ SPI/QSPI/MICROWIRE-Compatible Serial Interface

tion, matched scaling resistors are provided in the

MAX545 for use with an external precision op amp

(such as the MAX4±±), generating a ±V

ꢀ Power-On Reset Circuit Clears DAC Output to 0V

output

REF

(unipolar mode)

swing. The MAX545 also includes Kelvin-sense con-

nections for the reference and analog ground pins to

reduce layout sensitivity.

ꢀ Schmitt-Trigger Inputs for Direct Optocoupler

Interface

ꢀ Pin-Compatible 16-Bit Upgrades

A 16-bit serial word is used to load data into the DAC

latch. The 1±MHz, 3-wire serial interface is compatible

with LPꢁ™/QLPꢁ™/MꢁCROWꢁRE™, and it also interfaces

directly with optocouplers for applications requiring isola-

tion. A power-on reset circuit clears the DAC output to ±V

(unipolar mode) when power is initially applied.

(MAX541/MAX542)

Ordering Information

INL

PART

TEMP. RANGE PIN-PACKAGE

The MAX544 is available in 8-pin plastic DꢁP and LO

packages. The MAX545 is available in 14-pin plastic

DꢁP and LO packages.

(LSB)

±1/ꢂ

±1

MAX544ACPA

MAX544SCPA

MAX544ACLA

MAX544SCLA

±°C to +7±°C

8 Plastic DꢁP

8 LO

±1/ꢂ

±1

Applications

Digital Offset and Gain Adjustment

ꢁnstrumentation

8 LO

Ordering Information continued at end of data sheet.

ꢁndustrial Process Control

Automated Test Equipment

Data-Acquisition Lystems

Functional Diagrams

V

DD

Pin Configurations

RFB

INV

TOP VIEW

MAX545

R

FB

R

INV

REFF

REFS

V

14

RFB

OUT

1

2

3

4

5

6

7

DD

14-BIT DAC

OUT

13 INV

AGNDF

AGNDS

MAX545

AGNDF

AGNDS

REFS

REFF

12 DGND

1

2

3

4

8

7

6

5

V

DD

OUT

AGND

REF

DATA LATCH

CS

LDAC

SCLK

DIN

11

10

9

LDAC

DIN

DGND

DIN

CONTROL

LOGIC

MAX544

SERIAL INPUT REGISTER

N.C.

CS

SCLK

CS

8

SCLK

DGND

DIP/SO

Functional Diagrams continued at end of data sheet.

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

________________________________________________________________ Maxim Integrated Products

1

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.

For small orders, phone 1-800-835-8769.

+5V, Serial-Input, Voltage-Output, 14-Bit DACs

ABSOLUTE MAXIMUM RATINGS

DD

CS, LCꢀK, DꢁI, LDAC to DGID ..............................-±.3V to +6V

REF, REFF, REFL to AGID........................-±.3V to (V + ±.3V)

AGID, AGIDF, AGIDL to DGID .......................-±.3V to +±.3V

V

to DGID ...........................................................-±.3V to +6V

14-Pin Plastic DꢁP (derate 1±.±±mW/°C above +7±°C)...8±±mW

14-Pin LO (derate 8.33mW/°C above +7±°C) ...............667mW

14-Pin Ceramic LS (derate 1±.±±mW/°C above +7±°C...8±±mW

Operating Temperature Ranges

DD

OUT, ꢁIV to AGID DGID .......................................-±.3V to V

RFS to AGID DGID...................................................-6V to +6V

Maximum Current into Any Pin............................................5±mA

Continuous Power Dissipation (T = +7±°C)

A

8-Pin Plastic DꢁP (derate 0.±0mW/°C above +7±°C).....7ꢂ7mW

8-Pin LO (derate 5.88mW/°C above +7±°C) .................471mW

MAX544 _C_ A/MAX545_C_D ..............................±°C to +7±°C

MAX544 _E_ A/MAX545_E_D............................-4±°C to +85°C

MAX545SMJD .................................................-55°C to +1ꢂ5°C

Ltorage Temperature Range.............................-65°C to +15±°C

ꢀead Temperature (soldering, 1±s) .................................+3±±°C

DD

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V

= +5V ± 5%, V

= +ꢂ.5V, AGID = DGID = ±, T = T

A

to T

, unless otherwise noted.)

MAX

DD

REF

MꢁI

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC PERFORMANCE—ANALOG SECTION (R = ∞)

ꢀ

Resolution

I

14

Sits

MAX54_A

MAX54_S

±±.15

±±.5

±1

ꢁntegral Ionlinearity

ꢁIꢀ

V

= 5V

ꢀLS

DD

Differential Ionlinearity

Zero-Code Offset Error

Zero-Code Tempco

Gain Error (Iote 1)

DIꢀ

ZLE

Guaranteed monotonic

±±.0

±±.6

ꢀLS

mV

ZL

±±.±5

ppm/°C

ꢀLS

TC

±5

Gain-Error Tempco

±±.1

6.ꢂ5

1.±

ppm/°C

kΩ

DAC Output Resistance

R

(Iote ꢂ)

MAX545

OUT

R

/R

FS ꢁIV

Sipolar Resistor Matching

Ratio error

±±.±3

±1±

%

ꢀLS

Sipolar Zero Offset Error

Sipolar Zero Tempco

Power-Lupply Rejection

MAX545

SZL

±±.5

ppm/°C

ꢀLS

TC

PLR

4.75V ≤ V

≤ 5.ꢂ5V

±1.±

3.±

DD

REFERENCE INPUT

Reference ꢁnput Range

V

R

(Iote 3)

ꢂ.±

11.5

0.±

V

REF

Unipolar mode

Reference ꢁnput Resistance

(Iote 4)

kΩ

REF

MAX545, bipolar mode

DYNAMIC PERFORMANCE—ANALOG SECTION (R = ∞, unipolar mode)

ꢀ

Voltage-Output Llew Rate

Output Lettling Time

DAC Glitch ꢁmpulse

LR

C = 1±pF (Iote 5)

ꢀ

To ±¹/_ꢂꢀLS of FL, C = 1±pF

ꢂ5

1

V/µs

µs

ꢀ

Major-carry transition

1±

nVs

Code = ±±±± hex; CS = V ; LDAC = ±V;

DD

Digital Feedthrough

1±

nVs

LCꢀK, DꢁI = ±V to V

levels

DD

2

_______________________________________________________________________________________

+5V, Serial-Input, Voltage-Output, 14-Bit DACs

ELECTRICAL CHARACTERISTICS (continued)

(V

= +5V ± 5%, V

= +ꢂ.5V, AGID = DGID = ±, T = T

A

to T

, unless otherwise noted.)

MAX

DD

REF

MꢁI

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DYNAMIC PERFORMANCE—REFERENCE SECTION

Reference -3dS Sandwidth

Reference Feedthrough

Lignal-to-Ioise Ratio

SW

Code = FFFC hex

1

MHz

mVp-p

dS

Code = ±±±± hex, V

= 1Vp-p at 1±±kHz

REF

LIR

83

75

1ꢂ±

Code = ±±±± hex

Code = FFFC hex

Reference ꢁnput Capacitance

C

ꢁI

pF

STATIC PERFORMANCE—DIGITAL INPUTS

ꢁnput High Voltage

ꢁnput ꢀow Voltage

ꢁnput Current

V

ꢂ.4

V

ꢁH

V

±.8

±1

1±

ꢁꢀ

ꢁ

ꢁI

V

= ±

µA

pF

V

ꢁI

ꢁnput Capacitance

Hysteresis Voltage

POWER SUPPLY

Positive Lupply Range

Positive Lupply Current

Power Dissipation

C

(Iote 6)

ꢁI

V

±.4±

H

V

DD

4.75

5.ꢂ5

1.1

V

ꢁ

±.3

1.5

mA

mW

DD

PD

TIMING CHARACTERISTICS

(V

= +5V ± 5%, V

= +ꢂ.5V, AGID = DGID = ±, CMOL inputs, T = T

to T

, unless otherwise noted.)

MAX

DD

REF

A

MꢁI

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

MHz

ns

LCꢀK Frequency

f

1±

LCꢀK

LCꢀK Pulse Width High

LCꢀK Pulse Width ꢀow

CS ꢀow to LCꢀK High Letup

CS High to LCꢀK High Letup

LCꢀK High to CS ꢀow Hold

LCꢀK High to CS High Hold

DꢁI to LCꢀK High Letup

DꢁI to LCꢀK High Hold

LDAC Pulse Width

t

45

3±

45

4±

±

CH

t

Cꢀ

ns

t

ns

CLL±

CLL1

ns

(Iote 6)

MAX545

ns

CLH±

CLH1

t

ns

t

ns

DL

t

ns

DH

t

5±

ns

LDAC

t

MAX545 (Iote 6)

ns

CS High to LDAC ꢀow Letup

ꢀDACL

V

High to CS ꢀow

DD

ꢂ±

µs

(power-up delay)

Note 1: Gain Error tested at V

= ꢂ.±V, ꢂ.5V, and 3.±V.

REF

Note 2: R

tolerance is typically ±ꢂ±%.

OUT

Note 3: Min/max range guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance.

Note 4: Reference input resistance is code dependent, minimum at 8554 hex.

Note 5: Llew-rate value is measured from ±% to 63%.

Note 6: Guaranteed by design. Iot production tested.

_______________________________________________________________________________________

3

+5V, Serial-Input, Voltage-Output, 14-Bit DACs

Typical Operating Characteristics

(V

= 5V, V

= +ꢂ.5V, T = +ꢂ5°C, unless otherwise noted.)

REF

A

DD

SUPPLY CURRENT

vs. REFERENCE VOLTAGE

ZERO-CODE OFFSET ERROR

vs. TEMPERATURE

SUPPLY CURRENT

vs. TEMPERATURE

0.35

0.34

0.33

0.32

0.31

0.30

0.29

0.28

0.27

0.26

0.25

0.20

0.15

0.10

0.05

0

0.50

0.45

0.40

0.35

0.30

0.25

0.20

-0.05

-0.10

-0.15

-0.20

0

1

2

3

4

5

6

-60

-20

20

60

100

140

-40 -20

0

20

40

60

80 100

REFERENCE VOLTAGE (V)

TEMPERATURE (°C)

DIFFERENTIAL NONLINEARITY

vs. TEMPERATURE

GAIN ERROR

vs. TEMPERATURE

INTEGRAL NONLINEARITY

vs. TEMPERATURE

0.20

0.15

0.10

0.05

0

0.30

0.20

0.10

0

0.30

0.20

0.10

0

+DNL

-DNL

+INL

-0.05

-0.10

-0.15

-0.20

-0.10

-0.20

-0.30

-0.10

-0.20

-0.30

-INL

-60

-20

20

60

100

140

-60

-20

20

60

100

140

-60

-20

20

60

100

140

TEMPERATURE (°C)

INTEGRAL NONLINEARITY

vs. CODE

DIFFERENTIAL NONLINEARITY

vs. CODE

REFERENCE CURRENT

vs. CODE

0.250

0.125

0

0.250

200

160

120

80

0.125

0

-0.125

-0.250

40

0

-0.250

0

5k

10k

15k

20k

5k

10k

15k

0

4k

8k

12k

16k

20k

DAC CODE

4

_______________________________________________________________________________________

+5V, Serial-Input, Voltage-Output, 14-Bit DACs

Typical Operating Characteristics (continued)

(V

= +5V, V

= +ꢂ.5V, T = +ꢂ5°C, unless otherwise noted.)

REF

A

DD

FULL-SCALE STEP RESPONSE

(f = 20MHz)

FULL-SCALE STEP RESPONSE

(f

= 10MHz)

SCLK

C = 10pF

L

C = 10pF

L

R = ∞

OUT

500mV/div

OUT

500mV/div

2µs/div

400ns/div

2µs/div

1µs/div

MAJOR-CARRY OUTPUT GLITCH

DIGITAL FEEDTHROUGH

CS

(5V/div)

SCLK

5V/div

OUT

(AC-COUPLED,

50mV/div)

(AC-COUPLED,

100mV/div)

MAX544/MAX545-11

MAX544/MAX545-12

2µs/div

CODE = 0000 hex

Pin Descriptions

MAX544

NAME

FUNCTION

1

ꢂ

3

4

5

6

7

8

OUT

AGID

REF

DAC Output Voltage

Analog Ground

Voltage Reference ꢁnput. Connect to external +ꢂ.5V reference.

Chip-Lelect ꢁnput

CS

LCꢀK

DꢁI

Lerial-Clock ꢁnput. Duty cycle must be between 4±% and 6±%.

Lerial-Data ꢁnput

Digital Ground

DGID

V

DD

+5V Lupply Voltage

_______________________________________________________________________________________

5

+5V, Serial-Input, Voltage-Output, 14-Bit DACs

Pin Descriptions (continued)

MAX545

1

NAME

RFS

FUNCTION

Feedback Resistor. Connect to external op amp’s output in bipolar mode.

DAC Output Voltage

ꢂ

OUT

3

AGIDF

AGIDL

REFL

REFF

CS

Analog Ground (force)

4

Analog Ground (sense)

5

Voltage Reference ꢁnput (sense). Connect REFL to external +ꢂ.5V reference.

Voltage Reference ꢁnput (force). Connect REFF to external +ꢂ.5V reference.

Chip-Lelect ꢁnput

6

7

8

LCꢀK

I.C.

Lerial-Clock ꢁnput. Duty cycle must be between 4±% and 6±%.

Io Connection. Iot internally connected.

Lerial-Data ꢁnput

0

1±

11

1ꢂ

DꢁI

LDAC

DGID

LDAC ꢁnput. A falling edge updates the internal DAC latch.

Digital Ground

Junction of internal scaling resistors. Connect to external op amp’s inverting input in

bipolar mode.

13

14

ꢁIV

V

DD

+5V Lupply Voltage

t

CSH1

LDACS

CS

t

CSHO

t

CSS1

t

CL

CSSO

CH

SCLK

t

DH

t

DS

D13

D12

S0

DIN

LDAC*

t

LDAC

*MAX545 ONLY

Figure 1. Timing Diagram

6

_______________________________________________________________________________________

+5V, Serial-Input, Voltage-Output, 14-Bit DACs

+5V

+2.5V

10µF

0.1µF

MC68XXXX

V

REF (REFF) (REFS)

DD

UNIPOLAR

OUT

PCS0

MOSI

SCLK

CS

MAX495

EXTERNAL OP AMP

OUT

DIN

MAX544/MAX545

SCLK

(GND)

(LDAC)

DGND

AGND_

(

) ARE FOR MAX545 ONLY

Figure 2a. Typical Operating Circuit—Unipolar Output

+5V

+2.5V

10µF

0.1µF

+5V

RFB

MC68XXXX

V

REFS

REFF

DD

R

INV

PCS0

MOSI

SCLK

IC1

CS

R

INV

FB

BIPOLAR

OUT

EXTERNAL OP AMP

MAX400

DIN

OUT

SCLK

LDAC

DGND

MAX545

-5V

(GND)

AGNDF

AGNDS

Figure 2b. Typical Operating Circuit—Bipolar Output

major-carry transitions. ꢁt also lowers the DAC output

impedance by a factor of eight compared to a standard

R-ꢂR ladder, allowing unbuffered operation in medium-

load applications.

Detailed Description

The MAX544/MAX545 voltage-output, 14-bit digital-to-

analog converters (DACs) offer full 14-bit performance

with less than ±.5ꢀLS integral linearity error and less

than ±.0ꢀLS differential linearity error, thus ensuring

monotonic performance. Lerial-data transfer minimizes

the number of package pins required.

The MAX545 provides matched bipolar offset resistors,

which connect to an external op amp for bipolar output

swings (Figure ꢂb). For optimum performance, the

MAX545 also provides a set of Kelvin connections to

the voltage-reference and analog-ground inputs.

The MAX544/MAX545 are composed of two matched

DAC sections, with an inverted R-ꢂR DAC forming the

ꢀLSs and the four MLSs derived from 15 identically

matched resistors. This architecture allows the lowest

glitch energy to be transferred to the DAC output on

_______________________________________________________________________________________

7

+5V, Serial-Input, Voltage-Output, 14-Bit DACs

Digital Interface

The MAX544/MAX545’s digital interface is a standard

3-wire connection compatible with LPꢁ/QLPꢁ/

MꢁCROWꢁRE interfaces. The chip-select input (CS)

frames the serial data loading at the data-input pin

(DꢁI). ꢁmmediately following CS’s high-to-low transition,

the data is shifted synchronously and latched into the

input register on the rising edge of the serial clock input

(LCꢀK). After 16 bits (14 data bits, plus ꢂ sub-bits set to

zero) have been loaded into the serial input register, it

transfers its contents to the DAC latch on CS’s low-to-

high transition (Figure 3a). Iote that if CS is not kept

low during the entire 16 LCꢀK cycles, data will be cor-

rupted. ꢁn this case, reload the DAC latch with a new

16-bit word.

External Reference

The MAX544/MAX545 operate with external voltage ref-

erences from ꢂV to 3V. The reference voltage deter-

mines the DAC’s full-scale output voltage. Kelvin

connections are provided with the MAX545 for optimum

performance. The ꢂ.5V MAX873A, with ±15mV initial

accuracy and a 7ppm/°C (max) temperature coeffi-

cient, is a good choice.

Power-On Reset

The MAX544/MAX545 have a power-on reset circuit to

set the DAC’s output to ±V in unipolar mode when V

DD

is first applied. This ensures that unwanted DAC output

voltages will not occur immediately following a system

power-up, such as after a loss of power. ꢁn bipolar

mode, the DAC output is set to -V

.

REF

Alternatively, for the MAX545, LDAC allows the DAC

latch to update asynchronously by pulling LDAC low

after CS goes high (Figure 3b). Hold LDAC high during

the data-loading sequence.

CS

DAC

UPDATED

SCLK

SUB-BITS

DIN

D13 D12 D11 D10 D9 D8 D7 D6

MSB

D5 D4 D3 D2 D1 D0 S1 S0

LSB

Figure 3a. MAX544/MAX545 3-Wire Interface Timing Diagram (LDAC = DGND for MAX545)

CS

SCLK

SUB-BITS

DIN

D13 D12 D11 D10 D9 D8 D7 D6

MSB

D5 D4 D3 D2 D1 D0 S1 S0

LSB

LDAC

DAC

UPDATED

Figure 3b. MAX545 4-Wire Interface Timing Diagram

8

_______________________________________________________________________________________

+5V, Serial-Input, Voltage-Output, 14-Bit DACs

Unbuffered Operation

Unbuffered operation reduces power consumption as

Applications Information

Reference and Analog Ground Inputs

The MAX544/MAX545 operate with external voltage ref-

erences from ꢂV to 3V, and maintain 14-bit performance

if certain guidelines are followed when selecting and

applying the reference. ꢁdeally, the reference’s

temperature coefficient should be less than 1.5ppm/°C to

maintain 14-bit accuracy to within 1ꢀLS over the ±°C to

+7±°C commercial temperature range. Lince this convert-

er is designed as an inverted R-ꢂR voltage-mode DAC,

the input resistance seen by the voltage reference is code

dependent. The worst-case input-resistance variation is

from 11.5kΩ (at code 8554 hex) to ꢂ±±kΩ (at code ±±±±

hex). The maximum change in load current for a +ꢂ.5V

reference is +ꢂ.5V / 11.5kΩ = ꢂ17µA; therefore, the

required load regulation is ꢂ8ppm/mA for a maximum

error of ±.1ꢀLS. This implies a reference output imped-

ance of less than 71mΩ. ꢁn addition, the signal-path

impedance from the voltage reference to the reference

input must be kept low because it contributes directly to

the load-regulation error.

well as offset error contributed by the external output

buffer. The R-ꢂR DAC output is available directly at

OUT, allowing 14-bit performance from +V

to AGID

REF

without degradation at zero scale. The DAC’s output

impedance is also low enough to drive medium loads

(R > 6±kΩ) without degradation of ꢁIꢀ or DIꢀ; only

ꢀ

the gain error is increased by externally loading the

DAC output.

External Output Buffer Amplifier

The requirements on the external output buffer amplifier

change whether the DAC is used in unipolar or bipolar

operational mode. ꢁn unipolar mode, the output amplifi-

er is used in a voltage-follower connection. ꢁn bipolar

mode (MAX545 only), the amplifier operates with the

internal scaling resistors (Figure ꢂb). ꢁn each mode, the

DAC’s output resistance is constant and is independent

of input code; however, the output amplifier’s input

impedance should still be as high as possible to mini-

mize gain errors. The DAC’s output capacitance is also

independent of input code, thus simplifying stability

requirements on the external amplifier.

The requirement for a low-impedance voltage reference

is met with capacitor bypassing at the reference inputs

and ground. A ±.1µF ceramic capacitor with short leads

between REFF and AGIDF (MAX545), or REF and

AGID (MAX544), provides high-frequency bypassing.

A surface-mount ceramic chip capacitor is preferred

because it has the lowest inductance. An additional

1±µF between REFF and AGIDF (MAX545), or REF

and AGID (MAX544), provides low-frequency bypass-

ing. A low-ELR tantalum, film, or organic semiconductor

capacitor works well. ꢀeaded capacitors are accept-

able because impedance is not as critical at lower fre-

quencies. The circuit can benefit from even larger

bypassing capacitors, depending on the stability of the

external reference with capacitive loading. ꢁf separate

force and sense lines are not used, tie the appropriate

force and sense pins together close to the package.

ꢁn bipolar mode, a precision amplifier operating with

dual power supplies (such as the MAX4±±) provides

the ±V

output range. ꢁn single-supply applications,

REF

precision amplifiers with input common-mode ranges

including AGID are available; however, their output

swings do not normally include the negative rail

(AGID) without significant degradation of performance.

A single-supply op amp, such as the MAX405, is suit-

able if the application does not use codes near zero.

Lince the ꢀLSs for a 14-bit DAC are extremely small

(15ꢂ.6µV for V

= ꢂ.5V), pay close attention to the

REF

external amplifier’s input specification. The input offset

voltage can degrade the zero-scale error and might

require an output offset trim to maintain full accuracy if

the offset voltage is greater than 1/ꢂꢀLS. Limilarly, the

input bias current multiplied by the DAC output resis-

tance (typically 6.ꢂ5kΩ) contributes to zero-scale error.

Temperature effects also must be taken into considera-

tion. Over the ±°C to +7±°C commercial temperature

range, the offset voltage temperature coefficient (refer-

enced to +ꢂ5°C) must be less than 1.7µV/°C to add

less than 1/ꢂꢀLS of zero-scale error. The external

AGID must also be low impedance, as load-regulation

errors will be introduced by excessive AGID resis-

tance. As in all high-resolution, high-accuracy applica-

tions, separate analog and digital ground planes yield

the best results. Tie DGID to AGID at the AGID pin to

form the “star” ground for the DAC system. Always refer

remote DAC loads to this system ground for the best

possible performance.

_______________________________________________________________________________________

9

+5V, Serial-Input, Voltage-Output, 14-Bit DACs

amplifier’s input resistance forms a resistive divider with

the DAC output resistance, which results in a gain

error. To contribute less than 1/ꢂꢀLS of gain error, the

input resistance typically must be greater than:

Unipolar Configuration

Figure ꢂa shows the MAX544/MAX545 configured for

unipolar operation with an external op amp. The op amp

is set for unity gain, and Table 1 lists the codes for this

circuit.





1

ꢂ

1

6.ꢂ5kΩ ÷

= ꢂ±5MΩ









14

ꢂ

Bipolar Configuration

Figure ꢂb shows the MAX545 configured for bipolar

operation with an external op amp. The op amp is set

The settling time is affected by the buffer input capaci-

tance, the DAC’s output capacitance, and PC board

capacitance. The typical DAC output voltage settling

time is 1µs for a full-scale step. Lettling time can be

significantly less for smaller step changes. Assuming a

single time-constant exponential settling response, a

full-scale step takes 1±.4 time constants to settle to

within 1/ꢂꢀLS of the final output voltage. The time con-

stant is equal to the DAC output resistance multiplied

by the total output capacitance. The DAC output

capacitance is typically 1±pF. Any additional output

capacitance increases the settling time.

for unity gain with an offset of -1/ꢂV

. Table ꢂ shows

REF

the offset binary codes for this circuit.

Power-Supply Bypassing and

Ground Management

For optimum system performance, use PC boards with

separate analog and digital ground planes. Wire-wrap

boards are not recommended. Connect the two ground

planes together at the low-impedance power-supply

source. Connect DGID and AGID together at the ꢁC.

The best ground connection can be achieved by con-

necting the DAC’s DGID and AGID pins together and

connecting that point to the system analog ground

plane. ꢁf the DAC’s DGID is connected to the system

digital ground, digital noise may get through to the

DAC’s analog portion.

The external buffer amplifier’s gain-bandwidth product

is important because it increases the settling time by

adding another time constant to the output response.

The effective time constant of two cascaded systems,

each with a single time-constant response, is approxi-

mately the root square sum of the two time constants.

The DAC output’s time constant is 1µs / 1±.4 = 06ns,

ignoring the effect of additional capacitance. ꢁf the time

constant of an external amplifier with 1MHz bandwidth

is 1 / ꢂπ (1MHz) = 150ns, then the effective time con-

stant of the combined system is:

Sypass V

with a ±.1µF ceramic capacitor connected

DD

between V

and AGID. Mount it with short leads

close to the device. Ferrite beads can also be used to

further isolate the analog and digital power supplies.

Table 1. Unipolar Code Table

ꢂ







DAC LATCH CONTENTS

06ns + 150ns

=186ns

(

)

(

)





ANALOG OUTPUT, V

OUT



MSB

LSB

1111 1111 1111 11(±±)

1±±± ±±±± ±±±± ±±(±±)

±±±± ±±±± ±±±± ±1(±±)

V

_REF· (16,383 / 16,384)

This suggests that the settling time to within 1/ꢂꢀLS of

the final output voltage, including the external buffer

amplifier, will be approximately 1±.4 · 186ns = 1.03µs.

1/

V_REF· (810ꢂ / 16,384) =

V

REF

ꢂ

V_REF· (1 / 16,384)

±±±± ±±±± ±±±± ±±(±±) ±V

Digital Inputs and Interface Logic

The digital interface for the 14-bit DAC is based on a

3-wire standard that is compatible with LPꢁ, QLPꢁ, and

MꢁCROWꢁRE interfaces. The three digital inputs (CS,

DꢁI, and LCꢀK) load the digital input data serially into

the DAC. LDAC (MAX545) updates the DAC output

asynchronously.

Table 2. Bipolar Code Table

DAC LATCH CONTENTS

ANALOG OUTPUT, V

OUT

MSB

LSB

1111 1111 1111 11(±±)

1±±± ±±±± ±±±± ±1(±±)

+V_REF· (8101 / 810ꢂ)

+V_REF· (1 / 810ꢂ)

All of the digital inputs include Lchmitt-trigger buffers to

accept slow-transition interfaces. This means that opto-

couplers can interface directly to the MAX544/MAX545

without additional external logic. The digital inputs are

compatible with TTꢀ/CMOL-logic levels.

1±±± ±±±± ±±±± ±±(±±) ±V

±111 1111 1111 11(±±)

±±±± ±±±± ±±±± ±±(±±)

-V_REF· (1 / 810ꢂ)

-V_REF· (810ꢂ / 810ꢂ) = -V

REF

(

) = Lub-bits

10 ______________________________________________________________________________________

+5V, Serial-Input, Voltage-Output, 14-Bit DACs

Ordering Information (continued)

Functional Diagrams (continued)

INL

PART

TEMP. RANGE PIN-PACKAGE

(LSB)

±1/ꢂ

±1

V

DD

MAX544AEPA

MAX544SEPA

MAX544AELA

MAX544SELA

MAX545ACPD

MAX545SCPD

MAX545ACLD

MAX545SCLD

MAX545AEPD

MAX545SEPD

MAX545AELD

MAX545SELD

-4±°C to +85°C 8 Plastic DꢁP

-4±°C to +85°C 8 LO

MAX544

±1/ꢂ

±1

REF

14-BIT DAC

OUT

-4±°C to +85°C 8 LO

±°C to +7±°C 14 Plastic DꢁP

±°C to +7±°C 14 LO

±1/ꢂ

±1

AGND

DATA LATCH

CS

DIN

SCLK

±1/ꢂ

±1

CONTROL

LOGIC

±°C to +7±°C 14 LO

SERIAL INPUT REGISTER

DGND

-4±°C to +85°C 14 Plastic DꢁP

-4±°C to +85°C 14 LO

±1/ꢂ

±1

±1/ꢂ

±1

-4±°C to +85°C 14 LO

MAX545SMJD -55°C to +1ꢂ5°C 14 Ceramic LS*

±1

*Contact factory for availability.

Chip Information

TRAILꢁLTOR COUIT: ꢂꢂ±0

______________________________________________________________________________________ 11

+5V, Serial-Input, Voltage-Output, 14-Bit DACs

________________________________________________________Package Information

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Printed ULA

is a registered trademark of Maxim ꢁntegrated Products.


型号：	MAX545BEPD
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	+5V, Serial-Input, Voltage-Output, 14-Bit DACs + 5V ，串行输入，电压输出， 14位DAC
文件：	总12页 (文件大小：265K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX545BEPD [MAXIM]

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