MAX5621AETK-T [MAXIM]
D/A Converter, 1 Func, Serial Input Loading, 10 X 10 MM, 0.80 MM HEIGHT, EXPOSED PAD, MO-220, QFN-68;
| 型号： | MAX5621AETK-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Serial Input Loading, 10 X 10 MM, 0.80 MM HEIGHT, EXPOSED PAD, MO-220, QFN-68 |
| 文件： | 总16页 (文件大小：666K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2715; Rev 0; 1/03
16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
General Description
Features
The MAX5621/MAX5622/MAX5623 are 16-bit digital-to-
analog converters (DACs) with 16 sample-and-hold
(SHA) outputs for applications where a high number of
programmable voltages are required. These devices
include a clock oscillator and a sequencer that updates
the DAC with codes from an internal SRAM. No external
components are required to set offset and gain.
ꢀ Integrated 16-Bit DAC and 16-Channel SHA with
SRAM and Sequencer
ꢀ 16 Voltage Outputs
ꢀ 0.005% Output Linearity
ꢀ 200µV Output Resolution
ꢀ Flexible Output Voltage Range
ꢀ Remote Ground Sensing
The MAX5621/MAX5622/MAX5623 feature a -4.5V to
+9.2V output voltage range. Other features include a
200µV/step resolution, with output linearity error, typi-
cally 0.005% of full-scale range (FSR). The 100kHz
refresh rate updates each SHA every 320µs, resulting
in negligible output droop. Remote ground sensing
allows the outputs to be referenced to the local ground
of a separate device.
ꢀ Fast Sequential Loading: 1.3µs per Register
ꢀ Burst and Immediate Mode Addressing
ꢀ No External Components Required for Setting
Gain and Offset
ꢀ Integrated Output Clamp Diodes
ꢀ Three Output Impedance Options
MAX5621 (50Ω), MAX5622 (500Ω), and
MAX5623 (1kΩ)
These devices are controlled through a 20MHz
SPI™/QSPI™/MICROWIRE™-compatible 3-wire serial
interface. Immediate update mode allows any channel’s
output to be updated within 20µs. Burst mode allows
multiple values to be loaded into memory in a single,
high-speed data burst. All channels are updated within
330µs after data has been loaded.
Ordering Information
PART
TEMP RANGE
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
PIN-PACKAGE
64 TQFP
MAX5621AECB
MAX5621AETK
MAX5622AECB
MAX5622AETK
MAX5623AECB
68 Thin QFN-EP*
64 TQFP
Each device features an output clamp and output resis-
tors for filtering. The MAX5621 features a 50Ω output
impedance and is capable of driving up to 250pF of out-
put capacitance. The MAX5622 features a 500Ω output
impedance and is capable of driving up to 10nF of output
capacitance. The MAX5623 features a 1kΩ output imped-
ance and is capable of driving up to 10nF of output
capacitance.
68 Thin QFN-EP*
64 TQFP
MAX5623AETK
-40oC to +85oC
68 Thin QFN-EP*
*EP = Exposed pad.
Pin Configurations
The MAX5621/MAX5622/MAX5623 are available in 64-pin
TQFP (10mm x 10mm) and 68-pin thin QFN (10mm x
10mm) packages.
TOP VIEW
1
51
N.C.
N.C.
50
V
2
N.C.
DD
3
4
49
GS
CH
V
48
V
47 OUT10
LDAC
RST
CS
SS
________________________Applications
5
6
46
N.C.
OUT9
N.C.
MEMS Mirror Servo Control
Industrial Process Control
Automatic Test Equipment
7
45
DIN
8
44
43
42
41
40
39
38
37
36
35
SCLK
9
OUT8
AGND
V
DD
V
LOGIC
IMMED
MAX5621
MAX5622
MAX5623
10
11
12
13
14
15
16
17
ECLK
CLKSEL
DGND
N.C.
OUT7
N.C.
OUT6
N.C.
CL
Instrumentation
V
LSHA
AGND
V
SS
N.C.
THIN QFN
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor, Corp.
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
ABSOLUTE MAXIMUM RATINGS
V
V
V
V
to AGND.......................................................-0.3V to +12.2V
to AGND .........................................................-6.0V to +0.3V
Maximum Current into Logic Inputs ................................. 20mA
DD
SS
DD
Continuous Power Dissipation (T = +70°C)
A
to V ...........................................................................+15V
64-Pin TQFP (derate 13.3mW/°C above +70°C) ............1066mW
68-Pin Thin QFN (derate 28.6mW/°C above +70°C)......2285mW
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
SS
, V
, V
to AGND or DGND..............-0.3V to +6V
LDAC LOGIC LSHA
REF to AGND............................................................-0.3V to +6V
GS to AGND................................................................V to V
CL and CH to AGND...................................................V to V
Logic Inputs to DGND..............................................-0.3V to +6V
DGND to AGND........................................................-0.3V to +2V
Maximum Current into OUT_ ............................................ 10mA
SS
SS
DD
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +10V, V = -4V, V
= V
= V
= +5V, V
= +2.5V, AGND = DGND = V
= 0V, R ≥ 10MΩ, C = 50pF,
DD
SS
LOGIC
= 400kHz, T = T
LDAC
LSHA
REF
GS L L
CLKSEL = +5V, f
to T
, unless otherwise noted. Typical values are at T = +25°C.)
ECLK
A
MIN
MAX A
PARAMETER
DC CHARACTERISTICS
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
N
16
Bits
V
V
SS
+
V
DD
-
Output Range
V
(Note 1)
OUT_
0.75
2.4
Offset Voltage
Code = 4F2C hex
(Note 2)
15
50
200
1
mV
µV/°C
%
Offset Voltage Tempco
Gain Error
Gain Tempco
5
ppm/°C
%FSR
Integral Linearity Error
INL
DNL
V
V
= -3.25V to +7.6V
0.005
0.015
4
OUT_
OUT_
= -3.25V to +7.6V; monotonicity
Differential Linearity Error
1
LSB
mA
guaranteed to 14 bits
Sinking and sourcing
MAX5621
Maximum Output Drive Current
I
2
35
OUT
50
500
1000
250
10
65
DC Output Impedance
R
Ω
MAX5622
350
700
650
OUT
MAX5623
1300
MAX5621
pF
nF
Maximum Capacitive Load
MAX5622
MAX5623
10
DC Crosstalk
Internal oscillator enabled (Note 3)
Internal oscillator enabled
-90
-80
dB
dB
Power-Supply Rejection Ratio
PSRR
2
_______________________________________________________________________________________
16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= +10V, V = -4V, V
= V
= V
= +5V, V
= +2.5V, AGND = DGND = V
= 0V, R ≥ 10MΩ, C = 50pF,
GS L L
DD
SS
LOGIC
= 400kHz, T = T
LDAC
LSHA
REF
CLKSEL = +5V, f
to T
, unless otherwise noted. Typical values are at T = +25°C.)
ECLK
A
MIN
MAX A
PARAMETER
DYNAMIC CHARACTERISTICS
Sample-and-Hold Settling
SCLK Feedthrough
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 4)
0.08
%
0.5
0.5
0.25
1
nV-s
nV-s
mV
f
Feedthrough
SEQ
Hold-Step
1
Droop Rate
V
= 0V (Note 5), T = +25°C
40
mV/s
OUT_
A
µV
Output Noise
250
RMS
REFERENCE INPUT
Input Resistance
Reference Input Voltage
GROUND-SENSE INPUT
Input Voltage Range
Input Bias Current
GS Gain
7
kΩ
V
I
2.5
1
V
REF
V
-0.5
-60
+0.5
0
V
GS
-0.5V ≤ V ≤ +0.5V
µA
V/V
GS
GS
(Note 6)
0.998
1.002
DIGITAL INTERFACE DC CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Current
V
2.0
80
V
V
IH
V
0.8
1
IL
µA
TIMING CHARACTERISTICS (Figure 2)
Sequencer Clock Frequency
External Clock Frequency
SCLK Frequency
f
Internal oscillator
(Note 7)
100
120
480
20
kHz
kHz
MHz
ns
SEQ
f
f
ECLK
SCLK
SCLK Pulse Width High
SCLK Pulse Width Low
t
15
15
CH
t
ns
CL
CS Low to SCLK High Setup
Time
t
15
ns
CSSO
CS High to SCLK High Setup
Time
t
15
10
ns
ns
CSS1
SCLK High to CS Low Hold Time
t
CSH0
_______________________________________________________________________________________
3
16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= +10V, V = -4V, V
= V
= V
= +5V, V
= +2.5V, AGND = DGND = V
= 0V, R ≥ 10MΩ, C = 50pF,
DD
SS
LOGIC
= 400kHz, T = T
LDAC
LSHA
REF
GS
L
L
CLKSEL = +5V, f
to T
, unless otherwise noted. Typical values are at T = +25°C.)
ECLK
A
MIN
MAX A
PARAMETER
SCLK High to CS High Hold Time
DIN to SCLK High Setup Time
DIN to SCLK High Hold Time
RST to CS Low
SYMBOL
CONDITIONS
MIN
0
TYP
MAX UNITS
t
ns
ns
ns
CSH1
t
15
0
DS
DH
t
(Note 8)
500
µs
POWER SUPPLIES
Positive Supply Voltage
Negative Supply Voltage
Supply Difference
V
(Note 9)
(Note 9)
8.55
10
-4
11.60
-2.75
14.5
V
V
V
DD
V
-5.25
SS
V
- V (Note 9)
SS
DD
V
,
LOGIC
Logic Supply Voltage
V
,
4.75
5
5.25
V
LDAC
V
LSHA
Positive Supply Current
Negative Supply Current
I
32
32
1
42
40
1.5
3
mA
mA
DD
I
SS
(Note 10)
= 20MHz (Note 11)
Logic Supply Current
I
mA
LOGIC
f
2
SCLK
Note 1: The nominal zero-scale (code = 0) voltage is -4.0535V. The nominal full-scale (code = FFFF hex) voltage is +9.0535V. The
output voltage is limited by the Output Range specification, restricting the usable range of DAC codes. The nominal zero-
scale voltage can be achieved when V < -4.9V, and the nominal full-scale voltage can be achieved when V > +11.5V.
SS
DD
Note 2: Gain is calculated from measurements:
for voltages V
for voltages V
for voltages V
for voltages V
= 10V and V = -4V at codes C000 hex and 4F2C hex
DD
DD
DD
DD
SS
= 11.6V and V = -2.9V at codes FFFF hex and 252E hex
SS
= 9.25V and V = -5.25V at codes D4F6 hex and 0 hex
SS
= 8.55V and V = -2.75V at codes C74A hex and 281C hex
SS
Note 3: Steady-state change in any output with an 8V change in an adjacent output.
Note 4: Settling during the first update for an 8V step. The output settles to within the linearity specification on subsequent updates.
Tested with an external sequencer clock frequency of 480kHz.
Note 5: External clock mode with the external clock not toggling.
Note 6: The output voltage is the sum of the DAC output and the voltage at GS. GS gain is measured at 4F2C hex.
Note 7: The sequencer runs at f
= f /4. Maximum speed is limited by settling of the DAC and SHAs. Minimum speed is
ECLK
SEQ
limited by acceptable droop and update time after a Burst Mode Update.
V rise to CS low = 500µs maximum.
DD
Note 8:
Note 9: Guaranteed by gain-error test.
Note 10: The serial interface is inactive. V = V
, V = 0V.
LOGIC IL
IH
Note 11: The serial interface is active. V = V
, V = 0V.
LOGIC IL
IH
4
_______________________________________________________________________________________
16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
Typical Operating Characteristics
(V
= +10V, V = -4V, V
= +2.5V, V = 0V, T = +25°C, unless otherwise noted.)
REF GS
A
DD
SS
INTEGRAL NONLINEARITY
VS. TEMPERATURE
INTEGRAL NONLINEARITY vs. CODE
DIFFERENTIAL NONLINEARITY vs. CODE
0.007
0.005
0.003
0.001
1.4
1.0
0.010
0.008
0.006
0.004
0.002
0
0.6
0.2
-0.001
-0.003
-0.005
-0.007
-0.2
-0.6
-1.0
-1.4
4018 11769 19520 27271 35021 42723 58268
INPUT CODE
4018 11769 19520 27271 35021 42723 58268
INPUT CODE
-40
-15
10
35
60
85
TEMPERATURE (°C)
DIFFERENTIAL NONLINEARITY
VS. TEMPERATURE
OFFSET VOLTAGE
VS. TEMPERATURE
DROOP RATE vs. TEMPERATURE
100
10
1.0
0.9
0.8
0.7
0.6
0.5
-10
-12
-14
-16
-18
-20
CODE = 4F2C hex
EXTERNAL CLOCK MODE
NO CLOCK APPLIED
V
DD
= +8.55V
SS
V
= -4V
CODE = 4F2C hex
1
0.100
0.010
0.001
0.0001
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
NEGATIVE SUPPLY PSRR
VS. FREQUENCY
POSITIVE SUPPLY PSRR
VS. FREQUENCY
GAIN ERROR VS. TEMPERATURE
-90
-90
0.05
0.04
0.03
0.02
0.01
0
-80
-70
-80
-70
-60
-50
-40
-30
-60
-50
-40
-30
-20
-20
-10
CODE = C168 hex
-10
0
OFFSET CODE = 4F2C hex
0
0.001
0.01
0.1
1
10
100
-40
-15
10
35
60
85
0.01
0.1
1
10
100
FREQUENCY (kHz)
TEMPERATURE (°C)
FREQUENCY (kHz)
_______________________________________________________________________________________
5
16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
Typical Operating Characteristics (continued)
(V
= +10V, V = -4V, V
= +2.5V, V = 0V, T = +25°C, unless otherwise noted.)
REF GS
A
DD
SS
LOGIC SUPPLY CURRENT
vs. LOGIC SUPPLY VOLTAGE
LOGIC SUPPLY CURRENT
VS. LOGIC INPUT HIGH VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
36
34
32
30
28
26
24
22
20
900
1200
I
DD
SS
1000
800
600
400
200
0
800
700
600
500
400
I
INTERFACE INACTIVE
INTERFACE INACTIVE
f
= 20MHz
SCLK
-40
-15
10
35
60
85
4.75
5.00
5.25
5.50
2.0
2.5
3.0
3.5
4.0
4.5
5.0
TEMPERATURE (°C)
LOGIC SUPPLY VOLTAGE (V)
LOGIC INPUT HIGH VOLTAGE (V)
POSITIVE SETTLING TIME
(8V STEP)
NEGATIVE SETTLING TIME
(8V STEP)
POSITIVE SETTLING TIME
(100mV STEP)
MAX5621 toc13
MAX5621 toc14
MAX5621 toc15
3.5V
0V
3.5V
0V
3.5V
ECLK
ECLK
ECLK
0V
V
OUT_
50mV/div
AC-COUPLED
5V/div
V
V
5V/div OUT_
OUT_
1µs/div
1µs/div
1µs/div
NEGATIVE SETTLING TIME
(100mV STEP)
OUTPUT NOISE
MAX5621 toc16
MAX5621 toc17
3.5V
0V
ECLK
OUT_
1mV/div
50mV/div
AC-COUPLED
V
OUT_
1µs/div
250µs/div
6
_______________________________________________________________________________________
16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
Pin Description
PIN
NAME
FUNCTION
TQFP
THIN QFN
1, 2, 20, 22, 24, 27, 29, 34,
36, 38, 42, 44, 50, 52, 54,
57, 59, 61
1, 2, 17, 21, 23, 25, 28, 30,
34, 36, 38, 40, 44, 46, 51,
53, 55, 57, 60, 62, 64, 68
N.C.
GS
No Connection. Not internally connected.
3
3
Ground-Sensing Input
+5V DAC Power Supply
Reset Input
4
4
V
LDAC
5
5
RST
CS
6
6
Chip-Select Input
Serial Data Input
Serial Clock Input
+5V Logic Power Supply
Immediate Update Mode
External Sequencer Clock Input
Clock-Select Input
Digital Ground
7
7
DIN
8
8
SCLK
9
9
V
LOGIC
IMMED
ECLK
10
10
11
11
12
12
CLKSEL
DGND
13
13
14
14
V
+5V Sample-and-Hold Power Supply
Analog Ground
Negative Power Supply
Positive Power Supply
Output Clamp Low Voltage
Output 0
LSHA
15, 25, 40, 55, 62
15, 26, 42, 58, 65
AGND
16, 32, 46
16, 33, 48
V
SS
17, 39, 48
18, 41, 50
V
DD
18, 33, 49
19, 35, 52
CL
19
21
20
22
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
CH
Output 1
23
24
Output 2
26
27
Output 3
28
29
Output 4
30
31
Output 5
35
37
Output 6
37
39
Output 7
41
43
Output 8
43
45
Output 9
45
47
Output 10
31, 47, 64
51
32, 49, 67
54
Output Clamp High Voltage
Output 11
OUT11
OUT12
OUT13
OUT14
OUT15
REF
53
56
Output 12
56
59
Output 13
58
61
Output 14
60
63
Output 15
63
66
Reference Voltage Input
_______________________________________________________________________________________
7
16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
CH
OUT0
ECLK
CLOCK
CLKSEL
SAMPLE-
AND-HOLD
ARRAY
R
SAMPLE
E
G
I
S
T
E
R
DATA READY
SEQUENCER
OUT15
CL
R
E
G
I
S
T
E
R
GAIN AND
OFFSET
CORRECTION
GS
READ ENABLE
16-BIT
DAC
SEQUENTIAL
ADDRESS
16 x 16
SRAM
REF
2:1
M
U
LAST
ADDRESS
X
CS
SCLK
DIN
ADDR SELECT
MAX5621
MAX5622
MAX5623
SERIAL
INTERFACE
WRITE ENABLE
D[15:0]
IMMED
RST
Figure 1. Functional Diagram
t
CSH1
CS
t
CSHO
t
CSS1
t
t
t
CL
CSSO
CH
SCLK
DIN
t
DH
t
DS
B23
B22
B0
Figure 2. Serial Interface Timing Diagram
8
_______________________________________________________________________________________
16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
Detailed Description
V
+ 0.75V ≤ V
≤ V - 2.4V
(
)
(
)
SS
OUT_
DD
Digital-to-Analog Converter
The MAX5621/MAX5622/MAX5623 16-bit digital-to-ana-
log converters (DACs) are composed of two matched
sections. The four MSBs are derived through 15 identi-
cal matched resistors and the lower 12 bits are derived
through a 12-bit inverted R-2R ladder.
The device has a fixed theoretical output range deter-
mined by the reference voltage, gain, and midscale offset.
The output voltage for a given input code is calculated
with the following:
Sample-and-Hold Amplifiers
The MAX5621/MAX5622/MAX5623 contain 16 buffered
sample/hold circuits with internal hold capacitors.
Internal hold capacitors minimize leakage current,
dielectric absorption, feedthrough, and required board
space. The MAX5621/MAX5622/MAX5623 provide a
very low 1mV/s droop rate.
code
65535
VOUT
=
× VREF × 5.2428 -
1.6214× V
+ VGS
(
)
REF
where code is the decimal value of the DAC input
code, V is the reference voltage, and V is the
REF
GS
Output
The MAX5621/MAX5622/MAX5623 include output buffers
on each channel. The device contains output resistors in
series with the buffer output (Figure 3) for ease of output
filtering and capacitive load driving stability.
voltage at the ground-sense input. With a 2.5V refer-
ence, the nominal end points are -4.0535V and
+9.0535V (Table 1). Note that these are “virtual” inter-
nal end-point voltages and cannot be reached with all
combinations of negative and positive power-supply
voltages. The nominal, usable DAC end-point codes for
the selected power supplies can be calculated as:
Output loads increase the analog supply current (I
DD
and I ). Excessively loading the outputs drastically
SS
increases power dissipation. Do not exceed the maxi-
mum power dissipation specified in the Absolute
Maximum Ratings.
Lower end-point code = 32768 - ((2.5V - (V +0.75)) /
SS
200µV) (result ≥ 0)
Upper end-point code = 32768 + ((V
The maximum output voltage range depends on the
analog supply voltages available and the output clamp
voltages (see the Output Clamp section):
- 2.4 - 2.5V) /
DD
200µV) (result ≤ 65535)
V
REF
CH
GAIN
AND
OFFSET
R
O
OUT_
16-BIT
DAC
DAC
DATA
A = 1
V
C
HOLD
R
L
CL
ONE OF 16 SHA CHANNELS
GS
Figure 3. Analog Block Diagram
Table 1. Code Table
DAC INPUT CODE
NOMINAL OUTPUT
VOLTAGE (V)
V
= +2.5V
REF
MSB
LSB
1111 1111 1111 1111
9.0535
6.15
2.5
Full-scale output
1100 0111 0100 1010
1000 0000 0000 0000
Maximum output with V
Midscale output
= 8.55V
DD
0100 1111 0010 1100
0
V
= 0; all outputs default to this code after power-up
OUT_
0010 1000 0001 1100
0000 0000 0000 0000
-2.0
Minimum output with V = -2.75V
SS
-4.0535
Zero-scale output
_______________________________________________________________________________________
9
16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
The resistive voltage-divider formed by the output resis-
Table 2. Channel/Output Selection
tor (R ) and the load impedance (R ), scales the out-
O
L
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OUTPUT
put voltage. Determine V
as follows:
OUT_
OUT0 selected
OUT1 selected
OUT2 selected
OUT3 selected
OUT4 selected
OUT5 selected
OUT6 selected
OUT7 selected
OUT8 selected
OUT9 selected
OUT10 selected
OUT11 selected
OUT12 selected
OUT13 selected
OUT14 selected
OUT15 selected
RL
RL +RO
Scaling Factor =
VOUT_ = VCHOLD × scaling factor
Ground Sense
The MAX5621/MAX5622/MAX5623 include a ground-
sense input (GS), which allows the output voltages to
be referenced to a remote ground. The voltage at GS is
added to the output voltage with unity gain. Note that
the resulting output voltage must be within the valid
output voltage range set by the power supplies.
Output Clamp
The MAX5621/MAX5622/MAX5623 clamp the output
between two externally applied voltages. Internal
diodes at each channel restrict the output voltage to:
V
+ 0.7V ≥ V
≥ V − 0.7V
(
)
(
)
CH
OUT_
CL
The clamping diodes allow the MAX5621/MAX5622/
MAX5623 to drive devices with restricted input ranges.
The diodes also allow the outputs to be clamped during
power-up or fault conditions. To disable output clamping,
Serial Input Data Format and
Control Codes
The 24-bit serial input format, shown in Figure 4, compris-
es 16 data bits (D15–D0), 4 address bits (A3–A0), 1
required zero bit after the address bits, 2 control bits (C1,
C0), and a fill zero. The address code selects the output
channel as shown in Table 2. The control code configures
the device as follows:
connect CH to V
and CL to V , setting the clamping
SS
DD
voltages beyond the maximum output voltage range.
Serial Interface
The MAX5621/MAX5622/MAX5623 are controlled by an
SPI/QSPI/MICROWIRE-compatible 3-wire interface.
Serial data is clocked into the 24-bit shift register in an
MSB-first format, with the 16-bit DAC data preceding
the 4-bit SRAM address, required zero bit, 2-bit control,
and a fill 0 (Figure 4). The input word is framed by CS.
The first rising edge of SCLK after CS goes low clocks
in the MSB of the input word.
1) If C1 = 1, immediate update mode is selected.
If C1 = 0, burst mode is selected.
2) If C0 = 0, the internal sequencer clock is selected. If
C0 = 1, the external sequencer clock is selected.
This must be repeated with each data word to main-
tain external input.
When each serial word is complete, the value is stored
in the SRAM at the address indicated and the control
bits are saved. Note that data can be corrupted if CS is
not held low for an integer multiple of 24 bits.
The operating modes can also be selected externally
through CLKSEL and IMMED. In the case where the
control bit in the serial word and the external signal
conflict, the signal that is a logic 1 is dominant.
All of the digital inputs include Schmitt-trigger buffers to
accept slow-transition interfaces. Their switching thresh-
old is compatible with TTL and most CMOS logic levels.
DATA
ADDRESS
CONTROL
C1 C0 0
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D0 A3 A2 A1 A0
0
MSB
LSB
Figure 4. Input Word Sequence
10 ______________________________________________________________________________________
16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
Table 3. Update Mode
2/f
SEQ
SHA ARRAY
UPDATE
SEQUENCE
UPDATE MODE
Immediate update mode
Burst mode
UPDATE TIME
2/f
1
2
3
7
SKIP 12
7
8
9
SEQ
33/f
SEQ
CHANNEL 12
UPDATED
Modes of Operation
The MAX5621/MAX5622/MAX5623 feature three modes
of operation:
CS
INTERRUPTED
CHANNEL REFRESHED
LOAD ADDRESS 12
•
•
•
Sequence mode
Immediate update mode
Burst mode
DIN
24-BIT
WORD
Figure 5. Immediate Update Mode Timing Example
Sequence Mode
Sequence mode is the default operating mode. The
internal sequencer continuously scrolls through the
SRAM, updating each of the 16 SHAs. At each SRAM
address location, the stored 16-bit DAC code is loaded
to the DAC. Once settled, the DAC output is acquired
by the corresponding SHA. Using the internal
sequencer clock, the process typically takes 320µs to
update all 16 SHAs (20µs per channel). Using an exter-
nal sequencer clock the update process takes 128
clock cycles (eight clock cycles per channel).
being refreshed. Under conditions of extremely frequent
immediate updates (i.e., 1000 successive updates),
unacceptable droop can result.
Figure 5 shows an example of an immediate update
operation. In this example, data for channel 12 is
loaded while channel 7 is being refreshed. The
sequencer operation is interrupted, and no other chan-
nels are refreshed as long as CS is held low. Once CS
returns high, and the remainder of an f
period (if
SEQ
any) has expired, channel 12 is updated to the new
data. Once channel 12 has been updated, the
sequencer resumes normal operation at the interrupted
channel 7.
Immediate Update Mode
Immediate update mode is used to change the con-
tents of a single SRAM location, and update the corre-
sponding SHA output. In immediate update mode, the
selected output is updated before the sequencer
resumes operation. Select immediate update mode by
driving either IMMED or C1 high.
Burst Mode
Burst mode allows multiple SRAM locations to be
loaded at high speed. During burst mode, the output
voltages are not updated until the data burst is com-
plete and control returns to the sequencer. Select burst
mode by driving both IMMED and C1 low.
The sequencer is interrupted when CS is taken low. The
input word is then stored in the proper SRAM address.
The DAC conversion and SHA sample in progress are
completed transparent to the serial bus activity. The
SRAM location of the addressed channel is then modi-
fied with the new data. The DAC and SHA are updated
with the new voltage. The sequencer then resumes
scrolling at the interrupted SRAM address.
The sequencer is interrupted when CS is taken low. All
or part of the memory can be loaded while CS is low.
Each data word is loaded into its specified SRAM
address. The DAC conversion and SHA sample in
progress are completely transparent to the serial bus
activity. When CS is taken high, the sequencer
resumes scrolling at the interrupted SRAM address.
New values are updated when their turn comes up in
the sequence.
This operation can take up to two cycles of the
sequencer clock. Up to one cycle is needed to allow the
sequencer to complete the operation in progress before
it is freed to update the new channel. An additional
cycle is required to read the new data from memory,
update the DAC, and strobe the sample-and-hold. The
sequencer resumes scrolling from the location at which
it was interrupted. Normal sequencing is suppressed
while loading data, thus preventing other channels from
After burst mode is used, it is recommended that at
least one full sequencer loop (320µs) is allowed to
occur before the serial port is accessed again. This
ensures that all outputs are updated before the
sequencer is interrupted.
______________________________________________________________________________________ 11
16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
+5V
+10V
2/f
SEQ
SHA ARRAY
UPDATE
SEQUENCE
6
7
SKIP
SKIP SKIP
7
8
5
6
7
0.1µF
0.1µF
33/f TO UPDATE
SEQ
ALL CHANNELS
V
V
V
CS
V
LDAC
LSHA
DD
LOGIC
LOAD MULTIPLE
ADDRESSES
REF
GS
+2.5V
OUT0
OUT1
DIN
CS
DIN
MAX5621
MAX5622
MAX5623
SCLK
Figure 6. Burst Mode Timing Example
IMMED
CLKSEL
ECLK
Figure 6 shows an example of a burst mode operation.
As with the immediate update example, CS falls while
channel 7 is being refreshed. Data for multiple chan-
nels is loaded, and no channels are refreshed as long
as CS remains low. Once CS returns high, sequencing
resumes with channel 7 and continues normal refresh
RST
OUT15
CL
AGND
V
DGND
SS
operation. Thirty-three f
cycles are required before
SEQ
0.1µF
all channels have been updated.
-4V
External Sequencer Clock
An external clock can be used to control the
sequencer, altering the output update rate. The
sequencer runs at 1/4 the frequency of the supplied
clock (ECLK). The external clock option is selected by
driving either C0 or CLKSEL high.
Figure 7. Typical Operating Circuit
Applications Information
When CLKSEL is asserted, the internal clock oscillator
is disabled. This feature allows synchronizing the
sequencer to other system operations, or shutting down
of the sequencer altogether during high-accuracy sys-
tem measurements. The low 1mV/s droop of these
devices ensures that no appreciable degradation of the
output voltages occurs, even during extended periods
of time when the sequencer is disabled.
Power Supplies and Bypassing
Grounding and power-supply decoupling strongly influ-
ence device performance. Digital signals may couple
through the reference input, power supplies, and
ground connection. Proper grounding and layout can
reduce digital feedthrough and crosstalk. At the device
level, a 0.1µF capacitor is required for the V , V
,
SS
DD
and V pins. They should be placed as close to the
L_
pins as possible. More substantial decoupling at the
board level is recommended and is dependent on the
number of devices on the board (Figure 7).
Power-On Reset
A power-on reset (POR) circuit sets all channels to 0V
(code 4F2C hex) in sequence, requiring 320µs. This pre-
vents damage to downstream ICs due to arbitrary refer-
ence levels being presented following system power-up.
This same function is available by driving RST low.
During the reset operation, the sequencer is run by the
internal clock, regardless of the state of CLKSEL. The
reset process cannot be interrupted, and serial inputs
are ignored until the entire reset process is complete.
The MAX5621/MAX5622/MAX5623 have three separate
+5V logic power supplies, V
, V
, and V
.
LSHA
LDAC LOGIC
V
V
V
powers the 16-bit digital-to-analog converter,
powers the control logic of the SHA array, and
powers the serial interface, sequencer, internal
LDAC
LSHA
LOGIC
clock and SRAM. Additional filtering of V
and
LDAC
V
LSHA
improves the overall performance of the device.
12 ______________________________________________________________________________________
16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
Pin Configurations (continued)
Chip Information
TRANSISTOR COUNT: 16,229
PROCESS: BiCMOS
TOP VIEW
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
N.C.
N.C.
GS
1
48
47 CH
46
V
DD
2
3
4
5
6
7
8
9
V
SS
V
45 OUT10
44 N.C.
LDAC
RST
CS
43 OUT9
42 N.C.
DIN
SCLK
41 OUT8
40 AGND
MAX5621
MAX5622
MAX5623
V
LOGIC
IMMED 10
ECLK 11
39 V
DD
38 N.C.
37 OUT7
36 N.C.
35 OUT6
34 N.C.
33 CL
CLKSEL 12
DGND 13
V
14
AGND 15
16
LSHA
V
SS
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TQFP
______________________________________________________________________________________ 13
16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
14 ______________________________________________________________________________________
16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
68L QFN THIN, 10x10x0.8 MM
21-0142
A
______________________________________________________________________________________ 15
16-Bit DACs with 16-Channel
Sample-and-Hold Outputs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
68L QFN THIN, 10x10x0.8 MM
21-0142
A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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