MAX5651ETJ_技术文档

19-3936; Rev 0; 2/06

16-Bit, Parallel-Input, Voltage-Output DACs

with Internal Reference

General Description

Features

♦ 16-Bit Resolution

The MAX5650/MAX5651/MAX5652 parallel-input, volt-

age-output, 16-bit, digital-to-analog converters (DACs)

provide monotonic 16-bit output voltage over the full

extended operating temperature range. The MAX5650/

MAX5651 include an internal precision low drift

(10ppm/°C) bandgap voltage reference, while the

MAX5652 requires an external reference. The MAX5650

operates from a +5V single supply and has a +4.096V

internal reference. The MAX5651 operates from either a

+3V or +5V single supply and has a +2.048V internal

reference. The MAX5652 operates from either a +3V or

+5V single supply and accepts an input reference voltage

♦ Parallel 16-Bit or 2-Byte Double Buffered Interface

♦ Guaranteed Monotonic

♦ Maximum INL: ±± LꢀB

♦ Fast 2µs ꢀettling Time

♦ Clear Input (CLR) ꢀets Output to Zero-ꢀcale or

Midscale

♦ Integrated Precision Resistors for Bipolar

Operation

♦ Integrated Precision Bandgap Reference:

+±.096V (MAX5650)

between +2V and AV . TheMAX5650/MAX5651/

DD

MAX5652 parallel inputs are double buffered and con-

figurable as a single 16-bit wide input or a 2-byte input.

The MAX5650/MAX5651/MAX5652 unbuffered DAC

+2.0±8V (MAX5651)

voltage output ranges from 0 to V

.

REF

The MAX5650/MAX5651/MAX5652 feature an active-low

hardware clear input (CLR) that clears the registers and

the output to zero-scale (0000 hex) or midscale (8000

hex), depending on the state of the MID/ZERO input.

These devices include matched scaling resistors for use

with a precision external op amp (such as the MAX400)

to generate a bipolar output-voltage swing.

Ordering Information

PACKAGE

CODE

PART

PIN-PACKAGE

MAX5650ETJ

MAX5651ETJ**

MAX5652ETJ**

32 TQFN-EP* (5mm x 5mm)

T3255-4

The MAX5650/MAX5651/MAX5652 are available in a 32-

pin, 5mm x 5mm TQFN package and are guaranteed

over the extended temperature range (-40°C to +85°C).

Note: All devices specified over the -40°C to +85°C

temperature range.

*EP = Exposed paddle. Connect to AGND or leave unconnected.

**Future product—contact factory for availability.

For 14-bit, pin-compatible versions of the MAX5650/

MAX5651/MAX5652, refer to the MAX5653/MAX5654/

MAX5655 datasheet.

Functional Diagram

For 12-bit, pin-compatible versions of the MAX5650/

MAX5651/MAX5652, refer to the MAX5656/MAX5657/

MAX5658 datasheet.

DV

DD

AV

DD

REF

INA

D15

BANDGAP

REFERENCE

(MAX5650/

MAX5651

ONLY)

Applications

8-BIT MSB

INPUT

REGISTER

R

Automatic Test Equipment

Process Control

Digital Calibration

Actuator Control

Servo Loops

MTAP

Waveform Generators

Motor Control

D8

D7

16-BIT DAC

REGISTER

INB

8-BIT LSB

INPUT

REGISTER

16-BIT DAC

OUT

Selector Guide

D0

GND

ꢀUPPLY

PART

REFERENCE

(V)

INL

(LꢀB, max)

CSMSB

VOLTAGE (V)

WR

MAX5650ETJ +4.75 to +5.25 Internal, +4.096

4

—

MAX5650

MAX5651

MAX5652

CSLSB

LDAC

CLR

MAX5651ETJ

MAX5652ETJ

+2.7 to +5.25

Internal, +2.048

External

POWER-ON

RESET

DGND

MID/ZERO

AGND

Pin Configuration appears at end of data sheet.

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

16-Bit, Parallel-Input, Voltage-Output DACs

with Internal Reference

ABꢀOLUTE MAXIMUM RATINGꢀ

AV

DV

to DV ……………………………………………........... 6V

INB to AGND..……………………………………………-6V to +6V

INB to MTAP………………………………………………-6V to +6V

Maximum Current into Any Pin ......................................... 50mA

DD

to AGND, GND…………………………...…… -0.3V to +6V

to DGND…..…………………………………… -0.3V to +6V

DGND to GND……………………………………… -0.3V to +0.3V

DGND, GND to AGND…………………………….. -0.3V to +0.3V

D0–D15, CSLSB, CSMSB, WR, LDAC, CLR, MID/ZERO,

Continuous Power Dissipation (T = +70°C)

A

32-Pin TQFN (derate 20.8mW/°C above +70°C)….2758.6mW

Operating Temperature Range …………………..-40°C to +85°C

Storage Temperature Range…………………….-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

to DGND…………………………………-0.3V to (DV + 0.3V)

DD

REF to AGND……………………………….-0.3V to (AV + 0.3V)

DD

OUT, MTAP, INA to AGND, GND...........................-0.3V to AV

DD

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERIꢀTICꢀ—MAX5650

(AV

= DV

= +4.75V to +5.25V, AGND = DGND = GND = 0V, V

= internal, R = ∞, C = 10pF, C

= 1µF,

DD

REF

L

REF

T

A

= T

to T

, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)

MAX A

MIN

PARAMETER

ꢀYMBOL

CONDITIONꢀ

MIN

TYP

MAX

UNITꢀ

ꢀTATIC PERFORMANCE—ANALOG ꢀECTION

Resolution

N

16

Bits

Differential Nonlinearity

DNL

Guaranteed monotonic

0.5

1

LSB

Integral Nonlinearity

INL

4

LSB

µV

Zero-Code Offset Error

ZSE

80

Zero-Code Temperature

Coefficient

ppmFS/

°C

ZSTC

(Note 2)

(Note 3)

(Note 2)

(Note 4)

0.05

0.1

Gain Error

10

LSB

Gain-Error Temperature

Coefficient

ppm/°C

DAC Output Resistance

Bipolar Resistor Ratio

R

6.2

1

kΩ

Ω/Ω

%

OUT

R

/ R

INA

INB

Bipolar Resistor Ratio Error

0.05

Bipolar Resistor Ratio

Temperature Coefficient

(Note 2)

0.5

ppm/°C

Bipolar Resistor Value

VOLTAGE REFERENCE (R

Voltage Reference

R

and R

(Note 4)

12.4

kΩ

INB

INA

= 10kΩ, C

= 1µF)

REF

REF(MIN)

V

T

A

= +25°C

4.081

4.106

10

4.111

0.6

V

REF

Reference Voltage Temperature

Coefficient

TCV

(Note 2)

0 ≤ I

ppm/°C

REF

V

/

OUT

Reference Load Regulation

Short-Circuit Current

≤ V

/ 10kΩ

0.1

6

µV/µA

mA

OUT

REF

I

OUT

Reference Load

I

400

0.5

µA

ms

REF

Reference Power-Up Time

Power-Supply Rejection Ratio

Settle to 0.5 LSB

AV = DV = 4.75V to 5.25V (FS code)

4

PSRR

mV/V

DD

2

_______________________________________________________________________________________

16-Bit, Parallel-Input, Voltage-Output DACs

with Internal Reference

ELECTRICAL CHARACTERIꢀTICꢀ—MAX5650 (continued)

(AV

= DV

= +4.75V to +5.25V, AGND = DGND = GND = 0V, V

= internal, R = ∞, C = 10pF, C

= 1µF,

DD

REF

L

REF

T

A

= T

to T

, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)

MAX A

MIN

PARAMETER

ꢀYMBOL

CONDITIONꢀ

MIN

TYP

MAX

UNITꢀ

DYNAMIC PERFORMANCE—ANALOG ꢀECTION

Output Settling Time

DAC Glitch Impulse

7F60H to 80A0H or 80A0H to 7F60H to 0.5 LSB

Major carry transition

2

µs

10

nV·s

Code = 0000 hex; CSLSB = CSMSB =

Digital Feedthrough

3

nV·s

DV , D0–D15 transition from 0 to DV

DD

DYNAMIC PERFORMANCE—VOLTAGE REFERENCE ꢀECTION

Frequency = 0.1Hz to 10Hz

Frequency = 10Hz to 1kHz

15

12

µV

P-P

Noise Voltage (Note 6)

µV

RMS

For zero-scale to full-scale or full-scale to

zero-scale transition

V

Glitch Impulse

10

nV·s

REF

ꢀTATIC PERFORMANCE—DIGITAL INPUTꢀ

Input High Voltage

Input Low Voltage

Input Current

V

(Note 8)

2.4

V

IH

V

0.8

1

IL

I

µA

pF

IN

Input Capacitance

POWER ꢀUPPLY

Analog Supply Range

C

5

IN

AV

DV

4.75

5.25

V

DD

AV

-

AV

DD

+ 0.3

DD

Digital Supply Range

(Note 9)

DD

0.3

I

+

DVDD

AVDD

I

Positive Supply Current

All digital inputs at DV or 0V, AV = DV

DD

2

mA

DD

TIMING CHARACTERIꢀTICꢀ (Figure ±)

CSMSB and CSLSB Pulse Width

WR Pulse Width

t

40

ns

CS

t

WR

CSMSB or CSLSB to WR

Setup Time

t

0

ns

CWS

CSMSB or CSLSB to WR

Hold Time

t

CWH

Data Valid to WR Setup Time

Data Valid to WR Hold Time

LDAC Pulse Width

t

40

0

ns

DWS

t

DWH

t

40

LDAC

CLR Pulse Width

t

CLR

Note 1: 100% production tested at T = +25°C and T = +85°C. Guaranteed by design at T = -40°C.

A

Note 2: Temperature coefficient is determined by the box method in which the maximum change over the temperature range is

divided by ∆T.

Note 3: Gain error is measured at the full-scale code and is calculated with respect to the reference voltage (REF).

Note ±: Resistor tolerance is typically 20%.

Note 5: Guaranteed by design, not production tested.

Note 6: Noise is measured at the reference output.

Note 7: Min/max range guaranteed by gain-error test. Operation outside min/max limits results in degraded performance.

Note 8: The devices draw higher supply current when the digital inputs are driven between (DV - 0.5V) and (DGND + 0.5V).

DD

See Digital Supply Current vs. Digital Input Voltage in the Typical Operating Characteristics.

Note 9: For optimal performance AV = DV

.

DD

_______________________________________________________________________________________

3

16-Bit, Parallel-Input, Voltage-Output DACs

with Internal Reference

Typical Operating Characteristics

(AV

= DV

= +5V, AGND = DGND = GND = 0V, R = ∞, C = 10pF, C

= 1µF for the MAX5650/MAX5651, T = +25°C, unless

DD

L

REF A

otherwise noted.)

ZERO-CODE OFFSET ERROR

vs. TEMPERATURE (MAX5650)

GAIN ERROR

vs. TEMPERATURE (MAX5650)

INTEGRAL NONLINEARITY

vs. TEMPERATURE

25

20

15

10

5

1.0

0.5

0

2

1

+INL

0

-1

-2

-3

-0.5

-1.0

-INL

0

-40

-15

10

35

60

85

-40

-15

10

35

60

85

-40

-15

10

35

60

85

TEMPERATURE (°C)

REFERENCE VOLTAGE

vs. TEMPERATURE (MAX5650)

TOTAL SUPPLY CURRENT

vs. TEMPERATURE (MAX5650)

REFERENCE-VOLTAGE NOISE (MAX5650)

4.100

4.099

4.098

4.097

4.096

4.095

1.2

1.1

1.0

0.9

0.8

0.7

f = 0.1Hz TO 10Hz

10µV/div

CODE = FFFF

-40

-15

10

35

60

85

-40

-15

10

35

60

85

1s/div

TEMPERATURE (°C)

REFERENCE VOLTAGE

vs. DIGITAL INPUT CODE

FULL-SCALE

STEP RESPONSE (MAX5650)

DIGITAL SUPPLY CURRENT

vs. DIGITAL INPUT VOLTAGE (MAX5650)

MAX5650 toc09

4.09699

4.09698

4.09697

4.09696

4.09695

4.09694

4.09693

100

10

D1

5V/div

0

1

0.1

0.01

V

OUT

0.001

0.0001

0.00001

2V/div

0

ALL DIGITAL INPUTS

CONNECTED TOGETHER

AV = DV = 5.25V

DD

CODE FFFF TO OOOO STEP

400ns/div

0

20000

40000

60000

50000 70000

10000

30000

CODE

0

1

2

3

4

5

6

DIGITAL INPUT VOLTAGE (V)

±

_______________________________________________________________________________________

16-Bit, Parallel-Input, Voltage-Output DACs

with Internal Reference

Typical Operating Characteristics (continued)

(AV

= DV

= +5V, AGND = DGND = GND = 0V, R = ∞, C = 10pF, C = 1µF for the MAX5650/MAX5651, T = +25°C, unless

REF A

DD

L

otherwise noted.)

FULL-SCALE

STEP RESPONSE (MAX5650)

MAJOR-CARRY GLITCH

MAX5650 toc10

MAX5650 toc11

MAX5650 toc12

D1

5V/div

D15

5V/div

D15

5V/div

0V

V

OUT

20mV/div

OUT

V

OUT

20mV/div

2V/div

0V

CODE 0000 TO FFFF STEP

400ns/div

CODE 7FFF TO 8000 STEP

CODE 8000 TO 7FFF STEP

1µs/div

SMALL-SIGNAL

SETTLING TIME

SMALL-SIGNAL

SETTLING TIME

DIGITAL FEEDTHROUGH (MAX5650)

MAX5650 toc14

MAX5650 toc15

D1

5V/div

V

OUT

V

10mV/div

OUT

10mV/div

0V

V

OUT

20mV/div

FS TRANSITION

CODE 0000 TO 00A2 STEP

400ns/div

CODE 00A2 TO 0000 STEP

400ns/div

1µs/div

REFERENCE FEEDTHROUGH (MAX5652)

REFERENCE BANDWIDTH (MAX5652)

0

-20

5

0

V

= 3.5V + 0.5V

P-P

REF

CODE = 0000h

-5

-10

-40

-15

-20

-25

-30

-35

-40

-45

-50

-60

-80

CODE = FFFFh

-100

-120

V

= 3.5V + 0.5V

REF

P-P

0.01

0.1

1

10

100 1000 10,000

10

100

1000

10,000

FREQUENCY (kHz)

_______________________________________________________________________________________

5

16-Bit, Parallel-Input, Voltage-Output DACs

with Internal Reference

Pin Description

1

NAME

D0

FUNCTION

Data Input Bit 0 (LSB)

Data Input Bit 1

2

D1

3

D2

Data Input Bit 2

4

D3

Data Input Bit 3

5

D4

Data Input Bit 4

6

D5

Data Input Bit 5

7

D6

Data Input Bit 6

8

D7

Data Input Bit 7

9

D8

Data Input Bit 8

10

11

12

13

14

15

16

17

18

D9

Data Input Bit 9

D10

D11

D12

D13

D14

D15

DGND

Data Input Bit 10

Data Input Bit 11

Data Input Bit 12

Data Input Bit 13

Data Input Bit 14

Data Input Bit 15 (MSB)

Digital Ground

DV

Digital Supply. Bypass DV

to DGND with a 0.1µF capacitor as close to the device as possible.

DD

Lower 8-Bit Active-Low Chip Select. When CSLSB is driven low the data inputs D0–D7 are loaded to

the input and DAC registers depending on the state of WR and LDAC (see Table 1).

19

20

CSLSB

CSMSB

Upper 8-Bit Active-Low Chip Select. When CSMSB is driven low the data inputs D8–D15 are loaded

to the input and DAC registers depending on the state of WR and LDAC (see Table 1).

Active-Low Write Input. While chip select (CSLSB and/or CSMSB) is low, the data on D0–D7 and/or

D8–D15 is presented to the input register when WR is low. A rising edge on WR then latches the data

to the input register (see Table 1). Hold WR low to make the input register transparent.

21

22

23

WR

LDAC

CLR

Asynchronous Active-Low Load DAC Input. When LDAC is low, the data in the input register is

presented to the DAC register. A rising edge on LDAC then latches the data to the DAC register (see

Table 1). Hold WR and LDAC low to perform a write-through operation.

Asynchronous Active-Low Clear DAC Input. Pull CLR low to clear the input and DAC registers and

set the DAC output to midscale (8000 hex), if MID/ZERO is high, or zero scale (0000 hex), if

MID/ZERO is low.

Midscale/Zero-Scale Clear Output Value Select. Pull MID/ZERO low for zero-scale clear output (0000

hex) or high for midscale clear output (8000 hex).

24

25

26

MID/ZERO

MTAP

Internal Scaling Resistor Midpoint Tap. Connect to the inverting input of an external op amp.

Internal Resistor Input B. Free end of internal resistor (R ). Connect to the output of an external

INB

output buffer for bipolar operation.

INB

27

28

29

AV

Analog Supply. Bypass AV

Analog Ground

to AGND with a 0.1µF capacitor as close to the device as possible.

DD

AGND

INA

Internal Resistor Input A. Free end of internal resistor (R ). Connect to REF for bipolar operation.

INA

6

_______________________________________________________________________________________

16-Bit, Parallel-Input, Voltage-Output DACs

with Internal Reference

Pin Description (continued)

NAME

FUNCTION

Internal Reference Voltage Output (MAX5650/MAX5651). Connect a 1µF < C

< 47µF between

REF

REF and AGND as close to the device as possible. The internal reference voltage of the MAX5650 is

+4.096V and +2.048V for the MAX5651.

30

REF

External Reference Voltage Input (MAX5652). Connect to an external voltage reference source

between +2V and AV

.

DD

31

32

—

OUT

GND

EP

DAC Output

DAC Ground

Exposed paddle. Connect to AGND or leave unconnected.

Typical Application Circuits

DV

DD

AV

DD

REF

INA

D15

BANDGAP

REFERENCE

(MAX5650/

MAX5651

ONLY)

8-BIT MSB

INPUT

REGISTER

R

8-BIT BUS

MTAP

D8

D7

16-BIT DAC

REGISTER

INB

8-BIT LSB

INPUT

REGISTER

OUT

0 TO V

µC

16-BIT DAC

REF

D0

CSMSB

WR

GND

CONTROL

LINES

MAX5650

MAX5651

MAX5652

CSLSB

LDAC

CLR

POWER-ON

RESET

DGND

AGND

MID/ZERO

Figure 1. Typical Application Circuit for µC Byte-Wide Interface

_______________________________________________________________________________________

7

16-Bit, Parallel-Input, Voltage-Output DACs

with Internal Reference

Typical Application Circuits (continued)

ACTUATOR

DRIVE

CIRCUIT

DV

DD

AV

DD

REF

INA

R

D15

BANDGAP

8-BIT MSB

INPUT

REGISTER

REFERENCE

(MAX5650/

MAX5651

ONLY)

16-BIT BUS

R

INB

D8

D7

+12V

16-BIT DAC

REGISTER

MTAP

8-BIT LSB

INPUT

REGISTER

0 TO V

REF

OUT

ASIC

16-BIT DAC

0 TO V

D0

REF

CSMSB

GND

CONTROL

LINES

WR

MAX5650

MAX5651

MAX5652

CSLSB

LDAC

CLR

POWER-ON

RESET

DGND

AGND

MID/ZERO

Figure 2. Typical Application Circuit for Unipolar Configuration

8

_______________________________________________________________________________________

16-Bit, Parallel-Input, Voltage-Output DACs

with Internal Reference

Typical Application Circuits (continued)

DV

DD

AV

DD

REF

INA

R

D15

BANDGAP

8-BIT MSB

INPUT

REGISTER

REFERENCE

(MAX5650/

MAX5651 ONLY)

8-BIT BUS

R

INB

D8

D7

+5V

16-BIT DAC

REGISTER

MTAP

8-BIT LSB

INPUT

REGISTER

+/- V

REF

OUT

FPGA

16-BIT DAC

-5V

0 TO V

D0

REF

CSMSB

GND

CONTROL

LINES

WR

MAX5650

MAX5651

MAX5652

CSLSB

LDAC

CLR

POWER-ON

RESET

DGND

AGND

MID/ZERO

Figure 3. Typical Application Circuit for Bipolar Configuration

_______________________________________________________________________________________

9

16-Bit, Parallel-Input, Voltage-Output DACs

with Internal Reference

t

CS

CSLSB

t

CS

CSMSB

t

CWH

CWS

t

CWS

WR

CWH

t

WR

LDAC

WR

t

LDAC

t

DWS

t

DWH

D0–D15

VALID

DATA

VALID

DATA

Figure 4. Timing Diagram

Detailed Description

The MAX5650/MAX5651/MAX5652 parallel-input, volt-

age-output DACs offer full 16-bit performance with less

than 4 LSB integral nonlinearity and less than 1 LSB

differential nonlinearity, ensuring monotonic perfor-

mance over the full operating temperature range. The

DAC is composed of an inverted R2R ladder with the

unbuffered output available directly at OUT, allowing

16-bit performance from the reference voltage to the

DAC ground (GND). The parallel inputs are double-

buffered and configurable as a single 16-bit wide input

or a 2-byte input. The MAX5650/MAX5651 include inter-

nal precision low-drift (10ppm/°C) bandgap voltage ref-

erences of +4.096V and +2.048V, respectively. The

MAX5652 accepts an external reference voltage

between +2V and AV_DD. The MAX5650 operates with a

supply voltage range of +4.75V to +5.25V, while the

MAX5651/MAX5652 operate with a supply voltage

range of +2.7V to +5.25V.

The MAX5652 accepts an external reference with a

voltage range extending from +2V to AV_DD. The output

voltage of the DAC is determined as follows:

V

= V

x N / 65536

OUT

REF

where N is the numeric value of the DAC’s binary input

code (0 to 65535) and V_REFis the reference voltage.

At a full-scale transition, the instantaneous charge

demand from the external reference is about 550pC.

For a reference with a 1µF load capacitor, the charge

demand causes an instantaneous reference voltage

drop of 550µV. A 10µF load capacitor causes a voltage

drop of 55µV. This glitch recovers in a time inversely

proportional to the bandwidth of the voltage reference,

which should be sufficiently fast to recover before the

next DAC transition to avoid accumulation of the glitch

energy and a shift in the average reference voltage. For

a +4.096V reference with 1µF bypass capacitor, it

takes three time constants to recover to 0.5 LSB accu-

racy. Therefore, a 96kHz bandwidth reference recovers

in 5µs while a 960kHz bandwidth reference recovers in

0.5µs.

Voltage Reference

The MAX5650/MAX5651 provide a 10ppm/°C (typ)

internal precision bandgap voltage reference with a

load regulation specification of less than 0.6µV/µA

(maximum) over the entire operating temperature

range. The reference voltage for the MAX5650 is

+4.096V, while the reference voltage for the MAX5651

is +2.048V. Connect a capacitor ranging between 1µF

and 47µF from REF to ground as close to the device as

possible. Use a low-ESR ceramic capacitor such as the

GRM series from Murata.

For further voltage-reference selection assistance, visit

www.maxim-ic.com/appnotes.cfm/appnote_number/754.

10 ______________________________________________________________________________________

16-Bit, Parallel-Input, Voltage-Output DACs

with Internal Reference

Digital Interface

The MAX5650/MAX5651/MAX5652 accept a single 16-

bit wide input or an 8 plus 8-bit wide input. Data latches

or transfers directly to the DAC depending on the state

of the control inputs CLR, CSLSB, CSMSB, LDAC,

MID/ZERO, and WR. All digital inputs are compatible

with both TTL and CMOS logic.

while CSLSB is low, latches the lower byte (D0–D7) into

the input register. The rising edge of WR, while CSMSB is

low, latches the upper byte (D8–D15) into the input regis-

ter. The sequence of loading the MSB and LSB does not

matter. See Figure 1 for byte-wide interface circuit.

The DAC register is transparent when LDAC is low. The

rising edge of LDAC latches data into the DAC register.

The DAC’s analog output reflects the data held in the

DAC register. Both the input register and DAC register

are transparent when CSLSB, CSMSB, WR, and LDAC

are driven low. In this case, any change at D0–D15 appears

at the output instantly. See Table 1 for the truth table.

The double buffered input consists of an input register

and a DAC register (see the Functional Diagram). Data

is loaded into the input register using CSLSB, CSMSB,

and WR. The input register is transparent when WR and

CSLSB and/or CSMSB are low. The rising edge of WR,

Table 1. Truth Table

CLR CSLSB CSMSB

WR

LDAC

FUNCTION

1

0

1

0

1

Loads least significant byte into the input register. DAC output remains unchanged.

Latches least significant byte into the input register. DAC output remains unchanged.

Loads most significant byte into the input register. DAC output remains unchanged.

0

Latches most significant byte into the input register. DAC output remains

unchanged.

1

X

0

X

1

0

Transfers data from the input register into the DAC register and updates the DAC

output.

1

Latches data from the input register into the DAC register. DAC output remains

unchanged.

Most significant input and DAC registers are transparent. DAC output updates

immediately with the most significant input data and least significant input register

data.

1

X

0

X

0

1

0

1

0

No operation.

Both most significant and least significant input registers and DAC register are

transparent. DAC output updates immediately with the most significant and least

significant input data.

1

0

1

0

1

0

Loads all 16 bits into the input register. DAC output remains unchanged.

Least significant input and DAC registers are transparent. DAC output updates

immediately with the least significant input data and most significant register data.

Transfers data held in the input register to the DAC register and updates the DAC

output.

1

0

1

X

1

X

0

1

X

No operation.

Sets the input and DAC registers and DAC output to midscale (if MID/ZERO = 1) or

zero-scale (if MID/ZERO = 0).

0 = Low state.

1 = High state.

X = Don’t care.

= Rising edge.

______________________________________________________________________________________ 11

16-Bit, Parallel-Input, Voltage-Output DACs

with Internal Reference

The MAX5650/MAX5651/MAX5652 provide an asyn-

chronous clear input (CLR). Asserting CLR resets the

where D is the decimal value of the DACs binary input

input and DAC registers and DAC output to midscale if

code. Table 3 shows digital codes and corresponding

the MID/ZERO input is high and to zero scale when

MID/ZERO is low.

output voltages for bipolar operation.

Table 2. Unipolar Code Table

Power-On Reset (POR)

The MAX5650/MAX5651/MAX5652 provide an internal

POR circuit. On power-up, the input and DAC registers

and DAC output are set to 0000 hex if MID/ZERO is low

or 8000 hex if MID/ZERO is high. Wait 10µs after

power-up before pulling CSMSB or CSLSB low.

DAC LATCH CONTENTꢀ

MꢀB LꢀB

ANALOG OUTPUT, V

OUT

1111 1111 1111 1111

V

x (65,535 / 65,536)

x (32,768 / 65,536)

REF

1000 0000 0000 0000

= 0.5V

REF

Internal Scaling Resistors

The MAX5650/MAX5651/MAX5652 include two internal

scaling resistors of 12.4kΩ (typ) each that are matched

to 0.05% or better. Use these resistors with a precision

external op amp to generate a bipolar output swing

(see the Bipolar Operation section). The free ends of

these resistors are accessible at INA and INB while the

midpoint is accessible at MTAP. Connect INB to the

output of the op amp and INA to REF for bipolar opera-

tion. Negative voltages are only allowed at INB (see the

Absolute Maximum Ratings section).

0000 0000 0000 0001

0000 0000 0000 0000

V

x (1 / 65,536)

REF

0V

Table 3. Bipolar Code Table

DAC LATCH CONTENTꢀ

ANALOG OUTPUT, V

OUT

MꢀB

LꢀB

1111 1111 1111 1111

1000 0000 0000 0001

1000 0000 0000 0000

0111 1111 1111 1111

+V

0V

x (32,767 / 32,768)

x (1 / 32,768)

REF

Applications Information

-V

(1 / 32,768)

REF

Unipolar Buffered/Unbuffered Operation

Unbuffered operation reduces power consumption as

well as the offset error contributed by the external out-

put buffer (see Figure 1). The R2R DAC output is avail-

able directly at OUT, allowing 16-bit performance from

-V

= -V

x (32,768 / 32,768)

REF

0000 0000 0000 0000

REF

Power-Supply and Layout Considerations

Careful PC board layout is important for optimal system

performance. Wire-wrapped boards, sockets, and

breadboards are not recommended. Keep analog and

digital signals separate to reduce noise injection and

digital feedthrough. Connect AGND and DGND to the

highest quality ground available. Star-connect all

ground return paths back to AGND or use a multilayer

board with a low-inductance ground plane. Connect

analog and digital ground planes together at a low-

impedance power-supply source. For the MAX5652,

keep the trace between the reference source to the ref-

erence input short and low impedance. Bypass each

supply with a 0.1µF capacitor as close as possible to

the IC for optimal 16-bit performance.

+V

to GND without degradation at zero scale.

REF

The typical application circuit (Figure 2) shows the

MAX5650/MAX5651/MAX5652 configured for a

buffered unipolar voltage-output operation. Use the

integrated precision matched resisters for op-amp

input impedance matching. Table 2 shows digital

codes and corresponding output voltages for unipolar

buffered or unbuffered operation.

Bipolar Operation

For bipolar voltage-output operation, use an external op

amp (such as the MAX400) in conjunction with the

internal scaling resistors (see Figure 3). Connect the

free end of the internal resistor (INB) to the output of the

external op amp and the free end of the other resistor

(INA) to REF. Connect the midpoint of the resistors to

the inverting input of the op amp. Connect the output of

the DAC to the noninverting input of the external op

amp. The resulting transfer function is as follows:

Chip Information

PROCESS: BiCMOS

V

= V

[(2D/65,536) −1]

OUT

REF

12 ______________________________________________________________________________________

16-Bit, Parallel-Input, Voltage-Output DACs

with Internal Reference

Pin Configuration

TOP VIEW

24 23 22 21 20 19 18 17

16

15

MTAP 25

INB 26

D15

D14

14 D13

27

28

29

30

31

32

AV

DD

D12

D11

13

12

AGND

INA

MAX5650

MAX5651

MAX5652

11 D10

REF

10

9

D9

D8

OUT

GND

+

1

2

3

4

5

6

7

8

TQFN

5mm x 5mm

______________________________________________________________________________________ 13

16-Bit, Parallel-Input, Voltage-Output DACs

with Internal Reference

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information

go to www.maxim-ic.com/packages.)

D2

D

b

0.10 M

C A B

C

L

D2/2

D/2

k

L

MARKING

AAAAA

E/2

E2/2

C

(NE-1) X

e

L

E2

E

PIN # 1 I.D.

0.35x45°

DETAIL A

e/2

PIN # 1

I.D.

e

(ND-1) X

e

DETAIL B

e

L

C

L

C

L

L1

L

e

0.10

C

A

0.08

C

A3

A1

PACKAGE OUTLINE,

16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm

1

-DRAWING NOT TO SCALE-

I

21-0140

2

COMMON DIMENSIONS

20L 5x5 28L 5x5

EXPOSED PAD VARIATIONS

D2 E2

MIN. NOM. MAX. MIN. NOM. MAX.

3.00 3.10 3.20 3.00 3.10 3.20

PKG.

SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.

16L 5x5

32L 5x5

40L 5x5

L

DOWN

BONDS

ALLOWED

YES

NO

exceptions

PKG.

CODES

±0.15

A

0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80

0.02 0.05 0.02 0.05 0.02 0.05 0.02 0.05 0.02 0.05

0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF.

T1655-2

T1655-3

**

A1

0

A3

b

T1655N-1 3.00 3.10 3.20 3.00 3.10 3.20

NO

0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25

4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10

T2055-3

T2055-4

T2055-5

T2855-3

3.00 3.10 3.20 3.00 3.10 3.20

YES

D

E

NO

**

YES

3.15 3.25 3.35 3.15 3.25 3.35 0.40

e

0.80 BSC.

0.25

0.65 BSC.

0.25

0.50 BSC.

0.25

0.50 BSC.

0.25

0.40 BSC.

3.15 3.25 3.35 3.15 3.25 3.35

YES

NO

**

k

-

0.25 0.35 0.45

T2855-4

T2855-5

2.60 2.70 2.80 2.60 2.70 2.80

3.15 3.25 3.35 3.15 3.25 3.35

L

0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60

L1

-

0.30 0.40 0.50

NO

YES

T2855-6

T2855-7

**

N

ND

NE

16

4

20

5

28

7

32

8

40

10

2.80

2.60 2.70

2.60 2.70 2.80

5

7

T2855-8

3.15 3.25 3.35 3.15 3.25 3.35 0.40

WHHB

WHHC

WHHD-1

WHHD-2

-----

JEDEC

T2855N-1 3.15 3.25 3.35 3.15 3.25 3.35

NO

YES

NO

YES

NO

**

3.20

3.00 3.10 3.20

T3255-3

T3255-4

T3255-5

3.00 3.10

3.00 3.10 3.20 3.00 3.10 3.20

3.20

NOTES:

3.00 3.10

3.00 3.10 3.20

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

3. N IS THE TOTAL NUMBER OF TERMINALS.

T3255N-1 3.00 3.10 3.20 3.00 3.10 3.20

T4055-1 3.20 3.30 3.40 3.20 3.30 3.40

YES

**^{SEE COMMON DIMENSIONS TABLE}

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL

CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE

OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1

IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN

0.25 mm AND 0.30 mm FROM TERMINAL TIP.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR

T2855-3 AND T2855-6.

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.

12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.

13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", ±0.05.

PACKAGE OUTLINE,

16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm

2

-DRAWING NOT TO SCALE-

21-0140

I

2

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

1± ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Printed USA

is a registered trademark of Maxim Integrated Products. Inc.


型号：	MAX5651ETJ
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	16-Bit, Parallel-Input Voltage-Output DACs with Internal Reference 16位并行输入，电压输出DAC，内置基准
文件：	总14页 (文件大小：280K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX5651ETJ [MAXIM]

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