MAX5734BUTN+T [MAXIM]
D/A Converter, 1 Func, Serial Input Loading, 20us Settling Time, 8 X 8 MM, 0.80 MM HEIGHT, MO-220WLLD-5, TQFN-56;
| 型号： | MAX5734BUTN+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Serial Input Loading, 20us Settling Time, 8 X 8 MM, 0.80 MM HEIGHT, MO-220WLLD-5, TQFN-56 WLL 信息通信管理 转换器 |
| 文件： | 总28页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3148; Rev 7; 11/05
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
General Description
Features
♦ Guaranteed Monotonic to 16 Bits
The MAX5732–MAX5735 are 32-channel, 16-bit, voltage-
output, digital-to-analog converters (DACs). All devices
accept a 3V external reference input. The devices
include an internal offset DAC that allows all the outputs
to be offset and a ground-sensing function, allowing out-
put voltages to be referenced to a remote ground.
♦ 32 Individual DACs in an 8mm x 8mm, 56-Pin,
Thin QFN Package or 64-Pin TQFP Package
♦ Four Output Voltage Ranges
0 to +5V (MAX5732)
0 to +10V (MAX5733)
-2.5V to +7.5V (MAX5734)
-5V to +5V (MAX5735)
A 33MHz SPI™-/QSPI™-/MICROWIRE™- and digital
signal processor (DSP)-compatible serial interface con-
trols the MAX5732–MAX5735. Each DAC has a double-
buffered input structure that helps minimize the digital
noise feedthrough from the digital inputs to the outputs,
and allows for synchronous or asynchronous updating
of the outputs. The MAX5732–MAX5735 also provide a
DOUT that allows for read-back or daisy chaining multi-
ple devices. The devices provide separate power
inputs for the analog and digital sections and provide
separate power inputs for the output buffer amplifiers.
The MAX5732–MAX5735 include proprietary deglitch
circuits to prevent output glitches at power-up and
eliminate the need for power sequencing. The devices
provide a software-shutdown mode to allow efficient
power management. The MAX5732–MAX5735 con-
sume 50µA of supply current in shutdown.
♦ Buffered Voltage Outputs Capable of Driving
10kΩ || 100pF
♦ Glitch-Free Power-Up
♦ SPI-/QSPI-/MICROWIRE-/DSP-Compatible 33MHz
Serial Interface
Ordering Information
OUTPUT
VOLTAGE
(V)
MAX
INL
(LSB)
PIN-
PKG
PART
PACKAGE CODE
56 Thin
MAX5732AUTN
0 to +5
0 to +5
8
T5688-3
QFN-EP*
56 Thin
MAX5732BUTN
16
T5688-3
QFN-EP*
The MAX5732–MAX5735 provide buffered outputs that
can drive 10kΩ in parallel with 100pF. The MAX5732 has
a 0 to +5V output range; the MAX5733 has a 0 to +10V
range; the MAX5734 has a -2.5V to +7.5V range; the
MAX5735 has a -5V to +5V range. The MAX5732–
MAX5735 are available in a 56-pin, 8mm x 8mm, thin
QFN package and 64-pin TQFP package and operate
over the 0°C to +85°C temperature range.
Note: All devices operate over the 0°C to +85°C temperature
range.
*EP = Exposed pad (internally connected to V ).
SS
Ordering Information continued at end of data sheet.
Pin Configurations
Applications
TOP VIEW
Automatic Test Systems
Optical Router Controls
Industrial Process Controls
Arbitrary Function Generators
Avionics Equipment
42 41 40 39 38 37 36 35 34 33 32 31 30 29
OUT20 43
V
28
27
26
25
SS
44
45
AV
OUT19
OUT18
DD
REF
OUT17 46
OUT16 47
REFGND
24 GS
AV
48
49
50
51
CC
23 CLR
Digital Offset/Gain Adjustment
REFGND
22
21
20
LDAC
DGND
AV
DD
MAX5732–MAX5735
DV
DD
OUT15
OUT14 52
19 DIN
OUT13
OUT12
OUT11
53
54
55
18
17
16
SCLK
DOUT
CS
EXPOSED PADDLE
SPI/QSPI are trademarks of Motorola, Inc.
15 DSP
OUT10 56
1
2
3
4
5
6
7
8
9
10 11 12 13 14
MICROWIRE is a trademark of National Semiconductor Corp.
Pin Configurations continued at end of data sheet.
8mm x 8mm THIN QFN-EP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
ABSOLUTE MAXIMUM RATINGS
AV
to V , AGND, DGND, REFGND..................-0.3V to +12V
Maximum Current into REF............................................... 10mA
Maximum Current into Any Pin ......................................... 50mA
CC
SS
V
to AGND, DGND................................................-6V to +0.3V
SS
AV , DV
to AGND, DGND, REFGND.................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
DD
DD
A
AGND to DGND.....................................................-0.3V to +0.3V
REF to AGND, DGND,
REFGND...............-0.3V to the lower of (AV + 0.3V) and +6V
DD
Thin QFN (derate 31.3mW/°C above +70°C)...................2.5W
TQFP (derate 25mW/°C above +70°C)............................2.0W
Operating Temperature Ranges
REFGND to AGND.................................................-0.3V to +0.3V
Digital Inputs to AGND, DGND,
MAX573__UCB ...................................................0°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
REFGND..............-0.3V to the lower of (DV
+ 0.3V) and +6V
DOUT to DGND.......-0.3V to the lower of (DV + 0.3V) and +6V
DD
DD
OUT_ to V .........-0.3V to the lower of (AV
+ 0.3V) and +12V
SS
CC
GS to AGND ................................................................-1V to +1V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX5732 (0 to +5V Output Voltage Range)
(AV
= +5.25V to +5.5V (Note 1), AV
= +5V 5ꢀ, DV
= +2.7V to AV , V = AGND = DGND = REFGND = GS = 0, V
=
CC
DD
DD
DD SS
REF
+3.0V, R = ∞, C = 50pF referenced to ground, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
L
L
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS
Resolution
N
16
Bits
MAX5732A
MAX5732B
4
8
8
16
1
Integral Nonlinearity (Note 2)
INL
LSB
Differential Nonlinearity
Zero-Scale Error
DNL
Guaranteed monotonic (Note 3)
LSB
mV
V
V
= -0.5V, AV
= +5.25V (Note 4)
8
8
40
50
0.5
OS
SS
CC
Full-Scale Error
(Note 4)
mV
Gain Error
0.1
ꢀFSR
ppm
FSR/°C
Gain Temperature Coefficient
20
50
DC Crosstalk
V
= -0.5V, AV
= +5V (Note 5)
250
µV
SS
CC
DYNAMIC CHARACTERISTICS
Output-Voltage Settling Time
Full-scale change to 0.5 LSB
20
1
µs
Voltage-Output Slew Rate
Digital Feedthrough
V/µs
nV-s
nV-s
nV-s
nV-s
(Note 6)
5
Digital Crosstalk
(Note 7)
5
Digital-to-Analog Glitch Impulse
DAC-to-DAC Crosstalk
Major carry transition
(Note 8)
120
15
Output Noise Spectral Density at
1kHz
Full-scale code
250
50
nV/√Hz
ANALOG OUTPUTS (OUT0 to OUT31)
Output Voltage Range
V
= -0.5V, AV
= +5.25V (Note 1)
CC
0
5
V
SS
Resistive Load to Ground
10
kΩ
2
_______________________________________________________________________________________
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
ELECTRICAL CHARACTERISTICS—MAX5732 (0 to +5V Output Voltage Range) (continued)
(AV
= +5.25V to +5.5V (Note 1), AV
= +5V 5ꢀ, DV
= +2.7V to AV , V = AGND = DGND = REFGND = GS = 0, V
=
CC
DD
DD
DD SS
REF
+3.0V, R = ∞, C = 50pF referenced to ground, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
L
L
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
50
MAX
UNITS
pF
Capacitive Load to Ground
DC Output Impedance
100
0.1
Ω
Sourcing, full-scale code, output connected
to AGND
5
Short-Circuit Current
mA
Sinking, zero-scale code, output connected
-5
to AV
CC
GROUND-SENSE ANALOG INPUT (GS)
Input Voltage Range
GS Gain
V
A
Relative to AGND
-0.5
0.995
35
+0.5
V
GS
GS
1.000
3.000
1.005
V/V
kΩ
Input Resistance
-0.5V ≤ V ≤ +0.5V, V = -0.5V
GS SS
REFERENCE INPUT (REF)
Input Resistance
1
MΩ
Reference Input Voltage Range
V
Referred to REFGND
2.900
3.100
V
REF
DIGITAL INPUTS (CS, SCLK, DIN, LDAC, CLR, DSP)
0.7 ×
DV
DV
= +2.7V to +3.6V
DD
DD
DV
Input-Voltage High
V
V
DD
IH
= +4.75V to +5.25V
2.4
Input-Voltage Low
Input Capacitance
Input Current
V
0.8
1
V
IL
IN
IN
C
10
pF
µA
I
Digital inputs = 0 or DV
DD
POWER REQUIREMENTS (AV , V , AGND, AV , DV , DGND)
CC SS
DD
DD
Output-Amplifier Positive Supply
Voltage
AV
(Note 1)
4.75
-0.5
5.50
0
V
V
V
CC
Output-Amplifier Negative Supply
Voltage
V
SS
Output-Amplifier Supply Voltage
Difference
AV
- V
5.75
CC
SS
Analog Supply Voltage
Digital Supply Voltage
AV
DV
4.75
2.70
5.25
5.25
15
V
V
DD
DD
V
through V
= 0
10
10
2.5
5
mA
µA
OUT0
OUT31
Analog Supply Current
Digital Supply Current
AI
DI
AI
DD
DD
CC
SS
Software shutdown
V
V
V
= DV , V = 0, f
= 20MHz
3.5
6.5
10
IH
DD IL
SCLK
mA
= +2.4V, V = +0.8V, f = 20MHz
SCLK
IH
IL
through V
= 0
4
mA
µA
mA
µA
dB
OUT0
OUT31
Output-Amplifier Positive Supply
Current
Software shutdown
20
-4
V
through V
= 0
-10
OUT0
OUT31
Output-Amplifier Negative Supply
Current
I
V
= -0.5V
SS
Software shutdown
-20
-95
Power-Supply Rejection Ratio
PSRR
_______________________________________________________________________________________
3
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
ELECTRICAL CHARACTERISTICS—MAX5733 (0 to +10V Output Voltage Range)
(AV
= +10.5V to +11V, AV
L
= 5V 5ꢀ, DV
= +2.7V to AV , V = AGND = DGND = REFGND = GS = 0, V = +3.0V,
CC
DD
DD
DD SS
REF
R = ∞, C = 50pF referenced to ground, T = T
L
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
MIN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS
Resolution
N
16
Bits
MAX5733A
MAX5733B
4
8
8
16
1
Integral Nonlinearity (Note 2)
INL
LSB
Differential Nonlinearity
Zero-Scale Error
DNL
Guaranteed monotonic (Note 3)
LSB
mV
V
V
= -0.5V, AV
= +10V (Note 4)
8
8
40
50
0.5
OS
SS
CC
Full-Scale Error
(Note 4)
mV
Gain Error
0.1
ꢀ FSR
ppm
FSR/°C
Gain Temperature Coefficient
20
50
DC Crosstalk
V
= -0.5V, AV
= +10V (Note 5)
250
µV
SS
CC
DYNAMIC CHARACTERISTICS
Output-Voltage Settling Time
Full-scale change to 0.5 LSB
20
1
µs
Voltage-Output Slew Rate
Digital Feedthrough
V/µs
nV-s
nV-s
nV-s
nV-s
(Note 6)
5
Digital Crosstalk
(Note 7)
5
Digital-to-Analog Glitch Impulse
DAC-to-DAC Crosstalk
Major carry transition
(Note 8)
120
15
Output Noise Spectral Density at
1kHz
Full-scale code
250
nV/√Hz
ANALOG OUTPUTS (OUT0 to OUT31)
Output Voltage Range
V
= -0.5V, AV
= +10.5V (Note 1)
CC
0
10
V
SS
Resistive Load to Ground
Capacitive Load to Ground
DC Output Impedance
10
50
50
kΩ
pF
Ω
100
0.1
Sourcing, full scale, output connected to
AGND
5
Short-Circuit Current
mA
Sinking, zero scale, output connected to
-5
AV
CC
GROUND-SENSE ANALOG INPUT (GS)
Input Voltage Range
GS Gain
V
A
Relative to AGND
-0.5
0.995
70
+0.5
V
GS
GS
1.000
3.000
1.005
V/V
kΩ
Input Resistance
-0.5V ≤ V ≤ +0.5V, V = -0.5V
GS SS
REFERENCE INPUT (REF)
Input Resistance
1
MΩ
Reference Input Voltage Range
V
Referred to REFGND
2.900
3.100
V
REF
4
_______________________________________________________________________________________
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
ELECTRICAL CHARACTERISTICS—MAX5733 (0 to +10V Output Voltage Range) (continued)
(AV
= +10.5V to +11V, AV
L
= 5V 5ꢀ, DV
= +2.7V to AV , V = AGND = DGND = REFGND = GS = 0, V = +3.0V,
REF
SS
CC
DD
DD
DD
R = ∞, C = 50pF referenced to ground, T = T
L
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
MIN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (CS, SCLK, DIN, LDAC, CLR, DSP)
0.7 ×
DV
DV
= +2.7V to +3.6V
DD
DD
DV
Input-Voltage High
V
V
DD
IH
= +4.75V to +5.25V
2.4
Input-Voltage Low
Input Capacitance
Input Current
V
0.8
1
V
IL
IN
IN
C
10
pF
µA
I
Digital inputs = 0 or DV
DD
POWER REQUIREMENTS (AV , V , AGND, AV , DV , DGND)
CC SS
DD
DD
Output-Amplifier Positive Supply
Voltage
AV
(Note 1)
10
11
0
V
V
V
CC
Output-Amplifier Negative Supply
Voltage
V
-0.5
SS
Output-Amplifier Supply Voltage
Difference
AV
- V
11
CC
SS
Analog Supply Voltage
Digital Supply Voltage
AV
DV
4.75
2.70
5.25
5.25
15
V
V
DD
DD
V
through V
= 0
10
10
2.5
5
mA
µA
OUT0
OUT31
Analog Supply Current
Digital Supply Current
AI
DI
AI
DD
DD
CC
SS
Software shutdown
V
V
V
= DV , V = 0, f
= 20MHz
3.5
6.5
10
IH
DD IL
SCLK
mA
= +2.4V, V = +0.8V, f = 20MHz
SCLK
IH
IL
through V
= 0
4
mA
µA
mA
µA
dB
OUT0
OUT31
Output-Amplifier Positive Supply
Current
Software shutdown
20
-4
V
through V
= 0
-10
OUT0
OUT31
Output-Amplifier Negative Supply
Current
I
V
= -0.5V
SS
Software shutdown
-20
-95
Power-Supply Rejection Ratio
PSRR
_______________________________________________________________________________________
5
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
ELECTRICAL CHARACTERISTICS—MAX5734 (-2.5V to +7.5V Output Voltage Range)
(AV
= +7.75V to +8.25V, AV
= +5V 5ꢀ, DV
= +2.7V to AV , V = -2.75V to -3.25V, AGND = DGND = REFGND = GS = 0,
CC
DD
DD DD SS
program the offset DAC to 4000hex. V
noted. Typical values are at T = +25°C.)
= +3.0V, R = ∞, C = 50pF referenced to ground, T = T
to T
, unless otherwise
MAX
REF
L
L
A
MIN
A
PARAMETER
DC CHARACTERISTICS
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
N
16
Bits
MAX5734A
MAX5734B
4
8
8
16
1
Integral Nonlinearity (Note 2)
INL
LSB
Differential Nonlinearity
Zero-Scale Error
DNL
Guaranteed monotonic (Note 3)
LSB
mV
V
V
= -3.25V, AV
= +7.75V (Note 4)
8
8
40
50
0.5
OS
SS
CC
Full-Scale Error
(Note 4)
mV
Gain Error
0.1
ꢀFSR
ppm
FSR/°C
Gain Temperature Coefficient
20
50
DC Crosstalk
V
= -3.25V, AV
= +7.75V (Note 4)
250
µV
SS
CC
DYNAMIC CHARACTERISTICS
Output-Voltage Settling Time
Full-scale change to 0.5 LSB
20
1
µs
Voltage-Output Slew Rate
Digital Feedthrough
V/µs
nV-s
nV-s
nV-s
nV-s
(Note 6)
5
Digital Crosstalk
(Note 7)
5
Digital-to-Analog Glitch Impulse
DAC-to-DAC Crosstalk
Major carry transition
(Note 8)
120
15
Output Noise Spectral Density at
1kHz
Full-scale code
250
nV/√Hz
ANALOG OUTPUTS (OUT0 to OUT31)
Output Voltage Range
V
= -2.75V, AV
= +7.75V (Note 1)
-2.5
10
+7.5
100
V
SS
CC
Resistive Load to Ground
Capacitive Load to Ground
DC Output Impedance
50
50
kΩ
pF
Ω
0.1
Sourcing, full scale, output connected to
AGND
5
Short-Circuit Current
mA
Sinking, zero scale, output connected to
-5
AV
CC
GROUND-SENSE ANALOG INPUT (GS)
Input Voltage Range
GS Gain
V
A
Relative to AGND
-0.5
0.995
70
+0.5
V
GS
GS
1.000
3.000
1.005
V/V
kΩ
Input Resistance
-0.5V ≤ V ≤ +0.5V, V = -0.5V
GS SS
REFERENCE INPUT (REF)
Input Resistance
1
MΩ
Reference Input Voltage Range
V
Referred to REFGND
2.900
3.100
V
REF
6
_______________________________________________________________________________________
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
ELECTRICAL CHARACTERISTICS—MAX5734 (-2.5V to +7.5V Output Voltage Range)
(continued)
(AV
= +7.75V to +8.25V, AV
= +5V 5ꢀ, DV
= +2.7V to AV , V = -2.75V to -3.25V, AGND = DGND = REFGND = GS = 0,
CC
DD
DD DD SS
program the offset DAC to 4000hex. V
noted. Typical values are at T = +25°C.)
= +3.0V, R = ∞, C = 50pF referenced to ground, T = T
to T
, unless otherwise
MAX
REF
L
L
A
MIN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (CS, SCLK, DIN, LDAC, CLR, DSP)
0.7 ×
DV
DV
= +2.7V to +3.6V
DD
DD
DV
Input-Voltage High
V
V
DD
IH
= +4.75V to +5.25V
2.4
Input-Voltage Low
Input Capacitance
Input Current
V
0.8
1
V
IL
IN
IN
C
10
pF
µA
I
Digital inputs = 0 or DV
DD
POWER REQUIREMENTS (AV , V , AGND, AV , DV , DGND)
CC SS
DD
DD
Output-Amplifier Positive Supply
Voltage
AV
(Note 1)
7.50
8.25
-2.50
11
V
V
V
CC
Output-Amplifier Negative Supply
Voltage
V
-3.25
SS
Output-Amplifier Supply Voltage
Difference
AV
- V
SS
CC
Analog Supply Voltage
Digital Supply Voltage
AV
DV
4.75
2.70
5.25
5.25
15
V
V
DD
DD
V
through V
= 0
10
10
2.5
5
mA
µA
OUT0
OUT31
Analog Supply Current
Digital Supply Current
AI
DI
AI
DD
DD
CC
SS
Software shutdown
V
V
V
= DV , V = 0, f
= 20MHz
3.5
6.5
10
IH
DD IL
SCLK
mA
= +2.4V, V = +0.8V, f = 20MHz
SCLK
IH
IL
through V
= 0
4
mA
µA
mA
µA
dB
OUT0
OUT31
Output-Amplifier Positive Supply
Current
Software shutdown
20
-4
V
through V
= 0
-10
OUT0
OUT31
Output-Amplifier Negative Supply
Current
I
V
= -2.75V
SS
Software shutdown
-20
-95
Power-Supply Rejection Ratio
PSRR
_______________________________________________________________________________________
7
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
ELECTRICAL CHARACTERISTICS—MAX5735 (-5V to +5V Output Voltage Range)
(AV
= +5.25V to +5.5V, AV
= +5V 5ꢀ, DV
= +2.7V to AV , V = -5.25V to -5.5V, AGND = DGND = REFGND = GS = 0,
SS
DD DD
CC
DD
program the offset DAC to 8000hex. V
noted. Typical values are at T = +25°C.)
= +3.0V, R = ∞, C = 50pF referenced to ground, T = T
to T
, unless otherwise
REF
L
L
A
MIN
MAX
A
PARAMETER
DC CHARACTERISTICS
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
N
16
Bits
MAX5735A
MAX5735B
4
8
8
16
1
Integral Nonlinearity (Note 2)
INL
LSB
Differential Nonlinearity
Zero-Scale Error
Full-Scale Error
Gain Error
DNL
Guaranteed monotonic (Note 3)
LSB
mV
V
V
= -5.25V, AV
= +5.25V (Note 4)
8
8
40
50
0.5
OS
SS
CC
(Note 4)
mV
0.1
ꢀFSR
ppm
FSR/°C
Gain Temperature Coefficient
20
DC Crosstalk
V
= -5.75V, AV
= +5.25V (Note 5)
50
250
µV
SS
CC
DYNAMIC CHARACTERISTICS
Output-Voltage Settling Time
Voltage-Output Slew Rate
Digital Feedthrough
Full-scale change to 0.5 LSB
20
1
µs
V/µs
nV-s
nV-s
nV-s
nV-s
(Note 6)
5
Digital Crosstalk
(Note 7)
5
Digital-to-Analog Glitch Impulse
DAC-to-DAC Crosstalk
Major carry transition
(Note 8)
120
15
Output Noise Spectral Density at
1kHz
Full-scale code
250
nV/√Hz
ANALOG OUTPUTS (OUT0 through OUT31)
Output Voltage Range
V
= -5.25V, AV
= +5.25V (Note 1)
-5
+5
V
SS
CC
Resistive Load to Ground
10
50
50
kΩ
pF
Ω
Capacitive Load to Ground
DC Output Impedance
100
0.1
Sourcing, full scale, output connected to
AGND
5
Short-Circuit Current
mA
Sinking, zero scale, output connected to
-5
AV
CC
GROUND-SENSE ANALOG INPUT (GS)
Input Voltage Range
GS Gain
V
Relative to AGND
-0.5
0.995
70
+0.5
V
GS
GS
A
1.000
3.000
1.005
V/V
kΩ
Input Resistance
-0.5V ≤ V ≤ +0.5V, V = -0.5V
GS SS
REFERENCE INPUT (REF)
Input Resistance
1
MΩ
Reference Input Voltage Range
V
Referred to REFGND
2.900
3.100
V
REF
8
_______________________________________________________________________________________
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
ELECTRICAL CHARACTERISTICS—MAX5735 (-5V to +5V Output Voltage Range) (continued)
(AV
= +5.25V to +5.5V, AV
= +5V 5ꢀ, DV
= +2.7V to AV , V = -5.25V to -5.5V, AGND = DGND = REFGND = GS = 0,
SS
DD DD
CC
DD
program the offset DAC to 8000hex. V
noted. Typical values are at T = +25°C.)
= +3.0V, R = ∞, C = 50pF referenced to ground, T = T
to T
, unless otherwise
REF
L
L
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (CS, SCLK, DIN, LDAC, CLR, DSP)
0.7 ×
DV
DV
= +2.7V to +3.6V
= +4.75V to 5.25V
DD
DD
DV
Input-Voltage High
V
V
DD
IH
2.4
Input-Voltage Low
Input Capacitance
Input Current
V
0.8
1
V
IL
IN
IN
C
10
pF
µA
I
Digital inputs = 0 or DV
DD
POWER REQUIREMENTS (AV , V , AGND, AV , DV , DGND)
CC SS
DD
DD
Output-Amplifier Positive Supply
Voltage
AV
(Note 1)
4.75
5.50
-4.75
11
V
V
V
CC
Output-Amplifier Negative Supply
Voltage
V
-5.50
SS
Output-Amplifier Supply Voltage
Difference
AV
- V
SS
CC
Analog Supply Voltage
Digital Supply Voltage
AV
DV
4.75
2.70
5.25
5.25
15
V
V
DD
DD
V
through V
= 0
10
10
2.5
5
mA
µA
OUT0
OUT31
Analog Supply Current
Digital Supply Current
AI
DI
AI
DD
DD
CC
SS
Software shutdown
V
V
V
= DV , V = 0, f
= 20MHz
3.5
6.5
10
IH
DD IL
SCLK
mA
= +2.4V, V = +0.8V, f = 20MHz
SCLK
IH
IL
through V
= 0
4
mA
µA
mA
µA
dB
OUT0
OUT31
Output-Amplifier Positive Supply
Current
Software shutdown
20
-4
V
through V
= 0
-10
OUT0
OUT31
Output-Amplifier Negative Supply
Current
I
V
= -0.5V
SS
Software shutdown
-20
-95
Power-Supply Rejection Ratio
PSRR
Note 1: AV
should be at least 0.25V higher than the maximum output voltage required from the DAC. Full-scale output is 5V for
CC
the MAX5732.
Note 2: Linearity guaranteed from code 2047 to full scale and from (V + 0.3V) to (AV
- 0.3V).
CC
SS
Note 3: DNL guaranteed over all codes for (V + 0.3V) to (AV
- 0.3V).
SS
CC
Note 4: Zero-scale error is measured at code 0. Full-scale error is measured at code FFFFhex.
Note 5: DC crosstalk is the change in the output level of one DAC at zero or full scale in response to the full-scale output change of all
other DACs.
Note 6: Digital feedthrough is a measure of the impulse injected into the analog outputs from the digital control inputs when the
device is not being written to. It is measured with a worst-case change on the digital inputs.
Note 7: Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale while a full-scale code change is written
into another DAC.
Note 8: DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one converter due to both the digital change and
subsequent analog output change at another converter.
_______________________________________________________________________________________
9
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
TIMING CHARACTERISTICS—DV
= +4.75V to +5.25V
DD
DD
(Figures 2 and 3, AV
= +4.75V to +5.25V, DV
= +4.75V to +5.25V, AGND = DGND = REFGND = GS = 0, T = T
to T
,
MAX
DD
A
MIN
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
Serial Clock Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Fall to CS Fall Setup Time
CS Fall to SCLK Fall Setup Time
CS Rise to SCLK Fall
SYMBOL
CONDITIONS
MIN
0
TYP
MAX
UNITS
MHz
ns
f
33
SCLK
t
10
10
6
CH
t
ns
CL
t
ns
SCS
CSS
t
5
ns
t
t
At end of cycle in SPI mode only
15
0
ns
CS1
CS2
SCLK Fall to CS Rise Setup Time
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
SCLK Fall to DOUT Fall
SCLK Fall to DOUT Rise
CS Pulse-Width High
ns
t
10
2
ns
DS
DH
t
ns
t
Load capacitance = 20pF
Load capacitance = 20pF
20
20
ns
SCL
SDH
t
ns
t
50
20
20
20
ns
CSPWH
CS Pulse-Width Low
t
ns
CSPWL
LDAC Pulse-Width Low
CLR Pulse-Width Low
t
ns
LDAC
t
ns
CLR
TIMING CHARACTERISTICS—DV
= +2.7V to +5.25V
DD
DD
(Figures 2 and 3, AV
= +4.75V to +5.25V, DV
= +2.7V to +5.25V, AGND = DGND = REFGND = GS = 0, T = T
to T
,
MAX
DD
A
MIN
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
Serial Clock Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Fall to CS Fall Setup Time
CS Fall to SCLK Fall Setup Time
CS Rise to SCLK Fall
SYMBOL
CONDITIONS
MIN
0
TYP
MAX
UNITS
MHz
ns
f
25
SCLK
t
10
10
10
10
18
0
CH
t
ns
CL
t
ns
SCS
CSS
t
ns
t
t
At end of cycle in SPI mode only
ns
CS1
CS2
SCLK Fall to CS Rise Setup Time
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
SCLK Fall to DOUT Fall
SCLK Fall to DOUT Rise
CS Pulse-Width High
ns
t
10
2
ns
DS
DH
t
ns
t
Load capacitance = 20pF (Note 9)
Load capacitance = 20pF (Note 9)
35
35
ns
SCL
SDH
t
ns
t
50
20
20
20
ns
CSPWH
CS Pulse-Width Low
t
ns
CSPWL
LDAC Pulse-Width Low
CLR Pulse-Width Low
t
ns
LDAC
t
ns
CLR
Note 9: The maximum clock frequency (f
) is 10MHz in daisy-chain mode when DV
< 4.75V.
SCLK
DD
10 ______________________________________________________________________________________
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
Typical Operating Characteristics
(AV
= +10.5V 5ꢀ, AV
= +5V 5ꢀ, DV
= +5V, V = AGND = DGND = REFGND = GS = 0, V
= +3.000V, R = ∞, C =
CC
DD
DD
SS
REF
L
L
50pF referenced to ground, output gain = 2.5, T = T
A
to T
, unless otherwise noted. Typical values are at T = +25°C).
MAX A
MIN
INTEGRAL NONLINEARITY
vs. INPUT CODE
DIFFERENTIAL NONLINEARITY
vs. INPUT CODE
WORST-CASE INL vs. TEMPERATURE
3.0
2.5
5
4
0.4
0.3
0.2
0.1
0
3
2.0
1.5
1.0
0.5
0
2
1
0
-0.1
-0.2
-1
-40
-40
-40
-15
10
35
60
85
85
85
0
10k 20k 30k 40k 50k 60k 70k
INPUT CODE
0
10k 20k 30k 40k 50k 60k 70k
INPUT CODE
TEMPERATURE (°C)
ZERO-SCALE ERROR
vs. TEMPERATURE
FULL-SCALE ERROR
vs. TEMPERATURE
WORST-CASE DNL vs. TEMPERATURE
0.25
0.20
6
5
4
3
2
1
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.15
0.10
0.05
0
V
= -0.5V
SS
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-15
10
35
60
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
9.0
8.9
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8.0
60
59
58
57
56
55
54
53
52
51
50
111
110
109
108
107
106
105
104
103
102
101
ALL DIGITAL INPUTS
ALL DIGITAL INPUTS
AT ZERO OR DV
DV = +3V
DD
DV = +5V
DD
AT ZERO OR DV
DD
DD
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-15
10
35
60
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
______________________________________________________________________________________ 11
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
Typical Operating Characteristics (continued)
(AV
= +10.5V 5ꢀ, AV
= +5V 5ꢀ, DV
= +5V, V = AGND = DGND = REFGND = GS = 0, V
= +3.000V, R = ∞, C =
REF L L
CC
DD
DD
SS
50pF referenced to ground, output gain = 2.5, T = T
A
to T
, unless otherwise noted. Typical values are at T = +25°C).
MAX A
MIN
LARGE-SIGNAL STEP RESPONSE
(LOW TO HIGH)
LARGE-SIGNAL STEP RESPONSE
(HIGH TO LOW)
DIGITAL FEEDTHROUGH
MAX5732 toc10
MAX5732 toc11
MAX5732 toc12
CS
5V/div
CS
5V/div
SCLK
5V/div
OUT_
5V/div
OUT_
5V/div
OUT_
10mV/div
400ns/div
2µs/div
2µs/div
MAJOR CARRY TRANSITION
(8000hex TO 7FFFhex)
MAJOR CARRY TRANSITION
(7FFFhex TO 8000hex)
NOISE VOLTAGE DENSITY
MAX5732 toc13
MAX5732 toc15
MAX5732 toc14
1000
CS
CS
5V/div
5V/div
100
10
1
OUT_
20mV/div
OUT_
20mV/div
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
FREQUENCY (MHz)
1µs/div
1µs/div
12 ______________________________________________________________________________________
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
Pin Description
PIN
NAME
AV
FUNCTION
Output Amplifier Positive Supply Input. Bypass to V with a 0.1µF capacitor.
TQFN
TQFP
1, 42, 48
1, 48, 55
CC
SS
2
3
4
2
3
4
OUT9 DAC9 Buffered Analog Output Voltage
OUT8 DAC8 Buffered Analog Output Voltage
OUT7 DAC7 Buffered Analog Output Voltage
5, 15–18, 33,
34, 49, 64
5
N.C.
No Connection. Internally connected. Do not make any connections to N.C.
6
6
OUT6 DAC6 Buffered Analog Output Voltage
OUT5 DAC5 Buffered Analog Output Voltage
OUT4 DAC4 Buffered Analog Output Voltage
AGND Analog Ground
7
7
8
9, 38
10
8
9, 44
10
OUT3 DAC3 Buffered Analog Output Voltage
11, 28, 39
12
11, 32, 45
12
V
Output-Amplifier Negative-Supply Input
SS
OUT2 DAC2 Buffered Analog Output Voltage
OUT1 DAC1 Buffered Analog Output Voltage
OUT0 DAC0 Buffered Analog Output Voltage
13
13
14
14
Digital Serial-Interface Select Input. Drive low for DSP-interface mode. Drive high for SPI-
interface mode.
15
19
DSP
16
20
CS
Active-Low Digital Chip-Select Input
17
18
19
20
21
21
22
23
24
25
DOUT Digital Serial Data Output. Use DOUT to daisy-chain and read the contents of the DAC registers.
SCLK Digital Serial Clock Input Clock
DIN
DV
Digital Serial Data Input
Digital Power Supply Input. Bypass to DGND with a 0.1µF capacitor.
DD
DGND Digital Ground
Active-Low Digital-Load DAC Input. Drive this asynchronous input low to transfer the contents of
the input register to their respective DAC registers and set all DAC outputs accordingly.
22
23
24
26
27
28
LDAC
CLR
GS
Active-Low Digital-Clear Input. Drive this asynchronous input low to clear the contents of the
input and DAC registers and set all the DAC outputs to zero.
Ground-Sense Analog Input. Offsets the DAC amplifier outputs by 0.5V to compensate for
a remote system ground potential difference.
REFGN
REF
25, 49
26
29, 56
30
Reference Ground
Analog Reference Voltage Input
27, 50
29
31, 57
35
AV
Analog Power Supply Input. Bypass to AGND with a 0.1µF capacitor.
DD
OUT31 DAC31 Buffered Analog Output Voltage
OUT30 DAC30 Buffered Analog Output Voltage
OUT29 DAC29 Buffered Analog Output Voltage
OUT28 DAC28 Buffered Analog Output Voltage
OUT27 DAC27 Buffered Analog Output Voltage
OUT26 DAC26 Buffered Analog Output Voltage
OUT25 DAC25 Buffered Analog Output Voltage
30
36
31
37
32
38
33
39
34
40
35
41
______________________________________________________________________________________ 13
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
Pin Description (continued)
PIN
NAME
FUNCTION
TQFN
36
37
40
41
43
44
45
46
47
51
52
53
54
55
56
TQFP
42
43
46
47
50
51
52
53
54
58
59
60
61
62
63
OUT24 DAC24 Buffered Analog Output Voltage
OUT23 DAC23 Buffered Analog Output Voltage
OUT22 DAC22 Buffered Analog Output Voltage
OUT21 DAC21 Buffered Analog Output Voltage
OUT20 DAC20 Buffered Analog Output Voltage
OUT19 DAC19 Buffered Analog Output Voltage
OUT18 DAC18 Buffered Analog Output Voltage
OUT17 DAC17 Buffered Analog Output Voltage
OUT16 DAC16 Buffered Analog Output Voltage
OUT15 DAC15 Buffered Analog Output Voltage
OUT14 DAC14 Buffered Analog Output Voltage
OUT13 DAC13 Buffered Analog Output Voltage
OUT12 DAC12 Buffered Analog Output Voltage
OUT11 DAC11 Buffered Analog Output Voltage
OUT10 DAC10 Buffered Analog Output Voltage
Exposed Paddle. Internally connected to V . Connect externally to a metal pad for thermal
SS
dissipation.
EP
—
EP
14 ______________________________________________________________________________________
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
AV
CC
INPUT
REGISTER
DAC0
REGISTER
DAC0
OUT0
OUT1
OUT_
V
SS
AV
CC
INPUT
REGISTER
DAC1
REGISTER
DAC1
V
SS
AV
CC
INPUT
REGISTER
DAC_
REGISTER
DAC_
V
SS
AV
CC
INPUT
REGISTER
DAC30
REGISTER
DAC30
OUT30
V
SS
AV
CC
INPUT
REGISTER
DAC31
REGISTER
DAC31
OUT31
V
SS
AV
CC
OFFSET
DAC
REGISTER
INPUT
REGISTER
OFFSET DAC
V
SS
AGND
AV
DD
POWER
MANAGEMENT
DV
DD
MAX5732–MAX5735
DIGITAL CONTROL LOGIC
DGND
REFGND
Figure 1. Functional Diagram
______________________________________________________________________________________ 15
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
range; the MAX5734 has a -2.5V to +7.5V output range;
Detailed Description
and the MAX5735 has a -5V to +5V output range.
The MAX5732–MAX5735 are 32-channel, 16-bit, volt-
age-output DACs (Figure 1). The devices accept a 3V
external reference input at REF. An internal offset DAC
allows all outputs to be offset (see Table 1). The devices
provide a ground-sensing function that allows the output
voltages to be referenced to a remote ground.
External Reference Input (REF)
The REF voltage sets the full-scale output voltage for all
32 DACs. REF accepts a +3V 3ꢀ input. Reference
voltages outside these limits can result in a degradation
of device performance.
A 33MHz SPI-/QSPI/-MICROWIRE- and DSP-compatible
serial interface controls the MAX5732–MAX5735 (Figure 2).
Each DAC includes a double-buffered input structure to
minimize the digital noise feedthrough from the digital
inputs to the outputs, and allows for synchronous or
asynchronous updating of the outputs. The two buffers
are organized as an input register followed by a DAC
register that stores the contents of the output. Input reg-
isters update the DAC registers independently or simul-
taneously with a single software or hardware command.
The MAX5732–MAX5735 also have a DOUT that allows
for read-back or daisy chaining multiple devices.
REF is a buffered input. The typical input impedance is
10MΩ, and it does not vary with code. Use a high-
accuracy, low-noise voltage reference such as the
MAX6126AASA30 (3ppm/°C temp drift and 0.02ꢀ initial
accuracy) to improve static accuracy. REF does not
accept AC signals.
Ground Sense (GS)
The MAX5732–MAX5735 include a GS that allows the
output voltages to be referenced to a remote ground.
The GS input voltage range (V ) is -0.5V to +0.5V.
GS
V
GS
is added to the output voltage with unity gain. The
resulting output voltage must be within the valid output-
voltage range set by the power supplies. See the
Output Amplifiers (OUT0–OUT31) section for the effect
of the GS inputs on the DAC outputs.
The MAX5732–MAX5735 analog and digital sections
have separate power inputs. Separate power inputs are
also provided for the output buffer amplifiers.
Proprietary deglitch circuits prevent output glitches at
power-up and eliminate the need for power sequenc-
ing. A software-shutdown mode allows efficient power
management. The MAX5732–MAX5735 consume 50µA
of supply current in shutdown.
Offset DAC
The MAX5732–MAX5735 feature an offset DAC that
determines the output voltage range. While each part
number has an output voltage range associated with it,
it is the offset DAC that determines the end-point volt-
ages of the range. Table 1 shows the offset DAC code
required during power-up.
All DACs provide buffered outputs that can drive 10kΩ
in parallel with 100pF. The MAX5732 has a 0 to +5V
output range; the MAX5733 has a 0 to +10V output
t
t
CL
CH
3
X
X
1
2
32
X
SCLK
DIN
t
DH
C2
C1
C0
D0
t
t
SCS
CS1
t
DS
t
CS2
t
CSS
CS
(µC MODE)
t
CSPWH
t
CSPWL
CS
(DSP MODE)
Figure 2. Serial-interface Timing
16 ______________________________________________________________________________________
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
Table 1. Offset DAC Codes
PART NUMBER D15 D14 D13 D12 D11 D10
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
MAX5732
MAX5733
MAX5734
MAX5735
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Note: For the MAX5732, the maximum code for the offset DAC is 16384. For the MAX5733/MAX5734/MAX5735, the maximum code
for the offset DAC is 40000.
Note: The offset DAC of every device can be pro-
grammed with any of the four output voltage ranges.
Table 2. Serial Data Format
However, the specifications in the Electrical
Characteristics table are only guaranteed (production
tested) for the offset code associated with each partic-
ular part number. For example, the MAX5734 specifica-
tions are only valid with the MAX5734 offset- DAC code
shown in Table 1.
DON’T-
CARE
BITS
CONTROL ADDRESS
DATA BITS
BITS
BITS
C2, C1,
AND C0
A5–A0
—
D15–D0
011
100000
XXXXXXX
See table 1
The offset DAC is summed with GS (Figure 1). The offset
DAC can also cancel the offset of the output buffers.
Any change in the offset DAC affects all 32 DACs.
The input code, the voltage reference, the offset DAC
output, the voltage on GS, and the gain of the output
amplifier determine the output voltage. Calculate V
as follows:
The offset DAC is also configured identically to the
other 32 DACs with an input and DAC register. Write to
the offset DAC through the serial interface by using
control bits C2, C1, and C0 = 001 followed by the data
bits D15–D0. The CLR command affects the offset DAC
as well as the other DACs.
OUT
GAIN × V
REF
×
DAC code − offset DAC code
(
)
V
=
+ V
GS
OUT
16
2
where GAIN = 5/3 for the MAX5732, or GAIN = 10/3 for
the MAX5733/MAX5734/MAX5735.
The data format for the offset DAC codes are: control bits
C2, C1, and C0 = 011, address bits A5–A0 = 100000, 7
don’t-care bits, and 16 data bits as shown in Table 2.
Load-DAC (LDAC) Input
The MAX5732–MAX5735 feature an active-low LDAC
logic input that allows the outputs OUT_ to update
asynchronously. Keep LDAC high during normal opera-
tion (when the device is controlled only through the ser-
ial interface). Drive LDAC low to simultaneously update
all DAC outputs with data from their respective input
registers. Figure 3 shows the LDAC timing with respect
to OUT_.
Output Amplifiers (OUT0–OUT31)
All DAC outputs are internally buffered. The internal
buffers provide gain, improved load regulation, and tran-
sition glitch suppression for the DAC outputs. The output
buffers slew at 1V/µs and can drive 10kΩ in parallel with
100pF. The output buffers are powered by AV
and
CC
V
. AV
and V
determine the maximum output
SS
CC
SS
voltage range of the device.
A software command can also activate the LDAC oper-
ation. To activate LDAC by software, set control bits
t
LDAC
LDAC
0.5 LSB
t
S
OUT_
Figure 3. LDAC Timing
______________________________________________________________________________________ 17
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
C2, C1, and C0 = 010, address bits A5–A0 = 111111,
and all data bits to don’t care. See Table 3 for the data
format. This operation updates all DAC outputs.
Serial Interface
A 3-wire SPI-/QSPI-/MICROWIRE- and DSP-compatible
serial interface controls the MAX5732–MAX5735. The
interface requires a 32-bit command word to control the
device. The command word consists of 3 control bits, 6
address bits, 7 don’t-care bits, and 16 data bits. Table 5
shows the general serial-data format. The control bits
control various write and read commands as well as the
load DAC and clear commands. Table 6 shows the con-
trol-bit functions. The address bits select the register(s)
to be written. Table 7 shows the address functions. The
data bits control the value of the DAC outputs.
Note: The software load DAC does not affect the offset DAC.
Clear (CLR)
The MAX5732–MAX5735 feature an active-low CLR
logic input that sets all channels including the offset
DAC to 0V (code 0000hex). The offset DAC needs to be
reprogrammed after CLR is asserted. Driving CLR low
clears the contents of both the input and DAC registers.
The serial interface can also issue a software clear com-
mand. Setting the control bits C2, C1, and C0 = 111
(Table 4) performs the same function as driving logic-
input CLR low. Table 4 shows the clear-data format for
the software-controlled clear command. This register-
reset process cannot be interrupted. All serial input data
is ignored until the entire reset process is complete.
Table 6. Control-Bit Functions
CONTROL
BITS
CONTROL-BIT DESCRIPTION
C2 C1 C0
No operation (NOP); no internal registers
change state. The NOP command can be
passed to DOUT depending on the state of the
configuration register. Address bits A5–A0 and
data bits D15–D0 are ignored.
Table 3. Load-DAC Data Format
0
0
0
0
0
1
0
1
0
DON’T-
CARE
BITS
CONTROL ADDRESS
DATA BITS
BITS
BITS
Loads D15–D0 into the input register(s) for the
selected address. Depending on the address
bits, this command could write to:
The configuration register (A[5:0] = 100001)
One of the input registers of the 32 DAC channels
All 32 DAC input registers (A[5:0] = 111111)
The offset DAC input register (A[5:0] = 100000)
C2, C1,
AND C0
A5–A0
—
D15–D0
010
111111
XXXXXXX XXXXXXXXXXXXXXXX
Table 4. Clear-Data Format
Loads DAC register(s) from the input register(s).
Depending on the address bits, this command
can update one or all of the DAC registers from
the stored input register value(s). Data bits
D15–D0 are ignored.
DON’T-
CONTROL ADDRESS
CARE
DATA BITS
D15–D0
BITS
BITS
BITS
C2, C1,
AND C0
A5–A0
—
Write-through; loads D15–D0 into the input and
DAC registers, depending on the address bits.
0
1
1
0
1
0
111
See table 7 XXXXXXX XXXXXXXXXXXXXXXX
Read command; depending on the address bits,
one of the DAC-register values or the
configuration-register value may be read back
through DOUT. Data bits D15–D0 are ignored.
Table 5. Serial-Data Format
DON’T-
CONTROL ADDRESS
CARE
DATA BITS
1
1
0
1
1
0
Reserved for internal testing; do not use.
Reserved for internal testing; do not use.
BITS
BITS
BITS
MSB
LSB
Clear register(s); depending on the address bits,
one or all registers (except the offset-DAC registers)
are cleared to zero. Data bits D15–D0 are ignored.
C2, C1,
and C0
1
1
1
A5–A0
XXXXXXX
D15–D0
18 ______________________________________________________________________________________
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
Table 7. Address-Bit Functions
ADDRESS BITS
ADDRESS BITS
CONTROL FUNCTION
CONTROL FUNCTION
A5 A4 A3 A2 A1 A0
A5 A4 A3 A2 A1 A0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
Command reserved; do not use.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
DAC0
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
DAC7
DAC8
DAC9
DAC10
DAC11
DAC12
DAC13
DAC14
DAC15
DAC16
DAC17
DAC18
DAC19
DAC20
DAC21
DAC22
DAC23
DAC24
DAC25
DAC26
DAC27
DAC28
DAC29
DAC30
DAC31
Offset DAC
All channels (DAC31–DAC0);
used for write commands only.
Read commands cannot be
used with these address bits.
1
1
1
1
1
1
Configuration register; control
bits C2, C1, and C0 = 010 and
C2, C1, and C0 = 011 set the error
flag in the configuration register.
Do not use these control bits with
these address bits.
1
0
0
0
0
1
______________________________________________________________________________________ 19
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
Table 8. Configuration-Register Data Format
16 DATA BITS
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ERRF SING
GLT
DT
SHDN
X
X
X
X
X
X
X
X
X
X
X
X = Don’t care.
Table 9. Configuration-Register Commands
DATA BIT
NAME
DESCRIPTION
Error flag; ERRF goes logic-high when an invalid command is attempted. ERRF is cleared each
time the configuration register is read back to DOUT. Clear-register commands C2, C1, and C0 =
111 resets ERRF. Conditions that trigger ERRF include:
Attempted read of address bits A5–A0 = 111111 (all 32 DACs)
Access to reserved addresses
D15
ERRF
Access to the configuration register (address bits A5–A0 = 100001 when used with control bits
C2, C1, and C0 = 010 and 011)
Default is logic-low (no error flags); ERRF is read only.
Single device; SING determines the manner in which data is output to DOUT. A logic-high sets the
device to operate in stand-alone mode or in parallel; only the 16 data bits are output to DOUT. A
logic-low sets the device to operate in a daisy chain of devices. In this case, the entire 32-bit
command word is output to DOUT.
D14
SING
Default is logic-low (daisy-chain mode); SING is read/write.
Glitch-suppression enable; the MAX5732–MAX5735 feature glitch-suppression circuitry on the
analog outputs that minimizes the output glitch during a major carry transition. A logic-low disables
the internal glitch-suppression circuitry, which improves settling time. A logic-high enables glitch-
suppression, suppressing up to 120nV-s glitch impulse on the DAC outputs.
D13
D12
GLT
DT
Default is logic-low (glitch suppression disabled); GLT is read/write.
Digital output enable; a logic-low enables DOUT. A logic-high disables DOUT. Disabling DOUT
reduces power consumption and digital noise feedthrough to the DAC outputs from the DOUT
output buffer.
Default is logic-low (DOUT enabled); DT is read/write.
Shutdown; a logic-high shuts down all 32 DACs. The logic interface remains active, and the data is
retained in the input and DAC registers. Read/write operations can be performed while the device
is disabled; however, no changes can occur at the device outputs. A logic-low powers up all 32
DACs if the device was previously in shutdown. Upon waking up, the DAC outputs return to the last
stored value in the DAC registers. Default is logic-low (normal operation); SHDN is read/write.
D11
SHDN
X
D10–D0
Don’t care.
Configuration Register
The configuration register controls the advanced fea-
tures of the MAX5732–MAX5735. Write to the configura-
tion register by setting the control bits C2, C1, and C0
= 001 and address bits A5–A0 = 100001. Table 8
shows the configuration-register data format for the
D15–D0 data bits. Table 9 shows the commands con-
trolled by the configuration register.
DSP Mode (DSP)
The MAX5732–MAX5735 provide a hardware-selectable
DSP-interface mode. DSP mode, when active, allows
chip select (CS) to go high before the entire 32-bit com-
mand word is clocked in. The active-low DSP logic input
selects microcontroller (µC)- or DSP-interface mode.
Drive DSP low for DSP-interface mode. Drive DSP high
for µC-interface mode. Figure 2 illustrates serial timing
for both µC- and DSP-interface modes.
20 ______________________________________________________________________________________
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
SING
When SING = 0 (default power-up mode), the device is
in daisy-chain mode. DOUT follows DIN after 32 clock
cycles. For the read command, DOUT provides the
read data in the next cycle following CS rising edge.
The 16 data bits of the previous command word are
clocked out on the last 16 clock cycles of the current
command word.
MAX573_
DIN(0)
CONTROLLER
DEVICE
SCLK
CS
DOUT(0)
DOUT(1)
DOUT(2)
1
DSP
When SING = 1, the device is in stand-alone mode. To
reduce the time it takes to read data out, the read data is
provided at DOUT as the 16 data bits of the current com-
mand are clocked in. The device acts on an incoming
command word independent of the rising edge of CS.
MAX573_
DIN(1)
SCLK
CS
Daisy Chain Operation
Any number of the MAX5732–MAX5735 devices can be
daisy chained by connecting the DOUT of one device
to the DIN of another device in a chain. All devices
must be in SING = 0 mode. Connecting the CS inputs
of all devices together eliminates the need to issue
NOP commands to devices early in the chain (see
DSP
MAX573_
DIN(2)
SCLK
CS
Figure 4). The maximum clock frequency (f
) is
SCLK
DSP
10MHz when DV
< +4.75V.
DD
Data Readback
The contents of the MAX5732–MAX5735 DAC and con-
figuration registers can be read on DOUT by issuing a
read-data command. Setting control bits C2, C1, and
C0 = 100, puts the device in read-data mode. The
address bits select the register to be read. The con-
tents of the register (16 data bits) are clocked out at
DOUT. The output-data format depends on the status of
Figure 4. Daisy-Chain Configuration
DSP and SING. Table 10 shows the manner in which
data is written to DOUT. Note that when the device is in
DSP mode (DSP = 0), only the 16-bit data of the selected
register is written to DOUT.
Table 10. Read-Data Modes with SING and DSP Controls
CONFIGURATION
DESCRIPTION
DSP
SING
READ DATA AT DOUT
DOUT provides the 16 data bits from the previous command word. Data
appears at DOUT on the last 16 clock edges of the current command word.
See Figure 7.
0
0
1
0
1
0
Stand alone
DOUT provides the 16 data bits from the current command word. Data appears at
DOUT on the last 16 clock edges of the current command word. See Figure 7.
Stand alone
Daisy chain
Data on DOUT follows the current command word after 32 clock cycles. For
read commands, the read data from the previous command word appears at
DOUT on the last 16 clock edges of the current command word. See Figure 4.
DOUT provides the 16 data bits from the current command word. Data appears
at DOUT on the last 16 clock edges of the current command word. For read
commands, the read data from the current command word appears at DOUT
on the last 16 clock edges of the current command word. See Figures 8 and 9.
Multiple DOUTs connected
in parallel (not daisy
chained)
1
1
______________________________________________________________________________________ 21
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
DIN(0)
W
WD2
W
WD1
WD0
R
XX
R
XX
R
XX
X
XX
X
XX
X
XX
W
CS
DOUT(0)
DOUT(1)
W
WD2
W
W
WD1
WD2
W
W
W
WD0
WD1
WD2
R
XX
R
R
XX
XX
R
RD0
RD1
RD2
X
R
R
XX
RD0
RD1
X
X
XX
XX
W
W
WD0
WD1
R
W
WD0
R
R
RD0
DOUT(2)
Figure 5. Example 1 of a Daisy-Chain Data Sequence
W/WD0 = 32-bit word with a write command; WD0 writes data for device 0. The 0 refers to the position in the daisy chain (0 is closest
to the bus master). Devices 1 and 2 are devices further down the chain.
R/RD2 = 32-bit word with a read command; RD2 reads data from device 2.
X = Don’t care (for X in the data or command position).
DIN(0)
W
WD2
R
XX
WD0
R
XX
W
WD1
R
XX
X
XX
X
XX
X
XX
W
CS
DOUT(0)
DOUT(1)
W
WD2
R
XX
W
R
WD0
RD1
R
W
R
XX
W
R
WD1
XX
R
RD0
WD1
RD2
X
R
XX
RD0
WD1
X
X
R
XX
XX
W
WD2
WD0
RD1
W
R
W
WD2
W
WD0
W
RD0
DOUT(2)
Figure 6. Example 2 of a Daisy-Chain Data Sequence
W/WD0 = 32-bit word with a write command; WD0 writes data for device 0. The 0 refers to the position in the daisy chain (0 is closest
to the bus master). Devices 1 and 2 are devices further down the chain.
R/RD2 = 32-bit word with a read command; RD2 reads data from device 2.
X = Don’t care (for X in the data or command position).
22 ______________________________________________________________________________________
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
Read-Data Format
The MAX5732–MAX5735 support daisy-chain connec-
MAX573_
tions of multiple devices. The default (power-up) config-
DIN
uration for the MAX5732–MAX5735 assumes that the
device may be part of a daisy chain of devices. DOUT
CONTROLLER
DEVICE
SCLK
DOUT
CS
follows DIN after 32 clock cycles. For a read command,
DOUT provides read data (instead of the data value
shifted in) in the next cycle following a CS rising edge.
Figures 5 and 6 show examples of daisy-chain
data sequences.
1 OR 0
DSP
Figure 7. Stand-Alone Configuration
Shutdown Mode
The MAX5732–MAX5735 feature a software-controlled
low-power shutdown mode. When bit 11 of the configu-
ration register is a logic high, the analog section of the
device is disabled, and the outputs go high impedance.
In shutdown, supply current is reduced to 50µA. Data
stored in the DAC and input registers is retained, and
the device outputs return to their previous values when
the device is brought out of shutdown. The serial inter-
face remains active while the device is in shutdown.
MAX573_
DIN
CONTROLLER
DEVICE
SCLK
CS
DOUT
DOUT
DOUT
1 OR 0
1 OR 0
1 OR 0
DSP
MAX573_
DIN
SCLK
CS
Power-Up State
The MAX5732–MAX5735 monitor the four power supplies
and maintain the output buffers in a known state until suffi-
cient voltage is available to ensure that no output glitches
occur. Once the minimum voltage threshold has been
passed, the device outputs come up in the clear state (all
DSP
MAX573_
DIN
SCLK
CS
outputs = 0). For proper power sequencing, V must be
SS
applied first. Power sequencing is not necessary if V is
SS
DSP
connected to AGND.
Figure 8. Example of a Parallel Configuration with Read-Back
DIN(0)
A1 A0 Sp Sp Sp Sp Sp Sp Sp
C2 C1 C0 A5 A4 A3 A2
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SCLK
CS (µC)
OR
CS (DSP)
DOUT(0)
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13
Figure 9. Read Data Timing When Not Daisy Chained
______________________________________________________________________________________ 23
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
HVDRV0
DAC0
MAX5732
MAX5733
VOLTAGE
REFERENCE
DAC31
HVDRV31
14 TO 16 BITS
DWDM
PIPE
MEMS MIRRORS WITH
X AND Y CONTROL
CONTROL
ALGORITHM
DSP
14 TO 16 BITS
THIN-FILM FILTER OR
PLANAR LIGHT WAVE
SEPARATORS
ADC
WITH OPTICAL
LENSES
POSITION OR
OPTICAL
FEEDBACK
DWDM
PIPE
VOLTAGE
REFERENCE
MEMS
MIRRORS WITH
X AND Y
PGA OR
FIXED GAIN AMPS
CONTROL
OPTICAL LENSES
AND COLLIMATORS
Figure 10. MEMS Mirror Control
The offset DAC simultaneously adjusts the voltage
range of all 32 DACs, allowing optimization to the appli-
cation. The remote-sense feature allows the pin elec-
tronic voltages to be referenced to the ground potential
at the DUT site.
Applications Information
MEMS Micromirror Control
The MAX5732/MAX5733 are the highest resolution 32-
channel DACs available in the smallest footprint, mak-
ing the devices ideal for optical MEMS mirror control
(Figure 10). A high-resolution DAC forms the core ana-
log block for controlling the X and Y position of the mir-
ror. As the density of the optical cross-connects
increases, the number of DAC channels also increases.
By offering the highest resolution and the greatest den-
sity, the MAX5732/MAX5733 improve performance and
reduce the board footprint.
The B grade linearity error of 2.44mV (max) is more than
sufficient for most ATE applications. The A grade device
cuts this error to 1.22mV (max) for higher accuracy.
The pipelined register architecture allows all 32 DACs
to be updated simultaneously. This is valuable during
test setups, as all values in the tester can be set and
then updated in unison with a single command. This
feature can be accessed through the serial port or the
LDAC input.
The low output noise of the MAX5734 allows direct con-
nection to the pin electronics, eliminating the cost and
PC board area of external filtering.
Automatic Test Equipment (ATE)
Applications
The MAX5734 includes many features suited for ATE
applications. The device is the most compact level-set-
ting solution available for high-density pin electronics
boards. The MAX5734 provides a -2.5V to +7.5V output
voltage range (required by most ATE applications).
Modern pin electronics integrated circuits (PEICs) are
typically fabricated on high-speed processes with low
breakdown voltages. Some devices require external
24 ______________________________________________________________________________________
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
protection on their reference inputs to satisfy absolute
maximum ratings. The MAX5734 features outputs that
are almost rail-to-rail. This allows the AV and V
supplies to be set to voltages within the absolute maxi-
mum ratings of the PEIC. This guarantees that the PEIC
is protected in all situations.
digital feedthrough and crosstalk. Bypass all power sup-
plies with an additional 0.1µF and 1µF on each pin, as
close to the device as possible. Refer to the MAX5732–
MAX5735 evaluation kit for a suggested layout.
CC
SS
The MAX5732–MAX5735 have four separate power
supplies. AV
powers the internal analog circuitry
DD
(except for the output buffers) and DV
powers the
DD
Additional protection is provided by the MAX5734
glitch-free power-up into the clear state with all DAC
outputs set to approximately 0V. Either the serial port or
the CLR input can assert the clear function.
digital section of the device. AV
output buffers.
and V power the
CC
SS
The MAX5732–MAX5735 feature an exposed paddle on
the backside of the package for improved power dissi-
pation. The exposed paddle is electrically connected to
Power Supplies, Bypassing,
Decoupling, and Layout
Grounding and power-supply decoupling strongly influ-
ence device performance. Digital signals can couple
through the reference input, power supplies, and ground
connection. Proper grounding and layout can reduce
V
, and should be soldered to a large copper plane
SS
that shares the same potential. For more information on
the exposed paddle QFN package, refer to the following
website: http://pdfserv.maxim-ic.com/arpdf/AppNotes/
4hfan081.pdf
Pin Configurations (continued)
Chip Information
TRANSISTOR COUNT: 152,000
TOP VIEW
PROCESS: BiCMOS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AV
1
2
3
4
5
6
7
8
9
48 AV
CC
CC
OUT9
OUT8
OUT7
N.C.
47 OUT21
46 OUT22
45
V
SS
44 AGND
43 OUT23
42 OUT24
41 OUT25
40 OUT26
39 OUT27
38 OUT28
37 OUT29
36 OUT30
35 OUT31
34 N.C.
OUT6
OUT5
OUT4
AGND
MAX5732–MAX5735
OUT3 10
11
V
SS
OUT2 12
OUT1 13
OUT0 14
N.C. 15
N.C. 16
33 N.C.
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TQFP
______________________________________________________________________________________ 25
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
Ordering Information (continued)
OUTPUT
VOLTAGE
(V)
MAX
INL
(LSB)
PIN-
PKG
PART
PACKAGE CODE
MAX5732AUCB**
MAX5732BUCB**
0 to +5
0 to +5
8
64 TQFP
C64-8
C64-8
16 64 TQFP
56 Thin
8
MAX5733AUTN
0 to +10
0 to +10
T5688-3
T5688-3
QFN-EP*
56 Thin
16
MAX5733BUTN
QFN-EP*
MAX5733AUCB**
MAX5733BUCB**
0 to +10
0 to +10
8
64 TQFP
C64-8
C64-8
16 64 TQFP
-2.5 to
+7.5
56 Thin
8
MAX5734AUTN
MAX5734BUTN
MAX5734AUCB**
MAX5734BUCB**
MAX5735AUTN
MAX5735BUTN
T5688-3
T5688-3
C64-8
QFN-EP*
-2.5 to
+7.5
56 Thin
16
QFN-EP*
-2.5 to
+7.5
8
64 TQFP
-2.5 to
+7.5
16 64 TQFP
C64-8
56 Thin
8
-5 to +5
-5 to +5
T5688-3
T5688-3
QFN-EP*
56 Thin
16
QFN-EP*
MAX5735AUCB**
MAX5735BUCB**
-5 to +5
-5 to +5
8
64 TQFP
C64-8
C64-8
16 64 TQFP
Note: All devices operate over the 0°C to +85°C temperature
range.
*EP = Exposed pad (internally connected to V ).
SS
**Future product—contact factory for availability.
26 ______________________________________________________________________________________
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
56L THIN QFN, 8x8x0.8mm
1
E
21-0135
2
PACKAGE OUTLINE
56L THIN QFN, 8x8x0.8mm
2
E
21-0135
2
______________________________________________________________________________________ 27
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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