MAX5815BAUD T [MAXIM]
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface; 超小尺寸，四通道， 8位/ 10位/ 12位缓冲输出DAC ，内置基准和I²C接口
| 型号： | MAX5815BAUD T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface |
| 文件： | 总30页 (文件大小：4336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-6167; Rev 0; 2/12
General Description
Benefits and Features
The MAX5813/MAX5814/MAX5815 4-channel, low-power,
8-/10-/12-bit, voltage-output digital-to-analog converters
(DACs) include output buffers and an internal reference
that is selectable to be 2.048V, 2.500V, or 4.096V. The
MAX5813/MAX5814/MAX5815 accept a wide supply
voltage range of 2.7V to 5.5V with extremely low power
(3mW) consumption to accommodate most low-voltage
applications. A precision external reference input allows
rail-to-rail operation and presents a 100kI (typ) load to
an external reference.
The MAX5813/MAX5814/MAX5815 have an I2C-compatible,
2-wire interface that operates at clock rates up to
400kHz. The DAC output is buffered and has a low sup-
ply current of less than 250FA per channel and a low
offset error of Q0.5mV (typ). On power-up, the MAX5813/
MAX5814/MAX5815 reset the DAC outputs to zero, pro-
viding additional safety for applications that drive valves
or other transducers which need to be off on power-up.
The internal reference is initially powered down to allow
use of an external reference. The MAX5813/MAX5814/
MAX5815 allow simultaneous output updates using soft-
ware LOAD commands or the hardware load DAC logic
input (LDAC).
S Four High-Accuracy DAC Channels
12-Bit Accuracy Without Adjustment
ꢀ1 ꢁLB ꢂIꢁ Buꢃꢃered ꢄoltage ꢅutꢆut
ꢀGuaranteed Monotonic ꢅver All ꢅꢆerating
Conditions
ꢀꢂndeꢆendent Mode Lettings ꢃor Each DAC
S Three Precision Lelectable ꢂnternal Reꢃerences
ꢀ2.048ꢄ, 2.500ꢄ, or 4.096ꢄ
S ꢂnternal ꢅutꢆut Buꢃꢃer
ꢀRail-to-Rail ꢅꢆeration with External Reꢃerence
4.5µs Lettling Time
ꢅutꢆuts Directly Drive 2kI ꢁoads
S Lmall 5mm x 4.4mm 14-Pin TLLꢅP or Ultra-Lmall
1.6mm x 2.2mm 12-Bumꢆ WꢁP Package
S Wide 2.7ꢄ to 5.5ꢄ Luꢆꢆly Range
S Leꢆarate 1.8ꢄ to 5.5ꢄ ꢄ
Power-Luꢆꢆly ꢂnꢆut
DDꢂꢅ
S Fast 400kHz ꢂ2C-Comꢆatible, 2-Wire Lerial
ꢂnterꢃace
S Power-ꢅn-Reset to Zero-Lcale DAC ꢅutꢆut
S LDAC and CLR For Asynchronous Control
S Three Loꢃtware-Lelectable Power-Down ꢅutꢆut
ꢂmꢆedances
A clear logic input (CLR) allows the contents of the CODE
and the DAC registers to be cleared asynchronously and
sets the DAC outputs to zero. The MAX5813/MAX5814/
MAX5815 are available in a 14-pin TSSOP and an ultra-
small, 12-bump WLP package and are specified over the
-40NC to +125NC temperature range.
ꢀ1kI, 100kI, or High ꢂmꢆedance
Functional Diagram
V
DDIO
V
REF
DD
Applications
MAX5813
MAX5814
MAX5815
INTERNAL REFERENCE/
EXTERNAL BUFFER
Programmable Voltage and Current Sources
Gain and Offset Adjustment
SCL
SDA
1 OF 4 DAC CHANNELS
Automatic Tuning and Optical Control
Power Amplifier Control and Biasing
Process Control and Servo Loops
Portable Instrumentation
CODE
REGISTER
DAC
LATCH
8-/10-/12-BIT
DAC
ADDR0
(ADDR1)
OUTA
OUTB
OUTC
OUTD
BUFFER
2
C SERIAL
INTERFACE
I
CLR
CLEAR/
RESET
CLEAR/
RESET
CODE
LOAD
100kI
1kI
(LDAC)
POWER-DOWN
DAC CONTROL LOGIC
Data Acquisition
POR
GND
Ordering Information appears at end of data sheet.
( ) TSSOP PACKAGE ONLY
For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/MAX5813.related
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
ABLꢅꢁUTE MAXꢂMUM RATꢂIGL
V
V
to GND ................................................ -0.3V to +6V
Maximum Continuous Current into Any Pin .................... Q50mA
Operating Temperature Range........................ -40NC to +125NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (TSSOP only)(soldering, 10s)...........+300NC
Soldering Temperature (reflow) .................................... +260NC
DD, DDIO
OUT_, REF to GND....0.3V to the lower of (V
+ 0.3V) and +6V
DD
SCL, SDA, LDAC, CLR to GND .............................. -0.3V to +6V
ADDR_ to GND............................................-0.3V to the lower of
(V
+ 0.3V) and +6V
DDIO
Continuous Power Dissipation (T = +70NC)
A
TSSOP (derate at 10mW/NC above 70NC)...................797mW
WLP (derate at 16.1mW/NC above 70NC)..................1288mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAꢁ CHARACTERꢂLTꢂCL (Iote 1)
TSSOP
WLP
Junction-to-Ambient Thermal Resistance (θ
Junction-to-Ambient Thermal Resistance (θ ) .......100NC/W
)
JA
JA
(Note 2)........................................................................62NC/W
Iote 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Iote 2: Visit www.maxim-ic.com/aꢆꢆ-notes/index.mvꢆ/id/1891 for information about the thermal performance of WLP packaging.
EꢁECTRꢂCAꢁ CHARACTERꢂLTꢂCL
(V
= 2.7V to 5.5V, V
= 1.8V to 5.5V, V
= 0V, C = 200pF, R = 2kI, T = -40NC to +125NC, unless otherwise noted. Typical
DD
DDIO
GND
L
L
A
values are at T = +25NC.) (Note 3)
A
PARAMETER
LYMBꢅꢁ
CꢅIDꢂTꢂꢅIL
MꢂI
TYP
MAX
UIꢂTL
Bits
DC PERFꢅRMAICE (Iote 4)
MAX5813
MAX5814
MAX5815
MAX5813
MAX5814
MAX5815
MAX5813
MAX5814
MAX5815
8
10
Resolution and Monotonicity
Integral Nonlinearity (Note 5)
Differential Nonlinearity (Note 5)
N
12
-0.25
-0.5
-1
Q0.05
Q0.25
Q0. 5
Q0.05
Q0.1
Q0.2
Q0.5
Q10
+0.25
+0.5
+1
INL
LSB
-0.25
-0.5
-1
+0.25
+0.5
+1
DNL
OE
LSB
Offset Error (Note 6)
Offset Error Drift
-5
+5
mV
FV/NC
%FS
Gain Error (Note 6)
GE
-1.0
Q0.1
+1.0
ppm of
FS/NC
Gain Temperature Coefficient
With respect to V
With respect to V
Q3.0
REF
Zero-Scale Error
Full-Scale Error
0
10
mV
-0.5
+0.5
%FS
REF
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products
2
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
EꢁECTRꢂCAꢁ CHARACTERꢂLTꢂCL (continued)
(V
= 2.7V to 5.5V, V
= 1.8V to 5.5V, V
= 0V, C = 200pF, R = 2kI, T = -40NC to +125NC, unless otherwise noted. Typical
DD
DDIO
GND
L
L
A
values are at T = +25NC.) (Note 3)
A
PARAMETER
LYMBꢅꢁ
CꢅIDꢂTꢂꢅIL
MꢂI
TYP
MAX
UIꢂTL
DAC ꢅUTPUT CHARACTERꢂLTꢂCL
No load
0
0
V
DD
V
-
DD
Output Voltage Range (Note 7)
2kI load to GND
V
0.2
2kI load to V
0.2
V
DD
DD
V
= 3V Q10%,
| P 5mA
DD
300
300
0.3
|I
OUT
Load Regulation
V
= V /2
FV/mA
OUT
OUT
FS
V
= 5V Q10%,
| P 10mA
DD
|I
OUT
V
= 3V Q10%,
| P 5mA
DD
|I
OUT
DC Output Impedance
V
= V /2
I
FS
V
= 5V Q10%,
| P 10mA
DD
0.3
|I
OUT
Maximum Capacitive Load
Handling
C
500
pF
L
Resistive Load Handling
R
2
kI
L
Sourcing (output
shorted to GND)
30
Short-Circuit Output Current
V
V
= 5.5V
mA
DD
Sinking (output
50
shorted to V
)
DD
DC Power-Supply Rejection
DYIAMꢂC PERFꢅRMAICE
Voltage-Output Slew Rate
= 3V Q10% or 5V Q10%
100
FV/V
V/Fs
Fs
DD
SR
Positive and negative
1.0
2.2
2.6
4.5
2
¼ scale to ¾ scale, to P 1 LSB, MAX5813
¼ scale to ¾ scale, to P 1 LSB, MAX5814
¼ scale to ¾ scale, to P 1 LSB, MAX5815
Major code transition
Voltage-Output Settling Time
DAC Glitch Impulse
nV*s
nV*s
External reference
3.5
3.3
Channel-to-Channel
Feedthrough (Note 8)
Internal reference
Code = 0, all digital inputs from 0V to
Digital Feedthrough
Power-Up Time
0.2
nV*s
V
DDIO
Startup calibration time (Note 9)
From power-down
200
50
Fs
Fs
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products
3
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
EꢁECTRꢂCAꢁ CHARACTERꢂLTꢂCL (continued)
(V
= 2.7V to 5.5V, V
= 1.8V to 5.5V, V
= 0V, C = 200pF, R = 2kI, T = -40NC to +125NC, unless otherwise noted. Typical
DD
DDIO
GND
L
L
A
values are at T = +25NC.) (Note 3)
A
PARAMETER
LYMBꢅꢁ
CꢅIDꢂTꢂꢅIL
MꢂI
TYP
90
MAX
UIꢂTL
f = 1kHz
External reference
f = 10kHz
82
f = 1kHz
112
102
125
110
160
145
12
2.048V internal
reference
f = 10kHz
Output Voltage-Noise Density
(DAC Output at Midscale)
nV/√Hz
f = 1kHz
2.5V internal
reference
f = 10kHz
f = 1kHz
4.096V internal
reference
f = 10kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 1kHz
External reference
76
385
14
2.048V internal
reference
91
450
15
Integrated Output Noise
(DAC Output at Midscale)
FV
P-P
2.5V internal
reference
99
470
16
4.096V internal
reference
124
490
114
99
External reference
f = 10kHz
f = 1kHz
175
153
200
174
295
255
13
2.048V internal
reference
f = 10kHz
Output Voltage-Noise Density
(DAC Output at Full Scale)
nV/√Hz
f = 1kHz
2.5V internal
reference
f = 10kHz
f = 1kHz
4.096V internal
reference
f = 10kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
External reference
94
540
19
2.048V internal
reference
143
685
21
Integrated Output Noise
(DAC Output at Full Scale)
FV
P-P
2.5V internal
reference
159
705
26
4.096V internal
reference
213
750
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products
4
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
EꢁECTRꢂCAꢁ CHARACTERꢂLTꢂCL (continued)
(V
= 2.7V to 5.5V, V
= 1.8V to 5.5V, V
= 0V, C = 200pF, R = 2kI, T = -40NC to +125NC, unless otherwise noted. Typical
DD
DDIO
GND
L
L
A
values are at T = +25NC.) (Note 3)
A
PARAMETER
REFEREICE ꢂIPUT
LYMBꢅꢁ
CꢅIDꢂTꢂꢅIL
MꢂI
1.24
75
TYP
MAX
UIꢂTL
Reference Input Range
Reference Input Current
Reference Input Impedance
REFEREICE ꢅUPUT
V
V
V
REF
DD
I
V
= V
= 5.5V
55
74
FA
kI
REF
REF
DD
R
100
REF
REF
V
V
V
= 2.048V, T = +25NC
2.043
2.494
4.086
2.048
2.5
2.053
2.506
4.106
Q10
REF
REF
REF
A
Reference Output Voltage
V
= 2.5V, T = +25NC
V
A
= 4.096V, T = +25NC
4.096
Q3
A
MAX5815A
Reference Temperature
Coefficient (Note 10)
ppm/NC
MAX5813/MAX5814/MAX5815B
External load
Q10
25
Q25
Reference Drive Capacity
Reference Capacitive Load
Reference Load Regulation
Reference Line Regulation
PꢅWER REQUꢂREMEITL
kI
pF
200
2
I
= 0 to 500FA
mV/mA
mV/V
SOURCE
0.05
V
= 4.096V
4.5
2.7
1.8
5.5
5.5
REF
Supply Voltage
V
V
V
DD
All other options
I/O Supply Voltage
V
5.5
DDIO
V
V
V
V
V
= 2.048V
= 2.5V
= 4.096V
= 3V
0.85
0.9
1.25
1.25
1.40
1.1
REF
REF
REF
REF
REF
Internal reference
External reference
Supply Current (Note 11)
I
1.1
mA
DD
0.65
0.9
= 5V
1.25
Interface Supply Current
(Note 11)
I
1
FA
FA
DDIO
All DACs off, internal reference ON
All DACs off, internal reference OFF,
140
0.5
1
Power-Down Mode Supply
Current
T
= -40NC to +85NC
I
A
PD
All DACs off, internal reference OFF,
= +125NC
1.2
2.5
T
A
DꢂGꢂTAꢁ ꢂIPUT CHARACTERꢂLTꢂCL (LCꢁ, LDA, ADDR0, ADDR1, LDAC, CLR)
0.7 x
2.2V < V
< 5.5V
< 2.2V
V
V
DDIO
DDIO
V
DDIO
Input High Voltage (Note 11)
V
IH
0.8 x
1.8V < V
V
DDIO
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products
5
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
EꢁECTRꢂCAꢁ CHARACTERꢂLTꢂCL (continued)
(V
= 2.7V to 5.5V, V
= 1.8V to 5.5V, V
= 0V, C = 200pF, R = 2kI, T = -40NC to +125NC, unless otherwise noted. Typical
DD
DDIO
GND
L
L
A
values are at T = +25NC.) (Note 3)
A
PARAMETER
LYMBꢅꢁ
CꢅIDꢂTꢂꢅIL
MꢂI
TYP
MAX
UIꢂTL
0.3 x
2.2V < V
1.8V < V
< 5.5V
DDIO
V
DDIO
Input Low Voltage (Note 11)
V
V
IL
0.2 x
< 2.2V
DDIO
V
DDIO
Hysteresis Voltage
V
0.15
V
H
Input Leakage Current
Input Capacitance (Note 10)
ADDR_ Pullup/Pulldown Strength
DꢂGꢂTAꢁ ꢅUTPUT (LDA)
Output Low Voltage
I
V
= 0V or V
(Note 11)
Q0.1
Q1
10
90
FA
pF
kI
IN
IN
DDIO
C
IN
R
, R
(Note 12)
30
50
PU PD
V
I
= 3mA
0.2
V
OL
SINK
ꢂ2C TꢂMꢂIG CHARACTERꢂLTꢂCL (LCꢁ, LDA, LDAC, CLR)
SCL Clock Frequency
f
400
kHz
SCL
Bus Free Time Between a STOP
and a START Condition
t
1.3
0.6
Fs
BUF
Hold Time Repeated for a
START Condition
t
t
Fs
HD;STA
SCL Pulse Width Low
SCL Pulse Width High
t
1.3
0.6
Fs
Fs
LOW
t
HIGH
Setup Time for Repeated START
Condition
0.6
Fs
SU;STA
Data Hold Time
Data Setup Time
t
0
900
ns
ns
HD;DAT
t
100
SU;DAT
SDA and SCL Receiving
Rise Time
20 +
C /10
B
t
300
300
250
ns
ns
ns
r
SDA and SCL Receiving
Fall Time
20 +
t
t
f
f
C /10
B
20 +
SDA Transmitting Fall Time
C /10
B
Setup Time for STOP Condition
Bus Capacitance Allowed
t
0.6
10
Fs
pF
ns
SU;STO
C
V
= 2.7V to 5.5V
400
B
DD
Pulse Width of Suppressed Spike
t
50
sp
CLR Removal Time Prior to a
Recognized START
t
100
ns
CLRSTA
t
20
20
ns
ns
ns
CLR Pulse Width Low
CLPW
t
LDAC Pulse Width Low
LDPW
t
Applies to execution edge
400
SCLK Rise to LDAC Fall to Hold
LDH
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products
6
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
EꢁECTRꢂCAꢁ CHARACTERꢂLTꢂCL (continued)
(V
= 2.7V to 5.5V, V
= 1.8V to 5.5V, V
= 0V, C = 200pF, R = 2kI, T = -40NC to +125NC, unless otherwise noted. Typical
GND L L A
DD
DDIO
values are at T = +25NC.) (Note 3)
A
Iote 3: Limits are 100% production tested at T = +25NC and/or T = +125NC. Limits over the operating temperature range and
A
A
relevant supply voltage range are guaranteed by design and characterization. Typical values are at T = +25NC and are
A
not guaranteed.
Iote 4: DC Performance is tested without load.
Iote 5: Linearity is tested with unloaded outputs to within 20mV of GND and V
.
DD
Iote 6: Gain and offset tested at code 4065 and 30, respectively with V
= V
.
REF
DD
Iote 7: Subject to zero and full-scale error limits and V
settings.
REF
Iote 8: Measured with all other DAC outputs at midscale with one channel transitioning 0 to full scale.
Iote 9: On power-up, the device initiates an internal 200µs (typ) calibration sequence. All commands issued during this time will
be ignored.
Iote 10: Guaranteed by design.
Iote 11: All channels active at V , unloaded. Static logic inputs with V = V
Iote 12: An unconnected condition on the ADDR_ pins is sensed via a resistive pullup and pulldown operation; for proper
and V = V
.
FS
IL
GND
IH
DDIO
operation, ADDR_ pins should be tied to V
, GND, or left unconnected with minimal capacitance.
DDIO
SDA
t
t
t
SU;DAT
LOW
BUF
t
f
t
r
t
t
t
r
HD;STA
SP
t
f
SCL
t
HIGH
t
t
t
SU;STO
HD;STA
SU;STA
t
CLPW
t
HD;DAT
S
S
r
P
S
CLR
t
LDPW
t
LDH
t
CLRSTA
LDAC
Figure 1. I2C Serial Interface Timing Diagram
Typical Operating Characteristics
(MAX5815, 12-bit performance, T = +25°C, unless otherwise noted.)
A
INL vs. CODE
INL vs. CODE
DNL vs. CODE
1.0
0.8
1.0
0.8
1.0
0.8
V
= V = 3V
V
= V = 5V
V
= V = 3V
DD REF
DD
REF
DD
REF
NO LOAD
NO LOAD
NO LOAD
0.6
0.6
0.6
0.4
0.4
0.4
0.2
0.2
0.2
0
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products
7
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
Typical Operating Characteristics (continued)
(MAX5815, 12-bit performance, T = +25°C, unless otherwise noted.)
A
DNL vs. CODE
INL AND DNL vs. SUPPLY VOLTAGE
INL AND DNL vs. TEMPERATURE
1.0
0.8
1.0
0.8
1.0
0.8
V
= V = 3V
REF
V
= V = 3V
DD REF
DD
V
= V = 5V
REF
DD
NO LOAD
0.6
0.6
0.6
MAX INL
MAX INL
0.4
0.4
0.4
MAX DNL
MIN DNL
MAX DNL
MIN DNL
0.2
0.2
0.2
0
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
MIN INL
MIN INL
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
OFFSET AND ZERO-SCALE ERROR
vs. SUPPLY VOLTAGE
OFFSET AND ZERO-SCALE ERROR
vs. TEMPERATURE
FULL-SCALE ERROR AND GAIN ERROR
vs. SUPPLY VOLTAGE
1.0
0.8
1.0
0.8
0.020
0.016
0.012
0.008
0.004
0
V
= 2.5V (EXTERNAL)
REF
NO LOAD
V
= 2.5V (EXTERNAL)
REF
NO LOAD
ZERO-SCALE ERROR
0.6
0.6
ZERO-SCALE ERROR
GAIN ERROR
0.4
0.4
OFFSET ERROR (V = 5V)
DD
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.004
-0.008
-0.012
-0.016
-0.020
FULL-SCALE ERROR
OFFSET ERROR (V = 3V)
DD
OFFSET ERROR
V
= 2.5V (EXTERNAL)
REF
NO LOAD
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
FULL-SCALE ERROR AND GAIN ERROR
vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
1.4
1.2
1.0
0.8
0.6
0.4
0.10
0.05
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
(INTERNAL) = 4.096V
V
= 2.5V (EXTERNAL)
OUT_ = FULL SCALE
NO LOAD
(EXTERNAL) = V = 5V
DD
REF
NO LOAD
REF
NO LOAD
OUT_ = FULL SCALE
V
REF
T
= +25°C
A
V
V
(INTERNAL) = 4.096V,
= 5V
REF
DD
GAIN ERROR (V = 5V)
DD
V
(INTERNAL) = 2.5V,
REF
V
= 2.5V (EXTERNAL)
REF
V
= 5V
DD
V
(INTERNAL) = 2.5V
REF
V
V
(INTERNAL) = 2.048V,
REF
= 5V
DD
FULL-SCALE ERROR
GAIN ERROR (V = 3V)
DD
-0.05
-0.10
V
V
(INTERNAL) = 2.048V,
REF
= 5V
V
(EXTERNAL) = V = 3V
DD
DD
REF
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
(V)
V
DD
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products
8
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
Typical Operating Characteristics (continued)
(MAX5815, 12-bit performance, T = +25°C, unless otherwise noted.)
A
POWER-DOWN MODE SUPPLY CURRENT
vs. TEMPERATURE
I
vs. CODE
VDD
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.6
NO LOAD
POWER-DOWN MODE
ALL DACs
V
= V = 5V
DD REF
V
= 5V,
DD
V
= 5V,
DD
1.2
V
= 4.096V
REF
V
= 2.5V
REF
T
= +125°C
= +25°C
A
0.8
0.4
0
T
A
V
DD
= 5V,
T
A
= +85°C
V
= 2.048V
REF
V
= V = 3V
REF
DD
T
A
= -40°C
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
SETTLING TO ±± LSꢀ
I
(EXTERNAL) vs. CODE
REF
(V = V
DD
= 5V, R = 2kI, C = 200pF)
REF
L L
60
V
= V
REF
DD
NO LOAD
V
OUT
50
40
30
20
10
0
0.5V/div
1/4 SCALE TO 3/4 SCALE
V
= 5V
REF
ZOOMED V
1 LSB/div
OUT
V
= 3V
REF
3.75µs
TRIGGER PULSE
5V/div
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
4µs/div
MAJOR CODE TRANSITION
GLITCH ENERGY
SETTLING TO ±± LSꢀ
(V = V
DD
= 5V, R = 2kI, C = 200pF)
(V = V
= 5V, R = 2kI, C = 200pF)
REF
L L
DD
REF
L
L
1 LSB CHANGE
(MIDCODE TRANSITION
0x800 TO 0x7FF)
3/4 SCALE TO 1/4 SCALE
GLITCH IMPULSE = 2nV*s
4.3µs
ZOOMED V
OUT
ZOOMED V
1 LSB/div
1.25mV/div
OUT
V
OUT
0.5V/div
TRIGGER PULSE
5V/div
TRIGGER PULSE
5V/div
4µs/div
2µs/div
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products
9
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
Typical Operating Characteristics (continued)
(MAX5815, 12-bit performance, T = +25°C, unless otherwise noted.)
A
MAJOR CODE TRANSITION
GLITCH ENERGY
V
vs. TIME TRANSIENT
OUT
EXITING POWER-DOWN
(V = V
= 5V, R = 2kI, C = 200pF)
DD
REF
L
L
MAX5813 toc20
1 LSB CHANGE
(MIDCODE TRANSITION
0x7FF TO 0x800)
GLITCH IMPULSE = 2nV*s
V
SCL
0V
0V
5V/div
36TH EDGE
ZOOMED V
OUT
1.25mV/div
DAC OUTPUT
500mV/div
TRIGGER PULSE
5V/div
V
= 5V, V = 2.5V
REF
DD
EXTERNAL
10µs/div
2µs/div
CHANNEL-TO-CHANNEL FEEDTHROUGH
(V = V = 5V, T = +25NC,
DD
REF
A
R = 2kI, C = 200pF)
POWER-ON RESET TO 0V
L
L
MAX5813 toc22
MAX5813 toc21
V
DD
TRANSITIONING
DAC
1V/div
V
= V = 5V
REF
DD
2V/div
R = 2kI
L
10kI LOAD TO V
DD
0V
0V
STATIC DAC
1.25mV/div
NO LOAD
V
OUT
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 3.5nV*s
2V/div
TRIGGER PULSE
10V/div
4µs/div
20µs/div
CHANNEL-TO-CHANNEL FEEDTHROUGH
(V = 5V, V
T = +25NC, R = 2kI, C = 200pF)
A
= 4.096V (INTERNAL),
CHANNEL-TO-CHANNEL FEEDTHROUGH
(V = V = 5V, T = +25NC, NO LOAD)
DD
REF
L
L
DD
REF
A
MAX5813 toc24
MAX5813 toc23
TRANSITIONING
DAC
1V/div
R = 2kI
TRANSITIONING
DAC
1V/div
L
NO LOAD
NO LOAD
STATIC DAC
1.25mV/div
NO LOAD
STATIC DAC
1.25mV/div
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 3.3nV*s
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 1.8nV*s
TRIGGER PULSE
10V/div
TRIGGER PULSE
10V/div
5µs/div
5µs/div
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 10
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
Typical Operating Characteristics (continued)
(MAX5815, 12-bit performance, T = +25°C, unless otherwise noted.)
A
CHANNEL-TO-CHANNEL FEEDTHROUGH
DIGITAL FEEDTHROUGH
= 5V, R = 2kI, C = 200pF)
(V = 5V, V
DD
= 4.096V (INTERNAL),
REF
(V = V
DD
REF
L
L
MAX5813 toc26
T = +25NC, NO LOAD)
A
MAX5813 toc25
V
V
= 5V
DD
= 5V (EXTERNAL)
REF
DACS AT MIDSCALE
TRANSITIONING DAC
1V/div
NO LOAD
NO LOAD
STATIC DAC
1.25mV/div
V
OUT
1.65mV/div
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 1.1nV*S
TRIGGER PULSE
10V/div
DIGITAL FEEDTHROUGH = 0.1nV·s·
40ns/div
4µs/div
OUTPUT LOAD REGULATION
OUTPUT CURRENT LIMITING
10
8
500
V
= V
REF
V
= V
DD REF
DD
400
300
200
100
0
6
V
= 5V
DD
4
V
= 5V
DD
2
0
V
= 3V
DD
-2
-4
-6
-8
-10
-100
-200
-300
-400
-500
V
= 3V
DD
-30 -20 -10
0
10 20 30 40 50 60
(mA)
-30 -20 -10
0
10 20 30 40 50 60 70
(mA)
I
I
OUT
OUT
NOISE-VOLTAGE DENSITY
VS. FREQUENCY (DAC AT MIDSCALE)
HEADROOM AT RAILS
vs. OUTPUT CURRENT
350
300
250
200
150
100
50
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0
V
= 5V, V = 4.096V
REF
DD
(INTERNAL)
V
= 5V, SOURCING
DD
V
= 5V, V = 2.5V
REF
DD
(INTERNAL)
V
= 5V, V = 2.048V
DD
REF
(INTERNAL)
V
= 3V, SOURCING
DD
V
= 3V AND 5V
SINKING
DD
V
= 5V, V = 4.5V
REF
V
= V
REF
DD
DD
(EXTERNAL)
DAC = FULL SCALE
0
100
1k
10k
100k
0
1
2
3
4
I
5
6
7
8
9
10
FREQUENCY (Hz)
(mA)
OUT
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 11
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
Typical Operating Characteristics (continued)
(MAX5815, 12-bit performance, T = +25°C, unless otherwise noted.)
A
0.1Hz TO 10Hz OUTPUT NOISE, EXTERNAL
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (V = 5V, V = 2.048V)
REFERENCE (V = 5V, V
= 4.5V)
DD
REF
DD
REF
MAX5813 toc31
MAX5813 toc32
MIDSCALE UNLOADED
= 12µV
MIDSCALE UNLOADED
= 13µV
V
V
P-P
P-P
2µV/div
2µV/div
4s/div
4s/div
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (V = 5V, V = 2.5V)
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (V = 5V, V = 4.096V)
DD
REF
DD
REF
MAX5813 toc33
MAX5813 toc34
MIDSCALE UNLOADED
= 16µV
MIDSCALE UNLOADED
= 15µV
V
V
P-P
P-P
2µV/div
2µV/div
4s/div
4s/div
V
REF
DRIFT vs. TEMPERATURE
REFERENCE LOAD REGULATION
SUPPLY CURRENT vs. INPUT LOGIC VOLTAGE
30
25
20
15
10
5
0
2000
V
= 2.7V
DD
V
= 5V
DD
1800
1600
1400
1200
1000
800
600
400
200
0
V
= 2.5V (INTERNAL)
BOX METHOD
REF
INTERNAL REFERENCE
-0.2
-0.4
-0.6
-0.8
-1.0
V
= 5V
DDIO
V
= 2.048V, 2.5V, AND 4.096V
REF
V
2
= 3V
DDIO
V
= 1.8V
3
DDIO
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TEMPERATURE DRIFT (ppm/°C)
0
50 100 150 200 250 300 350 400 450 500
REFERENCE OUTPUT CURRENT (µA)
0
1
4
5
INPUT LOGIC VOLTAGE (V)
Maxim Integrated Products 12
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
Pin/Bump Configurations
TOP VIEW
TOP VIEW
MAX5813/MAX5814/MAX5815
+
REF
OUTA
OUTB
GND
1
2
3
4
5
6
7
14 LDAC
13
1
2
3
4
+
OUTA
OUTB
OUTC
OUTD
V
DDIO
A
B
C
12 CLR
11 SDA
10 SCL
MAX5813
MAX5814
MAX5815
REF
CLR
GND
SDA
V
V
DD
DDIO
OUTC
OUTD
SCL
ADDR0
9
8
ADDR0
ADDR1
V
DD
TSSOP
WLP
Pin/Bump Description
PIN
BUMP
WLP
B1
NAME
FUNCTION
TSSOP
1
2
REF
Reference Voltage Input/Output
Buffered Channel A DAC Output
Buffered Channel B DAC Output
Ground
A1
OUTA
OUTB
GND
3
A2
4
B2
5
A3
OUTC
OUTD
Buffered Channel C DAC Output
Buffered Channel D DAC Output
6
A4
7
B4
V
Supply Voltage Input. Bypass V
with a 0.1FF capacitor to GND.
DD
DD
8
—
ADDR1
ADDR0
SCL
I2C Interface Address Selection Bit 1
I2C Interface Address Selection Bit 0
I2C Interface Clock Input
9
C4
C3
C2
C1
B3
10
11
12
13
14
SDA
I2C Bidirectional Serial Data
Active-Low Clear Input
CLR
V
Digital Interface Power-Supply Input
Load DAC. Active-low hardware load DAC input.
DDIO
—
LDAC
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 13
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
loaded into the DAC registers. The CODE register can be
updated using both CODE and CODE_LOAD user com-
Detailed Description
mands. The contents of the DAC register hold the current
DAC output settings. The DAC register can be updated
directly from the serial interface using the CODE_LOAD
commands or can upload the current contents of the
CODE register using LOAD commands or the LDAC
hardware pin.
The MAX5813/MAX5814/MAX5815 are 4-channel, low-
power, 8-/10-/12-bit buffered voltage-output DACs. The
2.7V to 5.5V wide supply voltage range and low-power
consumption accommodates most low-power and low-
voltage applications. The devices present a 100kI load
to the external reference. The internal output buffers
allow rail-to-rail operation. An internal voltage reference
is available with software selectable options of 2.048V,
2.5V, or 4.096V. The devices feature a fast 400kHz I2C-
compatible interface. The MAX5813/MAX5814/MAX5815
include a serial-in/parallel-out shift register, internal
CODE and DAC registers, a power-on-reset (POR) cir-
cuit to initialize the DAC outputs to code zero, and con-
trol logic. CLR is available to asynchronously clear the
device independent of the serial interface.
The contents of both CODE and DAC registers are main-
tained during power-down states, so that when the DACs
are powered on, they return to their previously stored
output settings. Any CODE or LOAD commands issued
during power-down states continue to update the register
contents. SW_CLEAR and SW_RESET commands reset
the contents of all CODE and DAC registers to their zero-
scale defaults.
Internal Reference
The MAX5813/MAX5814/MAX5815 include an internal
precision voltage reference that is software selectable
to be 2.048V, 2.500V, or 4.096V. When an internal refer-
ence is selected, that voltage is available on the REF pin
for other external circuitry (see Figure 9) and can drive
a 25kI load.
DAC Outputs (OUT_)
The MAX5813/MAX5814/MAX5815 include internal buf-
fers on all DAC outputs. The internal output buffers
provide improved load regulation for the DAC outputs.
The output buffers slew at 1V/Fs (typ) and drive up to
2kI in parallel with 500pF. The analog supply voltage
(V ) determines the maximum output voltage range
DD
External Reference
The external reference input has a typical input
impedance of 100kI and accepts an input voltage
of the devices as V
powers the output buffer. Under
DD
no-load conditions, the output buffers drive from GND to
, subject to offset and gain errors. With a 2kω load to
V
DD
from +1.24V to V . Connect an external voltage
DD
GND, the output buffers drive from GND to within 200mV
of V . With a 2kω load to V , the output buffers drive
supply between REF and GND to apply an exter-
nal reference. The MAX5813/MAX5814/MAX5815
power up and reset to external reference mode. Visit
www.maxim-ic.com/products/references for a list of
available external voltage-reference devices.
DD
DD
DD
to within 200mV of GND and V
.
The DAC ideal output voltage is defined by:
D
V
= V ×
REF
OUT
N
2
Load DAC (LDAC) Input
The MAX5813/MAX5814/MAX5815 feature an active-
low LDAC logic input that allows the outputs to update
where D = code loaded into the DAC register, V
reference voltage, N = resolution.
=
REF
asynchronously. Connect LDAC to V
or keep LDAC
DDIO
Internal Register Structure
The user interface is separated from the DAC logic to
minimize digital feedthrough. Within the serial interface
is an input shift register, the contents of which can be
routed to control registers, individual, or multiple DACs
as determined by the user command.
high during normal operation when the device is con-
trolled only through the serial interface. Drive LDAC low
to simultaneously update the DAC outputs with data
from the CODE registers. Holding LDAC low causes the
DAC registers to become transparent and CODE data is
passed through to the DAC registers immediately updat-
ing the DAC outputs. A software CONFIG command can
be used to configure the LDAC operation of each DAC
independently.
Within each DAC channel there is a CODE register
followed by a DAC latch register (see the Detailed
Functional Diagram). The contents of the CODE register
hold pending DAC output settings which can later be
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 14
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
Figure 2
Clear Input (CLR)
The MAX5813/MAX5814/MAX5815 feature an asynchro-
nous active-low CLR logic input that simultaneously sets
all four DAC outputs to zero. Driving CLR low clears the
contents of both the CODE and DAC registers and also
aborts the on-going I2C command. To allow a new I2C
S
Sr
P
SCL
SDA
command, drive CLR high, satisfying the t
timing
CLRSTA
requirement.
Interface Power Supply (V
)
DDIO
The MAX5813/MAX5814/MAX5815 feature a separate
supply pin (V ) for the digital interface (1.8V to 5.5V).
VALID START, REPEATED START, AND STOP PULSES
DDIO
Connect V
to the I/O supply of the host processor.
DDIO
I2C Serial Interface
The MAX5813/MAX5814/MAX5815 feature an I2C-/
SMBusK-compatible, 2-wire serial interface consisting of
a serial data line (SDA) and a serial clock line (SCL). SDA
and SCL enable communication between the MAX5813/
MAX5814/MAX5815 and the master at clock rates up
to 400kHz. Figure 1 shows the 2-wire interface timing
diagram. The master generates SCL and initiates data
transfer on the bus. The master device writes data to the
MAX5813/MAX5814/MAX5815 by transmitting the proper
slave address followed by the command byte and then
the data word. Each transmit sequence is framed by a
START (S) or Repeated START (Sr) condition and a STOP
(P) condition. Each word transmitted to the MAX5813/
MAX5814/MAX5815 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX5813/MAX5814/MAX5815 must transmit the
proper slave address followed by a series of nine SCL
pulses for each byte of data requested. The MAX5813/
MAX5814/MAX5815 transmit data on SDA in sync with
the master-generated SCL pulses. The master acknowl-
edges receipt of each byte of data. Each read sequence
is framed by a START or Repeated START condition, a
not acknowledge, and a STOP condition. SDA operates
as both an input and an open-drain output. A pullup
resistor, typically 4.7kI is required on SDA. SCL oper-
ates only as an input. A pullup resistor, typically 4.7kI, is
required on SCL if there are multiple masters on the bus,
or if the single master has an open-drain SCL output.
P
S
S
P
P
S
P
INVALID START/STOP PULSE PAIRINGS -ALL WILL BE RECOGNIZED AS STARTS
Figure 2. I2C START, Repeated START, and STOP Conditions
signals. The MAX5813/MAX5814/MAX5815 can accom-
modate bus voltages higher than V
up to a limit of
are not recommend-
DDIO
5.5V; bus voltages lower than V
DDIO
ed and may result in significantly increased interface cur-
rents. The MAX5813/MAX5814/MAX5815 digital inputs
are double buffered. Depending on the command issued
through the serial interface, the CODE register(s) can
be loaded without affecting the DAC register(s) using
the write command. To update the DAC registers, either
drive the LDAC input low to asynchronously update all
DAC outputs, or use the software LOAD command.
I2C START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A mas-
ter initiates communication by issuing a START condition.
A START condition is a high-to-low transition on SDA with
SCL high. A STOP condition is a low-to-high transition
on SDA while SCL is high (Figure 2). A START condition
from the master signals the beginning of a transmission
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the MAX5813/
MAX5814/MAX5815 from high voltage spikes on the bus
lines and minimize crosstalk and undershoot of the bus
SMBus is a trademark of Intel Corp.
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 15
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
to the MAX5813/MAX5814/MAX5815. The master termi-
nates transmission and frees the bus, by issuing a STOP
CLOCK PULSE
START
FOR
condition. The bus remains active if a Repeated START
condition is generated instead of a STOP condition.
CONDITION
ACKNOWLEDGMENT
I2C Early STOP and
Repeated START Conditions
SCL
1
2
9
NOT ACKNOWLEDGE
The MAX5813/MAX5814/MAX5815 recognize a STOP
condition at any point during data transmission except
if the STOP condition occurs in the same high pulse as
a START condition. Transmissions ending in an early
STOP condition will not impact the internal device set-
tings. If the STOP occurs during a readback byte, the
transmission is terminated and a later read mode request
will begin transfer of the requested register data from
the beginning (this applies to combined format I2C read
mode transfers only, interface verification mode transfers
will be corrupted). See Figure 2.
SDA
ACKNOWLEDGE
Figure 3. I2C Acknowledge
2
Table 1. I C Slave Address LSBs for
TSSOP Package
TSSOP PACKAGE (A[6:4] = 001)
I2C Slave Address
The slave address is defined as the seven most sig-
nificant bits (MSBs) followed by the R/W bit. See
Figure 4. For the TSSOP packages, the three most signifi-
cant bits are 001 with the 4 LSBs determined by ADDR1
and ADDR0 as shown in Table 1. For the WLP package,
the five most significant bits are 00011 with the 2 LSBs
determined by ADDR0 as shown in Table 2. Setting
the R/W bit to 1 configures the MAX5813/MAX5814/
MAX5815 for read mode. Setting the R/W bit to 0 config-
ures the MAX5813/MAX5814/MAX5815 for write mode.
The slave address is the first byte of information sent
to the MAX5813/MAX5814/MAX5815 after the START
condition.
ADDR1
ADDR0
A3
0
A2
0
A1
0
A0
0
V
V
V
V
DDIO
DDIO
DDIO
DDIO
N.C.
0
0
1
0
GND
0
0
1
1
N.C.
N.C.
N.C.
GND
GND
GND
V
DDIO
N.C.
1
0
0
0
1
0
1
0
GND
1
0
1
1
V
DDIO
N.C.
1
1
0
0
1
1
1
0
GND
1
1
1
1
The MAX5813/MAX5814/MAX5815 have the ability to
detect an unconnected state on the ADDR input for
additional address flexibility; if leaving the ADDR input
unconnected, be certain to minimize all loading on the
pin (i.e. provide a landing for the pin, but do not allow
any board traces).
2
Table 2. I C Slave Address LSBs for WLP
Package
WLP PACKAGE (A[6:2] = 00011)
ADDR0
A1
0
A0
0
V
DDIO
I2C Broadcast Address
A broadcast address is provided for the purpose of
updating or configuring all MAX5813/MAX5814/MAX5815
devices on a given I2C bus. All MAX5813/MAX5814/
MAX5815 devices acknowledge and respond to the
broadcast device address 00010000. The devices will
respond to the broadcast address, regardless of the
state of the address pins. The broadcast mode is intend-
ed for use in write mode only (as indicated by R/W = 0 in
the address given).
N.C.
1
0
GND
1
1
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 16
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
I2C Acknowledge
In write mode, the acknowledge bit (ACK) is a clocked 9th
bit that the MAX5813/MAX5814/MAX5815 use to hand-
shake receipt of each byte of data as shown in Figure 3.
The MAX5813/MAX5814/MAX5815 pull down SDA during
the entire master-generated 9th clock pulse if the previous
byte is successfully received. Monitoring ACK allows for
detection of unsuccessful data transfers. An unsuccessful
data transfer occurs if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccess-
ful data transfer, the bus master will retry communication.
bytes. The data bytes are stored in a temporary register
and then transferred to the appropriate register during
the ACK periods between bytes. This avoids any glitch-
ing or digital feedthrough to the DACs while the interface
is active.
I2C Write Operations
A master device communicates with the MAX5813/
MAX5814/MAX5815 by transmitting the proper slave
address followed by command and data words. Each
transmit sequence is framed by a START or Repeated
START condition and a STOP condition as described
above. Each word is 8 bits long and is always followed
by an acknowledge clock (ACK) pulse as shown in the
Figure 4 and Figure 5. The first byte contains the address
of the MAX5813/MAX5814/MAX5815 with R/W = 0 to
indicate a write. The second byte contains the register
(or command) to be written and the third and fourth bytes
contain the data to be written. By repeating the register
address plus data pairs (Byte #2 through Byte #4 in
Figure 4 and Figure 5), the user can perform multiple
register writes using a single I2C command sequence.
There is no limit as to how many registers the user can
write with a single command. The MAX5813/MAX5814/
MAX5815 support this capability for all user-accessible
write mode commands.
In read mode, the master pulls down SDA during the
9th clock cycle to acknowledge receipt of data from the
MAX5813/MAX5814/MAX5815. An acknowledge is sent
by the master after each read byte to allow data transfer
to continue. A not-acknowledge is sent when the master
reads the final byte of data from the MAX5813/MAX5814/
MAX5815, followed by a STOP condition.
I2C Command Byte and Data Bytes
A command byte follows the slave address. A command
byte is typically followed by two data bytes unless it is
the last byte in the transmission. If data bytes follow the
command byte, the command byte indicates the address
of the register that is to receive the following two data
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
WRITE ADDRESS
2
BYTE #1: I C SLAVE ADDRESS*
START
STOP
SDA
SCL
0
0
1
A3 A2 A1 A0 W
A
23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 A
COMMAND EXECUTED
ACK. GENERATED BY MAX5813/MAX5814/MAX5815
A
2
*I C SLAVE ADDRESS FOR THE TSSOP PACKAGE IS USED
Figure 4. I2C Single Register Write Sequence
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 17
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
WRITE COMMAND1
BYTE #2: COMMAND1 BYTE
(B[23:16])
WRITE DATA1
BYTE #3: DATA1 HIGH BYTE
(B[15:8])
WRITE DATA1
BYTE #4: DATA1 LOW BYTE
(B[7:0])
WRITE ADDRESS
BYTE #1: I C SLAVE ADDRESS*
2
START
23 22 21 20 19 18 17 16
0
0
1
A3 A2 A1 A0 W
A
A
15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 A
SDA
SCL
COMMAND1
EXECUTED
ADDITIONAL COMMAND AND
DATA PAIRS (3 BYTE BLOCKS)
BYTE #7: DATAn LOW BYTE
(B[7:0])
BYTE #5: COMMANDn BYTE
(B[23:16])
BYTE #6: DATAn HIGH BYTE
(B[15:8])
STOP
23 22 21 20 19 18 17 16
A
15 14 13 12 11 10
9
8
A
7
6
5
4
3 2 1 0 A
COMMANDn
EXECUTED
ACK. GENERATED BY MAX5813/MAX5814/MAX5815
A
2
*I C SLAVE ADDRESS FOR THE TSSOP PACKAGE IS USED
Figure 5. Multiple Register Write Sequence (Standard I2C Protocol)
WRITE ADDRESS
BYTE #1: I C SLAVE
WRITE COMMAND 1
BYTE #2: COMMAND 1
BYTE
READ ADDRESS
BYTE #3: I C SLAVE
READ DATA
BYTE #4: DATA 1 HIGH
BYTE (B[15:8])
READ DATA
BYTE #5: DATA 1 LOW
BYTE (B[7:0])
2
2
REPEATED
START
ADDRESS*
ADDRESS*
START
STOP
0
0
1
A3 A2 A1 A0
W
A
0
0
N
N
N
N
N
N
A
0
0
~A
1 A3 A2 A1 A0 R A D D D D D D D D A D D D D D D D D
SDA
SCL
2
ACK. GENERATED BY I C MASTER
A
A
ACK. GENERATED BY MAX5813/MAX5814/MAX5815
2
*I C SLAVE ADDRESS FOR THE TSSOP PACKAGE IS USED
Figure 6. Standard I2C Register Read Sequence
Combined Format I2C Readback Operations
Each readback sequence is framed by a START or
Repeated START condition and a STOP condition. Each
word is 8 bits long and is followed by an acknowledge
clock pulse as shown in Figure 6. The first byte contains
the address of the MAX5813/MAX5814/MAX5815 with
R/W = 0 to indicate a write. The second byte contains
the register that is to be read back. There is a Repeated
START condition, followed by the device address with
R/W = 1 to indicate a read and an acknowledge clock.
The master has control of the SCL line but the MAX5813/
MAX5814/MAX5815 take over the SDA line. The final two
bytes in the frame contain the register data readback
followed by a STOP condition. If additional bytes beyond
those required to readback the requested data are pro-
vided, the MAX5813/MAX5814/MAX5815 will continue to
readback ones.
Readback of individual CODE registers is supported for
the CODE command (B[23:20] = 0000). For this com-
mand, which supports a DAC address, the requested
channel CODE register content will be returned; if all
DACs are selected, CODEA content will be returned.
Readback of individual DAC registers is supported for
all LOAD commands (B[23:20] = 0001, 0010, or 0011).
For these commands, which support a DAC address, the
requested DAC register content will be returned. If all
DACs are selected, DACA content will be returned.
Modified readback of the POWER register is supported
for the POWER command (B[23:20] = 0100). The power
status of each DAC is reported in locations B[3:0], with a
1 indicating the DAC is powered down and a 0 indicating
the DAC is operational (see Table 3).
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 18
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
Readback of all other registers is not directly supported.
All requests to read unsupported registers reads back
the device’s reference status and the device ID and revi-
sion information in the format as shown in Table 3.
MAX5814/MAX5815. The master still has control of the
SCL line but the MAX5813/MAX5814/MAX5815 take over
the SDA line. The final three bytes in the frame contain
the command and register data written in the first transfer
presented for readback, followed by a STOP condition. If
additional bytes beyond those required to read back the
requested data are provided, the MAX5813/MAX5814/
MAX5815 will continue to read back ones.
Interface Verification I2C
Readback Operations
While the MAX5813/MAX5814/MAX5815 support stan-
dard I2C readback of selected registers, it is also
capable of functioning in an interface verification mode.
This mode is accessed any time a readback operation
follows an executed write mode command. In this mode,
the last executed three-byte command is read back in its
entirety. This behavior allows verification of the interface.
It is not necessary for the write and read mode transfers
to occur immediately in sequence. I2C transfers involv-
ing other devices do not impact the MAX5813/MAX5814/
MAX5815 readback mode. Toggling between readback
modes is based on the length of the preceding write
mode transfer. Combined format I2C readback operation
is resumed if a write command greater than two bytes
but less than four bytes is supplied. For commands writ-
ten using multiple register write sequences, only the last
command executed is read back. For each command
written, the readback sequence can only be completed
one time; partial and/or multiple attempts to readback
executed in succession will not yield usable data.
Sample command sequences are shown in Figure 7.
The first command transfer is given in write mode with
R/W = 0 and must be run to completion to qualify for
interface verification readback. There is now a STOP/
START pair or Repeated START condition required, fol-
lowed by the readback transfer with R/W = 1 to indicate
a read and an acknowledge clock from the MAX5813/
2
Table 3. Standard I C User Readback Data
COMMAND BYTE (REQUEST)
READBACK DATA HIGH BYTE
READBACK DATA LOW BYTE
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
1
1
0
1
0
1
0
0
0
0
1
DAC selection
DAC selection
DAC selection
DAC selection
CODEn[11:4]
DACn[11:4]
DACn[11:4]
DACn[11:4]
CODEn[3:0]
DACn[3:0]
DACn[3:0]
DACn[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
0
0
1
1
X
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
PWD PWC PWB PWA
CODEA[11:4]
DACA[11:4]
DACA[11:4]
DACA[11:4]
CODEA[3:0]
DACA[3:0]
DACA[3:0]
DACA[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Any other command (TSSOP)
Any other command (WLP)
1111 1000
1001 1000
000
000
REV_ID[2:0] REF MODE
(010)
RF[1:0]
Table 4. Format DAC Data Bit Positions
PART
B15 B14 B13 B12 B11 B10
B9
D1
D3
D5
B8
D0
D2
D4
B7
x
B6
x
B5
B4
x
B3
x
B2
x
B1
x
B0
x
MAX5813
MAX5814
MAX5815
D7
D9
D6
D8
D5
D7
D9
D4
D6
D8
D3
D5
D7
D2
D4
D6
x
x
D1
D3
D0
D2
x
x
x
x
x
D11 D10
D1
D0
x
x
x
x
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 19
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
WRITE ADDRESS
BYTE #1: I C SLAVE ADDRESS*
2
START
STOP
7
6
5
4
3
2
1
0 A
0
0
1
A3 A2 A1 A0
W
A
23 22 21 20 19 18 17 16
A
15 14 13 12 11 10
9
8
A
SDA
SCL
POINTER UPDATED
(QUALIFIES FOR COMBINED READ BACK)
COMMAND EXECUTED
(QUALIFIES FOR INTERFACE READ BACK)
READ COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
READ DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
READ DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
WRITE ADDRESS
2
BYTE #1: I C SLAVE ADDRESS*
START
STOP
0
0
1
A3 A2 A1 A0
R
A
23 22 21 20 19 18 17 16
A
15 14 13 12 11 10
9
8
A
7
6
5
4
3
2
1
0 ~A
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
WRITE ADDRESS
2
REPEATED
START
BYTE #1: I C SLAVE ADDRESS*
START
0
0
1
A3 A2 A1 A0
W
A
23 22 21 20 19 18 17 16
A
15 14 13 12 11 10
9
8
A
7
6
5
4
3
2
1
0
A
SDA
SCL
POINTER UPDATED
(QUALIFIES FOR COMBINED READ BACK)
COMMAND EXECUTED
(QUALIFIES FOR INTERFACE READ BACK)
READ COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
READ DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
READ DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
WRITE ADDRESS
2
BYTE #1: I C SLAVE ADDRESS*
STOP
0
0
1
A3 A2 A1 A0
R
A
23 22 21 20 19 18 17 16
A
15 14 13 12 11 10
9
8
A
7
6
5
4
3
2
1
0 ~A
2
ACK. GENERATED BY I C MASTER
ACK. GENERATED BY MAX5813/MAX5814/MAX5815
A
A
2
*I C SLAVE ADDRESS FOR THE TSSOP PACKAGE IS USED
Figure 7. Interface Verification I2C Register Read Sequences
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 20
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
LOADn Command
µC
The LOADn command (B[23:20] = 0001) updates the
SDA
SCL
DAC register content for the selected DAC(s) by upload-
ing the current contents of the CODE register. The
LOADn command can be used with DAC SELECTION =
ALL DACs to issue a software load for all DACs, which
is equivalent to the LOAD_ALL (B[23:16] = 10000001)
command. See Table 5 and Table 6.
MAX5813
MAX5814
MAX5815
SCL
SDA
ADDR0
CODEn_LOAD_ALL Command
The CODEn_LOAD_ALL command (B[23:20] = 0010)
updates the CODE register contents for the selected
DAC(s) as well as the DAC register content of all DACs.
Channels for which the CODE register content has not
been modified since the last load to DAC register or LDAC
operation will not be updated to reduce digital crosstalk.
Issuing this command with DAC_ADDRESS = ALL is
equivalent to the CODE_ALL_LOAD_ALL command. The
CODEn_LOAD_ALL command by definition will modify at
least one CODE register. To avoid this, use the LOADn
command with DAC SELECTION = ALL DACs or use the
LOAD_ALL command. See Table 5 and Table 6.
(ADDR1)
MAX5813
MAX5814
MAX5815
+5V
SCL
SDA
ADDR0
(ADDR1)
( ) TSSOP PACKAGE ONLY
CODEn_LOADn Command
The CODEn_LOADncommand (B[23:20] = 0011)updates
the CODE register contents for the selected DAC(s) as
well as the DAC register content of the selected DAC(s).
Channels for which the CODE register content has not
been modified since the last load to DAC register or
LDAC operation will not be updated to reduce digital
crosstalk. Issuing this command with DAC SELECTION
= ALL DACs is equivalent to the CODE_ALL_LOAD_ALL
command. See Table 5 and Table 6.
Figure 8. Typical I2C Application Circuit
I2C Compatibility
The MAX5813/MAX5814/MAX5815 are fully compatible
with existing I2C systems. SCL and SDA are high-imped-
ance inputs; SDA has an open drain which pulls the data
line low to transmit data or ACK pulses. Figure 8 shows a
typical I2C application.
I2C User-Command Register Map
This section lists the user accessible commands and
registers for the MAX5813/MAX5814/MAX5815.
CODE_ALL Command
The CODE_ALL command (B[23:16] = 10000000)
updates the CODE register contents for all DACs. See
Table 5.
Table 5 provides detailed information about the Command
Registers.
LOAD_ALL Command
The LOAD_ALL command (B[23:16] = 10000001) updates
the DAC register content for all DACs by uploading the
current contents of the CODE registers. See Table 5.
CODEn Command
The CODEn command (B[23:20] = 0000) updates the
CODE register contents for the selected DAC(s). Changes
to the CODE register content based on this command will
not affect DAC outputs directly unless the LDAC is in a
low state or the DAC latch has been configured to be
transparent. Issuing the CODEn command with DAC
SELECTION = ALL DACs is equivalent to CODE_ALL
(B[23:16] = 10000000). See Table 5 and Table 6.
CODE_ALL_LOAD_ALL Command
The CODE_ALL_LOAD_ALL command (B[23:16] =
1000001x) updates the CODE register contents for all
DACs as well as the DAC register content of all DACs.
See Table 5.
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 21
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 22
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
D A C A
D A C B
D A C C
D A C D
L D _ E N
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 23
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
Table 6. DAC Selection
B19
0
B18
0
B17
0
B16
0
DAC SELECTED
DAC A
0
0
0
1
DAC B
0
0
1
0
DAC C
0
0
1
1
DAC D
X
1
X
X
ALL DACs
ALL DACs
1
X
X
X
ers up. The serial interface remains active in power-down
mode.
POWER Command
The MAX5813/MAX5814/MAX5815 feature a software-
controlled power-mode (POWER) command (B[23:20] =
0100). The POWER command updates the power-mode
settings of the selected DACs while the power settings of
the rest of the DACs remain unchanged. The new power
setting is determined by bits B[17:16] while the affected
DAC(s) are selected by bits B[11:8]. If all DACs are pow-
ered down, the device enters a STANDBY mode.
In STANDBY mode, the internal reference can be pow-
ered down or it can be set to remain powered-on for
external use. Also, in STANDBY mode, devices using the
external reference do not load the REF pin. See Table 7.
SW_RESET and SW_CLEAR Command
The SW_RESET (B[23:16] = 01010001) and SW_CLEAR
(B[23:16] = 01010000) commands provide a means of
issuing a software reset or software clear operation. Use
SW_CLEAR to issue a software clear operation to return
all CODE and DAC registers to the zero-scale value. Use
SW_RESET to reset all CODE, DAC, and configuration
registers to their default values.
In power-down, the DAC output is disconnected from the
buffer and is grounded with either one of the two select-
able internal resistors or set to high impedance. See Table
8 for the selectable internal resistor values in power-down
mode. In power-down mode, the DAC register retains its
value so that the output is restored when the device pow-
Table 7. POWER (100) Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
1
0
0
0
0
PD1 PD0
X
X
X
X
D
C
B
A
X
X
X
X
X
X
X
X
Power
Mode:
00 =
DAC Select:
Normal
01 = 1kI
10 =
1 = DAC Selected
0 = DAC Not
Selected
POWER Command
Don’t Care
Don’t Care
100kI
11 = Hi-Z
0
0
X
X
X
X
1
1
1
1
X
X
X
X
X
X
X
X
Default Values (all DACs) ➝
Table 8. Selectable DAC Output Impedance in Power-Down Mode
PD1 (B17)
PD0 (B16)
OPERATING MODE
0
0
1
1
0
1
0
1
Normal operation
Power-down with internal 1kI pulldown resistor to GND.
Power-down with internal 100kI pulldown resistor to GND.
Power-down with high-impedance output.
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 24
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
or 11 to select either the 2.5V, 2.048V, or 4.096V internal
reference, respectively.
CONFIG Command
The CONFIG command (B[23:19] = 0100) updates the
LDAC and LOAD functions of selected DACs. Issue the
command with B16 = 0 to allow the DAC latches to oper-
ate normally or with B16 = 1 to disable the DAC latches,
making them perpetually transparent. Mode settings of
the selected DACs are updated while the mode settings
of the rest of the DACs remain unchanged; DAC(s) are
selected by bits B[11:8]. See Table 9.
If RF2 (B18) is set to zero (default) in the REF command,
the reference will be powered down any time all DAC
channels are powered down (in STANDBY mode). If RF2
(B18 = 1) is set to one, the reference will remain powered
even if all DAC channels are powered down, allowing
continued operation of external circuitry. In this mode,
the 1FA shutdown state is not available. See Table 10.
REF Command
The REF command updates the global reference setting
used for all DAC channels. Set B[17:16] = 00 to use an
external reference for the DACs or set B[17:16] to 01, 10,
Table 9. CONFIG Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
1
1
0
0
0
0
LDB
X
X
X
X
D
C
B
A
X
X
X
X
X
X
X
X
DAC Select:
1 = DAC Selected
0 = DAC Not
Selected
CONFIG Command
Don’t Care
Don’t Care
Default Values (all DACs) ➝
0
X
X
X
X
1
1
1
1
X
X
X
X
X
X
X
X
Table 10. REF Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
X X X X X X
0
1
1
1
0
RF2 RF1 RF0
X
X
X
X
X
X
X
X
X
X
REF Mode:
00 = EXT
01 = 2.5V
10 = 2.0V
11 = 4.0V
REF Command
Don’t Care
Don’t Care
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Default Values ➝
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 25
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height and
Applications Information
the ideal value of 1 LSB. If the magnitude of the DNL P
1 LSB, the DAC guarantees no missing codes and is
monotonic. If the magnitude of the DNL R1 LSB, the DAC
output may still be monotonic.
Power-On Reset (POR)
When power is applied to V
and V
, the DAC out-
DD
DDIO
put is set to zero scale. To optimize DAC linearity, wait
until the supplies have settled and the internal setup and
calibration sequence completes (200Fs, typ).
Offset Error
Offset error indicates how well the actual transfer func-
tion matches the ideal transfer function at a single point.
Typically, the point at which the offset error is specified
is at or near the zero-scale point of the transfer function.
Power Supplies and
Bypassing Considerations
Bypass V
and V
with high-quality ceramic capac-
DD
DDIO
itors to a low-impedance ground as close as possible to
the device. Minimize lead lengths to reduce lead induc-
tance. Connect the GND to the analog ground plane.
Gain Error
Gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Layout Considerations
Digital and AC transient signals on GND can create noise
at the output. Connect GND to form the star ground for
the DAC system. Refer remote DAC loads to this system
ground for the best possible performance. Use proper
grounding techniques, such as a multilayer board with a
low-inductance ground plane, or star connect all ground
return paths back to the MAX5813/MAX5814/MAX5815
GND. Carefully layout the traces between channels to
reduce AC cross-coupling. Do not use wire-wrapped
boards and sockets. Use shielding to minimize noise immu-
nity. Do not run analog and digital signals parallel to one
another, especially clock signals. Avoid routing digital lines
underneath the MAX5813/MAX5814/MAX5815 package.
Settling Time
The settling time is the amount of time required from the
start of a transition, until the DAC output settles to the new
output value within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the amount of noise that appears
on the DAC output when the DAC digital control lines are
toggled.
Digital-to-Analog Glitch Impulse
A major carry transition occurs at the midscale point
where the MSB changes from low to high and all other
bits change from high to low, or where the MSB changes
from high to low and all other bits change from low to
high. The duration of the magnitude of the switching
glitch during a major carry transition is referred to as the
digital-to-analog glitch impulse.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function
from a straight line drawn between two codes once offset
and gain errors have been nullified.
The digital-to-analog power-up glitch is the duration of
the magnitude of the switching glitch that occurs as the
device exits power-down mode.
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 26
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
Detailed Functional Diagram
V
DD
REF
100kI R
IN
MAX5813
MAX5814
MAX5815
INTERNAL /EXTERNAL REFERENCE (USER OPTION)
CODE
REGISTER
A
DAC
LATCH
A
8-/10-/12-BIT
DAC A
OUTA
OUTB
OUTC
OUTD
BUFFER A
CLEAR/
RESET
CLEAR/
RESET
CODE
CODE
CODE
CODE
LOAD
100kI
1kI
1kI
1kI
1kI
POWER-DOWN
DAC CONTROL LOGIC
V
DDIO
CODE
REGISTER
B
DAC
LATCH
B
8-/10-/12-BIT
DAC B
BUFFER B
SCL
SDA
CLEAR/
RESET
CLEAR/
RESET
LOAD
100kI
POWER-DOWN
DAC CONTROL LOGIC
ADDR0
(ADDR1)
CLR
2
I C SERIAL
INTERFACE
CODE
REGISTER
C
DAC
LATCH
C
8-/10-/12-BIT
DAC C
BUFFER C
CLEAR/
RESET
CLEAR/
RESET
(LDAC)
LOAD
100kI
POWER-DOWN
DAC CONTROL LOGIC
POR
CODE
REGISTER
D
DAC
LATCH
D
8-/10-/12-BIT
DAC D
BUFFER D
CLEAR/
RESET
CLEAR/
RESET
LOAD
100kI
POWER-DOWN
DAC CONTROL LOGIC
GND
() TSSOP PACKAGE ONLY
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 27
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
100nF
4.7µF
100µF
R
PU
=
R
PU
=
5kI
5kI
V
DDIO
V
DD
(LDAC)
SDA
OUT
REF
DAC
MICRO-
CONTROLLER
SCL
MAX5813
MAX5814
MAX5815
ADDR0
(ADDR1)
CLR
R1
R2
R1 = R2
GND
( ) TSSOP PACKAGE ONLY
NOTE: ONE CHANNEL SHOWN
Figure 9. Bipolar Operating Circuit
Typical Operating Circuit
100nF
4.7µF
100µF
R
=
R
PU
=
PU
5kI
5kI
V
DDIO
V
DD
(LDAC)
SDA
OUT_
DAC
MICRO-
CONTROLLER
SCL
MAX5813
MAX5814
MAX5815
ADDR0
(ADDR1)
CLR
REF
GND
( ) TSSOP PACKAGE ONLY
NOTE: UNIPOLAR OPERATION (ONE CHANNEL SHOWN)
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 28
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
Ordering Information
PART
PIN-PACKAGE
14 TSSOP
14 TSSOP
14 TSSOP
14 TSSOP
12 WLP
RESOLUTION (BIT)
INTERNAL REFERENCE TEMPCO (ppm/NC)
MAX5813AUD+T*
MAX5814AUD+T*
MAX5815AAUD+T
MAX5815BAUD+T*
MAX5815AWC+T*
8
10 (typ)
10 (typ)
10
12
12
12
3 (typ),10 (max)
10 (typ)
10 (typ)
Note: All devices are specified over the -40°C to +125°C temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*Future product—Contact factory for availability.
Chip Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE PACKAGE OUTLINE
LAND
TYPE
CODE
NO.
PATTERN NO.
14 TSSOP
U14+1
21-0066
90-0113
Refer to
Application Note 1891
12 WLP
W121B2+1
21-0009
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 29
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
2/12
Initial release
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
30
©
2012 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
SI9130DB
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