MAX5895EGK+ [MAXIM]
D/A Converter, 2 Func, Parallel, Word Input Loading, 0.011us Settling Time, 10 X 10 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, MO-220, QFN-68;
| 型号： | MAX5895EGK+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 2 Func, Parallel, Word Input Loading, 0.011us Settling Time, 10 X 10 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, MO-220, QFN-68 |
| 文件： | 总31页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3545; Rev 2; 10/08
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
MAX895
General Description
Features
The MAX5895 programmable interpolating, modulating,
500Msps, dual digital-to-analog converter (DAC) offers
superior dynamic performance and is optimized for
high-performance, wideband single- and multicarrier
transmit applications. The device integrates a selectable
2x/4x/8x interpolating filter, a digital quadrature modula-
tor, and dual 16-bit high-speed DACs on a single IC. At
30MHz output frequency and 500Msps update rate, the
in-band SFDR is 88dBc while consuming 1.1W. The
device also delivers 71dB ACLR for four-carrier WCDMA
at a 61.44MHz output frequency.
o 71dB ACLR at f
= 61.44MHz (Four-Carrier
OUT
WCDMA)
®
o Meets Multicarrier UMTS, cdma2000 , GSM
Spectral Masks (f
= 122MHz)
OUT
o Noise Spectral Density = -158dBFS/Hz at
f
= 16MHz
OUT
o 92dBc SFDR at Low-IF Frequency (10MHz)
o 90dBc SFDR at High-IF Frequency (50MHz)
o Low Power: 511mW (f
o User Programmable
= 100MHz)
CLK
The selectable interpolating filters allow lower input data
rates while taking advantage of the high DAC update
rates. These linear-phase interpolation filters ease
reconstruction filter requirements and enhance the
passband dynamic performance. Individual offset and
gain programmability allow the user to calibrate out local
oscillator (LO) feedthrough and sideband suppression
errors generated by analog quadrature modulators.
Selectable 2x, 4x, or 8x Interpolating Filters
< 0.01dB Passband Ripple
> 99dB Stopband Rejection
Selectable Real or Complex Modulator Operation
Selectable Modulator LO Frequency: OFF, fIM/2, or
fIM/4
Selectable Output Filter: Lowpass or Highpass
Channel Gain and Offset Adjustment
The MAX5895 features a f /4 digital image-reject mod-
IM
o EV Kit Available (Order the MAX5895 EV Kit)
ulator. This modulator generates a quadrature-modulat-
ed IF signal that can be presented to an analog I/Q
modulator to complete the upconversion process. A
second digital modulation mode allows the signal to be
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
frequency-translated with image pairs at f /2 or f /4.
IM
IM
MAX5895EGK-D
MAX5895EGK+D
D = Dry pack.
68 QFN-EP*
The MAX5895 features a standard 1.8V CMOS, 3.3V tol-
erant data input bus for easy interface. A 3.3V SPI™ port
is provided for mode configuration. The programmable
modes include the selection of 2x/4x/8x interpolating fil-
68 QFN-EP*
*EP = Exposed pad.
ters, f /2, f /4 or no digital quadrature modulation with
IM
IM
+Denotes a lead-free/RoHS-compliant package.
image rejection, channel gain and offset adjustment, and
offset binary or two’s complement data interface.
Selector Guide
Pin-compatible 12- and 14-bit devices are also available.
Refer to the MAX5894 data sheet for the 14-bit version
and the MAX5893 data sheet for the 12-bit version.
RESOLUTION DAC UPDATE
INPUT
LOGIC
PART
(BITS)
RATE (Msps)
MAX5893
MAX5894
MAX5895
MAX5898
12
14
16
16
500
500
500
500
CMOS
CMOS
CMOS
LVDS
Applications
Base Stations: 3G Multicarrier UMTS, CDMA, and GSM
Broadband Wireless Transmitters
Broadband Cable Infrastructure
Instrumentation and Automatic Test Equipment (ATE)
Analog Quadrature Modulation Architectures
Simplified Diagram
OUTI
DAC
DATA
PORT A
Pin Configuration appears at end of data sheet.
DATACLK
DATA
PORT B
SPI is a trademark of Motorola, Inc.
cdma2000 is a registered trademark of the Telecommunications
Industry Association.
DAC
OUTQ
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
ABSOLUTE MAXIMUM RATINGS
DV
AV
, AV
, AV
to GND, DACREF ..................-0.3V to +2.16V
DD1.8
SDO, DATACLK, DATACLK/B14 Continuous Current ..........8mA
DD1.8
, DV
to GND, DACREF........-0.3V to +3.9V
Continuous Power Dissipation (T = +70°C)
DD3.3
CLK
DD3.3
A
DATACLK, A0–A15, B0–B13,
SELIQ/B15, DATACLK/B14, CS, RESET, SCLK,
SDI and SDO to GND, DACREF......-0.3V to (DV
CLKP, CLKN to GND, DACREF..............-0.3V to (AV
REFIO, FSADJ to GND, DACREF ........-0.3V to (AV
OUTIP, OUTIN, OUTQP,
68-Pin QFN (derate 41.7mW/°C above +70°C)
(Note 1) ...................................................................3333.3mW
Junction Temperature......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
+ 0.3V)
+ 0.3V)
+ 0.3V)
DD3.3
CLK
DD3.3
OUTQN to GND, DACREF..................-1V to (AV
+ 0.3V)
Thermal Resistance θ (Note 1)....................................0.8°C/W
DD3.3
JC
MAX895
Note 1: Thermal resistance based on a multilayer board with 4 x 4 via array in exposed pad area.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(DV
= AV
= 1.8V, AV
= AV
= DV
= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port
DD3.3
DD1.8
DD1.8
CLK
DD3.3
mode, 50Ω double-terminated outputs, external reference at 1.25V, T = -40°C to +85°C, unless otherwise noted. Typical values are
A
at T = +25°C, unless otherwise noted.) (Note 2)
A
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
16
1
Bits
LSB
LSB
%FS
ppm/°C
%FS
ppm/°C
mA
Differential Nonlinearity
Integral Nonlinearity
Offset Error
DNL
INL
OS
3
-0.025
-4
0.003 +0.025
0.03
Offset Drift
Full-Scale Gain Error
Gain-Error Drift
GE
0.6
+4
FS
110
Full-Scale Output Current
Output Compliance
I
2
20
OUTFS
-0.5
+1.1
V
Output Resistance
R
C
1
5
MΩ
OUT
Output Capacitance
DYNAMIC PERFORMANCE
Maximum Clock Frequency
Minimum Clock Frequency
Maximum DAC Update Rate
Minimum DAC Update Rate
Maximum Input Data Rate
pF
OUT
f
f
500
500
125
MHz
MHz
CLK
1
1
CLK
f
f
f
f
= f
= f
or f
or f
= f
= f
/2
/2
Msps
Msps
MWps
DAC
DAC
DAC
CLK
DAC
DAC
CLK
DAC
CLK
CLK
f
DATA
No interpolation
2x interpolation
4x interpolation
-157
-158
-157
f
f
= 125MHz,
DATACLK
= 16MHz, f
OUT
OFFSET
= 10MHz, -12dBFS
dBFS/
Hz
Noise Spectral Density
f
f
= 125MHz,
DATACLK
= 16MHz, f
4x interpolation
-149
OUT
OFFSET
= 10MHz, 0dBFS
2
_______________________________________________________________________________________
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
MAX895
ELECTRICAL CHARACTERISTICS (continued)
= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port
DD3.3
(DV
= AV
= 1.8V, AV
= AV
= DV
DD1.8
DD1.8
CLK
DD3.3
mode, 50Ω double-terminated outputs, external reference at 1.25V, T = -40°C to +85°C, unless otherwise noted. Typical values are
at T = +25°C, unless otherwise noted.) (Note 2)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
90
MAX
UNITS
f
f
f
f
f
f
f
f
f
= 10MHz
= 30MHz
= 50MHz
= 10MHz
= 30MHz
= 50MHz
= 10MHz
= 30MHz
= 50MHz
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
f
= 125MHz,
interpolation off, 0dBFS
DATACLK
85
73
77
90
In-Band SFDR
(DC to f /2)
f
= 125MHz,
2x interpolation, 0dBFS
DATACLK
SFDR
89
dBc
DATA
86
92
f
= 125MHz,
4x interpolation, 0dBFS
DATACLK
88
90
No interpolation
2x interpolation
4x interpolation
-103
-103
-103
f
f
= 125MHz,
DATACLK
OUT1
= 9MHz, f
=
OUT2
10MHz, -6.1dBFS
2x interpolation,
f
/4 complex
-74
-75
IM
f
f
= 125MHz,
DATACLK
modulation
= 79MHz, f
OUT1
OUT2
4x interpolation,
= 80MHz, -6.1dBFS
f
IM
/4 complex
modulation
Two-Tone IMD
TTIMD
dBc
f
f
= 62.5MHz,
DATACLK
= 9MHz, f
=
8x interpolation
8x interpolation,
-100
-75
OUT1
OUT2
10MHz, -6.1dBFS
f
f
= 62.5MHz,
DATACLK
OUT1
= 69MHz, f
f /4 complex
IM
OUT2
= 70MHz, -6.1dBFS
modulation
8x, highpass
interpolation,
f
f
= 62.5MHz,
DATACLK
= 179MHz, f
-65
-97
OUT1
OUT2
f
IM
/4 complex
= 180MHz, -6.1dBFS
modulation
spaced 1MHz
OUT
f
= 125MHz, f
DATACLK
apart from 32MHz, -12dBFS, 2x
interpolation
Four-Tone IMD
FTIMD
ACLR
dBc
4x interpolation
8x interpolation
80
79
f
f
= 61.44MHz,
= baseband
DATACLK
OUT
f
=
2x interpolation,
f /4 complex
IM
modulation
DATACLK
122.88MHz, f
61.44MHz
=
=
75
69
ACLR for WCDMA
(Note 3)
OUT
dB
f
=
4x interpolation,
f /4 complex
IM
modulation
DATACLK
122.88MHz, f
122.88MHz
OUT
_______________________________________________________________________________________
3
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
ELECTRICAL CHARACTERISTICS (continued)
= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port
DD3.3
(DV
= AV
= 1.8V, AV
= AV
= DV
DD1.8
DD1.8
CLK
DD3.3
mode, 50Ω double-terminated outputs, external reference at 1.25V, T = -40°C to +85°C, unless otherwise noted. Typical values are
at T = +25°C, unless otherwise noted.) (Note 2)
A
A
PARAMETER
SYMBOL
CONDITIONS
1x interpolation (Note 4)
MIN
TYP
MAX
UNITS
Output Propagation Delay
Output Rise Time
t
2.9
0.75
1.0
ns
ns
PD
t
10% to 90% (Note 5)
10% to 90% (Note 5)
To 0.5% (Note 5)
RISE
Output Fall Time
t
ns
FALL
MAX895
Output Settling Time
Output Bandwidth
11
ns
-1dB bandwidth (Note 6)
240
MHz
0.4 x
Passband Width
Ripple < -0.01dB
f
DATA
100
100
100
22
0.604 x f
0.604 x f
0.604 x f
, 2x interpolation
, 4x interpolation
, 8x interpolation
DATA
DATA
DATA
Stopband Rejection
dB
1x interpolation
2x interpolation
4x interpolation
8x interpolation
70
Clock
Cycles
Data Latency
146
311
DAC INTERCHANNEL MATCHING
Gain Match
∆Gain
∆Gain/°C
∆Phase
f
I
f
f
I
f
= DC - 80MHz, I
= 20mA
0.1
0.02
0.13
0.006
0.04
-95
dB
ppm/°C
Deg
OUT
OUTFS
Gain-Match Tempco
Phase Match
= 20mA
OUTFS
= 60MHz, I
= 60MHz, I
= 20mA
OUT
OUTFS
Phase-Match Tempco
DC Gain Match
∆Phase/°C
= 20mA
Deg/°C
dB
OUT
OUTFS
= 20mA
-0.2
+0.2
OUTFS
Channel-to-Channel Crosstalk
REFERENCE
= 50MHz, f
= 250MHz, 0dBFS
dB
OUT
DAC
Reference Input Range
Reference Output Voltage
Reference Input Resistance
Reference Voltage Drift
0.125
1.14
1.250
1.27
V
V
V
Internal reference
1.20
10
REFIO
R
kΩ
REFIO
50
ppm/°C
CMOS LOGIC INPUT/OUTPUT (A15–A0, SELIQ/B15, DATACLK/B14, B13–B0, DATACLK)
0.7 x
Input High Voltage
Input Low Voltage
V
V
V
IH
DV
DD1.8
0.3 x
V
IL
DV
DD1.8
Input Current
I
1
3
20
µA
pF
IN
Input Capacitance
C
IN
4
_______________________________________________________________________________________
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
MAX895
ELECTRICAL CHARACTERISTICS (continued)
= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port
DD3.3
(DV
= AV
= 1.8V, AV
= AV
= DV
DD1.8
DD1.8
CLK
DD3.3
mode, 50Ω double-terminated outputs, external reference at 1.25V, T = -40°C to +85°C, unless otherwise noted. Typical values are
at T = +25°C, unless otherwise noted.) (Note 2)
A
A
PARAMETER
Output High Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.8 x
V
200µA load
V
OH
DV
DD3.3
0.2 x
Output Low Voltage
V
200µA load
Three-state
V
OL
DV
DD3.3
Output Leakage Current
Rise/Fall Time
1
µA
ns
C
= 10pF, 20% to 80%
1.5
LOAD
CLOCK INPUT (CLKP, CLKN)
Sine-wave input
> 1.5
> 0.5
> 100
Differential Input Voltage Swing
V
V
P-P
DIFF
Square-wave input
Differential Input Slew Rate
Common-Mode Voltage
Input Resistance
V/µs
V
V
AC-coupled
AV
/2
COM
CLK
5
R
kΩ
pF
%
CLK
CLK
Input Capacitance
C
3
Minimum Clock Duty Cycle
Maximum Clock Duty Cycle
45
55
%
CLKP/CLKN, DATACLK TIMING (Figure 4, Notes 7, 8)
CLK to DATACLK Delay
t
DATACLK output mode, C
Capturing rising edge
Capturing falling edge
Capturing rising edge
Capturing falling edge
Capturing rising edge
Capturing falling edge
Capturing rising edge
Capturing falling edge
= 10pF
LOAD
6.2
ns
ns
D
1.0
2.1
0.4
-0.7
1.0
2.3
0.2
-0.4
Data Hold Time, DATACLK
Input/Output (Pin 14)
t
DH
Data Setup Time, DATACLK
Input/Output (Pin 14)
t
ns
ns
ns
DS
DH
Data Hold Time, DATACLK/B14
Input/Output (Pin 27)
t
Data Setup Time, DATACLK/B14
Input/Output (Pin 27)
t
DS
SERIAL-PORT INTERFACE TIMING (Figure 3, Note 7)
SCLK Frequency
CS Setup Time
f
10
MHz
ns
SCLK
t
2.5
0
SS
Input Hold Time
Input Setup Time
Data Valid Duration
t
ns
SDH
t
t
4.5
6.5
ns
SDS
SDV
16.5
ns
_______________________________________________________________________________________
5
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
ELECTRICAL CHARACTERISTICS (continued)
= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port
DD3.3
(DV
= AV
= 1.8V, AV
= AV
= DV
DD1.8
DD1.8
CLK
DD3.3
mode, 50Ω double-terminated outputs, external reference at 1.25V, T = -40°C to +85°C, unless otherwise noted. Typical values are
at T = +25°C, unless otherwise noted.) (Note 2)
A
A
PARAMETER
POWER SUPPLIES
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Supply Voltage
Digital I/O Supply Voltage
Clock Supply Voltage
DV
DV
1.71
3.0
1.8
3.3
3.3
3.3
1.8
1.89
3.6
V
V
V
DD1.8
DD3.3
MAX895
AV
3.135
3.135
1.71
3.465
3.465
1.89
CLK
AV
DD3.3
DD1.8
Analog Supply Voltage
V
AV
f
f
= 250MHz, 2x interpolation, 0dBFS,
= 10MHz, DATACLK output mode
CLK
I
I
110
27
225
21
3
130
32
250
32
5
AVDD3.3
AVDD1.8
DVDD1.8
DVDD3.3
OUT
Analog Supply Current
mA
f
f
= 250MHz, 2x interpolation, 0dBFS,
= 10MHz, DATACLK output mode
CLK
OUT
f
f
= 250MHz, 2x interpolation, 0dBFS,
= 10MHz, DATACLK output mode
CLK
OUT
Digital Supply Current
I
I
mA
mA
f
f
= 250MHz, 2x interpolation, 0dBFS,
= 10MHz, DATACLK output mode
CLK
OUT
Digital I/O Supply Current
f
f
= 250MHz, 2x interpolation, 0dBFS,
= 10MHz, DATACLK output mode
CLK
OUT
Clock Supply Current
Total Power Dissipation
I
mA
AVCLK
P
511
450
1
mW
TOTAL
AV
AV
DV
DV
AV
DD3.3
DD1.8
DD1.8
DD3.3
CLK
All I/O are static high or
low, bit 2 to bit 4 of
address 00h are set high
Power-Down Current
10
100
1
µA
AV
Ratio
Power-Supply Rejection
DD3.3
PSRR
(Note 9)
0.125
%FS/V
A
Note 2: All specifications are 100% tested at T ≥ +25°C. Specifications at T < +25°C are guaranteed by design and
A
A
characterization data.
Note 3: 3.84MHz bandwidth, single carrier.
Note 4: Excludes data latency.
Note 5: Measured single-ended into a 50Ω load.
Note 6: Excludes sin(x)/x rolloff.
Note 7: Guaranteed by design and characterization.
Note 8: Setup and hold time specifications characterized with 3.3V CMOS logic levels.
Note 9: Parameter defined as the change in midscale output caused by a 5% variation in the nominal supply voltage.
6
_______________________________________________________________________________________
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
MAX895
Typical Operating Characteristics
(DV
= AV
= 1.8V, AV
= AV
= DV
= 3.3V, modulator off, 2x interpolation, output is transformer-coupled to
DD3.3
DD1.8
DD1.8
CLK
DD3.3
50Ω load, T = +25°C, unless otherwise noted.)
A
SFDR vs. OUTPUT FREQUENCY
0UT-OF-BAND SFDR vs. OUTPUT FREQUENCY
IN-BAND SFDR vs. OUTPUT FREQUENCY
f
= 125MWps, NO INTERPOLATION
f
= 125MWps, 2x INTERPOLATION
f
= 125MWps, 2x INTERPOLATION
DATA
DATA
DATA
120
100
80
60
40
20
0
100
90
80
70
60
50
40
30
20
10
0
120
100
80
60
40
20
0
-0.1dBFS
-6dBFS
-0.1dBFS
-6dBFS
-0.1dBFS
-6dBFS
-12dBFS
-12dBFS
-0.1dBFS
-12dBFS
SPURS MEASURED BETWEEN
62.5MHz AND 125MHz
SPURS MEASURED BETWEEN
0MHz AND 62.5MHz
0
10
20
30
40
50
60
0
10
20
30
40
50
0
10
20
30
40
50
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
IN-BAND SFDR vs. OUTPUT FREQUENCY
IN-BAND SFDR vs. OUTPUT FREQUENCY
OUT-OF-BAND SFDR vs. OUTPUT FREQUENCY
f
= 125MWps, 4x INTERPOLATION
f
= 125MWps, 2x INTERPOLATION
DATA
f
= 125MWps, 4x INTERPOLATION
DATA
DATA
120
100
80
60
40
20
0
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
-6dBFS
-6dBFS
-0.1dBFS
-0.1dBFS
-6dBFS
-0.1dBFS
-12dBFS
-12dBFS
-12dBFS
UPPER SIDEBAND MODULATION
SPURS MEASURED BETWEEN
62.5MHz AND 125MHz
SPURS MEASURED BETWEEN
0MHz AND 62.5MHz
SPURS MEASURED BETWEEN
62.5MHz AND 250MHz
0
10
20
30
40
50
62.5
72.5
82.5
92.5
102.5
112.5
0
10
20
30
40
50
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
IN-BAND SFDR vs. OUTPUT FREQUENCY
IN-BAND SFDR vs. OUTPUT FREQUENCY
TWO-TONE IMD vs. OUTPUT FREQUENCY
f
= 125MWps, 4x INTERPOLATION
f
= 125MWps, 4x INTERPOLATION
f
= 125MWps, NO INTERPOLATION
DATA
DATA
DATA
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
120
100
80
60
40
20
0
-0.1dBFS
-12dBFS
-6dBFS
-0.1dBFS
-9dBFS
-6dBFS
-6dBFS
-12dBFS
-12dBFS
UPPER SIDEBAND MODULATION
SPURS MEASURED BETWEEN
62.5MHz AND 187.5MHz
LOWER SIDEBAND MODULATION
SPURS MEASURED BETWEEN
62.5MHz AND 125MHz
1MHz CARRIER SPACING
75
85
95
105
115
125
125
135
145
155
165
175
0
10
20
30
40
50
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
CENTER FREQUENCY (MHz)
_______________________________________________________________________________________
7
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
Typical Operating Characteristics (continued)
(DV
= AV
= 1.8V, AV
= AV
= DV
= 3.3V, modulator off, 2x interpolation, output is transformer-coupled to
DD3.3
DD1.8
DD1.8
CLK
DD3.3
50Ω load, T = +25°C, unless otherwise noted.)
A
TWO-TONE IMD vs. OUTPUT FREQUENCY
TWO-TONE IMD vs. OUTPUT FREQUENCY
GAIN MISMATCH vs. TEMPERATURE
f
= 125MWps, NO INTERPOLATION
f
= 125MWps, 4x INTERPOLATION
f
= 125MWps, 2x INTERPOLATION
DATA
DATA
DATA
120
100
80
60
40
20
0
120
90
60
30
0
0.100
0.075
0.050
0.025
0
-6dBFS
-12dBFS
f
A
= 22.7MHz
= -6dBFS
OUT
OUT
-12dBFS
MAX895
-9dBFS
-6dBFS
-9dBFS
1MHz CARRIER SPACING
COMPLEX MODULATION FOR
OUTPUT FREQUENCIES
GREATER THAN 50MHz
1MHz CARRIER SPACING
10 20
0
30
40
50
0
30
60
90
120
150
-40
-15
10
35
60
85
CENTER FREQUENCY (MHz)
CENTER FREQUENCY (MHz)
TEMPERATURE (°C)
MULTITONE POWER RATIO PLOT
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
f
= 125MWps, 2x INTERPOLATION
DATA
5
4
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
5
A
THROUGH A
= -18dBFS,
OUT1
OUT8
4
3
SPAN = 25MHz
2
3
1
2
0
-1
-2
-3
-4
-5
1
0
-1
8192
24586
40960
57344
f
= 35.7MHz, 1MHz TONE SPACING
8192
24576
40960
57344
CENTER
0
16384
32768
49152
65536
0
16384
32768
49152
65536
DIGITAL INPUT CODE
DIGITAL INPUT CODE
SUPPLY CURRENTS vs. DAC UPDATE RATE
SUPPLY CURRENTS vs. DAC UPDATE RATE
8x INTERPOLATION, f = 5MHz
SUPPLY CURRENTS vs. DAC UPDATE RATE
4x INTERPOLATION, f = 5MHz
2x INTERPOLATION, f
= 5MHz
OUT
OUT
OUT
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
1.8V TOTAL
1.8V TOTAL
1.8V TOTAL
3.3V TOTAL
3.3V TOTAL
3.3V TOTAL
0
0
0
100
150
200
(MHz)
250
300
100
200
300
(MHz)
400
500
100
200
300
(MHz)
400
500
f
f
DAC
f
DAC
DAC
8
_______________________________________________________________________________________
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
MAX895
Typical Operating Characteristics (continued)
(DV
= AV
= 1.8V, AV
= AV
= DV
= 3.3V, modulator off, 2x interpolation, output is transformer-coupled to
DD3.3
DD1.8
DD1.8
CLK
DD3.3
50Ω load, T = +25°C, unless otherwise noted.)
A
NOISE DENSITY vs. DAC UPDATE RATE
WCDMA ACLR vs. OUTPUT FREQUENCY
f
= 16MHz, 10MHz OFFSET
f
= 122.88MWps, 4x INTERPOLATION
OUT
DATA
-100
-110
-120
-130
-140
-150
-160
-170
-180
100
90
80
70
60
50
40
100
90
80
70
60
50
40
2x, 4x, AND 8x INTERPOLATION
SINGLE-CARRIER
ALTERNATE CHANNEL
SINGLE-CARRIER
SINGLE-CARRIER
ALTERNATE CHANNEL
A
= -12dBFS
OUT
SINGLE-CARRIER
ADJACENT CHANNEL
ADJACENT CHANNEL
FOUR-CARRIER
ALTERNATE CHANNEL
FOUR-CARRIER
ALTERNATE CHANNEL
FOUR-CARRIER
ADJACENT CHANNEL
FOUR-CARRIER
ADJACENT CHANNEL
100
200
300
(MHz)
400
500
0
40
80
120
160
0
40
80
f
f
(MHz)
f
(MHz)
CENTER
DAC
CENTER
WCDMA ACLR SPECTRAL PLOT
FOUR-CARRIER WCDMA ACLR SPECTRAL PLO
= 61.44MWps, 8x INTERPOLATION
f
= 61.44MWps, 8x INTERPOLATION
f
DATA
DATA
-20
-30
-40
-50
-60
-70
-80
-90
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-100
-110
-120
f
= 61.44MHz, SPAN = 25.5MHz
f
= 61.44MHz, SPAN = 40.6MHz
CENTER
CENTER
WCDMA ACLR SPECTRAL PLOT
= 122.88MWps, 4x INTERPOLATION
FOUR-CARRIER WCDMA ACLR SPECTRAL PLOT
= 122.88MWps, 4x INTERPOLATION
f
f
DATA
DATA
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
f
= 122.88MHz, SPAN = 40.6MHz
f
= 122.88MHz, SPAN = 25.5MHz
CENTER
CENTER
_______________________________________________________________________________________
9
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
Pin Description
PIN
1
NAME
CLKP
CLKN
N.C.
FUNCTION
Noninverting Differential Clock Input
Inverting Differential Clock Input
2
3, 4, 5
Internally Connected. Do not connect.
Digital Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to ground with a
0.1µF capacitor as close to the pin as possible.
6, 21, 30, 37
DV
DD1.8
MAX895
A-Port Data Inputs.
Dual-port mode:
7–12, 15–20,
22–25
A15–A0
I-channel data input. Data is latched on the rising/falling edge (programmable) of the DATACLK.
Single-port mode:
I-channel and Q-channel data input, with SELIQ.
CMOS I/O Power Supply. Accepts a 3.0V to 3.6V supply range. Bypass each pin to ground with a
0.1µF capacitor as close to the pin as possible.
13, 44
14
DV
DD3.3
DATACLK
Programmable Data Clock Input/Output. See the DATACLK Modes section for details.
Select I/Q-Channel Input or B-Port MSB Input.
Single-port mode:
If SELIQ = LOW, data is latched into Q-channel on the rising/falling edge (programmable) of
the DATACLK.
26
27
SELIQ/B15
If SELIQ = HIGH, data is latched into I-channel on the rising/falling edge (programmable) of the
DATACLK.
Dual-port mode:
Q-channel MSB input.
Alternate DATACLK Input/Output or B-Port Bit 14 Input.
Single-port mode:
See the DATACLK Modes section for details.
Dual-port mode:
DATACLK/B14
Q-channel bit 14 input.
If unused connect to GND.
B-Port Data Bits 13–0.
Dual-port mode:
28, 29, 31–36,
38–43
B13–B0
Q-channel inputs. Data is latched on the rising/falling (programmable) edge of the DATACLK.
Single-port mode:
Connect to GND.
45
46
47
48
49
50
SDO
SDI
Serial-Port Data Output
Serial-Port Data Input
SCLK
CS
Serial-Port Clock Input. Data on SDI is latched on the rising edge of SCLK.
Serial-Port Interface Select. Drive CS low to enable serial-port interface.
Reset Input. Set RESET low during power-up.
RESET
REFIO
Reference Input/Output. Bypass to ground with a 1µF capacitor as close to the pin as possible.
Current-Set Resistor Return Path. For a 20mA full-scale output current, connect a 2kΩ resistor
between FSADJ and DACREF. Internally connected to GND. Do not use as an external ground
connection.
51
52
DACREF
FSADJ
Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA full-
scale output current, connect a 2kΩ resistor between FSADJ and DACREF.
10 ______________________________________________________________________________________
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
MAX895
Pin Description (continued)
PIN
NAME
FUNCTION
Low Analog Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to GND with
a 0.1µF capacitor as close to the pin as possible.
53, 67
AV
DD1.8
54, 56, 59, 61,
64, 66
GND
Ground
Analog Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass each pin to GND with a
0.1µF capacitor as close to the pin as possible.
55, 60, 65
AV
DD3.3
57
58
62
63
OUTQN
OUTQP
OUTIN
OUTIP
Inverting Differential DAC Current Output for Q-Channel
Noninverting Differential DAC Current Output for Q-Channel
Inverting Differential DAC Current Output for I-Channel
Noninverting Differential DAC Current Output for I-Channel
Clock Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass to ground with a 0.1µF
capacitor as close to the pin as possible.
68
—
AV
CLK
EP
Exposed Pad. Must be connected to GND through a low-impedance path.
Functional Diagram
MODULATOR
DIGITAL
OFFSET
ADJUST
DIGITAL
GAIN
ADJUST
OUTIP
OUTIN
∑
IDAC
∑
A0–A15
f
DAC
DATACLK
I
Q
f
IM
I
/2, f /4
IM
DIGITAL
OFFSET
ADJUST
MAX5895
Q
B0–B15
SELIQ
DIGITAL
GAIN
ADJUST
OUTQP
OUTQN
QDAC
∑
∑
f
DAC
/2
/2
/2
/2
CONTROL REGISTERS
SERIAL INTERFACE
f
CLK
CLOCK BUFFERS
AND DIVIDERS
REFERENCE
RESET
SDO
SDI
CS
SCLK
DACREF FSADJ
REFIO
CLKN
CLKP
______________________________________________________________________________________ 11
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
The power-down modes can be used to turn off each
Detailed Description
DAC’s output current or the entire digital section.
The MAX5895 dual, 500Msps, high-speed, 16-bit, cur-
Programming both DACs into power-down simultane-
rent-output DAC provides superior performance in
ously will automatically power down the digital interpo-
communication systems requiring low-distortion ana-
lator filters. Note the SPI section is always active.
log-signal reconstruction. The MAX5895 combines two
The analog and digital sections of the MAX5895 have
separate power-supply inputs (AV , AV
DAC cores with 8x/4x/2x/1x programmable digital inter-
polation filters, a digital quadrature modulator, an SPI-
compatible serial interface for programming the device,
and an on-chip 1.20V reference. The full-scale output
current range is programmable from 2mA to 20mA to
optimize power dissipation and gain control.
,
DD1.8
DD3.3
AV
, DV
, and DV
), which minimize noise
coupling from one supply to the other. AV
CLK
DD3.3
DD1.8
and
DD1.8
MAX895
DV
operate from a typical 1.8V supply, and all
DD1.8
other supply inputs operate from a typical 3.3V supply.
Each channel contains three selectable interpolating fil-
ters making the MAX5895 capable of 1x, 2x, 4x, or 8x
interpolation, which allows for low-input and high-out-
put data rates. When operating in 8x interpolation
mode, the interpolator increases the DAC conversion
rate by a factor of eight, providing an eight-fold
increase in separation between the reconstructed
waveform spectrum and its first image. The MAX5895
accepts either two’s complement or offset binary input
data format and can operate from either a single- or
dual-port input bus.
Serial Interface
The SPI-compatible serial interface programs the
MAX5895 registers. The serial interface consists of the
CS, SDI, SCLK, and SDO. Data is shifted into SDI on
the rising edge of the SCLK when CS is low. When CS
is high, data presented at SDI is ignored and SDO is in
high-impedance mode. Note: CS must transition high
after each read/write operation. SDO is the serial data
output for reading registers to facilitate easy debug-
ging during development. SDI and SDO can be con-
nected together to form a 3-wire serial interface bus or
remain separate and form a 4-wire SPI bus.
The MAX5895 includes modulation modes at f /2 and
IM
f /4, where f is the data rate at the input of the modula-
IM
IM
The serial interface supports two-byte transfer in a
communication cycle. The first byte is a control byte
written to the MAX5895 only. The second byte is a data
byte and can be written to or read from the MAX5895.
tor. If 2x interpolation is used, this data rate is 2x the input
data rate. If 4x or 8x interpolation is used, this data rate is
4x the input data rate. Table 1 summarizes the modulator
operating data rates for dual-port mode.
Table 1. Quadrature Modulator Operating Data Rates (fIM is the Data Rate at the Input of
the Modulator) for Dual-Port Mode
MODULATION FREQUENCY
MODULATION FREQUENCY
INTERPOLATION RATE
MODULATION MODE (f
)
LO
RELATIVE TO f
RELATIVE TO f
DAC
DATA
f
IM
f
IM
f
IM
f
IM
f
IM
f
IM
f
IM
f
IM
/2
/4
/2
/4
/2
/4
/2
/4
f
f
f
f
f
f
f
f
/2
/4
/2
/4
/2
/4
/4
/8
f
f
/2
/4
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DATA
1x
2x
4x
8x
DATA
f
DATA
f
/2
DATA
2 x f
DATA
f
DATA
2 x f
DATA
f
DATA
12 ______________________________________________________________________________________
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
MAX895
When writing to the MAX5895, data is shifted into SDI;
data is shifted out of SDO in a read operation. Bits 0 to
3 of the control byte are the address bits. These bits set
the address of the register to be written to or read from.
Bits 4 to 6 of the control byte must always be set to 0.
Bit 7 is a read/write bit: 0 for write operation and 1 for
read operation. The most significant bit (MSB) is shifted
in first in default mode. If the serial port is set to LSB-
first mode, both the control byte and data byte are shifted
LSB in first. Figures 1 and 2 show the SPI serial interface
operation in the default write and read mode, respectively.
Figure 3 is a timing diagram for the SPI serial interface.
CS
SCLK
0
0
0
0
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDI
HIGH IMPEDANCE
SDO
Figure 1. SPI Serial Interface Write Cycle, MSB-First Mode
CS
READ CYCLE N - 1
READ CYCLE N
READ CYCLE N + 1
SCLK
SDI
ADDRESS
DATA
ADDRESS
DATA
ADDRESS
DATA
1 0 0 0 3 2 1 0
1 0 0 0 3 2 1 0
1 0 0 0 3 2 1 0
IGNORED
IGNORED
IGNORED
HIGH
IMPEDANCE
HIGH
HIGH
SDO
DATA N - 2
DATA N - 1
DATA N
IMPEDANCE
IMPEDANCE
Figure 2. SPI Serial Interface Read Cycle, MSB-First Mode
______________________________________________________________________________________ 13
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
t
SS
CS
MAX895
SCLK
SDI
t
t
SDH
SDS
t
SDV
SDO
Figure 3. SPI Serial-Interface Timing Diagram
14 ______________________________________________________________________________________
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
MAX895
of the registers. The following are descriptions of each
register.
Programming Registers
Programming its registers with the SPI serial interface
sets the MAX5895 operation modes. Table 2 shows all
Table 2. MAX5895 Programmable Registers
ADD
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Software Reset
0 = Normal
1 = Reset all
registers
Interpolator
Power-Down
0 = Normal
IDAC Power-
Down
0 = Normal
QDAC Power-
Down
0 = Normal
0 = MSB first
1 = LSB first
00h Unused
Unused
1 = Power-down 1 = Power-down 1 = Power-down
Interpolation Rate
(Bit 7, Bit 6)
00 = No interpolation
01 = 2x interpolation
10 = 4x interpolation
11 = 8x interpolation
Third
Interpolation
Filter
Configuration
0 = Lowpass
1 = Highpass
Modulation Mode
(Bit 4, Bit 3)
00 = Modulation off
01 = f /2
IM
10 = f /4
IM
11 = f /4
IM
Mixer Modulation Modulation
Mode
Sign
01h
02h
Unused
0 = Complex
1 = Real
0 = e-jω
1 = e+jω
0 = Input data
latched on
rising clock
edge
1 = Input data
latched on falling
clock edge
0 = Two’s
complement
input data
1 = Offset
binary input
data
0 = Single
port (A),
interleaved
I/Q
1 = Dual port on DATA CLK/B14
I/Q input
0 = Clock output
on DATACLK
1 = Clock output
0 = Data clock
input enabled
1 = Data clock
output enabled
Data
Synchronizer
0 = Enabled
1 = Disabled
Unused
03h Unused
04h 8-Bit IDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h
4-Bit IDAC Coarse-Gain Adjustment (see the Gain Adjustment
section). Bit 3 is MSB and bit 0 is LSB. Default: Fh
05h Unused
10-Bit IDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 06h register are the MSB bits. Bit 1 and bit 0 are the LSB
bits in 07h register. Default: 000h
06h
IDAC IOFFSET
Direction
0 = Current on
OUTIN
1 = Current on
OUTIP
IDAC Offset
Adjustment
Bit 1
(see 06h
register)
IDAC Offset
Adjustment
Bit 0
(see 06h
register)
07h
Unused
08h 8-Bit QDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h
4-Bit QDAC Coarse-Gain Adjustment (see the Gain Adjustment
section). Bit 3 is MSB and bit 0 is LSB. Default: Fh
09h Unused
10-Bit QDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 0Ah register are the MSB bits. Bit 1 and bit 0 are the
LSB bits in 0Bh register. Default: 000h
0Ah
0Bh
QDAC
IOFFSET
QDAC Offset QDAC Offset
Direction
0 = Current on
OUTQN
1 = Current on
OUTQP
Adjustment
Bit 1
(see 0Ah
register)
Adjustment
Bit 0
(see 0Ah
register)
Unused
0Ch Reserved, do not write to these bits.
0Dh Reserved, do not write to these bits.
0Eh Reserved, do not write to these bits.
Conditions in bold are default states after reset.
______________________________________________________________________________________ 15
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
Address 00h
to be e+jw, cancelling the lower image when
used with an external quadrature modulator.
Bit 6
Logic 0 (default) causes the serial port to use
MSB first address/data format. When set to a
logic 1, the serial port will use LSB first
address/data format.
Address 02h
Bit 7
Logic 0 (default) configures the data port for
two’s complement. A logic 1 configures the
data ports for offset binary.
Bit 5
Bit 4
When set to a logic 1, all registers reset to
their default state (this bit included).
Bit 6
Logic 0 (default) configures the data bus for
single-port, interleaved I/Q data. I and Q data
enter through one 16-bit bus. Logic 1 config-
ures the data bus for dual-port I/Q data. I and
Q data enter on separate buses.
Logic 1 stops the clock to the digital interpo-
lators. DAC outputs hold last value prior to
interpolator power-down.
MAX895
Bit 3
Bit 2
IDAC power-down mode. A logic 1 to this bit
powers down the IDAC.
Bit 5
Bit 4
Logic 0 (default) configures the data clock
for pin 14. A logic 1 configures the data clock
for pin 27 (DATACLK/B14).
QDAC power-down mode. A logic 1 to this bit
powers down the QDAC.
Logic 0 (default) sets the internal latches to
latch the data on the rising edge of DATACLK.
A logic 1 sets the internal latches to latch the
data on the falling edge of DATACLK.
Note: If both bit 2 and bit 3 are 1, the MAX5895 is in
full-power-down mode, leaving only the serial interface
active.
Address 01h
Bit 3
Bit 2
Logic 0 (default) configures the DATACLK
pin (pin 14 or pin 27) to be an input. A logic 1
configures the DATACLK pin to be an output.
Bits 7, 6 Configure the interpolation filters according
to the following table:
00
01
10
11
1x (no interpolation)
Logic 0 (default) enables the data synchro-
nizer circuitry. A logic 1 disables the data
synchronizer circuitry.
2x
4x
Address 03h
Bits 7–0 Unused.
Address 04h
Bits 7–0 These 8 bits define the binary number for
fine-gain adjustment of the IDAC full-scale
current (see the Gain Adjustment section). Bit
7 is the MSB. Default is all zeros.
8x (default)
Bit 5
Logic 0 configures FIR3 as a lowpass digital
filter (default). A logic 1 configures FIR3 as a
highpass digital filter.
Bits 4, 3 Configure the modulation frequency accord-
ing to the following table:
00
01
10
11
No modulation
Address 05h
f
IM
f
IM
f
IM
/2 modulation
Bits 3–0 These four bits define the binary number for
the coarse-gain adjustment of the IDAC full-
scale current (see the Gain Adjustment sec-
tion). Bit 3 is the MSB. Default is all ones.
/4 modulation (default)
/4 modulation
where f is the data rate at the input of the
IM
modulator.
Address 06h, Bits 7 to 0; Address 07h, Bit 1 and Bit 0
Bit 2
Bit 1
Configures the modulation mode for either
real or complex (image reject) modulation.
Logic 1 sets the modulator to the real mode
(default). Complex modulation is only avail-
These 10 bits represent a binary number that
defines the magnitude of the offset added to
the IDAC output (see the Offset Adjustment
section). Default is all zeros.
able for f /4 modulation.
IM
Quadrature modulator sign inversion. With I-
channel data leading Q-channel data by 90°,
logic 0 sets the complex modulation to be
e-jw (default), cancelling the upper image
when used with an external quadrature mod-
ulator. A logic 1 sets the complex modulation
16 ______________________________________________________________________________________
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
MAX895
Address 07h
Bit 7
tively. FINE is the register content of register 04h and
08h for the I- and Q-channel, respectively. The range of
coarse is from 0 to 15, with 15 being the default. The
range for FINE is from 0 to 255 with 0 being the default.
Given this, the gain can be adjusted in steps of approx-
imately 0.01dB.
Logic 0 (default) adds the 10 bits offset cur-
rent to OUTIN. A logic 1 adds the 10 bits off-
set current to OUTIP.
Address 08h
Bits 7–0 These eight bits define the binary number for
fine-gain adjustment of the QDAC full-scale
current (see the Gain Adjustment section). Bit
7 is the MSB. Default is all zeros.
Single-Port/Dual-Port Data Input Modes
The MAX5895 is capable of capturing data in single-
port and dual-port modes (selected through bit 6,
address 02h). In single-port mode, the data for both
channels is input through the A port (A15–A0).
The channel for the input data is determined through
the state of the SELIQ/B15 (pin 26) bit. When SELIQ is
set to logic-high, the input data is presented to the
I-channel, when set to logic-low, the input data is
presented to the Q-channel. The unused B-port inputs
(DATACLK/B14, B13–B0) should be grounded when
running in single-port mode.
Address 09h
Bits 3–0 These four bits define the binary number for
the coarse-gain adjustment of the QDAC full-
scale current (see the Gain Adjustment sec-
tion). Bit 3 is the MSB. Default is all ones.
Address 0Ah, Bits 7 to 0; Address 0Bh, Bit 1 and Bit 0
These 10 bits represent a binary number that
defines the magnitude of the offset added to
the QDAC output (see the Offset Adjustment
section). Default is all zeros.
Dual-port mode, as the name implies, requires that
each channel receives its data from a separate data
bus. SELIQ/B15 and DATACLK/B14 revert to data bit
inputs for the Q-channel in dual-port mode.
Address 0Bh
Bit 7
Logic 0 (default) adds the 10 bits offset to
OUTQN. A logic 1 adds the 10 bits offset to
OUTQP.
The MAX5895 control registers can be programmed to
allow either signed or unsigned binary format (bit 7,
address 02h) data in either single-port or dual-port
mode. Table 3 shows the corresponding DAC output
levels when using signed or unsigned data modes.
Offset Adjustment
Offset adjustment is achieved by adding a digital code
to the DAC inputs. The code OFFSET (see equation
below), as stored in the relevant control registers, has a
range from 0 to 1023 and a sign bit. The applied DAC
offset is 4 times the code stored in the register, provid-
ing an offset adjustment range of 4092 LSB codes.
The resolution is 4 LSB.
Table 3. DAC Output Code Table
DIGITAL INPUT CODE
OFFSET
BINARY
(UNSIGNED)
TWO'S
COMPLEMENT
(SIGNED)
OUT_P
OUT_N
0000 0000 0000
1000 0000 0000
4 x OFFSET
0
I
OUTFS
I
=
x I
OUTFS
OFFSET
16
0111 1111 1111 1111 0000 0000 0000 0000
1111 1111 1111 0111 1111 1111
I
/2
I
/2
OUTFS
OUTFS
0
2
I
OUTFS
Gain Trim
Gain trimming is done by varying the full-scale current
according to the following formula:
Data Synchronization Modes
Data synchronization circuitry is provided to allow oper-
ation with an input data clock. The data clock must be
frequency locked to the DAC clock (f
), but can
DAC
⎡
⎢
⎣
⎤
⎛
⎠ ⎝
256
⎦
have arbitrary phase with respect to the DAC clock.
The synchronization circuitry allows for phase jitter on
the input data clock of up to 1 data clock cycles.
Synchronization is initially established when the reset
pin is asynchronously deasserted and the input data
clock has been running for at least 4 clock cycles.
Subsequently, the MAX5895 monitors the phase rela-
3 ×I
3 ×I
REF
32
⎛
⎞ COARSE +1
⎛
⎞ FINE
1024
24
⎛
⎞
⎛
⎞
⎞
REF
I
=
−
⎜
⎝
⎟
⎜
⎟
⎟⎥ ⎜
⎟
⎠
⎜
⎝
⎟
⎜
⎝
OUTFS
⎠
⎝
4
⎠
16
⎠
where I
is the reference current (see the Internal
REF
Reference section). COARSE is the register content of
registers 05h and 09h for the I- and Q-channel, respec-
______________________________________________________________________________________ 17
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
tionship and detects if the phase drifts more than
1
Table 4. Clock Frequency Ratios in
data clock cycle. If this occurs, the synchronizer auto-
matically reestablishes synchronization. However, dur-
ing the resynchronization phase, up to 8 data words
may be lost or repeated.
Various Modes
INPUT
MODE
INTERPOLATION
RATE
f
:f
f
:f
DATA CLK
DAC CLK
Bit 2 of register 02h disables or enables (default) the
automatic data clock phase detection. Disabling the
data synchronization circuitry requires the data clock
and the DAC clock phase to be locked.
1x
2x
4x
8x
1x
2x
4x
8x
1:1
1:1
1:2
1:4
1:1
1:2
1:4
1:8
1:2
1:1
1:1
1:1
1:1
1:1
1:1
1:1
Single
Port
MAX895
DATACLK Modes
The MAX5895 has a main DATACLK available at
pin 14. An alternate DATACLK is available at pin 27
(DATACLK/B14) when configured in single-port data
input mode (bit 5, address 02h). The DATACLK can be
configured to accept an input clock signal for latching
the input data, or to source a clock signal that can drive
up to 10pF load while latching the input data (bit 3,
address 02h). If DATACLK is configured as an output, it
Dual Port
is frequency divided from the CLKP/CLKN input,
depending on the operating mode, see Table 4.
CLKP–CLKN
t
CLK
DATACLK
t
D
t
DS
t
DH
A0–A15/B0–B15
Figure 4. Data Input Timing Diagram
18 ______________________________________________________________________________________
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
MAX895
The MAX5895 can be configured to latch the input
data on either the rising edge or falling edge of the
DATACLK signal (bit 4, address 02h). Figure 4 shows
the timing requirements between the DATACLK signal
and the input data bus with latching on the rising edge.
Interpolating Filter
The MAX5895 features three cascaded FIR half-band
filters. The interpolating filters are enabled or disabled
in combinations to support 1x (no interpolation), 2x, 4x,
or 8x interpolation. Bits 7 and 6 of register 01h set the
interpolation rate (see Table 2). The last interpolation fil-
0
0
-20
-20
PASSBAND DETAIL
PASSBAND DETAIL
-40
0
-40
0
-0.0002
-0.0002
-60
-60
-0.0004
-0.0004
0
0.1
0.2
0.3
0.4
0.4
0
0.1
0.2
0.3
-80
-80
-100
-100
-120
-120
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
- NORMALIZED TO INPUT DATA RATE
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
- NORMALIZED TO INPUT DATA RATE
f
f
OUT
OUT
Figure 5. Interpolation Filter Frequency Response, 2x
Interpolation Mode
Figure 6. Interpolation Filter Frequency Response, 4x
Interpolation Mode
0
0
-20
-20
PASSBAND DETAIL
PASSBAND DETAIL
-40
0
-40
0
-0.0002
-0.0002
-60
-60
-0.0004
-0.0004
0
0.1
0.2
0.3
0.4
3.6
3.8
4.0
4.2
4.4
-80
-80
-100
-100
-120
-120
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
f
- NORMALIZED TO INPUT DATA RATE
f
- NORMALIZED TO INPUT DATA RATE
OUT
OUT
Figure 7. Interpolation Filter Frequency Response, 8x
Interpolation Mode (FIR3 Lowpass Mode)
Figure 8. Interpolation Filter Frequency Response, 8x
Interpolation Mode (FIR3 Highpass Mode)
______________________________________________________________________________________ 19
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
ter is located after the modulator. In the 8x interpolation
mode, the last filter (FIR3) can be configured as low-
pass or highpass (bit 5, address 01h) to select the
lower or upper sideband from the modulation output.
The frequency responses of these three filters are plot-
ted in Figures 5–8.
DAC image. The original spectral images, appearing at
around multiples of the input data rate, are attenuated
by the internal digital filters. This feature provides three
benefits:
1) Image separation reduces complexity of analog
reconstruction filters.
The programmable interpolation filters multiply the
MAX5895 input data rate by a factor of 2x, 4x, or 8x to
separate the reconstructed waveform spectrum and the
2) Lower input data rates eliminate board-level high-
speed data transmission.
MAX895
FILTER
RESPONSE
NO INTERPOLATION
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
IMAGE
INPUT
SPECTRUM
AND FIRST
FILTER
RESPONSE
f
f
f
f
2f
2f
2f
2f
3f
3f
3f
3f
4f
4f
4f
4f
5f
5f
5f
5f
6f
6f
6f
6f
7f
7f
7f
7f
8f
8f
8f
8f
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
IMAGE
2x INTERPOLATION
4x INTERPOLATION
8x INTERPOLATION
OUTPUT
SPECTRUM
OF THE
FIRST
FILTER
FILTER
RESPONSE
INPUT
SPECTRUM
AND
SECOND
FILTER
RESPONSE
IMAGE
OUTPUT
SPECTRUM
OF THE
SECOND
FILTER
IMAGE
INPUT
IMAGE
FILTER
SPECTRUM
AND THIRD
FILTER
RESPONSE
RESPONSE
f
f
2f
2f
3f
S
4f
4f
5f
5f
6f
6f
7f
S
8f
8f
S
S
S
S
S
S
OUTPUT
SPECTRUM
OF THE
THIRD
IMAGE
FILTER
3f
S
7f
S
S
S
S
S
S
S
Figure 9. Spectral Representation of Interpolating Filter Responses (Output Frequencies are Relative to the Data Input Frequency, f )
S
20 ______________________________________________________________________________________
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
MAX895
3) Sin(x)/x rolloff is reduced over the effective bandwidth.
in the second Nyquist zone between f /2 and f . The first
S S
interpolating filter removes this image. In fact, all of the
images at odd numbers of f are filtered. At the output of
Figure 9 illustrates a practical example of the benefits
when using the MAX5895 in 2x, 4x, and 8x interpolation
modes with the third filter configured as a lowpass filter.
With no interpolation filter, the first image signal appears
S
the first filter, the images are at 2f , 4f , etc. This signal is
S
S
then passed to the second interpolating filter, which is
FILTER
RESPONSE
NO INTERPOLATION
SIGNAL
IMAGE
INPUT
SPECTRUM
AND FIRST
FILTER
RESPONSE
f
S
f
S
f
S
f
S
2f
S
2f
S
2f
S
2f
S
3f
S
3f
S
3f
S
3f
S
4f
4f
4f
4f
S
S
S
S
SIGNAL
SIGNAL
SIGNAL
2x INTERPOLATION
IMAGE
OUTPUT
SPECTRUM
OF THE
FIRST
FILTER
INPUT
SPECTRUM
AND
SECOND
FILTER
RESPONSE
FILTER
RESPONSE
IMAGE
4x INTERPOLATION
OUTPUT
SPECTRUM
OF THE
SECOND
FILTER
IMAGE
SIGNAL
LOWER
SIDEBAND
UPPER
SIDEBAND
IMAGE
OUTPUT
SPECTRUM
OF THE
MODULATOR
f
S
2f
S
3f
S
4f
S
FOR COMPLEX MODULATION THE MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND
Figure 10. Spectral Representation of 4x Interpolation Filter with f /4 Modulation (Output Frequencies are Relative to the Data Input
IM
Frequency, f )
S
______________________________________________________________________________________ 21
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
FILTER
RESPONSE
NO INTERPOLATION
SIGNAL
SIGNAL
SIGNAL
SIGNAL
IMAGE
INPUT
SPECTRUM
AND FIRST
FILTER
RESPONSE
f
f
f
f
2f
S
2f
S
2f
S
2f
S
3f
S
3f
S
3f
S
3f
S
4f
4f
4f
4f
5f
S
5f
S
5f
S
5f
S
6f
S
6f
S
6f
S
6f
S
7f
S
7f
S
7f
S
7f
S
8f
S
8f
S
8f
S
8f
S
S
S
S
S
S
MAX895
IMAGE
2x INTERPOLATION
OUTPUT
SPECTRUM
OF THE
FIRST
FILTER
S
FILTER
RESPONSE
INPUT
SPECTRUM
AND
SECOND
FILTER
RESPONSE
IMAGE
S
4x INTERPOLATION
OUTPUT
SPECTRUM
OF THE
SECOND
FILTER
IMAGE
S
SIGNAL
LOWER
UPPER
SIDEBAND
IMAGE
SIDEBAND
OUTPUT
SPECTRUM
OF THE
MODULATOR
f
2f
3f
4f
5f
6f
7f
7f
8f
8f
S
S
S
S
S
S
S
S
FOR COMPLEX MODULATION THE MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND
FILTER RESPONSE
SIGNAL
INPUT
IMAGE
SPECTRUM
AND THIRD
FILTER
RESPONSE
f
2f
S
3f
S
4f
S
5f
S
6f
S
S
S
S
8x INTERPOLATION
SIGNAL
OUTPUT
SPECTRUM
OF THE
THIRD
IMAGE
FILTER
f
2f
S
3f
S
4f
S
5f
S
6f
S
7f
S
8f
S
S
Figure 11. Spectral Representation of 8x Interpolation Filter with f /4 Modulation and Lowpass Mode Enabled (Output Frequencies
IM
are Relative to the Data Input Frequency, f )
S
22 ______________________________________________________________________________________
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
MAX895
FILTER
RESPONSE
NO INTERPOLATION
SIGNAL
SIGNAL
SIGNAL
SIGNAL
IMAGE
INPUT
SPECTRUM
AND FIRST
FILTER
RESPONSE
f
f
f
f
2f
S
2f
S
2f
S
2f
S
3f
S
3f
S
3f
S
3f
S
4f
S
4f
S
4f
S
4f
S
5f
S
5f
S
5f
S
5f
S
6f
S
6f
S
6f
S
6f
S
7f
S
7f
S
7f
S
7f
S
8f
S
8f
S
8f
S
8f
S
S
S
S
S
IMAGE
2x INTERPOLATION
OUTPUT
SPECTRUM
OF THE
FIRST
FILTER
FILTER
RESPONSE
INPUT
SPECTRUM
AND
SECOND
FILTER
RESPONSE
IMAGE
4x INTERPOLATION
OUTPUT
SPECTRUM
OF THE
SECOND
FILTER
IMAGE
SIGNAL
LOWER
UPPER
SIDEBAND
IMAGE
SIDEBAND
OUTPUT
SPECTRUM
OF THE
MODULATOR
f
2f
3f
4f
5f
6f
7f
7f
8f
8f
S
S
S
S
S
S
S
S
FOR COMPLEX MODULATION THE MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND
FILTER
RESPONSE
SIGNAL
INPUT
IMAGE
SPECTRUM
AND THIRD
FILTER
RESPONSE
f
2f
S
3f
S
4f
S
5f
S
6f
S
S
S
S
8x INTERPOLATION
SIGNAL
OUTPUT
SPECTRUM
OF THE
THIRD
IMAGE
FILTER
f
2f
S
3f
S
4f
S
5f
S
6f
S
7f
S
8f
S
S
Figure 12. Spectral Representation of 8x Interpolation Filter with f /4 Modulation and Highpass Mode Enabled (Output Frequencies
IM
are Relative to the Data Input Frequency, f )
S
______________________________________________________________________________________ 23
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
similar to the first filter and removes the images at 2f , 6f ,
When f /2 is chosen as the LO frequency, the input
IM
S
S
10f , etc. Finally, the third filter removes images at 4f ,
signal is multiplied by [-1, 1] on both channels. This pro-
S
S
12f , 20f , etc. Figures 10, 11, and 12 similarly illustrate
duces images around f /2. The complex image-reject
IM
modulation mode is not available for this LO frequency.
S
S
the spectral responses when using the interpolating filters
combined with the digital modulator.
The outputs of the modulator can be expressed as:
Digital Modulator
The MAX5895 features digital modulation at frequen-
I t = A t × cos ωt − B t × sin ωt
( )
( )
(
)
( )
( )
cies of f /2 and f /4, where f is the data rate at the
IM
IM
IM
MAX895
input to the modulator. f equals f
in 1x, 2x, and 4x
Q t = A t × sin ωt + B t × cos ωt
( ) ( ) ( ) ( )
IM
DAC
(
)
interpolation modes. In 8x interpolation mode, f
IM
equals f
/2. The output rate of the modulator is
in complex modulation, e+jwt
DAC
always the same as the input data rate to the modula-
tor, f
.
IM
I t = A t × cos ωt + B t × sin ωt
( ) ( ) ( ) ( )
In complex modulation mode, data from the second
interpolation filter is frequency mixed with the on-chip
in-phase and quadrature (I/Q) local oscillator (LO).
Complex modulation provides the benefit of image
sideband rejection when combined with an external
quadrature modulator commonly found in wireless
communication systems.
(
(
)
)
Q t = A t × sin ωt + B t × cos ωt
( ) ( ) ( ) ( )
in complex modulation, e-jwt
where ω = 2 x π x f
.
LO
For real modulation, The outputs of the modulator can
be expressed as:
In the f = f /4 mode, real or complex modulation can
LO
IM
be used. The modulator multiplies successive input data
I t = A t × cos ωt
( )
( )
( )
samples by the sequence [1, 0, -1, 0] for a cos(ωt). The
modulator modulates the input signal up to f /4, creat-
IM
Q t = A t × cos ωt
( ) ( )
(
)
ing upper and lower images around f /4. The quadra-
IM
ture LO sin(ωt) is realized by delaying the cos(ωt)
sequence by one clock cycle. Using complex modula-
tion, complex IF is generated. The complex IF combined
with an external quadrature modulator provides image
rejection. The sign of the LO can be changed to allow
the user to select whether the upper or the lower image
should be rejected (bit 1 of register 01h).
If more than one MAX5895 is used, their LO phases can
be synchronized by simultaneously releasing RESET.
This sets the MAX5895 to its predefined initial phase.
Device Reset
The MAX5895 can be reset by holding the RESET pin
low for 10ns. This will program the control registers to
I-CHANNEL
INPUT DATA
I-CHANNEL
INPUT DATA
I-CHANNEL
OUTPUT DATA
I-CHANNEL
OUTPUT DATA
cos(ωt)
cos(ωt)
sin(ωt)
∑
∑
∑
sin(ωt)
TO
FIR3
TO
FIR3
sin(ωt)
sin(ωt)
Q-CHANNEL
∑
Q-CHANNEL
OUTPUT DATA
OUTPUT DATA
Q-CHANNEL
INPUT DATA
Q-CHANNEL
INPUT DATA
cos(ωt)
cos(ωt)
(a)
(b)
Figure 13. (a) Modulator in Complex Modulation Mode; (b) Modulator in Real Modulation Mode
24 ______________________________________________________________________________________
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
MAX895
Data Clock
The MAX5895 features synchronizers that allow for
arbitrary phase alignment between DATACLK and
CLKP/CLKN. The DATACLK causes internal switching
in the MAX5895 and the phase between DATACLK
(input mode) to CLKP/CLKN will influence the images
at DATACLK. Optimum image rejection is achieved
when DATACLK transitions are aligned with the falling
edge of CLKP. Figure 14 shows the image level near
DATACLK as a function of the DATACLK (input mode)
to CLKP/CLKN phase at 500Msps, 4x interpolation for a
10MHz, -6dBFS output signal.
their default values in Table 2. During power-on, RESET
must be held low until all power supplies have stabi-
lized. Alternatively, programming bit 5 of address 00h
to a logic-high also resets the MAX5895 after power-up.
Power-Down Mode
The MAX5895 features three power-saving modes.
Each DAC can be individually powered down through
bits 2 and 3 of address 00h. The interpolation filters can
also be powered down through bit 4 of address 00h,
preserving the output level of each DAC (the DACs
remain powered). Powering down both DACs will auto-
matically put the MAX5895 into full power-down, includ-
ing the interpolation filters.
Clock Interface
The MAX5895 features a flexible differential clock input
Applications Information
(CLKP, CLKN) with a separate supply (AV
) to
CLK
achieve optimum jitter performance. It uses an ultra-low
jitter clock to achieve the required noise density. Clock
Frequency Planning
System designers need to take the DAC into account
during frequency planning for high-performance appli-
cations. Proper frequency planning can ensure that
optimal system performance is achieved. The
MAX5895 is designed to deliver excellent dynamic per-
formance across wide bandwidths, as required for
communication systems and, in particular, for multicar-
rier applications. As with all DACs, some combinations
of output frequency and update rate produce better
performance than others.
jitter must be less than 0.5ps
to meet the specified
RMS
noise density. For that reason, the CLKP/CLKN input
source must be designed carefully. The differential
clock (CLKN and CLKP) input can be driven from a sin-
gle-ended or a differential clock source. Differential
clock drive is required to achieve the best dynamic
performance from the DAC. For single-ended opera-
tion, drive CLKP with a low noise source and bypass
CLKN to GND with a 0.1µF capacitor.
The CLKP and CLKN pins are internally biased to
Harmonics are often folded down into the band of inter-
est. Specifically, if the DAC outputs a frequency close
to f /N, the Mth harmonic of the output signal will be
S
AV
/2. This allows the user to AC-couple clock
CLK
aliased down to:
N− M
N
⎡
⎤
f = f − M x f
OUT
= f
S
S
⎢
⎣
⎥
⎦
f /4 IMAGES vs. CLKP/CLKN to DATACLK DELAY
S
f
= 125MWps, 4x INTERPOLATION
DATA
-50
-60
Thus, if N ≈ (M + 1), the Mth harmonic will be close to
the output frequency. SFDR performance of a current-
steering DAC is often dominated by third-order har-
monic distortion. If this is a concern, placing the output
f /4 - f
S
OUT
-70
signal at a different frequency other than f /4 should be
S
considered.
-80
Common to interpolating DACs are images near the
divided clocks. In a DAC configured for 4x interpolation
-90
this applies to images around f /4 and f /2. In a DAC
S
S
f /4 + f
S
OUT
configured for 8x interpolation this applies to images
around f /8, f /4, and f /2. Most of these images are
-100
-110
f
A
= 10MHz
= -6dBFS
OUT
OUT
S
S
S
not part of the in-band (0 to f
/2) SFDR specifica-
DATA
tion, though they are a consideration for out-of-band
(f /2 - f /2) SFDR and may depend on the rela-
0
2.0
4.0
6.0
8.0
DATA
DAC
CLKP/CLKN DELAY (ns)
tionship of the DATACLK to DAC update clock (see the
Data Clock section). When specifying the output recon-
struction filter for other than baseband signals, these
images should not be ignored.
Figure 14. Effect of CLKP/CLKN to DATACLK Phase on f /4
S
Images
______________________________________________________________________________________ 25
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
sources directly to the device without external resistors
to define the DC level. The input resistance of CLKP
and CLKN is 5kΩ.
A convenient way to apply a differential signal is with a
balun transformer as shown in Figure 15. Alternatively,
these inputs may be driven from a CMOS-compatible
clock source, however it is recommended to use
sine-wave or AC-coupled differential ECL/PECL drive for
best dynamic performance.
Output Interface (OUTI, OUTQ)
The MAX5895 outputs complementary currents (OUTIP,
OUTIN) and (OUTQP, OUTQN), that can be utilized in a
differential configuration. Load resistors convert these
two output currents into a differential output voltage.
100nF
CLKP
MAX895
MINI-CIRCUITS
ADTL1-12
24.9Ω
SINGLE-ENDED
IINPUT
MAX5895
The differential output between OUTIP (OUTQP) and
OUTIN (OUTQN) can be converted to a single-ended
output using a transformer or a differential amplifier.
Figure 16 shows a typical transformer-based applica-
tion circuit for generation of IF output signals. In this
configuration, the MAX5895 operates in differential
mode, which reduces even-order harmonics, and
increases the available output power. Pay close atten-
tion to the transformer core saturation characteristics
when selecting a transformer. Transformer core satura-
tion can introduce strong second harmonic distortion,
1:1 RATIO
24.9Ω
100nF
CLKN
Figure 15. Single-Ended-to-Differential Clock Conversion Using
a Balun Transformer
50Ω
V
IOUT
, SINGLE-ENDED
1:1
OUTIP
IDAC
100Ω
16
1:1
OUTIN
50Ω
MAX5895
50Ω
V
QOUT
, SINGLE-ENDED
1:1
OUTQP
QDAC
100Ω
16
1:1
OUTQN
50Ω
Figure 16. Differential-to-Single-Ended Conversion Using Wideband RF Transformers
26 ______________________________________________________________________________________
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
MAX895
especially at low output frequencies and high signal
amplitudes. It is recommended to connect the trans-
former center tap to ground.
25Ω
If a transformer is not used, the outputs must have a
resistive termination to ground. Figure 17 shows the
OUTIP
MAX5895 output configured for differential DC-coupled
mode. The DC-coupled configuration can be used to
eliminate waveform distortion due to highpass filter
effects. Applications include communication systems
employing analog quadrature upconverters and requir-
ing a high-speed DAC for baseband I/Q synthesis.
IDAC
50Ω
25Ω
16
OUTIN
If a single-ended DC-coupled unipolar output is desir-
able, OUTIP (OUTQP) should be selected as the out-
put, and connect OUTIN (OUTQN) to ground. Using the
MAX5895 output single-ended is not recommended
because it introduces additional noise and distortion.
MAX5895
25Ω
50Ω
The distortion performance of the DAC also depends
on the load impedance. The MAX5895 is optimized for
a 50Ω double termination. It can be used with a trans-
former output as shown in Figure 16 or just one 25Ω
resistor from each output to ground and one 50Ω resis-
tor between the outputs (Figure 17). Higher output ter-
mination resistors may be used, as long as each output
voltage does not exceed +1V with respect to GND, but
at the cost of degraded distortion performance and
increased output noise voltage.
OUTQP
OUTQN
QDAC
16
25Ω
Figure 17. The DC-Coupled Differential Output Configuration
______________________________________________________________________________________ 27
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
The MAX5895’s reference circuit (Figure 19) employs a
control amplifier, designed to regulate the full-scale
Reference Input/Output
The MAX5895 supports operation with the on-chip 1.2V
bandgap reference or an external reference voltage
source. REFIO serves as the input for an external, low-
impedance reference source, and as the output if the
DAC is operating with the internal reference.
current I
for the differential current outputs of the
OUT
DAC. The output current can be calculated as:
I
= 32 x I - 1LSB
OUTFS
REFIO
I
= 32 x I
- (I
/216)
OUT
OUTFS
REFIO
For stable operation with the internal reference, REFIO
should be decoupled to GND with a 1µF capacitor.
REFIO must be buffered with an external amplifier, if heavy
loading is required, due to its 10kΩ output resistance.
Alternatively, apply a temperature-stable external refer-
ence to REFIO (Figure 18). The internal reference is over-
driven by the external reference. For improved accuracy
and drift performance, choose a fixed output voltage ref-
erence such as the MAX6520 bandgap reference.
where I
REFIO SET
is the reference output current (I
=
REFIO
REFIO
V
/R
) and I
is the full-scale output current
OUT
MAX895
of the DAC. Located between FSADJ and DACREF,
is the reference resistor, which determines the
R
SET
amplifier’s output current for the DAC. Use Table 5 for a
matrix of different I
and R
selections.
OUTFS
SET
1.2V
REFERENCE
1.2V
REFERENCE
MAX5895
MAX5895
10kΩ
10kΩ
EXTERNAL
REFIO
REFIO
1.25V
REFERENCE
1µF
1µF
FSADJ
FSADJ
CURRENT-
SOURCE
ARRAY DAC
CURRENT-
SOURCE
ARRAY DAC
I
REF
I
REF
R
SET
R
SET
DACREF
DACREF
Figure 18. Typical External Reference Circuit
Figure 19. MAX5895 Internal Reference Architecture
Table 5. IOUTFS and RSET Selection Matrix Based on a Typical 1.20V Reference Voltage
FULL-SCALE
CURRENT
REFERENCE
CURRENT
R
(Ω)
OUTPUT VOLTAGE
* (mV
SET
I
(mA)
I
(µA)
CALCULATED
19.2k
1% EIA STD
19.1k
V
)
P-P
OUTFS
REF
IOUTP/N
2
62.50
100
5
156.26
312.50
468.75
625.00
7.68k
7.5k
250
500
10
15
20
3.84k
3.83k
2.56k
2.55k
750
1.92k
1.91k
1000
*Terminated into a 50Ω load.
28 ______________________________________________________________________________________
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
MAX895
Power Supplies, Bypassing,
Static Performance Parameter
Decoupling, and Layout
Definitions
Integral Nonlinearity (INL)
Grounding and power-supply decoupling strongly influ-
ence the MAX5895 performance. Unwanted digital
crosstalk can couple through the input, reference,
power-supply, and ground connections, which can
affect dynamic specifications like signal-to-noise ratio
or spurious-free dynamic range. In addition, electro-
magnetic interference (EMI) can either couple into or
be generated by the MAX5895. Observe the grounding
and power-supply decoupling guidelines for high-
speed, high-frequency applications. Follow the power-
supply and filter configuration guidelines to achieve
optimum dynamic performance.
Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best straight-line fit
(closest approximation to the actual transfer curve) or a
line drawn between the end points of the transfer func-
tion, once offset and gain errors have been nullified.
For a DAC, the deviations are measured at every indi-
vidual step.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step height and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function.
Using a multilayer PCB with separate ground and
power-supply planes, run high-speed signals on lines
directly above the ground plane. Since the MAX5895
has separate analog and digital sections, the PCB
should include separate analog and digital ground sec-
tions with only one point connecting the three planes at
the exposed paddle under the MAX5895. Run digital
signals above the digital ground plane and
analog/clock signals above the analog/clock ground
plane. Keep digital signals as far away from sensitive
analog inputs, reference lines, and clock inputs as
practical. Use a symmetric design of clock input and
the analog output lines to minimize 2nd-order harmonic
distortion components, thus optimizing the dynamic
performance of the DAC. Keep digital signal paths
short and run lengths matched to avoid propagation
delay and data skew mismatches.
Offset Error
The offset error is the difference between the ideal and
the actual offset current. For a DAC, the offset point is
the average value at the output for the two midscale
digital input codes with respect to the full-scale of the
DAC. This error affects all codes by the same amount.
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Dynamic Performance
Parameter Definitions
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the specified accuracy.
The MAX5895 requires five separate power-supply
inputs for the analog (AV
and AV
), digital
DD3.3
) circuitry.
CLK
DD1.8
), and clock (AV
(DV
and DV
DD1.8
DD3.3
Decouple each voltage supply pin with a separate
0.1µF capacitor as close to the device as possible and
with the shortest possible connection to the appropriate
ground plane. Minimize the analog and digital load
capacitances for optimized operation. Decouple all
power-supply voltages at the point they enter the PCB
with tantalum or electrolytic capacitors. Ferrite beads
with additional decoupling capacitors forming a pi-net-
work could also improve performance.
Noise Spectral Density
The DAC output noise is the sum of the quantization
noise and thermal noise. Noise spectral density is the
noise power in 1Hz bandwidth, specified in dBFS/Hz.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog output (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
maximum SNR can be derived from the DAC’s resolu-
tion (N bits):
The exposed pad (EP) MUST be soldered to the
ground. Use multiple vias, an array of at least 4 x 4
vias, directly under the EP to provide a low thermal and
electrical impedance path for the IC.
SNR = 6.02 x N + 1.76
dB
dB
dB
______________________________________________________________________________________ 29
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
However, noise sources such as thermal noise, refer-
ence noise, clock jitter, etc. affect the ideal reading.
Therefore, SNR is computed by taking the ratio of the
RMS signal to the RMS noise, which includes all spec-
tral components minus the fundamental, the first four
harmonics, and the DC offset.
Two-/Four-Tone Intermodulation
Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc (or
dBFS) of the worst 3rd-order (or higher) IMD products
to either output tone.
Adjacent Channel Leakage
Power Ratio (ACLR)
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the RMS amplitude of the carrier
frequency (maximum signal components) to the RMS
value of their next largest distortion component. SFDR
is usually measured in dBc and with respect to the car-
rier frequency amplitude or in dBFS with respect to the
DAC’s full-scale range. Depending on its test condition,
SFDR is observed within a predefined window or
to Nyquist.
Commonly used in combination with WCDMA (wide-
band code-division multiple-access), ACLR reflects the
leakage power ratio in dB between the measured pow-
ers within a channel relative to its adjacent channel.
ACLR provides a quantifiable method of determining
out-of-band spectral energy and its influence on an
adjacent channel when a bandwidth-limited RF signal
passes through a nonlinear device.
MAX895
Pin Configuration
TOP VIEW
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
CLKP
CLKN
N.C.
1
2
3
4
5
6
7
8
9
EXPOSED PAD
51 DACREF
50 REFIO
49 RESET
48 CS
N.C.
N.C.
47 SCLK
46 SDI
D
VDD1.8
A15
45 SDO
A14
44 DV
43 B0
42 B1
41 B2
40 B3
39 B4
38 B5
37 DV
36 B6
35 B7
DD3.3
A13
MAX5895
A12 10
A11 11
A10 12
D
VDD3.3 13
DATACLK 14
A9 15
DD1.8
A8 16
A7 17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
QFN
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
21-0122
68 QFN-EP
G6800-4
30 ______________________________________________________________________________________
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
MAX895
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
2
—
Initial release
—
—
—
4/07
10/08
Add note to setup and hold specifications.
5, 6
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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