MAX5898EGK [MAXIM]
D/A Converter, 1 Func, Parallel, Word Input Loading, 0.011us Settling Time, 10 X 10 MM, 0.90 MM HEIGHT, MO-220, QFN-68;
| 型号： | MAX5898EGK |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Parallel, Word Input Loading, 0.011us Settling Time, 10 X 10 MM, 0.90 MM HEIGHT, MO-220, QFN-68 |
| 文件： | 总32页 (文件大小：400K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3756; Rev 1; 7/07
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
General Description
Features
♦ 71dB ACLR at f
= 61.44MHz (Four-Carrier
The MAX5898 programmable interpolating, modulating,
500Msps, dual digital-to-analog converter (DAC) offers
superior dynamic performance and is optimized for high-
performance wideband, single- and multicarrier transmit
applications. The device integrates a selectable 2x/4x/8x
interpolating filter, a digital quadrature modulator, and
dual 16-bit, high-speed DACs on a single integrated cir-
cuit. At 30MHz output frequency and 500Msps update
rate, the in-band SFDR is 81dBc, while only consuming
1.2W. The device also delivers 71dB ACLR for four-
carrier WCDMA at a 61.44MHz output frequency.
OUT
WCDMA)
♦ Meets Multicarrier UMTS, cdma2000®, GSM
Spectral Masks (f = 122MHz)
OUT
♦ Noise Spectral Density = -160dBFS/Hz at
= 16MHz
♦ 90dBc SFDR at Low-IF Frequency (10MHz)
♦ 88dBc SFDR at High-IF Frequency (50MHz)
f
OUT
♦ Low Power: 831mW (f
♦ User Programmable
= 250MHz)
CLK
The selectable interpolating filters allow lower input data
rates while taking advantage of the high DAC update
rates. These linear-phase interpolation filters ease recon-
struction filter requirements and enhance the passband
dynamic performance. Each channel includes offset and
gain programmability, allowing the user to calibrate out
local oscillator (LO) feedthrough and sideband suppres-
sion errors generated by analog quadrature modulators.
Selectable 2x, 4x, or 8x Interpolating Filters
< 0.01dB Passband Ripple
> 95dB Stopband Rejection
Selectable Real or Complex Modulator Operation
Selectable Modulator LO Frequency: OFF, f / 2,
IM
or f / 4
IM
Selectable Output Filter: Lowpass or Highpass
Per Channel Gain and Offset Adjustment
♦ EV Kit Available (Order the MAX5898EVKIT)
Ordering Information
PKG
The MAX5898 features a f / 4 digital image-reject
IM
modulator. This modulator generates a quadrature-mod-
ulated IF signal that can be presented to an analog I/Q
modulator to complete the upconversion process. A
second digital modulation mode allows the signal to be
PART
TEMP RANGE PIN-PACKAGE
CODE
frequency-translated with image pairs at f / 2 or f / 4.
IM
IM
68 QFN-EP*
(10mm x 10mm)
MAX5898EGK+D -40°C to +85°C
MAX5898EGK-D -40°C to +85°C
G6800-4
The MAX5898 features a standard LVDS interface for
low electromagnetic interference (EMI). Interleaved
data is applied through a single 16-bit bus. A 3.3V
SPI™ port is provided for mode configuration. The pro-
grammable modes include the selection of 2x/4x/8x
68 QFN-EP*
(10mm x 10mm)
G6800-4
+Denotes a lead-free package.
D = Dry pack.
*EP = Exposed paddle.
interpolating filters, f / 2, f / 4 or no digital quadra-
IM
IM
Selector Guide
ture modulation with image rejection, individual channel
gain and offset adjustment, and offset binary or two’s-
complement data interface.
RESOLUTION DAC UPDATE
INPUT
LOGIC
PART
(BITS)
RATE (Msps)
Compatible versions with CMOS interfaces and 12-, 14-,
and 16-bit resolutions are also available. Refer to the
MAX5893 data sheet for 12-bit CMOS, MAX5894 for 14-
bit CMOS, and the MAX5895 for 16-bit CMOS versions.
MAX5893
MAX5894
MAX5895
MAX5898
12
14
16
16
500
500
500
500
CMOS
CMOS
CMOS
LVDS
Applications
Base Stations: 3G Multicarrier UMTS, CDMA, and GSM
Broadband Wireless Transmitters
Simplified Diagram
Broadband Cable Infrastructure
OUTI
DAC
DATA PORT
DATACLK
Instrumentation and Automatic Test Equipment (ATE)
Analog Quadrature Modulation Architectures
DAC
OUTQ
SPI is a trademark of Motorola, Inc.
cdma2000 is a registered trademark of Telecommunications
Industry Association.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
ABSOLUTE MAXIMUM RATINGS
DV
AV
, AV
, AV
to GND, DACREF ..................-0.3V to +2.16V
DOUT, DATACLKP, DATACLKN Continuous Current ..........8mA
DD1.8
DD3.3
DD1.8
, DV
to GND, DACREF........-0.3V to +3.9V
DD3.3
Continuous Power Dissipation (T = +70°C)
CLK
A
DATACLKP, DATACLKN, D0P–D15P,
D0N–D15N, SELIQP, SELIQN to GND,
DACREF ..........................................-0.3V to (DV
CS, RESET, SCLK, DIN, DOUT to
GND, DACREF ................................-0.3V to (DV
CLKP, CLKN to GND, DACREF..............-0.3V to (AV
68-Pin QFN (derate 41.7mW/°C above +70°C)
(Note 1) ...................................................................3333.3mW
Junction Temperature......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
+ 0.3V)
DD1.8
DD3.3
CLK
DD3.3
+ 0.3V)
+ 0.3V)
+ 0.3V)
REFIO, FSADJ to GND, DACREF ........-0.3V to (AV
OUTIP, OUTIN, OUTQP,
OUTQN to GND, DACREF...............-0.3V to (AV
+ 0.3V)
DD3.3
Note 1: Thermal resistance based on a multilayer board with 4 x 4 via array in exposed paddle area.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(DV
= AV
= 1.8V, AV
= AV
= DV
= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
DD3.3
DD1.8
DD1.8
CLK
DD3.3
50Ω double-terminated, external reference at 1.25V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C,
A
A
unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
16
1
Bits
LSB
LSB
%FS
ppm/°C
%FS
ppm/°C
mA
Differential Nonlinearity
Integral Nonlinearity
Offset Error
DNL
INL
OS
3
-0.02
-4
0.003 +0.02
0.03
Offset Drift
Gain Error
GE
(Note 3)
(Note 3)
0.06
110
+4
FS
Gain-Error Drift
Full-Scale Output Current
Output Compliance
I
2
20
OUTFS
-0.5
+1.1
V
Output Resistance
R
C
1
5
MΩ
OUT
Output Capacitance
DYNAMIC PERFORMANCE
Maximum Clock Frequency
Minimum Clock Frequency
Maximum DAC Update Rate
Minimum DAC Update Rate
Maximum Data Clock Frequency
Maximum Input Data Rate
pF
OUT
f
f
500
500
MHz
MHz
CLK
10
10
CLK
f
f
f
= f
= f
or f
or f
= f
= f
/ 2
/ 2
Msps
Msps
MHz
DAC
DAC
DAC
CLK
DAC
DAC
CLK
f
DAC
CLK
CLK
f
Interleaved data
Per channel
250
125
DATACLK
f
MWps
DATA
No interpolation
2x interpolation
4x interpolation
-156
-157
-157
f
f
= 125Mwps,
DATA
= 16MHz, f
OUT
OFFSET
= 10MHz, -12dBFS
dBFS/
Hz
Noise Spectral Density
f
f
= 125Mwps,
DATA
= 16MHz, f
4x interpolation
-154
OUT
OFFSET
= 10MHz, 0dBFS
2
_______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(DV
= AV
= 1.8V, AV
= AV
= DV
= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
DD3.3
DD1.8
DD1.8
CLK
DD3.3
50Ω double-terminated, external reference at 1.25V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C,
A
A
unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
90
MAX
UNITS
f
f
f
f
f
f
f
f
f
= 10MHz
= 30MHz
= 50MHz
= 10MHz
= 30MHz
= 50MHz
= 10MHz
= 30MHz
= 50MHz
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
f
= 125Mwps,
interpolation off,
-0.1dBFS
DATA
84
77
79
89
f
= 125Mwps,
2x interpolation,
-0.1dBFS
DATA
In-Band SFDR
SFDR
83
dBc
(DC to f
/ 2)
DATA
92
89
f
= 125Mwps,
4x interpolation,
-0.1dBFS
DATA
83
89
No interpolation
2x interpolation
4x interpolation
-96
-99
-95
f
f
= 125Mwps,
DATA
= 9MHz, f
=
OUT1
OUT2
10MHz, -6.1dBFS
2x interpolation,
f
/ 4 complex
-81
-71
-94
-71
IM
f
f
f
= 125Mwps,
= 79MHz,
= 80MHz,
DATA
OUT1
OUT2
modulation
4x interpolation,
-6.1dBFS
f
IM
/ 4 complex
modulation
Two-Tone IMD
TTIMD
dBc
f
f
= 62.5Mwps,
= 9MHz, f
DATA
OUT1
=
8x interpolation
8x interpolation,
OUT2
10MHz, -6.1dBFS
f
f
= 62.5Mwps,
DATA
= 69MHz, f
f
IM
/ 4 complex
OUT1
OUT2
= 70MHz, -6.1dBFS
modulation
8x, highpass
interpolation,
f
f
= 62.5Mwps,
DATA
= 179MHz, f
-71
-89
OUT1
OUT2
f
IM
/ 4 complex
= 180MHz, -6.1dBFS
modulation
f
= 125Mwps, f
spaced 1MHz
OUT
apart from 32MHz, -12dBFS, 2x
interpolation
DATA
Four-Tone IMD
FTIMD
ACLR
dBc
4x interpolation
8x interpolation
79
79
f
f
= 61.44Mwps,
= baseband
DATA
OUT
2x interpolation,
f
f
= 122.88Mwps,
= 61.44MHz
DATA
f
IM
/ 4 complex
76
68
ACLR for WCDMA
(Note 4)
OUT
modulation
dB
4x interpolation,
f
f
= 122.88Mwps,
= 122.88MHz
DATA
f
IM
/ 4 complex
OUT
modulation
_______________________________________________________________________________________
3
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(DV
= AV
= 1.8V, AV
= AV
= DV
= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
DD3.3
DD1.8
DD1.8
CLK
DD3.3
50Ω double-terminated, external reference at 1.25V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C,
A
A
unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Propagation Delay
Output Rise Time
t
1x interpolation (Note 5)
10% to 90% (Note 6)
10% to 90% (Note 6)
To 0.5% (Note 6)
2.9
0.75
1
ns
ns
PD
t
RISE
Output Fall Time
t
ns
FALL
Output Settling Time
Output Bandwidth
11
ns
-1dB bandwidth (Note 7)
240
MHz
0.4 x
Passband Width
Ripple < -0.01dB
f
DATA
100
100
100
22
0.604 x f
0.604 x f
0.604 x f
, 2x interpolation
, 4x interpolation
, 8x interpolation
DATA
DATA
DATA
Stopband Rejection
dB
1x interpolation
2x interpolation
4x interpolation
8x interpolation
70
Clock
Cycles
Data Latency
146
311
DAC INTERCHANNEL MATCHING
Gain Match
ΔGain
ΔGain/°C
ΔPhase
f
I
f
I
I
f
= DC - 80MHz, I
= 20mA
0.1
0.02
0.13
0.006
0.04
-95
dB
ppm/°C
Deg
OUT
OUTFS
Gain-Match Tempco
Phase Match
= 20mA
OUTFS
= 60MHz, I
= 20mA
OUT
OUTFS
Phase-Match Tempco
DC Gain Match
ΔPhase/°C
= 20mA
Deg/°C
dB
OUTFS
OUTFS
= 20mA (Note 3)
= 250MHz
-0.2
+0.2
Crosstalk
= 50MHz, f
dB
OUT
DAC
REFERENCE
Reference Input Range
Reference Output Voltage
Reference Input Resistance
Reference Voltage Drift
0.12
1.14
1.32
1.28
V
V
V
Internal reference
1.2
10
50
REFIO
R
kΩ
REFIO
ppm/°C
CMOS LOGIC INPUTS (SCLK, CS, RESET, DIN)
0.7 x
Input High Voltage
Input Low Voltage
V
V
V
IH
DV
DD3.3
0.3 x
V
IL
DV
DD3.3
Input Current
I
-10
0.1
3
+10
µA
pF
IN
Input Capacitance
C
IN
CMOS LOGIC OUTPUT (DOUT)
0.8 x
Output High Voltage
V
I
I
= 200µA
= 200µA
V
OH
LOAD
DV
DD3.3
0.2 x
Output Low Voltage
V
V
OL
SINK
DV
DD3.3
Output Leakage Current
Tri-state
1
µA
4
_______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(DV
= AV
= 1.8V, AV
= AV
= DV
= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
DD3.3
DD1.8
DD1.8
CLK
DD3.3
50Ω double-terminated, external reference at 1.25V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C,
A
A
unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Rise/Fall Time
C
= 10pF, 20% to 80%
1.5
ns
LOAD
LVDS LOGIC INPUTS (D15P–D0P, D15N–D0N, SELIQP, SELIQN)
Differential Input Logic High
Differential Input Logic Low
Input Common-Mode Voltage
Differential Input Resistance
Input Capacitance
V
100
mV
mV
V
IH
V
-100
IL
V
1.125
1.25
110
2.5
1.375
ICM
R
Ω
IN
IN
C
pF
LVDS CLOCK INPUT/OUTPUT (DATACLKP, DATACLKN)
Differential Input Amplitude High
Differential Input Amplitude Low
Differential Output Amplitude High
Differential Output Amplitude Low
Output Common-Mode Voltage
V
250
250
mV
mV
mV
mV
V
IH
V
-250
-250
IL
V
R
R
= 100Ω differential (Note 3)
= 100Ω differential (Note 3)
340
-340
1.25
OH
LOAD
V
OL
LOAD
V
OCM
R
= 100Ω differential, C
= 8pF,
LOAD
LOAD
Output Rise/Fall Time
0.9
ns
20% to 80%
CLOCK INPUTS (CLKP, CLKN) (Note 8)
Sine-wave input
> 1.5
> 0.5
> 100
Differential Input Voltage Swing
Differential Input Slew Rate
Common-Mode Voltage
V
V
P-P
DIFF
Square-wave input
V/µs
V
AV
/
CLK
2
V
AC-coupled
COM
Differential Input Resistance
Differential Input Capacitance
Minimum Clock Duty Cycle
Maximum Clock Duty Cycle
R
C
5
5
kΩ
pF
%
CLK
CLK
45
55
%
CLKP/CLKN, DATACLK TIMING (Figure 4) (Note 9)
CLK to DATACLK Delay
Data Hold Time
t
DATACLK output mode
1.4
ns
ns
ns
D
t
1.65
DH
Data Setup Time
t
-0.65
DS
SERIAL-PORT INTERFACE TIMING (Figure 3) (Note 9)
SCLK Frequency
f
10
MHz
ns
SCLK
CS Setup Time
t
2.5
0
SS
Input Hold Time
t
ns
SDH
Input Setup Time
t
t
4.5
6.5
ns
SDS
SDV
Data Valid Duration
POWER SUPPLIES
Digital Supply Voltage
Digital I/O Supply Voltage
16.5
ns
DV
DV
1.71
3.0
1.8
3.3
1.89
3.6
V
V
DD1.8
DD3.3
_______________________________________________________________________________________
5
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(DV
= AV
= 1.8V, AV
= AV
= DV
= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
DD3.3
DD1.8
DD1.8
CLK
DD3.3
50Ω double-terminated, external reference at 1.25V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C,
A
A
unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
AV
CONDITIONS
MIN
TYP
MAX
UNITS
Clock Supply Voltage
3.135
3.135
1.71
3.3
3.3
1.8
3.465
3.465
1.89
V
CLK
AV
AV
DD3.3
DD1.8
Analog Supply Voltage
Analog Supply Current
V
f
f
= 250MHz, 2x interpolation, 0dBFS,
= 10MHz
CLK
OUT
I
111
27
130
32
250
12
4
AVDD3.3
AVDD1.8
DVDD1.8
DVDD3.3
mA
f
f
= 250MHz, 2x interpolation, 0dBFS,
= 10MHz
CLK
OUT
I
f
f
= 250MHz, 2x interpolation, 0dBFS,
= 10MHz
CLK
OUT
Digital Supply Current
Digital I/O Supply Current
Clock Supply Current
Total Power Dissipation
I
I
229
9
mA
mA
mA
mW
f
f
= 250MHz, 2x interpolation, 0dBFS,
= 10MHz
CLK
OUT
f
f
= 250MHz, 2x interpolation, 0dBFS,
= 10MHz
CLK
I
2.3
831
AVCLK
OUT
f
f
= 250MHz, 2x interpolation, 0dBFS,
= 10MHz
CLK
P
TOTAL
OUT
AV
AV
DV
DV
AV
530
1
DD3.3
DD1.8
DD1.8
DD3.3
CLK
All I/O are static high or
low, bit 2 to bit 4 of
address 00h are set high
Power-Down Current
26
350
2
µA
AV
Ratio
Power-Supply Rejection
DD3.3
PSRR
(Note 10)
0.125
%FS/V
A
Note 2: All specifications are 100% tested at T ≥ +25°C. Specifications at T < +25°C are guaranteed by design and characterization.
A
A
Note 3: Specification is 100% production tested at T ≥ +25°C.
A
Note 4: 3.84MHz bandwidth, single carrier.
Note 5: Excludes data latency.
Note 6: Measured single-ended into a 50Ω load.
Note 7: Excludes sin(x)/x rolloff.
Note 8: Differential voltage swing defined as V + V
.
I PI I NI
V(CLKN)
V
V
N
P
V(CLKP)
Note 9: Guaranteed by design and characterization.
Note 10:Parameter defined as the change in midscale output caused by a 5% variation in the nominal supply voltage.
6
_______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Typical Operating Characteristics
(DV
= AV
= 1.8V, AV
= AV
= DV
= 3.3V, DATACLK output mode, external reference, V
= +1.25V,
DD1.8
DD1.8
CLK
DD3.3
DD3.3
REFIO
R
LOAD
= 50Ω double-terminated, I = 20mA, T = +25°C, unless otherwise noted.)
OUTFS A
SFDR vs. OUTPUT FREQUENCY
= 125Mwps, NO INTERPOLATION
IN-BAND SFDR vs. OUTPUT FREQUENCY
0UT-OF-BAND SFDR vs. OUTPUT FREQUENCY
= 125Mwps, 2x INTERPOLATION
f
f
= 125Mwps, 2x INTERPOLATION
f
DATA
DATA
DATA
120
100
80
60
40
20
0
120
100
80
60
40
20
0
100
90
80
70
60
50
40
30
20
10
0
-0.1dBFS
-12dBFS
-0.1dBFS
-6dBFS
-6dBFS
-0.1dBFS
-6dBFS
-12dBFS
-12dBFS
-0.1dBFS
SPURS MEASURED BETWEEN
62.5MHz AND 125MHz
SPURS MEASURED BETWEEN
0MHz AND 62.5MHz
0
10
20
30
40
50
60
0
10
20
30
40
50
0
10
20
30
40
50
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
IN-BAND SFDR vs. OUTPUT FREQUENCY
IN-BAND SFDR vs. OUTPUT FREQUENCY
= 125Mwps, 4x INTERPOLATION
OUT-OF-BAND SFDR vs. OUTPUT FREQUENCY
f
= 125Mwps, 2x INTERPOLATION
f
f = 125Mwps, 4x INTERPOLATION
DATA
DATA
DATA
90
80
70
60
50
40
30
20
10
0
120
100
80
60
40
20
0
90
80
70
60
50
40
30
20
10
0
-6dBFS -0.1dBFS
-0.1dBFS
-0.1dBFS
-6dBFS
-6dBFS
-12dBFS
-0.1dBFS
-12dBFS
-12dBFS
UPPER SIDEBAND MODULATION
SPURS MEASURED BETWEEN
62.5MHz AND 125MHz
SPURS MEASURED BETWEEN
0MHz AND 62.5MHz
SPURS MEASURED BETWEEN
62.5MHz AND 250MHz
62.5
72.5
82.5
92.5
102.5
112.5
0
10
20
30
40
50
0
10
20
30
40
50
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
IN-BAND SFDR vs. OUTPUT FREQUENCY
IN-BAND SFDR vs. OUTPUT FREQUENCY
TWO-TONE IMD vs. OUTPUT FREQUENCY
f
= 125Mwps, 4x INTERPOLATION
f
= 125Mwps, 4x INTERPOLATION
f
= 125Mwps, NO INTERPOLATION
DATA
DATA
DATA
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
0
-20
1MHz CARRIER SPACING
-0.1dBFS
-12dBFS
-0.1dBFS
-6dBFS
-40
-12dBFS
-6dBFS
-60
-6dBFS
-12dBFS
-80
LOWER SIDEBAND MODULATION
SPURS MEASURED BETWEEN
62.5MHz AND 125MHz
LOWER SIDEBAND MODULATION
SPURS MEASURED BETWEEN
125MHz AND 187.5MHz
-100
-120
-9dBFS
70
80
90
100
110
120
70
80
90
100
110
120
10
15
20
25
30
35
40
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
CENTER FREQUENCY (MHz)
_______________________________________________________________________________________
7
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Typical Operating Characteristics (continued)
(DV
= AV
= 1.8V, AV
= AV
= DV
= 3.3V, DATACLK output mode, external reference, V
= +1.25V,
DD1.8
DD1.8
CLK
DD3.3
DD3.3
REFIO
R
= 50Ω double-terminated, I = 20mA, T = +25°C, unless otherwise noted.)
OUTFS A
LOAD
CHANNEL-TO-CHANNEL
GAIN MISMATCH vs. TEMPERATURE
TWO-TONE IMD vs. OUTPUT FREQUENCY
= 125Mwps, 2x INTERPOLATION
TWO-TONE IMD vs. OUTPUT FREQUENCY
f
f
= 125Mwps, 4x INTERPOLATION
f
= 125Mwps, 2x INTERPOLATION
DATA
DATA
DATA
0
-20
0
-20
0.100
0.075
0.050
0.025
0
1MHz CARRIER SPACING
COMPLEX MODULATION FOR
OUTPUT FREQUENCIES
GREATER THAN 50MHz
1MHz CARRIER SPACING
COMPLEX MODULATION FOR
OUTPUT FREQUENCIES
GREATER THAN 50MHz
f
A
= 22.7MHz
= -6dBFS
OUT
OUT
-40
-40
-6dBFS
-6dBFS
-60
-60
-12dBFS
-12dBFS
-80
-80
-12dBFS
135
-100
-120
-100
-120
-9dBFS
-6dBFS
-9dBFS
-6dBFS
25
10
40
55
70
85
100
10
35
60
85
110
160
-40
-15
10
35
60
85
CENTER FREQUENCY (MHz)
CENTER FREQUENCY (MHz)
TEMPERATURE (°C)
EIGHT-TONE POWER RATIO PLOT
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
f
= 125Mwps, 2x INTERPOLATION
DATA
-20
-30
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
4.0
3.0
-40
2.0
-50
1.0
-60
-70
0
-1.0
-2.0
-3.0
-4.0
-5.0
-80
-90
-100
-110
-120
-0.5
-1.0
16,384
32,768
49,152
16,384
32,768
49,152
f
= 35.7MHz, 1MHz TONE SPACING
0
65,536
0
65,536
CENTER
SPAN = 12.5MHz, A
THROUGH A
= -18dBFS
OUT1
OUT8
DIGITAL INPUT CODE
DIGITAL INPUT CODE
SUPPLY CURRENT vs. DAC UPDATE RATE
SUPPLY CURRENT vs. DAC UPDATE RATE
SUPPLY CURRENT vs. DAC UPDATE RATE
2x INTERPOLATION, f
= 5MHz
4x INTERPOLATION, f
= 5MHz
8x INTERPOLATION, f = 5MHz
OUT
OUT
OUT
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
1.8V TOTAL
1.8V TOTAL
1.8V TOTAL
3.3V TOTAL
3.3V TOTAL
3.3V TOTAL
0
0
0
100
150
200
250
300
100
200
300
(MHz)
400
500
100
200
300
(MHz)
400
500
f
(MHz)
f
f
DAC
DAC
DAC
8
_______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Typical Operating Characteristics (continued)
(DV
= AV
= 1.8V, AV
= AV
= DV
= 3.3V, DATACLK output mode, external reference, V
= +1.25V,
DD1.8
DD1.8
CLK
DD3.3
DD3.3
REFIO
R
= 50Ω double-terminated, I = 20mA, T = +25°C, unless otherwise noted.)
OUTFS A
LOAD
NOISE DENSITY vs. DAC UPDATE RATE
= 16MHz, A = -12dBFS, 10MHz OFFSET
WCDMA ACLR vs. OUTPUT FREQUENCY
WCDMA ACLR vs. OUTPUT FREQUENCY
f
f
= 122.88Mwps, 4x INTERPOLATION
f
= 76.8Mwps, 4x INTERPOLATION
OUT
OUT
DATA
DATA
100
90
80
70
60
50
40
100
90
80
70
60
50
40
-100
-110
-120
-130
-140
-150
-160
-170
-180
ONE-CARRIER
ALTERNATE CHANNEL
ONE-CARRIER
ALTERNATE CHANNEL
ONE-CARRIER
ADJACENT CHANNEL
ONE-CARRIER
ADJACENT CHANNEL
4x INTERPOLATION
8x INTERPOLATION
FOUR-CARRIER
ALTERNATE CHANNEL
FOUR-CARRIER
ALTERNATE CHANNEL
FOUR-CARRIER
ADJACENT CHANNEL
FOUR-CARRIER
ADJACENT CHANNEL
2x INTERPOLATION
100
200
300
(MHz)
400
500
0
30.72
61.44
92.16 122.88 153.60
0
15.36 30.72 46.08 61.44 76.80 92.16 107.50
(MHz)
f
f
(MHz)
f
CENTER
DAC
CENTER
WCDMA ACLR SPECTRAL PLOT
= 61.44Mwps, 8x INTERPOLATION
FOUR-CARRIER WCDMA ACLR SPECTRAL PLOT
= 61.44Mwps, 8x INTERPOLATION
WCDMA ACLR SPECTRAL PLOT
f
f
f
= 122.88Mwps, 4x INTERPOLATION
DATA
DATA
DATA
-20
-30
-20
-20
-30
-30
-40
-40
-40
-50
-50
-50
-60
-60
-60
-70
-70
-70
-80
-80
-80
-90
-90
-90
-100
-110
-120
-100
-110
-120
-100
-110
-120
f
= 61.44MHz
f
= 61.44MHz
f
= 122.88MHz
CENTER
CENTER
CENTER
SPAN = 25.5MHz
SPAN = 40.6MHz
SPAN = 25.5MHz
FOUR-CARRIER WCDMA ACLR SPECTRAL PLOT
= 122.88Mwps, 4x INTERPOLATION
f
DATA
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
f
= 122.88MHz
CENTER
SPAN = 40.6MHz
_______________________________________________________________________________________
9
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Pin Description
PIN
1
NAME
CLKP
FUNCTION
Noninverting Differential Clock Input. Internally biased to AV
/ 2.
CLK
/ 2.
2
CLKN
Inverting Differential Clock Input. Internally biased to AV
Internally Connected. Do not connect.
CLK
3
N.C.
4
DATACLKP
DATACLKN
LVDS Data Clock Input/Output. External 100Ω termination to DATACLKN required.
5
Complementary LVDS Data Clock Input/Output. External 100Ω termination to DATACLKP required.
Digital Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to ground with a
0.1µF capacitor as close to the pin as possible.
6, 21, 30, 37
DV
DD1.8
Complementary LVDS Channel Select Input. Set SELIQN low and SELIQP high to direct data to
the channel. Set SELIQP low and SELIQN high to direct data to the channel. Internal 110Ω
termination to SELIQP.
7
SELIQN
SELIQP
LVDS Channel Select Input. Set SELIQN low and SELIQP high to direct data to the channel. Set
SELIQP low and SELIQN high to direct data to the channel. Internal 110Ω termination to SELIQN.
8
9
D15N
D15P
D14N
D14P
D13N
D13P
D12N
D12P
D11N
D11P
D10N
D10P
D9N
Complementary LVDS Data Bit 15 (MSB). Internal 110Ω termination to D15P.
LVDS Data Bit 15 (MSB). Internal 110Ω termination to D15N.
Complementary LVDS Data Bit 14. Internal 110Ω termination to D14P.
LVDS Data Bit 14. Internal 110Ω termination to D14N.
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
26
27
28
29
31
32
33
34
Complementary LVDS Data Bit 13. Internal 110Ω termination to D13P.
LVDS Data Bit 13. Internal 110Ω termination to D13N.
Complementary LVDS Data Bit 12. Internal 110Ω termination to D12P.
LVDS Data Bit 12. Internal 110Ω termination to D12N.
Complementary LVDS Data Bit 11. Internal 110Ω termination to D11P.
LVDS Data Bit 11. Internal 110Ω termination to D11N.
Complementary LVDS Data Bit 10. Internal 110Ω termination to D10P.
LVDS Data Bit 10. Internal 110Ω termination to D10N.
Complementary LVDS Data Bit 9. Internal 110Ω termination to D9P.
LVDS Data Bit 9. Internal 110Ω termination to D9N.
D9P
D8N
Complementary LVDS Data Bit 8. Internal 110Ω termination to D8P.
LVDS Data Bit 8. Internal 110Ω termination to D8N.
D8P
D7N
Complementary LVDS Data Bit 7. Internal 110Ω termination to D7P.
LVDS Data Bit 7. Internal 110Ω termination to D7N.
D7P
D6N
Complementary LVDS Data Bit 6. Internal 110Ω termination to D6P.
LVDS Data Bit 6. Internal 110Ω termination to D6N.
D6P
D5N
Complementary LVDS Data Bit 5. Internal 110Ω termination to D5P.
LVDS Data Bit 5. Internal 110Ω termination to D5N.
D5P
D4N
Complementary LVDS Data Bit 4. Internal 110Ω termination to D4P.
LVDS Data Bit 4. Internal 110Ω termination to D4N.
D4P
10 ______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Pin Description (continued)
PIN
35
36
38
39
40
41
42
43
NAME
D3N
D3P
D2N
D2P
D1N
D1P
D0N
D0P
FUNCTION
Complementary LVDS Data Bit 3. Internal 110Ω termination to D3P.
LVDS Data Bit 3. Internal 110Ω termination to D3N.
Complementary LVDS Data Bit 2. Internal 110Ω termination to D2P.
LVDS Data Bit 2. Internal 110Ω termination to D2N.
Complementary LVDS Data Bit 1. Internal 110Ω termination to D1P.
LVDS Data Bit 1. Internal 110Ω termination to D1N.
Complementary LVDS Data Bit 0 (LSB). Internal 110Ω termination to D0P.
LVDS Data Bit 0 (LSB). Internal 110Ω termination to D0N.
I/O Power Supply. Accepts a 3.0V to 3.6V supply range. Bypass with a 0.1µF capacitor as close to
the pin as possible.
44
DV
DD3.3
45
46
47
48
49
50
DOUT
DIN
Serial-Port Data Output
Serial-Port Data Input
SCLK
CS
Serial-Port Clock Input. Data on DIN is latched on the rising edge of SCLK.
Serial-Port Interface Select. Drive CS low to enable serial-port interface.
Reset Input. Hold RESET low during power-up.
RESET
REFIO
Reference Input/Output. Bypass to ground with a 1µF capacitor as close to the pin as possible.
Current-Set Resistor Return Path. For a 20mA full-scale output current, use a 1.25V external reference
and connect a 2kΩ resistor between FSADJ and DACREF. Internally connected to GND. DO NOT USE
AS AN EXTERNAL GROUND CONNECTION.
51
DACREF
FSADJ
Full-Scale Adjust Input. For a 20mA full-scale output current, use a 1.25V external reference and
connect a 2kΩ resistor between FSADJ and DACREF.
52
Low Analog Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to GND with
a 0.1µF capacitor as close to the pin as possible.
53, 67
AV
DD1.8
54, 56, 59, 61,
64, 66
GND
Ground
Analog Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass each pin to GND with a
0.1µF capacitor as close to the pin as possible.
55, 60, 65
AV
DD3.3
57
58
62
63
OUTQN
OUTQP
OUTIN
OUTIP
Inverting Differential DAC Current Output for Q Channel
Noninverting Differential DAC Current Output for Q Channel
Inverting Differential DAC Current Output for I Channel
Noninverting Differential DAC Current Output for I Channel
Clock Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass to ground with a 0.1µF
capacitor as close to the pin as possible.
68
EP
AV
CLK
GND
Exposed Paddle. Must be connected to GND through a low-impedance path.
______________________________________________________________________________________ 11
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Functional Diagram
MODULATOR
DIGITAL
OFFSET
ADJUST
DIGITAL
GAIN
ADJUST
OUTIP
OUTIN
∑
IDAC
∑
D0–D15
f
DAC
DATACLK
I
Q
MAX5898
f
IM
I
/ 2, f / 4
IM
DIGITAL
OFFSET
ADJUST
Q
DIGITAL
GAIN
ADJUST
SELIQ
OUTQP
OUTQN
QDAC
∑
∑
f
DAC
/2
/2
/2
/2
CONTROL REGISTERS
SERIAL INTERFACE
f
CLK
CLOCK BUFFERS
AND DIVIDERS
REFERENCE
RESET
DOUT
DIN
CS
SCLK
DACREF FSADJ
REFIO
CLKN
CLKP
rate by a factor of eight, providing an eight-fold increase
in separation between the reconstructed waveform spec-
trum and its first image. The MAX5898 accepts either
two’s complement or offset binary input data format on a
single interleaved LVDS input bus.
Detailed Description
The MAX5898 dual, 500Msps, high-speed, 16-bit, cur-
rent-output DAC provides superior performance in com-
munication systems requiring low-distortion analog-signal
reconstruction. The MAX5898 combines two DAC cores
with 8x/4x/2x programmable digital interpolation filters, a
digital quadrature modulator, an SPI-compatible serial
interface for programming the device, and an on-chip
1.2V reference. Individual DAC channel gain and offset
adjustments are available to compensate for downstream
signal-path imbalances. The full-scale output current
range is adjustable from 2mA to 20mA to optimize power
dissipation and gain control.
The MAX5898 includes modulation modes at f / 2 and
IM
f
IM
/ 4, where f is the data rate at the input of the mod-
IM
ulator. If 2x interpolation is used, this data rate is 2x the
input data rate. If 4x or 8x interpolation is used, this data
rate is 4x the input data rate. Table 1 summarizes the
modulator operating data rates.
The power-down modes can be used to turn off each
DAC’s output current or the entire digital section.
Programming both DACs into power-down simultane-
ously powers down the digital interpolation filters. Note
that the SPI section is always active.
Each channel contains three selectable interpolating fil-
ters making the MAX5898 capable of 2x, 4x, 8x, or no
interpolation, which allows for low input data rates and
high DAC update rates. When operating in 8x interpola-
tion mode, the interpolator increases the DAC conversion
The analog and digital sections of the MAX5898 have
separate power-supply inputs (AV
, AV
,
DD1.8
DD3.3
12 ______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
AV
, DV
, and DV ), which minimize noise
DD1.8
The serial interface supports two-byte transfer in a
communication cycle. The first byte is a control byte
written to the MAX5898 only. The second byte is a data
byte and can be written to or read from the MAX5898.
When writing to the MAX5898, data is shifted into DIN;
data is shifted out of DOUT in a read operation. Bits 0 to
3 of the control byte are the address bits. These bits set
the address of the register to be written to or read from.
Bits 4 to 6 of the control byte must always be set to 0.
Bit 7 is a read/write bit: 0 for write operation and 1 for
read operation. The most significant bit (MSB) is shifted
in first in default mode. If the serial port is set to LSB-first
mode, both the control byte and data byte are shifted LSB
first. Figures 1 and 2 show the SPI serial-interface opera-
tion in the default write and read mode, respectively.
Figure 3 is a timing diagram for the SPI serial interface.
CLK
DD3.3
coupling from one supply to the other. AV
and
DD1.8
DV
operate from a typical 1.8V supply, and all
DD1.8
other supply inputs operate from a typical 3.3V supply.
Serial Interface
The SPI-compatible serial interface programs the
MAX5898 registers. The serial interface consists of CS,
DIN, SCLK, and DOUT. Data is shifted into DIN on the
rising edge of SCLK when CS is low. When CS is high,
data presented at DIN is ignored and DOUT is in high-
impedance mode. Note: CS must transition high
after each read/write operation. DOUT is the serial
data output for reading registers to facilitate easy
debugging during development. DIN and DOUT can
be connected together to form a 3-wire serial interface
bus or remain separate and form a 4-wire SPI bus.
Table 1. Quadrature Modulator Operating Data Rates (fIM is the Data Rate at the Input of
the Modulator)
MODULATION FREQUENCY
RELATIVE TO f
MODULATION FREQUENCY
RELATIVE TO f
INTERPOLATION RATE
MODULATION MODE (f
)
LO
DAC
DATA
f
IM
f
IM
f
IM
f
IM
f
IM
f
IM
f
IM
f
IM
/ 2
/ 4
/ 2
/ 4
/ 2
/ 4
/ 2
/ 4
f
f
f
f
f
f
f
f
/ 2
/ 4
/ 2
/ 4
/ 2
/ 4
/ 4
/ 8
f
f
/ 2
/ 4
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DATA
DATA
1x
2x
4x
8x
f
DATA
f
/ 2
DATA
2 x f
DATA
f
DATA
2 x f
DATA
f
DATA
CS
SCLK
0
0
0
0
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
DIN
HIGH IMPEDANCE
DOUT
Figure 1. SPI Serial-Interface Write Cycle, MSB-First Mode
______________________________________________________________________________________ 13
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
CS
READ CYCLE N - 1
READ CYCLE N
READ CYCLE N + 1
SCLK
DIN
ADDRESS
DATA
ADDRESS
DATA
ADDRESS
DATA
1 0 0 0 3 2 1 0
1 0 0 0 3 2 1 0
1 0 0 0 3 2 1 0
IGNORED
IGNORED
IGNORED
HIGH
IMPEDANCE
HIGH
HIGH
DOUT
DATA N - 2
DATA N - 1
DATA N
IMPEDANCE
IMPEDANCE
Figure 2. SPI Serial-Interface Read Cycle, MSB-First Mode
t
SS
CS
SCLK
DIN
t
t
SDH
SDS
t
SDV
DOUT
Figure 3. SPI Serial-Interface Timing Diagram
14 ______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
of the registers. The following are descriptions of each
register.
Programming Registers
Programming its registers with the SPI serial interface
sets the MAX5898 operation modes. Table 2 shows all
Table 2. MAX5898 Programmable Registers
ADD
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Software Reset
0 = Normal
1 = Reset all
registers
Interpolator
Power-Down
0 = Normal
IDAC Power-
Down
0 = Normal
QDAC Power-
Down
0 = Normal
0 = MSB first
1 = LSB first
00h Unused
Unused
1 = Power-down 1 = Power-down 1 = Power-down
Interpolation Rate
(Bit 7, Bit 6)
00 = No interpolation
01 = 2x interpolation
10 = 4x interpolation
11 = 8x interpolation
Third
Interpolation
Filter
Configuration
0 = Lowpass
1 = Highpass
Modulation Mode
(Bit 4, Bit 3)
00 = Modulation off
01 = f / 2
IM
10 = f / 4
IM
11 = f / 4
IM
Mixer Modulation Modulation
Mode
Sign
0 = e-jω
1 = e+jω
01h
02h
Unused
0 = Complex
1 = Real
0 = Input data
latched on
rising clock
edge
1 = Input data
latched on falling
clock edge
0 = Two’s-
complement
input data
1 = Offset
binary input
data
Data
Synchronizer
Disable
0 = Enabled
1 = Disabled
0 = Data clock
output disabled
1 = Data clock
output enabled
Unused
Unused
Unused
03h Unused
04h 8-Bit IDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h
4-Bit IDAC Coarse-Gain Adjustment (see the Gain Adjustment
section). Bit 3 is MSB and bit 0 is LSB. Default: Fh
05h Unused
10-Bit IDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 06h register are the MSB bits. Bit 1 and bit 0 are the LSB
bits in the 07h register. Default: 000h
06h
IDAC IOFFSET
Direction
0 = Current on
OUTIN
1 = Current on
OUTIP
IDAC Offset
Adjustment
Bit 1
(see the 06h
register)
IDAC Offset
Adjustment
Bit 0
(see the 06h
register)
07h
Unused
08h 8-Bit QDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h
4-Bit QDAC Coarse-Gain Adjustment (see the Gain Adjustment
section). Bit 3 is MSB and bit 0 is LSB. Default: Fh
09h Unused
10-Bit QDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 0Ah register are the MSB bits. Bit 1 and bit 0 are the
LSB bits in the 0Bh register. Default: 000h
0Ah
0Bh
QDAC
IOFFSET
QDAC Offset QDAC Offset
Direction
0 = Current on
OUTQN
1 = Current on
OUTQP
Adjustment
Bit 1
(see the 0Ah
register)
Adjustment
Bit 0
(see the 0Ah
register)
Unused
0Ch Reserved, do not write to these bits.
0Dh Reserved, do not write to these bits.
0Eh Reserved, do not write to these bits.
Conditions in bold are power-up defaults.
______________________________________________________________________________________ 15
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Address 00h
Bit 2
Configures the modulation mode for either
real or complex (image reject) modulation.
Logic 1 sets the modulator to the real mode
(default). Complex modulation is only avail-
Bit 6
Logic 0 (default) causes the serial port to use
MSB first address/data format. When set to a
logic 1, the serial port uses LSB first address/
data format.
able for f / 4 modulation.
IM
Bit 1
Quadrature modulator sign inversion. With I-
channel data leading Q-channel data by 90°,
logic 0 sets the complex modulation to be
e-jw (default), cancelling the upper image. A
logic 1 sets the complex modulation to be
e+jw, cancelling the lower image.
Bit 5
Bit 4
When set to a logic 1 (default = 0), all registers
reset to their default state (this bit included).
Logic 1 (default = 0) stops the clock to the
digital interpolators. DAC outputs hold last
value prior to interpolator power-down.
Bit 3
Bit 2
IDAC power-down mode. A logic 1 (default = 0)
to this bit shuts down the output current from
the IDAC.
Address 02h
Bit 7
Logic 0 (default) configures the data port for
two’s complement. A logic 1 configures the
data ports for offset binary.
QDAC power-down mode. A logic 1 (default = 0)
to this bit shuts down the output current from
the QDAC.
Bit 4
Logic 0 (default) sets the internal latches to
latch the data on the rising edge of DATACLK.
A logic 1 sets the internal latches to latch the
data on the falling edge of DATACLK.
Note: If both bit 2 and bit 3 are 1, the MAX5898 is in
full-power-down mode, leaving only the serial interface
active.
Bit 3
Bit 2
Logic 0 (default) configures the DATACLK
pin (pin 4 or pin 5) to be an input. A logic 1
configures the DATACLK pin to be an output.
Address 01h
Bits 7, 6 Configure the interpolation filters according
to the following:
Logic 0 (default) enables the data synchro-
nizer circuitry. A logic 1 disables the data
synchronizer circuitry.
00
01
10
11
1x (no interpolation)
2x
Address 04h
4x
Bits 7–0 These 8 bits define the binary number for
fine-gain adjustment of the IDAC full-scale
current (see the Gain Adjustment section). Bit
7 is the MSB. Default is all zeros.
8x (default)
Bit 5
Logic 0 configures FIR3 as a lowpass digital
filter (default). A logic 1 configures FIR3 as a
highpass digital filter.
Address 05h
Bits 4, 3 Configure the modulation frequency accord-
ing to the following:
Bits 3–0 These four bits define the binary number for
the coarse-gain adjustment of the IDAC full-
scale current (see the Gain Adjustment sec-
tion). Bit 3 is the MSB. Default is all ones.
00
01
10
11
No modulation
f
IM
f
IM
f
IM
/ 2 modulation
/ 4 modulation (default)
/ 4 modulation
Address 06h, Bits 7–0; Address 07h, Bit 1 and Bit 0
These 10 bits represent a binary number that
defines the magnitude of the offset added to
the IDAC output (see the Offset Adjustment
section). Default is all zeros.
where f is the data rate at the input of the
IM
modulator.
16 ______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Address 07h
Bit 7
default. The range for FINE is from 0 to 255 with 0
being the default. The gain can be adjusted in steps of
approximately 0.01dB.
Logic 0 (default) adds the 10 bits offset cur-
rent to OUTIN. A logic 1 adds the 10 bits off-
set current to OUTIP.
Data Input Port
The MAX5898 captures input data on a single LVDS
port (D15P/N–D0P/N). The channel for the input data is
determined through the state of SELIQP/SELIQN. When
SELIQP is set to logic-high and SELIQN is set to logic-
low the input data is presented to the I channel. Setting
SELIQP to logic-low and SELIQN to logic-high presents
the input data to the Q channel.
Address 08h
Bits 7–0 These 8 bits define the binary number for
fine-gain adjustment of the QDAC full-scale
current (see the Gain Adjustment section). Bit
7 is the MSB. Default is all zeros.
Address 09h
Bits 3–0 These four bits define the binary number for
the coarse-gain adjustment of the QDAC full-
scale current (see the Gain Adjustment sec-
tion). Bit 3 is the MSB. Default is all ones.
The MAX5898 control registers can be programmed to
allow either signed or unsigned binary format (bit 7,
address 02h) data. Table 3 shows the corresponding DAC
output levels when using signed or unsigned data modes.
Address 0Ah, Bits 7–0; Address 0Bh, Bit 1 and Bit 0
These 10 bits represent a binary number that
defines the magnitude of the offset added to
the QDAC output (see the Offset Adjustment
section). Default is all zeros.
Table 3. DAC Output Code Table
DIGITAL INPUT CODE
OFFSET
BINARY
(UNSIGNED)
TWO'S
COMPLEMENT
(SIGNED)
OUT_P OUT_N
Address 0Bh
Bit 7
Logic 0 (default) adds the 10 bits offset to
OUTQN. A logic 1 adds the 10 bits offset to
OUTQP.
0000 0000 0000 0000 1000 0000 0000 0000
0111 1111 1111 1111 0000 0000 0000 0000
1111 1111 1111 1111 0111 1111 1111 1111
0
I
OUTFS
I
/
I
/
OUTFS
2
OUTFS
2
Offset Adjustment
I
0
OUTFS
Offset adjustment is achieved by adding a digital code to
the DAC inputs. The code OFFSET (see equation below),
as stored in the relevant control registers, has a range
from 0 to 1023 and a sign bit. The applied DAC offset
is four times the code stored in the register, providing an
offset adjustment range of 4092 LSB codes. The resolu-
tion is 4 LSB.
Data Synchronization Modes
Data synchronization circuitry is provided to allow oper-
ation with an input data clock. The data clock must be
frequency locked to the DAC clock (f
), but can
DAC
have arbitrary phase with respect to the DAC clock.
The synchronization circuitry allows for phase jitter on
the input data clock of up to 1 data clock cycles.
Synchronization is initially established when the reset
pin is asynchronously deasserted and the input data
clock has been running for at least four clock cycles.
Subsequently, the MAX5898 monitors the phase rela-
4 × OFFSET
I
=
×I
OUTFS
OFFSET
16
2
Gain Trim
Gain adjustment is peformed by varying the full-scale
current according to the following formula:
tionship and detects if the phase drifts more than
1
data clock cycle. If this occurs, the synchronizer auto-
matically re-establishes synchronization. However, dur-
ing the resynchronization phase, up to 8 data words
may be lost or repeated.
⎡
⎢
⎣
⎤
⎛
⎠ ⎝
256
⎦
3 ×I
3 ×I
REF
32
⎛
⎞ COARSE +1
⎛
⎞ FINE
1024
24
⎛
⎞
⎛
⎞
⎞
REF
I
=
−
⎜
⎝
⎟
⎜
⎟
⎟⎥ ⎜
⎟
⎠
⎜
⎝
⎟
⎜
⎝
OUTFS
⎠
⎝
4
⎠
16
⎠
where I
is the reference current (see the Reference
Bit 2 of register 02h disables or enables (default) the
automatic data clock phase detection. Disabling the
data synchronization circuitry requires the data clock
and the DAC clock phase to be locked.
REF
Input/Output section). COARSE is the register content
of registers 05h and 09h for the I and Q channel,
respectively. FINE is the register content of register 04h
and 08h for the I and Q channel, respectively. The
range of COARSE is from 0 to 15, with 15 being the
______________________________________________________________________________________ 17
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
DATACLK Modes
Table 4. Clock Frequency Ratios in
Various Modes
The MAX5898 employs a differential LVDS DATACLK
located at pins 4 and 5. The DATACLK can be config-
ured as either an input or as an output (bit 3, address
02h). If DATACLK is configured as an output, it is fre-
quency-divided from the CLKP/CLKN input, depending
on the operating mode, see Table 4.
INTERPOLATION
f
:f
f
:f
DATA CLK
DAC CLK
RATE
1x
2x
4x
8x
1:1
1:1
1:2
1:4
1:2
1:1
1:1
1:1
The MAX5898 can be configured to latch the input
data on either the rising edge or falling edge of the
DATACLK signal (bit 4, address 02h). Figure 4 shows
the timing requirements between the DATACLK signal
and the input data bus with latching on the rising edge.
CLKP–CLKN
DATACLKP–DATACLKN
t
t
t
DH
D
DS
D0–D15
SELIQ
Figure 4. Data-Input Timing Diagram
18 ______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
ter is located after the modulator. In the 8x interpolation
mode, the last filter (FIR3) can be configured as low-
pass or highpass (bit 5, address 01h) to select the
lower or upper sideband from the modulation output.
The frequency responses of these three filters are plot-
ted in Figures 5–8.
Interpolating Filter
The MAX5898 features three cascaded FIR half-band
filters. The interpolating filters are enabled or disabled
in combinations to support 1x (no interpolation), 2x, 4x,
or 8x interpolation. Bits 7 and 6 of register 01h set the
interpolation rate (see Table 2). The last interpolation fil-
0
0
-20
-20
PASSBAND DETAIL
PASSBAND DETAIL
-40
-60
0
-0.0002
-0.0004
-40
0
-0.0002
-60
-0.0004
0.4
0.4
0
0.1
0.2
0.3
0.2
0.3
0.1
0
-80
-80
-100
-100
-120
-120
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
- NORMALIZED TO INPUT DATA RATE
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
- NORMALIZED TO INPUT DATA RATE
f
f
OUT
OUT
Figure 6. Interpolation Filter Frequency Response, 4x
Interpolation Mode
Figure 5. Interpolation Filter Frequency Response, 2x
Interpolation Mode
0
0
-20
-20
PASSBAND DETAIL
PASSBAND DETAIL
0
-40
-40
0
-0.0002
-0.0002
-60
-60
-0.0004
0.2
0.3
0.4
-0.0004
0.1
0
3.6
3.8
4.0
4.2
4.4
-80
-80
-100
-100
-120
-120
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
f
- NORMALIZED TO INPUT DATA RATE
f
- NORMALIZED TO INPUT DATA RATE
OUT
OUT
Figure 8. Interpolation Filter Frequency Response, 8x
Interpolation Mode (FIR3 Highpass Mode)
Figure 7. Interpolation Filter Frequency Response, 8x
Interpolation Mode (FIR3 Lowpass Mode)
______________________________________________________________________________________ 19
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
The programmable interpolation filters multiply the
MAX5898 input data rate by a factor of 2x, 4x, or 8x to
separate the reconstructed waveform spectrum and the
DAC image. The original spectral images, appearing at
around multiples of the input data rate, are attenuated
by the internal digital filters. This feature provides three
benefits:
2) Lower input data rates eliminate board-level high-
speed data transmission.
3) Sin(x)/x rolloff is reduced over the effective bandwidth.
Figure 9 illustrates a practical example of the benefits
when using the MAX5898 in 2x, 4x, and 8x interpolation
modes with the third filter configured as a lowpass filter.
With no interpolation filter, the first image signal appears
1) Image separation reduces complexity of analog
reconstruction filters.
in the second Nyquist zone between f / 2 and f . The first
S
S
interpolating filter removes this image. In fact, all of the
FILTER
RESPONSE
NO INTERPOLATION
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
IMAGE
INPUT
SPECTRUM
AND FIRST
FILTER
RESPONSE
f
f
f
f
2f
2f
2f
2f
3f
3f
3f
3f
4f
4f
4f
4f
5f
5f
5f
5f
6f
6f
6f
6f
7f
7f
7f
7f
8f
8f
8f
8f
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
IMAGE
2x INTERPOLATION
4x INTERPOLATION
8x INTERPOLATION
OUTPUT
SPECTRUM
OF THE
FIRST
FILTER
FILTER
RESPONSE
INPUT
SPECTRUM
AND
SECOND
FILTER
RESPONSE
IMAGE
OUTPUT
SPECTRUM
OF THE
SECOND
FILTER
IMAGE
INPUT
IMAGE
FILTER
SPECTRUM
AND THIRD
FILTER
RESPONSE
RESPONSE
f
f
2f
2f
3f
S
4f
4f
5f
5f
6f
6f
7f
S
8f
8f
S
S
S
S
S
S
OUTPUT
SPECTRUM
OF THE
THIRD
IMAGE
FILTER
3f
S
7f
S
S
S
S
S
S
S
Figure 9. Spectral Representation of Interpolating Filter Responses (Output Frequencies are Relative to the Data Input Frequency, f )
S
20 ______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
images at odd numbers of f are filtered. At the output of
10f , etc. Finally, the third filter removes images at 4f ,
S S
12f , 20f , etc. Figures 10, 11, and 12 similarly illustrate
S S
S
the first filter, the images are at 2f , 4f , etc. This signal is
S
S
then passed to the second interpolating filter, which is
similar to the first filter and removes the images at 2f , 6f ,
the spectral responses when using the interpolating filters
combined with the digital modulator.
S
S
FILTER
RESPONSE
NO INTERPOLATION
SIGNAL
SIGNAL
SIGNAL
SIGNAL
IMAGE
INPUT
SPECTRUM
AND FIRST
FILTER
RESPONSE
f
S
f
S
f
S
f
S
2f
S
2f
S
2f
S
2f
S
3f
S
3f
S
3f
S
3f
S
4f
S
4f
S
4f
S
4f
S
2x INTERPOLATION
IMAGE
OUTPUT
SPECTRUM
OF THE
FIRST
FILTER
INPUT
SPECTRUM
AND
SECOND
FILTER
RESPONSE
FILTER
RESPONSE
IMAGE
4x INTERPOLATION
OUTPUT
SPECTRUM
OF THE
SECOND
FILTER
IMAGE
SIGNAL
LOWER
SIDEBAND
UPPER
SIDEBAND
IMAGE
OUTPUT
SPECTRUM
OF THE
MODULATOR
f
S
2f
S
3f
S
4f
S
FOR COMPLEX MODULATION THE MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND
Figure 10. Spectral Representation of 4x Interpolation Filter with f / 4 Modulation (Output Frequencies are Relative to the Data Input
IM
Frequency, f )
S
______________________________________________________________________________________ 21
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
FILTER
RESPONSE
NO INTERPOLATION
SIGNAL
SIGNAL
SIGNAL
SIGNAL
IMAGE
INPUT
SPECTRUM
AND FIRST
FILTER
RESPONSE
f
S
f
S
f
S
f
S
2f
S
2f
S
2f
S
2f
S
3f
S
3f
S
3f
S
3f
S
4f
S
4f
S
4f
S
4f
S
5f
S
5f
S
5f
S
5f
S
6f
S
6f
S
6f
S
6f
S
7f
S
7f
S
7f
S
7f
S
8f
S
8f
S
8f
S
8f
S
IMAGE
2x INTERPOLATION
OUTPUT
SPECTRUM
OF THE
FIRST
FILTER
FILTER
RESPONSE
INPUT
SPECTRUM
AND
SECOND
FILTER
RESPONSE
IMAGE
4x INTERPOLATION
OUTPUT
SPECTRUM
OF THE
SECOND
FILTER
IMAGE
SIGNAL
LOWER
UPPER
SIDEBAND
IMAGE
SIDEBAND
OUTPUT
SPECTRUM
OF THE
MODULATOR
f
2f
3f
4f
5f
6f
7f
7f
8f
8f
S
S
S
S
S
S
S
S
FOR COMPLEX MODULATION THE MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND
FILTER RESPONSE
SIGNAL
INPUT
IMAGE
SPECTRUM
AND THIRD
FILTER
RESPONSE
f
S
2f
S
3f
S
4f
S
5f
S
6f
S
S
S
8x INTERPOLATION
SIGNAL
OUTPUT
SPECTRUM
OF THE
THIRD
IMAGE
FILTER
f
S
2f
S
3f
S
4f
S
5f
S
6f
S
7f
S
8f
S
Figure 11. Spectral Representation of 8x Interpolation Filter with f / 4 Modulation and Lowpass Mode Enabled (Output Frequencies
IM
are Relative to the Data Input Frequency, f )
S
22 ______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
FILTER
RESPONSE
NO INTERPOLATION
SIGNAL
SIGNAL
SIGNAL
SIGNAL
IMAGE
INPUT
SPECTRUM
AND FIRST
FILTER
RESPONSE
f
f
f
f
2f
S
2f
S
2f
S
2f
S
3f
S
3f
S
3f
S
3f
S
4f
S
4f
S
4f
S
4f
S
5f
S
5f
S
5f
S
5f
S
6f
S
6f
S
6f
S
6f
S
7f
S
7f
S
7f
S
7f
S
8f
S
8f
S
8f
S
8f
S
S
S
S
S
IMAGE
2x INTERPOLATION
OUTPUT
SPECTRUM
OF THE
FIRST
FILTER
FILTER
RESPONSE
INPUT
SPECTRUM
AND
SECOND
FILTER
RESPONSE
IMAGE
4x INTERPOLATION
OUTPUT
SPECTRUM
OF THE
SECOND
FILTER
IMAGE
SIGNAL
LOWER
UPPER
SIDEBAND
IMAGE
SIDEBAND
OUTPUT
SPECTRUM
OF THE
MODULATOR
f
2f
3f
4f
5f
5f
6f
6f
7f
7f
8f
8f
S
S
S
S
S
S
S
S
MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND
FILTER
RESPONSE
SIGNAL
INPUT
IMAGE
SPECTRUM
AND THIRD
FILTER
RESPONSE
f
2f
S
3f
S
4f
S
S
S
S
S
S
8x INTERPOLATION
SIGNAL
OUTPUT
SPECTRUM
OF THE
THIRD
IMAGE
FILTER
f
2f
S
3f
S
4f
S
5f
S
6f
S
7f
S
8f
S
S
Figure 12. Spectral Representation of 8x Interpolation Filter with f / 4 Modulation and Highpass Mode Enabled (Output Frequencies
IM
are Relative to the Data Input Frequency, f )
S
______________________________________________________________________________________ 23
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
The outputs of the modulator can be expressed as:
Digital Modulator
The MAX5898 features digital modulation at frequencies
of f / 2 and f / 4, where f is the data rate at the
IM
IM
IM
I
t =I t × cos ωt − Q t × sin ωt
( ) ( ) ( ) ( )
(
)
input to the modulator. f equals f
in 1x, 2x, and 4x
OD
ID
ID
IM
DAC
interpolation modes. In 8x interpolation mode, f equals
IM
Q
t =I t × sin ωt +Q t × cos ωt
( ) ( ) ( )
(
)
(
)
OD
ID
ID
f
/ 2. The output rate of the modulator is always the
same as the input data rate to the modulator, f
DAC
.
IM
in complex modulation, e+jwt
In complex modulation mode, data from the second
interpolation filter is frequency-mixed with the on-chip
in-phase and quadrature (I/Q) local oscillator (LO).
Complex modulation provides the benefit of image
sideband rejection.
I
t =I t × cos ωt +Q t × sin ωt
( ) ( ) ( ) ( )
(
)
OD
ID
ID
Q
t =I t × sin ωt +Q t × cos ωt
( ) ( ) ( )
(
)
(
)
OD
ID
ID
In the f
= f / 4 mode, real or complex modulation
IM
LO
in complex modulation, e-jwt
can be used. The modulator multiplies successive input
For real modulation, the outputs of the modulator can
be expressed as:
data samples by the sequence [1, 0, -1, 0] for a cos(ωt).
The modulator modulates the input signal up to f / 4,
IM
creating upper and lower images around f / 4. The
IM
I
t =I t × cos ωt
( ) ( )
(
)
quadrature LO sin(ωt) is realized by delaying the cos(ωt)
sequence by one clock cycle. Using complex modula-
tion, complex IF is generated. The complex IF combined
with an external quadrature modulator provides image
rejection. The sign of the LO can be changed to allow
the user to select whether the upper or the lower image
should be rejected (bit 1 of register 01h).
OD
ID
Q
t = Q t × cos ωt
( ) ( )
(
)
OD
ID
where ω = 2 x π x f
.
LO
If more than one MAX5898 is used, their LO phases
can be synchronized by simultaneously releasing
RESET. This sets the MAX5898 to its predefined initial
phase.
When f / 2 is chosen as the LO frequency, the input
IM
signal is multiplied by [-1, 1] on both channels. This pro-
duces images around f / 2. The complex image-reject
IM
Device Reset
The MAX5898 can be reset by holding the RESET pin
low for 10ns. This will program the control registers to
their default values in Table 2. During power-on, RESET
must be held low until all power supplies have stabi-
lized. Alternately, programming bit 5 of address 00h to
a logic-high also resets the MAX5898.
modulation mode is not available for this LO frequency.
I-CHANNEL
INPUT DATA
I-CHANNEL
INPUT DATA
I-CHANNEL
OUTPUT DATA
I-CHANNEL
OUTPUT DATA
cos(ωt)
cos(ωt)
∑
∑
sin(ωt)
sin(ωt)
TO
TO
FIR3
FIR3
sin(ωt)
sin(ωt)
Q-CHANNEL
∑
Q-CHANNEL
∑
OUTPUT DATA
OUTPUT DATA
Q-CHANNEL
INPUT DATA
Q-CHANNEL
INPUT DATA
cos(ωt)
cos(ωt)
(a)
(b)
Figure 13. (a) Modulator in Complex Modulation Mode; (b) Modulator in Real Modulation Mode
24 ______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Power-Down Mode
The MAX5898 features three power-saving modes.
Each DAC can be individually powered down through
bits 2 and 3 of address 00h. The interpolation filters can
also be powered down through bit 4 of address 00h,
preserving the output level of each DAC (the DACs
remain powered). Powering down both DACs automati-
cally puts the MAX5898 into full power-down, including
the interpolation filters.
Data Clock
The MAX5898 features synchronizers that allow for arbi-
trary phase alignment between DATACLK and
CLKP/CLKN. The DATACLK causes internal switching in
the MAX5898 and the phase between DATACLK (input
mode) to CLKP/CLKN influences the images at DATACLK.
Figure 14 shows the image level near DATACLK as a
function of the DATACLK (input mode) to CLKP/CLKN
phase at 500Msps, 4x interpolation for a 10MHz, -6dBFS
output signal.
Applications Information
Frequency Planning
System designers need to take the DAC into account
during frequency-planning for high-performance appli-
cations. Proper frequency planning can ensure that
optimal system performance is achieved. The
MAX5898 is designed to deliver excellent dynamic per-
formance across wide bandwidths, as required for
communication systems. As with all DACs, some com-
binations of output frequency and update rate produce
better performance than others.
f / 4 IMAGES vs. CLKP/CLKN to DATACLK DELAY
S
f
= 125Mwps, 4x INTERPOLATION
DATA
-70
-75
f
A
= 10MHz
= -6dBFS
OUT
OUT
f / 4 - f
S OUT
-80
f / 4 + f
S
OUT
-85
Harmonics are often folded down into the band of inter-
est. Specifically, if the DAC outputs a frequency close
-90
f / 4 - f
S
OUT
f / 4 + f
to f / N, the Mth harmonic of the output signal will be
S
S
OUT
-95
aliased down to:
-100
N−M
N
⎡
⎤
f = f −M× f
OUT
= f
S
0
2
4
6
8
S
⎢
⎣
⎥
⎦
CLKP/CLKN DELAY (s)
Thus, if N ≈ (M + 1), the Mth harmonic will be close to
the output frequency. SFDR performance of a current-
steering DAC is often dominated by 3rd-order harmonic
distortion. If this is a concern, placing the output signal
Figure 14. Effect of CLKP/CLKN to DATACLK Phase on f / 4
S
Images
Clock Interface
at a frequency other than f / 4 should be considered.
S
The MAX5898 features a flexible differential clock input
(CLKP, CLKN) with a separate supply (AV
) to
Common to interpolating DACs are images near the
divided clocks. In a DAC configured for 4x interpolation,
CLK
achieve optimum jitter performance. Use an ultra-low
jitter clock to achieve the required noise density. Clock
this applies to images around f / 4 and f / 2. In a DAC
S
S
jitter must be less than 0.5ps
to meet the specified
configured for 8x interpolation, this applies to images
around f / 8, f / 4, and f / 2. Most of these images
RMS
noise density. For that reason, the CLKP/CLKN input
source must be designed carefully. The differential
clock (CLKN and CLKP) input can be driven from a sin-
gle-ended or a differential clock source. Differential
clock drive is required to achieve the best dynamic
performance from the DAC. For single-ended opera-
tion, drive CLKP with a low noise source and bypass
CLKN to GND with a 0.1µF capacitor.
S
S
S
are not part of the in-band (0 to f
/ 2) SFDR specifi-
DATA
cation, though they are a consideration for out-of-band
(f / 2 to f / 2) SFDR and may depend on the
DATA
DAC
relationship of the DATACLK to DAC update clock (see
the Data Clock section). When specifying the output
reconstruction filter for other than baseband signals,
these images should not be ignored.
The CLKP and CLKN pins are internally biased to
AV
/ 2. This allows the user to AC-couple clock
CLK
______________________________________________________________________________________ 25
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
sources directly to the device without external resistors
to define the DC level. The input resistance of CLKP
and CLKN is 5kΩ.
A convenient way to apply a differential signal is with a
balun transformer as shown in Figure 15. Alternatively,
these inputs may be driven from a CMOS-compatible
clock source, however it is recommended to use sine-
wave or AC-coupled differential ECL/PECL drive for best
dynamic performance.
Output Interface (OUTI, OUTQ)
The MAX5898 outputs complementary currents (OUTIP,
OUTIN, OUTQP, and OUTQN) that can be utilized in a
differential configuration. Load resistors convert these
two output currents into a differential output voltage.
The differential output between OUTIP (OUTQP) and
OUTIN (OUTQN) can be converted to a single-ended
output using a transformer or a differential amplifier.
Figure 16 shows a typical transformer-based applica-
tion circuit for generation of IF output signals. In this
configuration, the MAX5898 operates in differential
mode, which reduces even-order harmonics, and
increases the available output power. Pay close atten-
tion to the transformer core saturation characteristics
when selecting a transformer. Transformer core satura-
tion can introduce strong second harmonic distortion,
especially at low output frequencies and high signal
amplitudes. It is recommended to connect the trans-
former center tap to ground.
100nF
CLKP
MINI-CIRCUITS
ADTL1-12
24.9Ω
SINGLE-ENDED
IINPUT
MAX5898
1:1 RATIO
24.9Ω
100nF
CLKN
Figure 15. Single-Ended-to-Differential Clock Conversion Using
a Balun Transformer
50Ω
V
, SINGLE-ENDED
IOUT
1:1
OUTIP
IDAC
100Ω
16
1:1
OUTIN
50Ω
MAX5898
50Ω
V
, SINGLE-ENDED
QOUT
1:1
OUTQP
QDAC
100Ω
16
1:1
OUTQN
50Ω
Figure 16. Differential-to-Single-Ended Conversion Using Wideband RF Transformers
26 ______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
If a transformer is not used, the outputs must have a
resistive termination to ground. Figure 17 shows the
MAX5898 output configured for differential DC-coupled
mode. The DC-coupled configuration can be used to
eliminate waveform distortion due to highpass filter
effects. Applications include communication systems
employing analog quadrature upconverters and requir-
ing a high-speed DAC for baseband I/Q synthesis.
Reference Input/Output
The MAX5898 supports operation with the on-chip 1.2V
bandgap reference or an external reference voltage
source. REFIO serves as the input for an external, low-
impedance reference source, and as the output if the
DAC is operating with the internal reference.
For stable operation with the internal reference, REFIO
should be decoupled to GND with a 1µF capacitor.
If a single-ended DC-coupled unipolar output is desir-
able, OUTIP (OUTQP) should be selected as the out-
put, and connect OUTIN (OUTQN) to ground. Using
the MAX5898 output single-ended is not recommended
because it introduces additional noise and distortion.
REFIO must be buffered with an external amplifier,
if heavy loading is required, due to its 10kΩ output
resistance.
Alternatively, apply a temperature-stable external refer-
ence to REFIO (Figure 18). The internal reference is over-
driven by the external reference. For improved accuracy
and drift performance, choose a fixed output voltage ref-
erence such as the MAX6520 bandgap reference.
The distortion performance of the DAC also depends
on the load impedance. The MAX5898 is optimized for
a 50Ω double termination. It can be used with a trans-
former output as shown in Figure 16 or just one 25Ω
resistor from each output to ground and one 50Ω resis-
tor between the outputs (Figure 17). Higher output ter-
mination resistors can be used, as long as each output
voltage does not exceed +1V with respect to GND, but
at the cost of degraded distortion performance and
increased output noise voltage.
The MAX5898’s reference circuit (Figure 19) employs a
control amplifier, designed to regulate the full-scale
current I
for the differential current outputs of the
OUT
DAC. The output current can be calculated as:
I
= 32 x I
x 65,535 / 65,536
OUTFS
REF
where I
SET
is the reference output current (I
OUTFS
= V
/
REF
) and I
REF
REFIO
R
is the full-scale output current of the
DAC. Located between FSADJ and DACREF, R
is the
SET
reference resistor, which determines the amplifier’s output
current for the DAC. See Table 5 for a matrix of different
25Ω
OUTIP
I
and R
selections.
OUTFS
SET
Power Supplies, Bypassing,
Decoupling, and Layout
IDAC
50Ω
25Ω
16
Grounding and power-supply decoupling strongly influ-
ence the MAX5898 performance. Unwanted digital
crosstalk can couple through the input, reference,
power-supply, and ground connections, which can
affect dynamic specifications like signal-to-noise ratio
or spurious-free dynamic range. In addition, electro-
magnetic interference (EMI) can either couple into or
be generated by the MAX5898. Observe the grounding
and power-supply decoupling guidelines for high-
speed, high-frequency applications. Follow the power-
supply and filter configuration guidelines to achieve
optimum dynamic performance.
OUTIN
MAX5898
25Ω
50Ω
OUTQP
OUTQN
QDAC
16
Using a multilayer printed-circuit board (PCB) with sep-
arate ground and power-supply planes, run high-speed
signals on lines directly above the ground plane. Since
the MAX5898 has separate analog and digital sections,
the PCB should include separate analog and digital
25Ω
Figure 17. DC-Coupled Differential Output Configuration
______________________________________________________________________________________ 27
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
1.2V
1.2V
REFERENCE
REFERENCE
MAX5898
MAX5898
10kΩ
10kΩ
EXTERNAL
1.25V
REFERENCE
REFIO
REFIO
1μF
1μF
FSADJ
FSADJ
CURRENT-
CURRENT-
SOURCE
SOURCE
I
I
REF
REF
ARRAY DAC
ARRAY DAC
R
SET
R
SET
DACREF
DACREF
Figure 18. Typical External Reference Circuit
Figure 19. Internal Reference Architecture
Table 5. IOUTFS and RSET Selection Matrix Based on a Typical 1.20V Reference Voltage
FULL-SCALE
CURRENT
REFERENCE
CURRENT
R
(kΩ)
SET
OUTPUT VOLTAGE
* (mV
V
)
P-P
IOUTP/N
I
(mA)
I
(µA)
OUTFS
REF
CALCULATED
1% EIA STD
19.1
2
62.50
19.2
7.68
3.84
2.56
1.92
100
5
156.26
312.50
468.75
625.00
7.5
250
500
10
15
20
3.83
2.55
750
1.91
1000
*Terminated into a 50Ω load.
ground sections with only one point connecting the
three planes at the exposed paddle under the
MAX5898. Run digital signals above the digital ground
plane and analog/clock signals above the analog/clock
ground plane. Keep digital signals as far away from
sensitive analog inputs, reference lines, and clock
inputs as practical. Use a symmetric design of clock
input and the analog output lines to minimize 2nd-order
harmonic distortion components, thus optimizing the
dynamic performance of the DAC. Keep digital signal
paths short and run lengths matched to avoid propaga-
tion delay and data skew mismatches.
Decouple each voltage supply pin with a separate
0.1µF capacitor as close to the device as possible and
with the shortest possible connection to the appropriate
ground plane. Minimize the analog and digital load
capacitances for optimized operation. Decouple all
power-supply voltages at the point they enter the PCB
with tantalum or electrolytic capacitors. Ferrite beads
with additional decoupling capacitors forming a pi-net-
work could also improve performance.
The exposed paddle MUST be soldered to the ground.
Use multiple vias, an array of at least 4 x 4 vias, directly
under the EP to provide a low thermal and electrical
impedance path for the IC.
The MAX5898 requires five separate power-supply
inputs for the analog (AV
and AV
), digital
DD3.3
) circuitry.
CLK
DD1.8
), and clock (AV
(DV
and DV
DD1.8
DD3.3
28 ______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Signal-to-Noise Ratio (SNR)
Static Performance Parameter
For a waveform perfectly reconstructed from digital
Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
samples, the theoretical maximum SNR is the ratio of
the full-scale analog output (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
maximum SNR can be derived from the DAC’s resolu-
actual transfer function from either a best-straight-line
tion (N bits):
fit (closest approximation to the actual transfer curve)
or a line drawn between the end points of the transfer
function, once offset and gain errors have been nulli-
fied. For a DAC, the deviations are measured at every
individual step.
SNR = 6.02 x N + 1.76
dB
dB
dB
However, noise sources such as thermal noise, refer-
ence noise, clock jitter, etc., affect the ideal reading.
Therefore, SNR is computed by taking the ratio of the
RMS signal to the RMS noise, which includes all spec-
tral components minus the fundamental, the first four
harmonics, and the DC offset.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step height and the ideal value of 1 LSB. A DNL
error specification greater than -1 LSB guarantees a
monotonic transfer function.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the RMS amplitude of the carrier
frequency (maximum signal components) to the RMS
value of their next largest distortion component. SFDR
is usually measured in dBc with respect to the carrier
frequency amplitude or in dBFS with respect to the
DAC’s full-scale range. Depending on its test condition,
SFDR is observed within a predefined window or
to Nyquist.
Offset Error
The offset error is the difference between the ideal and
the actual offset current. For a DAC, the offset point is
the average value at the output for the two midscale
digital input codes with respect to the full scale of the
DAC. This error affects all codes by the same amount.
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Two-/Four-Tone Intermodulation
Distortion (IMD)
The two-/four-tone IMD is the ratio expressed in dBc (or
dBFS) of the worst 3rd-order (or higher) IMD products to
any output tone.
Adjacent Channel Leakage
Power Ratio (ACLR)
Dynamic Performance
Parameter Definitions
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the specified accuracy.
Commonly used in combination with WCDMA, ACLR
reflects the leakage power ratio in dB between the
measured powers within a channel relative to its adja-
cent channel. ACLR provides a quantifiable method of
determining out-of-band spectral energy and its influ-
ence on an adjacent channel when a bandwidth-limited
RF signal passes through a nonlinear device.
Noise Spectral Density
The DAC output noise is the sum of the quantization
noise and thermal noise. Noise spectral density is the
noise power in a 1Hz bandwidth, specified in dBFS/Hz.
______________________________________________________________________________________ 29
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Pin Configuration
TOP VIEW
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
EXPOSED PADDLE
CLKP
CLKN
1
2
3
4
5
6
7
8
9
51
DACREF
50 REFIO
49 RESET
48 CS
N.C.
DATACLKP
DATACLKN
47 SCLK
46 DIN
D
VDD1.8
SELIQN
SELIQP
D15N
45 DOUT
44 DV
DD3.3
MAX5898
43 D0P
42 D0N
41 D1P
40 D1N
39 D2P
38 D2N
D15P 10
D14N 11
D14P 12
D13N
13
D13P 14
D12N 15
D12P 16
D11N 17
37 DV
DD1.8
36 D3P
35 D3N
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
QFN
30 ______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
1
21-0122
C
2
______________________________________________________________________________________ 31
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
1
21-0122
C
2
____________________Revision History
Pages changed at Rev 1: 1, 2, 4, 5, 27, 28, 31
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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