MAX5974BETE+ [MAXIM]
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers; 有源钳位，扩频，电流模式PWM控制器
| 型号： | MAX5974BETE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers |
| 文件： | 总26页 (文件大小：2532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5331; Rev 0; 6/10
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
General Description
Features
SꢀPeak_Current-Mode_Control,_Active-Clamped_
The MAX5974_ provide control for wide-input-voltage,
active-clamped, current-mode PWM, forward converters
in Power-over-Ethernet (PoE) powered device (PD) appli-
cations. The MAX5974A/MAX5974C are well-suited for
universal or telecom input range, while the MAX5974B/
MAX5974D also accommodate low input voltage down
to 10.5V.
Forward_PWM_Controller
SꢀRegulation_Without_Optocoupler_(MAX5974A/
MAX5974B)
SꢀInternal_1%_Error_Amplifier
Sꢀ100kHz_to_600kHz_Programmable_Q8%_Switching_
Frequency,_Synchronization_Up_to_1.2MHz
The devices include several features to enhance supply
efficiency. The AUX driver recycles magnetizing cur-
rent instead of wasting it in a dissipative clamp circuit.
Programmable dead time between the AUX and main
driver allows for zero-voltage switching (ZVS). Under light-
load conditions, the devices reduce the switching fre-
quency (frequency foldback) to reduce switching losses.
SꢀProgrammable_Frequency_Dithering_for_Low-EMI,_
Spread-Spectrum_Operation
SꢀProgrammable_Dead_Time,_PWM_Soft-Start,_
Current_Slope_Compensation
SꢀProgrammable_Feed-Forward_Maximum_Duty-_
Cycle_Clamp,_80%_Maximum_Limit
SꢀFrequency_Foldback_for_High-Efficiency_Light-
The MAX5974A/MAX5974B feature unique circuitry to
achieve output regulation without using an optocoupler,
while the MAX5974C/MAX5974D utilize the traditional
optocoupler feedback method. An internal error amplifier
with a 1% reference is very useful in nonisolated design,
eliminating the need for an external shunt regulator.
Load_Operation
SꢀInternal_Bootstrap_UVLO_with_Large_Hysteresis
Sꢀ100µA_(typ)_Startup_Supply_Current
SꢀFast_Cycle-by-Cycle_Peak_Current-Limit,_35ns_
Typical_Propagation_Delay
The devices feature a unique feed-forward maximum
duty-cycle clamp that makes the maximum clamp volt-
age during transient conditions independent of the line
voltage, allowing the use of a power MOSFET with lower
breakdown voltage. The programmable frequency dither-
ing feature provides low-EMI, spread-spectrum operation.
Sꢀ115ns_Current-Sense_Internal_Leading-Edge_
Blanking
SꢀOutput_Short-Circuit_Protection_with_Hiccup_Mode
SꢀReverse_Current_Limit_to_Prevent_Transformer_
Saturation_Due_to_Reverse_Current
The MAX5974_ are available in 16-pin TQFN-EP pack-
ages and are rated for operation over the -40°C to +85°C
temperature range.
Sꢀ3mm_x_3mm,_Lead-Free,_16-Pin_TQFN-EP
Applications
PoE IEEE® 802.3af/at Powered Devices
High-Power PD (Beyond the 802.3af/at Standard)
Active-Clamped Forward DC-DC Converters
IP Phones
Wireless Access Nodes
Security Cameras
Ordering Information
PART
TOP_MARK
+AHY
PIN-PACKAGE
16 TQFN-EP*
16 TQFN-EP*
16 TQFN-EP*
16 TQFN-EP*
UVLO_THRESHOLD_(V)
FEEDBACK_MODE
Sample/Hold
MAX5974AETE+
MAX5974BETE+**
MAX5974CETE+
MAX5974DETE+**
20
10
20
10
+AHZ
Sample/Hold
+AIA
Continuously Connected
Continuously Connected
+AIB
Note: All devices are specified over the -40°C to +85°C operating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad. **Future product—Contact factory for availability.
IEEE is a registered service mark of the Institute of Electrical and Electronics Engineers, Inc.
_ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ _Maxim Integrated Products_ _ 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
ABSOLUTE_MAXIMUM_RATINGS
IN to GND..............................................................-0.3V to +24V
Continuous Power Dissipation (T = +70NC) (Note 1)
A
16-Pin TQFN (derate 20.8mW/NC above +70NC).......1666mW
EN, NDRV, AUXDRV to GND .....................-0.3V to (V + 0.3V)
IN
RT, DT, FFB, COMP, SS, DCLMP, DITHER/SYNC
Junction-to-Case Thermal Resistance (B ) (Note 1)
JC
to GND .................................................................-0.3V to +6V
FB to GND (MAX5974A/MAX5974B only)..................-6V to +6V
FB to GND (MAX5974C/MAX5974D only) ..............-0.3V to +6V
CS, CSSC to GND...................................................-0.8V to +6V
PGND to GND ......................................................-0.3V to +0.3V
Maximum Input/Output Current (continuous)
16-Pin TQFN...................................................................7NC/W
Junction-to-Ambient Thermal Resistance (B ) (Note 1)
JA
16-Pin TQFN.................................................................48NC/W
Operating Temperature Range.......................... -40NC to +85NC
Maximum Junction Temperature.....................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
NDRV, AUXDRV............................................................100mA
NDRV, AUXDRV (pulsed for less than 100ns).................. Q1A
Note_1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL_CHARACTERISTICS
(V = 12V (for MAX5974A/MAX5974C, bring V up to 21V for startup), V
= V
= V
= V = V
= V
=
DCLMP
IN
IN
CS
CSSC
DITHER/SYNC
FB
FFB
V , V = +2V, NDRV = AUXDRV = SS = COMP = unconnected, R = 34.8kI, R = 25kI, C = 1FF, T = -40NC to +85NC,
GND EN RT DT IN A
unless otherwise noted. Typical values are at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
UNDERVOLTAGE_LOCKOUT/STARTUP_(IN)
MAX5974A/
MAX5974C
19.1
9.4
19.8
9.8
7
20.4
10.25
7.35
Bootstrap UVLO Wakeup Level
V
V
rising
falling
V
V
INUVR
IN
MAX5974B/
MAX5974D
Bootstrap UVLO Shutdown
Level
V
V
V
6.65
INUVF
START
IN
= +18V (for MAX5974A/
MAX5974C);
= +9V (for MAX5974B/MAX5974D),
IN
IN Supply Current in
Undervoltage Lockout
I
100
1.8
150
3
FA
V
IN
when in bootstrap UVLO
IN Supply Current After Startup
I
V
IN
= +12V
mA
C
ENABLE_(EN)
V
V
V
rising
falling
1.17
1.09
1.215
1.14
1.26
1.19
1
ENR
EN
Enable Threshold
V
V
ENF
EN
Input Current
I
FA
EN
OSCILLATOR_(RT)
RT Bias Voltage
V
1.23
80
V
RT
NDRV Switching Frequency
Range
f
100
600
kHz
SW
NDRV Switching Frequency
Accuracy
-8
+8
82
%
%
Maximum Duty Cycle
D
MAX
f
= 250kHz
79
SW
2
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
ELECTRICAL_CHARACTERISTICS_(continued)
(V = 12V (for MAX5974A/MAX5974C, bring V up to 21V for startup), V
= V
= V
= V = V
= V
=
DCLMP
IN
IN
CS
CSSC
DITHER/SYNC
FB
FFB
V
, V = +2V, NDRV = AUXDRV = SS = COMP = unconnected, R = 34.8kI, R = 25kI, C = 1FF, T = -40NC to +85NC,
GND EN
RT
DT
IN
A
unless otherwise noted. Typical values are at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYNCHRONIZATION_(SYNC)
Synchronization Logic-High
Input
V
2.91
V
IH-SYNC
SYNCIN
Synchronization Pulse Width
50
ns
Synchronization Frequency
Range
1.1 x
2 x
f
SW
f
kHz
f
SW
Maximum Duty Cycle During
Synchronization
D
x f
SW
/
MAX
SYNC
%
f
DITHERING_RAMP_GENERATOR_(DITHER)
Charging Current
V
V
= 0V
45
43
50
50
2
55
57
FA
FA
V
DITHER
Discharging Current
= 2.2V
DITHER
Ramp’s High Trip Point
Ramp’s Low Trip Point
0.4
V
SOFT-START_AND_RESTART_(SS)
Charging Current
I
I
9.5
10
10.5
2
FA
SS-CH
I
V
= 2V, normal shutdown
0.65
1.34
mA
SS-D
SS
(V < V
or V < V
),
EN
ENF
IN
INUVF
Discharging Current
V
SS
= 2V, hiccup mode discharge for
1.6
2
2.4
FA
SS-DH
t
(Note 3)
RESTART
Discharge Threshold to Disable
Hiccup and Restart
V
0.15
V
SS-DTH
Minimum Restart Time During
Hiccup Mode
Clock
Cycles
t
1024
5
RSTRT-MIN
Normal Operating High Voltage
Duty-Cycle Control Range
DUTY-CYCLE_CLAMP_(DCLMP)
DCLMP Input Current
V
SS-HI
V
V
V
D
(typ) = (V /2.46V)
SS-DMAX
0
2
SS-DMAX
MAX
I
V
= 0 to 5V
-100
73
0
+100
77.5
58
nA
%
DCLMP
DCLMP
V
V
V
= 0.5V
= 1V
75.4
56
DCLMP
DCLMP
DCLMP
Duty-Cycle Control Range
V
54
DCLMP-R
D
MAX
(typ) =
1 - (V
/2.43V)
DCLMP
= 2V
14.7
16.5
18.3
NDRV_DRIVER
Pulldown Impedance
Pullup Impedance
Peak Sink Current
Peak Source Current
Fall Time
R
I
I
(sinking) = 100mA
(sourcing) = 50mA
1.9
4.7
1
3.4
8.3
I
I
NDRV-N
NDRV
R
NDRV-P
NDRV
A
0.65
14
A
t
C
C
= 1nF
= 1nF
ns
ns
NDRV-F
NDRV
Rise Time
t
27
NDRV-R
NDRV
3
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
ELECTRICAL_CHARACTERISTICS_(continued)
(V = 12V (for MAX5974A/MAX5974C, bring V up to 21V for startup), V
= V
= V
= V = V
= V
=
DCLMP
IN
IN
CS
CSSC
DITHER/SYNC
FB
FFB
V , V = +2V, NDRV = AUXDRV = SS = COMP = unconnected, R = 34.8kI, R = 25kI, C = 1FF, T = -40NC to +85NC,
GND EN RT DT IN A
unless otherwise noted. Typical values are at T = +25NC.) (Note 2)
A
PARAMETER
AUXDRV_DRIVER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Pulldown Impedance
Pullup Impedance
Peak Sink Current
Peak Source Current
Fall Time
R
I
I
(sinking) = 50mA
(sourcing) = 25mA
4.3
10.6
0.5
0.3
24
7.7
I
I
AUX-N
AUXDRV
R
18.9
AUX-P
AUXDRV
A
A
t
C
C
= 1nF
= 1nF
ns
ns
AUX-F
AUXDRV
Rise Time
t
45
AUX-R
AUXDRV
DEAD-TIME_PROGRAMMING_(DT)
DT Bias Voltage
V
1.215
40
V
DT
R
DT
R
DT
R
DT
R
DT
= 10kI
= 100kI
= 10kI
= 100kI
From NDRV falling
to AUXDRV falling
ns
300
310
350
40
410
420
NDRV to AUXDRV Delay
(Dead Time)
t
DT
AUXDRV rising to
NDRV rising
ns
360
CURRENT-LIMIT_COMPARATORS_(CS)
Cycle-by-Cycle Peak
Current-Limit Threshold
V
375
393
410
-88
mV
mV
CS-PEAK
Cycle-by-Cycle Reverse
Current-Limit Threshold
Turns AUXDRV off for the remaining
cycle if reverse current limit is exceeded
V
-118
-100
CS-REV
Current-Sense Blanking Time
for Reverse Current Limit
t
CS-BLANK-
REV
From AUXDRV falling edge
115
8
ns
Events
ns
Number of Consecutive Peak
Current-Limit Events to Hiccup
N
HICCUP
Current-Sense Leading-Edge
Blanking Time
t
From NDRV rising edge
115
CS-BLANK
From CS rising (10mV overdrive) to
NDRV falling (excluding leading-edge
blanking)
Propagation Delay from
Comparator Input to NDRV
t
35
ns
ns
PDCS
Minimum On-Time
t
100
47
150
200
58
ON-MIN
SLOPE_COMPENSATION_(CSSC)
Slope Compensation Current
Ramp Height
Current ramp’s peak added to CSSC
input per switching cycle
52
FA
PWM_COMPARATOR
Comparator Offset Voltage
Current-Sense Gain
V
V
- V
CSSC
1.35
3.1
1.7
2
V
PWM-OS
COMP
A
DV
/DV (Note 4)
COMP CSSC
3.33
3.6
V/V
CS-PWM
Current-Sense Leading-Edge
Blanking Time
t
From NDRV rising edge
Change in V = 10mV (including
115
150
ns
ns
CSSC-BLANK
CSSC
Comparator Propagation Delay
t
PWM
internal leading-edge blanking)
4
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
ELECTRICAL_CHARACTERISTICS_(continued)
(V = 12V (for MAX5974A/MAX5974C, bring V up to 21V for startup), V
= V
= V
= V = V
= V
=
DCLMP
IN
IN
CS
CSSC
DITHER/SYNC
FB
FFB
V , V = +2V, NDRV = AUXDRV = SS = COMP = unconnected, R = 34.8kI, R = 25kI, C = 1FF, T = -40NC to +85NC,
GND EN RT DT IN A
unless otherwise noted. Typical values are at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ERROR_AMPLIFIER
MAX5974A/
MAX5974B
1.5
1.202
-250
-500
1.52
1.54
1.227
+250
+100
V
V
when I
= 0,
FB
COMP
FB Reference Voltage
V
V
REF
= 2.5V
COMP
MAX5974C/
MAX5974D
1.215
MAX5974A/
MAX5974B
FB Input Bias Current
Voltage Gain
I
V
= 0 to 1.75V
nA
dB
mS
FB
FB
MAX5974C/
MAX5974D
A
EAMP
80
MAX5974A/
MAX5974B
1.8
1.8
2.55
3.2
3.5
Transconductance
g
M
MAX5974C/
MAX5974D
2.66
2
MAX5974A/
MAX5974B
Open loop (typical gain
= 1) -3dB frequency
Transconductance Bandwidth
BW
MHz
MAX5974C/
MAX5974D
30
Source Current
V
V
= 1V, V
= 2.5V
300
300
375
375
455
455
FA
FA
FB
COMP
Sink Current
= 1.75V, V
= 1V
FB
COMP
FREQUENCY_FOLDBACK_(FFB)
V
Gain
-to-FFB Comparator
CSAVG
10
30
V/V
FA
FFB Bias Current
I
V
FFB
= 0V, V = 0V (not in FFB mode)
26
33
FFB
CS
NDRV Switching Frequency
During Foldback
f
f /2
SW
kHz
SW-FB
Note_2: All devices are 100% production tested at T = +25NC. Limits over temperature are guaranteed by design.
A
Note_3: See the Output Short-Circuit Protection with Hiccup Mode section.
Note_4: The parameter is measured at the trip point of latch with V = 0V. Gain is defined as DV
/DV
COMP
for 0.15V <
CSSC
FB
DV
< 0.25V.
CSSC
5
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Operating Characteristics
(V = 12V (for MAX5974A/MAX5974C, bring V up to 21V for startup), V
= V
= V
= V = V
= V
=
DCLMP
IN
IN
CS
CSSC
DITHER/SYNC
FB
FFB
V
, V = 2V, NDRV = AUXDRV = SS = COMP = unconnected, R = 34.8kI, R = 25kI, unless otherwise noted.)
GND EN RT DT
IN UVLO WAKE-UP LEVEL
vs. TEMPERATURE
IN UVLO WAKE-UP LEVEL
vs. TEMPERATURE
IN UVLO SHUTDOWN LEVEL
vs. TEMPERATURE
20.1
10.1
10.0
9.9
7.3
7.2
7.1
7.0
6.9
6.8
MAX5974A/MAX5974C
MAX5974B/MAX5974D
20.0
19.9
19.8
19.7
19.6
19.5
9.8
9.7
9.6
9.5
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-40
0
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
EN RISING THRESHOLD
vs. TEMPERATURE
EN FALLING THRESHOLD
vs. TEMEPRATURE
UVLO SHUTDOWN CURRENT
vs. TEMPERATURE
1.220
1.218
1.216
1.214
1.212
1.210
1.150
1.149
1.148
1.147
1.146
1.145
1.144
1.143
1.142
140
120
100
80
MAX5974A/MAX5974C
MAX5974B/MAX5974D
60
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5974A/MAX5974C)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5974B/MAX5974D)
SUPPLY CURRENT
vs. SWITCHING FREQUENCY
10,000
1000
100
10,000
1000
100
2.4
2.0
1.6
1.2
0.8
0.4
0
T
= +85°C
A
T
= +85°C
A
T
= -40°C
A
T
= -40°C
A
10
10
0
2
4
6
8
10 12 14 16 18 20 22
0
2
4
6
8
10 12 14 16 18 20 22
100 200 300 400 500 600 700 800
SWITCHING FREQUENCY (kHz)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
6
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Operating Characteristics (continued)
(V = 12V (for MAX5974A/MAX5974C, bring V up to 21V for startup), V
= V
= V
= V = V
= V
=
DCLMP
IN
IN
CS
CSSC
DITHER/SYNC
FB
FFB
V , V = 2V, NDRV = AUXDRV = SS = COMP = unconnected, R = 34.8kI, R = 25kI, unless otherwise noted.)
GND EN RT DT
SWITCHING FREQUENCY
SOFT-START CHARGING CURRENT
vs. TEMPERATURE
SWITCHING FREQUENCY
vs. TEMPERATURE
vs. R VALUE
RT
1000
100
10
10.06
10.05
10.04
10.03
10.02
10.01
10.00
9.99
252
251
250
249
248
247
246
245
244
9.98
9.97
10
100
-40
-15
10
35
60
85
-40
-40
0
-15
10
35
60
85
R
VALUE (kΩ)
TEMPERATURE (°C)
TEMPERATURE (°C)
RT
MAXIMUM DUTY CYCLE
vs. SWITCHING FREQUENCY
MAXIMUM DUTY CYCLE
vs. TEMPERATURE
FREQUENCY DITHERING
vs. R
DITHER
83
82
81
80
79
78
77
76
75
81.0
80.9
80.8
80.7
80.6
80.5
80.4
80.3
80.2
14
12
10
8
6
4
2
0
0
100 200 300 400 500 600 700 800
SWITCHING FREQUENCY (kHz)
-15
10
35
60
85
300 400 500 600 700 800 900 1000
(kΩ)
TEMPERATURE (°C)
R
DITHER
MAXIMUM DUTY CYCLE
MAXIMUM DUTY CYCLE
MAXIMUM DUTY CYCLE
vs. SYNC FREQUENCY
vs. V
vs. V
SS
DCLMP
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
45
40
35
30
25
20
15
10
5
V
= 0.5V
SS
0
0
0.5
1.0
1.5
(V)
2.0
2.5
0.5
1.0
V
1.5
(V)
2.0
2.5
250
300
350
400
450
500
V
SYNC FREQUENCY (kHz)
SS
DCLMP
7
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Operating Characteristics (continued)
(V = 12V (for MAX5974A/MAX5974C, bring V up to 21V for startup), V
= V
= V
= V = V
= V
=
DCLMP
IN
IN
CS
CSSC
DITHER/SYNC
FB
FFB
V , V = 2V, NDRV = AUXDRV = SS = COMP = unconnected, R = 34.8kI, R = 25kI, unless otherwise noted.)
GND EN RT DT
PEAK CURRENT-LIMIT THRESHOLD
vs. TEMPERATURE
DEAD TIME vs. TEMPERATURE
DEAD TIME vs. R VALUE
DT
398
397
396
395
394
393
392
391
390
389
388
102
100
98
400
350
300
250
200
150
100
50
96
94
92
90
88
0
-40
-40
-40
-15
10
35
60
85
-40
-15
10
35
60
85
110
10 20 30 40 50 60 70 80 90 100
VALUE (kΩ)
TEMPERATURE (°C)
TEMPERATURE (°C)
R
DT
SLOPE COMPENSATION CURRENT
vs. TEMPERATURE
NDRV MINIMUM ON-TIME
vs. TEMPERATURE
REVERSE CURRENT-LIMIT THRESHOLD
vs. TEMPERATURE
-97
-98
54.0
53.5
53.0
52.5
52.0
51.5
51.0
50.5
50.0
170
165
160
155
150
145
140
-99
-100
-101
-102
-103
-104
-105
-106
-107
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
FEEDBACK VOLTAGE
vs. TEMPERATURE
CURRENT-SENSE GAIN
vs. TEMPERATURE
FEEDBACK VOLTAGE
vs. TEMPERATURE
3.40
3.39
3.38
3.37
3.36
3.35
3.34
3.33
3.32
3.31
3.30
1.220
1.219
1.218
1.217
1.216
1.215
1.214
1.213
1.212
1.211
1.210
1.522
1.521
1.520
1.519
1.518
1.517
1.516
MAX5974C/MAX5974D
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
8
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Operating Characteristics (continued)
(V = 12V (for MAX5974A/MAX5974C, bring V up to 21V for startup), V
= V
= V
= V = V
= V
DCLMP
=
IN
IN
CS
CSSC
DITHER/SYNC
FB
FFB
V , V = 2V, NDRV = AUXDRV = SS = COMP = unconnected, R = 34.8kI, R = 25kI, unless otherwise noted.)
GND EN RT DT
TRANSCONDUCTANCE HISTOGRAM
(MAX5974A/MAX5974B)
TRANSCONDUCTANCE HISTOGRAM
TRANSCONDUCTANCE
vs. TEMPERATURE
(MAX5974C/MAX5974D)
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
25
20
15
10
5
25
20
15
10
5
MAX5974C/MAX5974D
MAX5974A/MAX5974B
2.0
-40
0
0
-15
10
35
60
85
2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 2.60 2.62 2.64
TRANSCONDUCTANCE (mS)
2.56 2.58 2.60 2.62 2.64 2.66 2.68 2.70 2.72 2.74 2.76
TRANSCONDUCTANCE (mS)
TEMPERATURE (°C)
ENABLE RESPONSE
SHUTDOWN RESPONSE
MAX5974A/B/C/D toc31
MAX5974A/B/C/D toc32
V
V
EN
EN
MAX5974C
2V/div
2V/div
V
NDRV
V
NDRV
20V/div
10V/div
V
V
AUXDRV
AUXDRV
10V/div
20V/div
V
OUT
V
OUT
5V/div
5V/div
1ms/div
4µs/div
SHUTDOWN RESPONSE
V
SS
RAMP RESPONSE
MAX5974A/B/C/D toc33
MAX5974A/B/C/D toc34
V
EN
2V/div
V
SS
2V/div
V
NDRV
10V/div
V
NDRV
10V/div
V
AUXDRV
10V/div
V
AUXDRV
10V/div
V
OUT
5V/div
100µs/div
10µs/div
9
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Operating Characteristics (continued)
(V = 12V (for MAX5974A/MAX5974C, bring V up to 21V for startup), V
= V
= V
= V = V
= V
=
DCLMP
IN
IN
CS
CSSC
DITHER/SYNC
FB
FFB
V , V = 2V, NDRV = AUXDRV = SS = COMP = unconnected, R = 34.8kI, R = 25kI, unless otherwise noted.)
GND EN RT DT
V
RAMP RESPONSE
NDRV 10% TO 90% RISE TIME
NDRV 90% TO 10% FALL TIME
MAX5974A/B/C/D toc37
DCLMP
MAX5974A/B/C/D toc35
MAX5974A/B/C/D toc36
V
DCLMP
0ns
27.6ns
2V/div
V
V
NDRV
2V/div
NDRV
V
NDRV
2V/div
10V/div
V
AUXDRV
13.8ns
0ns
10V/div
10µs/div
10ns/div
10ns/div
AUXDRV 10% TO 90% RISE TIME
AUXDRV 90% TO 10% FALL TIME
PEAK NDRV CURRENT
MAX5974A/B/C/D toc40
MAX5974A/B/C/D toc38
MAX5974A/B/C/D toc39
PEAK SOURCE CURRENT
0ns
45.6ns
V
V
I
NDRV
AUXDRV
AUXDRV
2V/div
2V/div
0.5A/div
21ns
0ns
PEAK SINK CURRENT
10ns/div
10ns/div
200ns/div
PEAK AUXDRV CURRENT
SHORT-CIRCUIT BEHAVIOR
MAX5974A/B/C/D toc41
MAX5974A/B/C/D toc42
V
V
IN
PEAK SOURCE
CURRENT
I
AUXDRV
0.2A/div
NDRV
I
LX
PEAK SINK CURRENT
400ns/div
40ms/div
10
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Pin Configuration
TOP VIEW
12
11
10
9
CSSC
GND
FB
13
14
IN
8
7
6
5
MAX5974A
MAX5974B
MAX5974C
MAX5974D
EN
DCLMP 15
16
EP
COMP
SS
+
1
2
3
4
THIN QFN
Pin Description
PIN
NAME
FUNCTION
Dead-Time Programming Resistor Connection. Connect resistor R from DT to GND to set
DT
1
DT
the desired dead time between the NDRV and AUXDRV signals. See the Dead Time section to
calculate the resistor value for a particular dead time.
Frequency Dithering Programming or Synchronization Connection. For spread-spectrum frequency
operation, connect a capacitor from DITHER to GND and a resistor from DITHER to RT. To
synchronize the internal oscillator to the externally applied frequency, connect DITHER/SYNC to
the synchronization pulse.
DITHER/
SYNC
2
3
Switching Frequency Programming Resistor Connection. Connect resistor R from RT to GND to
RT
set the PWM switching frequency. See the Oscillator/Switching Frequency section to calculate the
RT
resistor value for the desired oscillator frequency.
Frequency Foldback Threshold Programming Input. Connect a resistor from FFB to GND to set the
output average current threshold below which the converter folds back the switching frequency to
1/2 of its original value. Connect to GND to disable frequency foldback.
4
5
FFB
Transconductance Amplifier Output and PWM Comparator Input. COMP is level shifted down and
connected to the inverting input of the PWM comparator.
COMP
11
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Pin Description (continued)
PIN
6
NAME
FB
FUNCTION
Transconductance Amplifier Inverting Input
Signal Ground
7
GND
Current Sense with Slope Compensation Input. A resistor connected from CSSC to CS programs
the amount of slope compensation. See the Programmable Slope Compensation section.
8
CSSC
Current-Sense Input. Current-sense connection for average current sense and cycle-by-cycle
current limit. Peak current-limit trip voltage is 400mV and reverse current-limit trip voltage is
-100mV.
9
CS
10
11
PGND
NDRV
Power Ground. PGND is the return path for gate-driver switching currents.
Main Switch Gate-Driver Output
pMOS Active Clamp Switch Gate-Driver Output. AUXDRV can also be used to drive a pulse
transformer for synchronous flyback application.
12
AUXDRV
Converter Supply Input. IN has wide UVLO hysteresis, enabling the design of efficient power
supplies. When the enable input EN is used to program a UVLO level for the power source,
connect a zener diode between IN and PGND to ensure that V is always clamped below its
IN
13
IN
absolute maximum rating of 24V.
Enable Input. The gate drivers are disabled and the device is in a low-power UVLO mode when the
14
15
EN
voltage on EN is below V
enable conditions. See the Enable Input section for more information about interfacing to EN.
. When the voltage on EN is above V
, the device checks for other
ENF
ENR
Feed-Forward Maximum Duty-Cycle Clamp Programming Input. Connect a resistive divider
between the input supply voltage DCLMP and GND. The voltage at DCLMP sets the maximum
DCLMP
duty cycle (D ) of the converter inversely proportional to the input supply voltage, so that the
MAX
MOSFET remains protected during line transients.
Soft-Start Programming Capacitor Connection. Connect a capacitor from SS to GND to program
the soft-start period. This capacitor also determines hiccup mode current-limit restart time. A
16
—
SS
EP
resistor from SS to GND can also be used to set the D
below 75%.
MAX
Exposed Pad. Internally connected to GND. Connect to a large ground plane to maximize thermal
performance. Not intended as an electrical connection point.
12
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Block Diagrams
13
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Block Diagrams (continued)
14
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
The reverse current-limit feature of the devices turns
Detailed Description
the AUX driver off for the remaining off period when
exceeds the -100mV threshold. This protects the
transformer core from saturation due to excess reverse
current under some extreme transient conditions.
The MAX5974A/MAX5974B/MAX5974C/MAX5974D are
optimized for controlling a 25W to 50W active-clamped,
self-driven synchronous rectification forward converter
in continuous-conduction mode. The main switch gate
driver (NDRV) and the active-clamped switch driver
(AUXDRV) are sized to optimize efficiency for 25W
design. The features-rich devices are ideal for PoE IEEE
802.3af/at-powered devices.
V
CS
Current-Mode Control Loop
The advantages of current-mode control over voltage-
mode control are twofold. First, there is the feed-forward
characteristic brought on by the controller’s ability to adjust
for variations in the input voltage on a cycle-by-cycle basis.
Second, the stability requirements of the current-mode
controller are reduced to that of a single-pole system,
unlike the double pole in voltage-mode control.
The MAX5974A/MAX5974C offer a 20V bootstrap UVLO
wake-up level with a 13V wide hysteresis. The low
startup and operating currents allow the use of a smaller
storage capacitor at the input without compromising
startup and hold times. The MAX5974A/MAX5974C are
well-suited for universal input (rectified 85V AC to 265V
AC) or telecom (-36V DC to -72V DC) power supplies.
The devices use a current-mode control loop where the
scaled output of the error amplifier (COMP) is compared
to a slope-compensated current-sense signal at CSSC.
The MAX5974B/MAX5974D have a UVLO rising threshold
of 10V and can accomodate for low-input voltage (12V
DC to 24V DC) power sources such as wall adapters.
Enable Input
The enable input EN is used to enable or disable the
device. Connect EN to IN for always enabled applica-
tions. Connecting EN to ground disables the device and
reduces current consumption to 100FA.
Power supplies designed with the MAX5974A/MAX5974C
use a high-value startup resistor, R , that charges a
IN
reservoir capacitor, C (see the Typical Application
IN
The enable input has an accurate threshold of 1.26V
(max). For applications that require a UVLO on the
power source, connect a resistive divider from the power
source to EN to GND as shown in Figure 1. A zener
diode between IN and PGND is required to prevent
IN from exceeding its absolute maximum rating of 24V
when the device is disabled. The zener diode should be
inactive below the maximum UVLO rising threshold volt-
Circuits). During this initial period, while the voltage is
less than the internal bootstrap UVLO threshold, the
device typically consumes only 100FA of quiescent cur-
rent. This low startup current and the large bootstrap
UVLO hysteresis help to minimize the power dissipation
across R even at the high end of the universal AC input
IN
voltage (265V AC).
age V
(21V for the MAX5974A/MAX5974C
INUVR(MAX)
Feed-forward maximum duty-cycle clamping detects chang-
es in line conditions and adjusts the maximum duty cycle
accordingly to eliminate the clamp voltage’s (i.e., the main
power FET’s drain voltage) dependence on the input voltage.
and 10.5V for the MAX5974B/MAX5974D). Design the
resistive divider by first selecting the value of R to be
on the order of 100kI. Then calculate R
EN1
as follows:
EN2
For EMI-sensitive applications, the programmable fre-
quency dithering feature allows up to Q10% variation in
the switching frequency. This spread-spectrum modula-
tion technique spreads the energy of switching harmon-
ics over a wider band while reducing their peaks, help-
ing to meet stringent EMI goals.
V
EN(MAX)
R
= R
EN1
EN2
V
− V
EN(MAX)
S(UVLO)
where V
is the maximum enable threshold volt-
age and is equal to 1.26V and V
UVLO threshold for the power source, below which the
devices are disabled.
EN(MAX)
is the desired
S(UVLO)
The devices include a cycle-by-cycle current limit
that turns off the main and AUX drivers whenever the
internally set threshold of 400mV is exceeded. Eight
consecutive occurrences of current-limit events trigger
hiccup mode, which protects external components by
In the case where EN is externally controlled and UVLO
for the power source is unnecessary, connect EN to IN
and an open-drain or open-collector output as shown in
Figure 2. The digital output connected to EN should be
capable of withstanding IN’s absolute maximum voltage
of 24V.
halting switching for a period of time (t ) and allow-
RSTRT
ing the overload current to dissipate in the load and
body diode of the synchronous rectifier before soft-start
is reattempted.
15
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Bootstrap Undervoltage Lockout
V
S
The devices have an internal bootstrap UVLO that is very
useful when designing high-voltage power supplies (see
the Block Diagrams). This allows the device to bootstrap
itself during initial power-up. The MAX5974A/MAX5974C
R
IN
soft-start when V exceeds the bootstrap UVLO thresh-
IN
old of V
(20V typ).
INUVR
IN
Because the MAX5974B/MAX5974D are designed for
use with low-voltage power sources such as wall adapt-
ers outputting 12V to 24V, they have a lower UVLO
wake-up threshold of 10V.
C
IN
MAX5974
R
EN1
Startup Operation
The device starts up when the voltage at IN exceeds
20V (MAX5974A/MAX5974C) or 10V (MAX5974B/
MAX5974D) and the enable input voltage is greater than
1.26V.
DIGITAL
CONTROL
EN
R
N
EN2
During normal operation, the voltage at IN is nor-
mally derived from a tertiary winding of the transformer
(MAX5974C/MAX5974D). However, at startup there is
no energy being delivered through the transformer;
hence, a special bootstrap sequence is required. In the
Figure 1. Programmable UVLO for the Power Source
Typical Application Circuits, C charges through the
IN
startup resistor, R , to an intermediate voltage. Only
IN
V
S
100FA of the current supplied through R is used by
IN
the ICs, the remaining input current charges C until
IN
V
V
reaches the bootstrap UVLO wake-up level. Once
exceeds this level, NDRV begins switching the
IN
IN
R
IN
n-channel MOSFET and transfers energy to the second-
ary and tertiary outputs. If the voltage on the tertiary
output builds to higher than 7V (the bootstrap UVLO
shutdown level), then startup has been accomplished
IN
C
IN
and sustained operation commences. If V drops below
7V before startup is complete, the device goes back to
IN
MAX5974
low-current UVLO. In this case, increase the value of C
IN
in order to store enough energy to allow for the voltage
at the tertiary winding to build up.
DIGITAL
CONTROL
EN
While the MAX5974A/MAX5974B derive their input volt-
age from the coupled inductor output during normal
operation, the startup behavior is similar to that of the
MAX5974C/MAX5974D.
N
Soft-Start
A capacitor from SS to GND, C , programs the soft-
SS
Figure 2. External Control of the Enable Input
start time. V controls the oscillator duty cycle during
SS
16
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
startup to provide a slow and smooth increase of the
duty cycle to its steady-state value. Calculate the value
p-Channel MOSFET Gate Driver
The AUXDRV output drives an external p-channel
MOSFET with the aid of a level shifter. The level shifter
of C as follows:
SS
consists of C
, R , and D5 as shown in the Typical
AUX AUX
Application Circuits. When AUXDRV is high, C
recharged through D5. When AUXDRV is low, the gate
of the p-channel MOSFET is pulled below the source by
is
AUX
I
× t
ss
SS-CH
2V
C
=
SS
the voltage stored on C , turning on the pFET.
AUX
where I
(10FA typ) is the current charging C dur-
SS
SS-CH
ing soft-start and t is the programmed soft-start time.
SS
Dead Time
A resistor can also be added from the SS pin to GND to
Dead time between the main and AUX output edges
allow ZVS to occur, minimizing conduction losses and
clamp V < 2V and, hence, program the maximum duty
SS
cycle to be less than 80% (see the Duty-Cycle Clamping
improving efficiency. The dead time (t ) is applied to
DT
section).
both leading and trailing edges of the main and AUX out-
puts as shown in Figure 3. Connect a resistor between
n-Channel MOSFET Gate Driver
The NDRV output drives an external n-channel MOSFET.
NDRV can source/sink in excess of 650mA/1000mA
peak current; therefore, select a MOSFET that yields
acceptable conduction and switching losses. The exter-
nal MOSFET used must be able to withstand the maxi-
mum clamp voltage.
DT and GND to set t to any value between 40ns and
DT
400ns:
10kΩ
40ns
R
=
× t
DT
DT
BLANKING, t
BLK
NDRV
AUXDRV
DEAD TIME, t
DT
Figure 3. Dead Time Between AUXDRV and NDRV
17
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
discharging capacitance at the FET’s drain, and gate-
Oscillator/Switching Frequency
charging current. Use a small RC network for additional
filtering of the leading-edge spike on the sense wave-
form when needed. Set the corner frequency between
10MHz and 20MHz.
The ICs’ switching frequency is programmable between
100kHz and 600kHz with a resistor R
connected
RT
between RT and GND. Use the following formula to
determine the appropriate value of R needed to gen-
RT
erate the desired output-switching frequency (f ):
SW
After the leading-edge blanking time, the device moni-
tors V
for any breaches of the peak current limit of
CS
9
8.7 ×10
400mV. The duty cycle is terminated immediately when
exceeds 400mV.
R
=
RT
V
CS
f
SW
Reverse Current Limit
The devices protect the transformer against saturation
due to reverse current by monitoring the voltage across
where f
is the desired switching frequency.
SW
Peak Current Limit
The current-sense resistor (R in the Typical
R
CS
while the AUX output is low and the p-channel FET
CS
Application Circuits), connected between the source
of the n-channel MOSFET and PGND, sets the current
limit. The current-limit comparator has a voltage trip level
is on.
Output Short-Circuit Protection
with Hiccup Mode
When the device detects eight consecutive peak current-
limit events, both NDRV and AUXDRV driver outputs are
(V
) of 400mV. Use the following equation to cal-
CS-PEAK
culate the value of R
:
CS
turned off for a restart period, t
device undergoes soft-start. The duration of the restart
period depends on the value of the capacitor at SS (C ).
. After t
, the
RSTRT
RSTRT
400mV
R
=
CS
I
PRI
SS
During this period, C is discharged with a pulldown cur-
SS
where I
is the peak current in the primary side of
PRI
rent of I
(2FA typ). Once its voltage reaches 0.15V,
SS-DH
the transformer, which also flows through the MOSFET.
When the voltage produced by this current (through the
current-sense resistor) exceeds the current-limit com-
parator threshold, the MOSFET driver (NDRV) terminates
the current on-cycle, within 35ns (typ).
the restart period ends and the device initiates a soft-start
sequence. An internal counter ensures that the minimum
restart period (t ) is 1024 clock cycles when the
RSTRT-MIN
time required for C to discharge to 0.15V is less than
SS
1024 clock cycles. Figure 4 shows the behavior of the
device prior and during hiccup mode.
The devices implement 115ns of leading-edge blanking
to ignore leading-edge current spikes. These spikes
are caused by reflected secondary currents, current-
V
CS-PEAK
(400mV)
V
CSBL
(BLANKED CS
VOLTAGE)
HICCUP
DISCHARGE WITH I
SS-DH
V
SS-HI
SOFT-START
VOLTAGE,
V
SS-DTH
V
SS
t
SS
t
RSTRT
Figure 4. Hiccup Mode Timing Diagram
18
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
SS
Frequency Foldback for High-Efficiency
Light-Load Operation
The frequency foldback threshold can be programmed
from 0 to 20% of the full load current using a resistor from
FFB to GND.
By connecting a resistor between SS and ground, the
voltage at SS can be made to be lower than 2V. V is
SS
calculated as follows:
V
= R ×I
SS SS-CH
SS
The CS voltage is sampled during the NDRV on-time,
averaged using an internal RC filter, and gained up
where R
is the resistor connected between SS and
SS
by 10 to generate a voltage, V
. When V
CSAVG
CSAVG
GND, and I
is the current sourced from SS to R
SS
SS-CH
falls below V
, the device folds back the switching
FFB
(10FA typ).
frequency to 1/2 the original value to reduce switching
losses and increase the converter efficiency. The new
switching frequency starts at the beginning of a new
DCLMP
using supply voltage feed-forward, connect
To set D
MAX
cycle as shown in Figure 5. Calculate the value of R
as follows:
a resistive divider between the supply voltage, DCLMP,
and GND as shown in the Typical Application Circuits.
This feed-forward duty-cycle clamp ensures that the
external n-channel MOSFET is not stressed during sup-
FFB
10 ×I
×R
CS
LOAD(LIGHT)
R
=
FFB
ply transients. V
is calculated as follows:
DCLMP
I
FFB
R
DCLMP2
where R
I
is the resistor between FFB and GND,
is the current at light-load conditions that
FFB
LOAD(LIGHT)
V
=
× V
S
DCLMP
R
+ R
DCLMP1
DCLMP2
triggers frequency foldback, R
is the value of the
CS
sense resistor connected between CS and PGND, and
is the current sourced from FFB to R (30FA typ).
where R
and R
are the resistive divider
DCLMP1
DCLMP2
I
values shown in the Typical Application Circuits and V
FFB
FFB
S
is the input supply voltage.
Duty-Cycle Clamping
The maximum duty cycle is determined by the lowest
of three voltages: 2V, the voltage at SS (V ), and the
Oscillator Synchronization
The internal oscillator can be synchronized to an external
clock by applying the clock to DITHER/SYNC directly. The
external clock frequency can be set anywhere between
1.1x to 2x the internal clock frequency.
SS
voltage (2.43V - V ). The maximum duty cycle is
DCLMP
calculated as:
V
MIN
D
=
MAX
2.43V
= minimum (2V, V , 2.43V - V ).
DCLMP
where V
MIN
SS
V
CSAVG
V
FFB
NDRV
t
t
x 2
t
x 2
SW
SW
SW
AUXDRV
COMP
Figure 5. Entering Frequency Foldback
19
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Using an external clock increases the maximum duty
cycle by a factor equal to f /f . This factor should
compensation amplitude, which is added to the current-
sense signal for stability of the peak current-mode
control loop. The ramp rate of the slope compensation
signal is given by:
SYNC SW
be accounted for in setting the maximum duty cycle
using any of the methods described in the Duty-Cycle
Clamping section. The formula below shows how the
maximum duty cycle is affected by the external clock
frequency:
R
× 50µA × f
CSSC
SW
m =
80%
V
f
SYNC
where m is the ramp rate of the slope-compensation
signal, R is the value of the resistor connected
MIN
D
=
×
MAX
2.43V
f
CSSC
SW
between CSSC and CS used to program the ramp rate,
and f is the switching frequency.
where V
is described in the Duty-Cycle Clamping
MIN
SW
section, f
is the switching frequency as set by the
SW
Error Amplifier
resistor connected between RT and GND, and f
is
SYNC
The MAX5974A/MAX5974B include an internal error
amplifier with a sample-and-hold input. The feedback
input of the MAX5974C/MAX5974D is continuously con-
nected. The noninverting input of the error amplifier is
connected to the internal reference and feedback is
provided at the inverting input. High open-loop gain and
unity-gain bandwidth allow good closed-loop bandwidth
and transient response. Calculate the power-supply out-
put voltage using the following equation:
the external clock frequency.
Frequency Dithering for Spread-
Spectrum Applications (Low EMI)
The switching frequency of the converter can be dith-
ered in a range of Q10% by connecting a capacitor from
DITHER/SYNC to GND, and a resistor from DITHER to RT
as shown in the Typical Application Circuits. This results
in lower EMI.
A current source at DITHER/SYNC charges the capaci-
R
+ R
FB1
R
FB2
tor C
to 2V at 50FA. Upon reaching this trip point,
DITHER
V
= V
×
OUT
REF
it discharges C
to 0.4V at 50FA. The charging
DITHER
FB2
and discharging of the capacitor generates a triangular
waveform on DITHER/SYNC with peak levels at 0.4V and
2V and a frequency that is equal to:
where V
= 1.52V for the MAX5974A/MAX5974B
= 1.215V for the MAX5974C/MAX5974D. The
REF
and V
REF
amplifier’s noninverting input is internally connected to
a soft-start circuit that gradually increases the reference
voltage during startup. This forces the output voltage to
come up in an orderly and well-defined manner under all
load conditions.
50µA
f
=
TRI
C
× 3.2V
DITHER
Typically, f
should be set close to 1kHz. The resistor
TRI
R
connected from DITHER/SYNC to RT deter-
DITHER
Applications Information
mines the amount of dither as follows:
Startup Time Considerations
R
4
3
The bypass capacitor at IN, C , supplies current
RT
DITHER
IN
%DITHER =
×
immediately after the devices wake up (see the Typical
R
Application Circuits). Large values of C
increase
IN
the startup time, but also supply gate charge for more
where %DITHER is the amount of dither expressed as a
cycles during initial startup. If the value of C is too
percentage of the switching frequency. Setting R
IN
DITHER
small, V drops below 7V because NDRV does not have
IN
to 10 x R generates Q10% dither.
RT
enough time to switch and build up sufficient voltage
across the tertiary output (MAX5974C/MAX5974D) or
coupled inductor output (MAX5974A/MAX5974B), which
powers the device. The device goes back into UVLO
Programmable Slope Compensation
The device generates a current ramp at CSSC such that
its peak is 50FA at 80% duty cycle of the oscillator. An
external resistor connected from CSSC to the CS then
converts this current ramp into programmable slope-
and does not start. Use a low-leakage capacitor for C
.
IN
20
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typically, offline power supplies keep startup times to
less than 500ms even in low-line conditions (85V AC
input for universal offline or 36V DC for telecom applica-
with adequate breakdown voltages, use the maximum
value of V . V occurs when the input
voltage is at its minimum and the duty cycle is at its
CLAMP CLAMP(MAX)
tions). Size the startup resistor, R , to supply both the
maximum. V
during normal opera-
IN
CLAMP(MAX-NORMAL)
maximum startup bias of the device (100FA) and the
tion is therefore:
charging current for C . C must be charged to 20V
IN
IN
V
within the desired 500ms time period. C must store
IN
S(MIN)
V
=
CLAMP(MAX-NORMAL)
enough charge to deliver current to the device for at
N
× V
P
O
1− N × V
least the soft-start time (t ) set by C . To calculate the
SS
SS
S
S(MIN)
approximate amount of capacitance required, use the
following formula:
where V
is the minimum voltage of the power
S(MIN)
source, N /N is the primary to secondary turns ratio,
P
S
I
= Q
f
GTOT SW
G
and V is the output voltage. The clamp capacitor,
O
(I +I )(t
)
IN
G
SS
n-channel, and p-channel FETs must have breakdown
voltages exceeding this level.
C
=
IN
V
HYST
If feed-forward maximum duty-cycle clamp is used then:
where I is the ICs’ internal supply current (1.8mA)
IN
after startup, Q
n-channel and p-channel FETs, f
ing frequency, V
is the total gate charge for the
GTOT
V
V
DCLMP
2.43
MIN
D
=
×
= 1−
is the ICs’ switch-
SW
MAX-FF
2.43
is the bootstrap UVLO hysteresis
HYST
(13V typ), and t is the soft-start time. R is then cal-
V
S
2.43
R
SS
IN
DCLMP2
+ R
DCLMP1 DCLMP2
= 1−
culated as follows:
R
V
− V
Therefore, V
mum duty clamp is:
during feed-forward maxi-
S(MIN)
INUVR
CLAMP(MAX-FF)
R
≅
IN
I
START
where V
is the minimum input supply voltage for
V
S(MIN)
S
V
=
CLAMP(MAX-FF)
the application (36V for telecom), V
strap UVLO wake-up level (20V), and I
supply current at startup (150FA max).
is the boot-
INUVR
1− D
+ R
MAX−FF
is the IN
START
2.43 × R
(
)
DCLMP1
DCLMP2
=
R
DCLMP2
Choose a higher value for R than the one calculated
IN
above if a longer startup time can be tolerated in order
to minimize power loss on this resistor.
The AUX driver controls the p-channel FET through a
level shifter. The level shifter consists of an RC network
(formed by C
in the Typical Application Circuits. Choose R
and R
) and diode D5, as shown
Active Clamp Circuit
Traditional clamp circuits prevent transformer saturation
AUX
AUX
and
AUX
C
AUX
so that the time constant exceeds 100/f . Diode
by channeling the magnetizing current (I ) of the trans-
SW
M
D5 is a small-signal diode with a voltage rating exceed-
ing 25V.
former onto a dissipative RC network. To improve effi-
ciency, the active clamp circuit recycles I between the
M
magnetizing inductance and clamp capacitor. V
is given by:
CLAMP
Additionally, C
complex poles formed with magnetizing inductance
should be chosen such that the
CLAMP
(L
) and C
are 2x to 4x away from the loop
MAG
CLAMP
V
S
bandwidth:
V
=
CLAMP
1− D
1-D
> 3 × f
BW
where V is the voltage of the power source and D is
S
the duty cycle. To select n-channel and p-channel FETs
2π L
× C
CLAMP
MAG
21
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
During on-time, the coupled output is:
Bias Circuit
Optocoupler Feedback (MAX5974C/MAX5974D)
An in-phase tertiary winding is needed to power the bias
circuit when using optocoupler feedback. The voltage
N
N
N
N
S
P
C
O
V
= −(V ×
− V )
OUT
COUPLED-ON
S
across the tertiary V during the on-time is:
T
where V is the input supply voltage.
S
N
N
T
S
Care must be taken to ensure that the voltage at FB
(equal to V attenuated by the feedback
V
= V
×
T
OUT
COUPLED-ON
resistive divider) is not more than 5V:
where V
is the output voltage and N /N is the turns
T S
OUT
R
ratio from the tertiary to the secondary winding. Select the
FB2
V
= V
×
< 5V
FB-ON
COUPLED-ON
turns ratio so that V is above the UVLO shutdown level
T
R
(
+ R
)
FB1
FB2
(7.5V max) by a margin determined by the holdup time
needed to “ride through” a brownout.
If this condition is not met, a signal diode should be
placed from GND (anode) to FB (cathode).
Coupled-Inductor Feedback (MAX5974A/MAX5974B)
When using coupled-inductor feedback, the power for
the devices can be taken from the coupled inductor dur-
ing the off-time. The voltage across the coupled induc-
Layout Recommendations
Typically, there are two sources of noise emission in a
switching power supply: high di/dt loops and high dV/dt
surfaces. For example, traces that carry the drain current
often form high di/dt loops. Similarly, the heatsink of the
main MOSFET presents a dV/dt source; therefore, mini-
mize the surface area of the MOSFET heatsink as much
as possible. Keep all PCB traces carrying switching cur-
rents as short as possible to minimize current loops. Use
a ground plane for best results.
tor, V , during the off-time is:
COUPLED
N
N
C
O
V
= V
×
COUPLED
OUT
where V
is the output voltage and N /N is the
C O
OUT
turns ratio from the coupled output to the main output
winding. Select the turns ratio so that V is
COUPLED
For universal AC input design, follow all applicable
safety regulations. Offline power supplies can require
UL, VDE, and other similar agency approvals.
above the UVLO shutdown level (7.5V max) by a margin
determined by the holdup time needed to “ride through”
a brownout.
This voltage appears at the input of the devices, less
a diode drop. An RC network consisting of R
and
SNUB
C
SNUB
is for damping the reverse recovery transients of
diode D6.
22
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Application Circuits
V
S
L1
3.3mH
36V TO 57V
D1
C
BULK
33µF
N
T
R
IN
100kI
D2
C
1µF
25V
IN
L2
6.8µH
5V, 5A
R
FB1
D3
GATE1
10I
R
10I
C
OUT5
0.1µF
GATE2
7.5kI
1%
C
C
C
C
OUT1 OUT2 OUT3 OUT4
T1
R
N
P
N
S
RDCLMP1
30.1kI
IN
N2
5i412DP
N
R
1%
FB2
2.49kI
EN
RDCLMP2
750I 1%
1%
D4
DCLMP
N
C
SS
0.1µF
N1
5i412DP
SS
DT
MAX5974C
MAX5974D
IN
R
DT
16.9kI 1%
N3
FDS3692
R
OPTO3
R
4.99kI
1%
OPTO1
825I
1%
(OPTOCOUPLER
FEEDBACK)
C
COMP1
2.2nF
C
CLAMP
47nF
R
10I
C
GATE3
DITHER
10nF
R
COMP2
499I
1%
DITHER/
SYNC
U1
FOD817CSD
NDRV
N
R
GATE4
R
RT
14.7kI 1%
10I
C
COMP2
6.8pF
N4
IRF6217
P
AUXDRV
RT
R
BIAS
C
AUX
47nF
4.02kI
1%
R
FFB
10.0kI 1%
R
F
C
INT
0.1µF
499I 1%
FFB
FB
CS
C
F
R
COMP2
330pF
R
R
G2
G1
121kI 1% 200kI 1%
2.00kI
1%
R
AUX
10kI
D5
COMP
CSSC
R
CSSC
4.02kI 1%
GND
PGND
U2
TLV4314AIDBVT-1.24V
R
OPTO2
1kI
1%
R
CS
0.2I
23
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Application Circuits (continued)
D6
R
FB1
54.9kI1%
C
R
SNUB
SNUB
V
S
10pF 69.8I1%
36V TO 57V
TO FB
R
FB2
C
33µF
63V
BULK
10kI 1%
R
IN
L
COUPLED
100kI
N
C
4 x 47µF
6.3V
C
1µF
25V
IN
5V, 5A
N
O
R
10I
R
D3
GATE2
DCLMP1
T1
30.1kI
C
C
C
C
OUT1 OUT2 OUT3 OUT4
R
GATE1
10I
N
P
N
S
C
OUT5
0.1µF
1%
N2
5i412DP
N
IN
EN
RDCLMP2
750I 1%
D4
N
DCLMP
C
SS
0.1µF
N1
5i412DP
SS
DT
MAX5974A
R
DT
MAX5974B
16.9kI 1%
N3
FDS3692
C
47nF
CLAMP
(COUPLED INDUCTOR
FEEDBACK)
R
10I
C
GATE3
DITHER
10nF
DITHER/
SYNC
NDRV
N
R
GATE4
R
RT
10I
N4
IRF6217
14.7kI 1%
P
AUXDRV
RT
C
AUX
47nF
R
FFB
10kI 1%
R
F
FFB
FB
499I 1%
CS
C
330pF
F
C
COMP
4.7nF
R
Z
R
AUX
D5
2kI 1%
10kI
COMP
CSSC
R
CSSC
GND
PGND
4.02kI 1%
C
INT
47nF
R
0.2I
CS
24
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Typical Application Circuits (continued)
L1
D1
V
S
N
T
C
D2
BULK
R
IN
L2
C
IN
T1
D3
GATE1
R
R
R
FB1
FB2
GATE2
C
C
OUT2
C
C
OUT3 OUT4
N
P
N
S
OUT1
R
N
IN
N2
R
DCLMP1
EN
D4
R
DCLMP2
N
DCLMP
C
SS
N1
SS
DT
MAX5974C
MAX5974D
R
DT
R
C
CLAMP
DITHER
R
GATE3
C
DITHER
NDRV
N
DITHER/
SYNC
N3
R
GATE4
R
RT
P
N4
AUXDRV
RT
C
AUX
R
FFB
FFB
CS
CSSC
FB
D5
R
AUX
R
CSSC
COMP
R
z
GND
PGND
R
CS
C
COMP
C
HF
Chip Information
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE_
TYPE
PACKAGE_
CODE
OUTLINE
NO.
LAND_
PATTERN_NO.
16 TQFN-EP
T1633+4
21-0136
90-0031
25
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
Revision History
REVISION
NUMBER
REVISION_
DATE
PAGES_
CHANGED
DESCRIPTION
0
6/10
Initial release
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
26_____________________ ________ Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©
2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
MAX5974DETE+T
Switching Controller, Current-mode, 600kHz Switching Freq-Max, BICMOS, 3 X 3 MM, ROHS COMPLIANT, TQFN-16
MAXIM
MAX5975A
Current-Mode PWM Controllers with Frequency Dithering for EMI-Sensitive Power Supplies
MAXIM
MAX5975AETE+
Switching Controller, Current-mode, 600kHz Switching Freq-Max, BICMOS, 3 X 3 MM, ROHS COMPLIANT, TQFN-16
MAXIM
MAX5975B
Current-Mode PWM Controllers with Frequency Dithering for EMI-Sensitive Power Supplies
MAXIM
MAX5975BETE+
Current-Mode PWM Controllers with Frequency Dithering for EMI-Sensitive Power Supplies
MAXIM
©2020 ICPDF网 联系我们和版权申明