MAX5987AETE_技术文档

19-6261; Rev 0; 4/12

E V A L U A T I O N K I T A V A I L A B L E

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Devices with Integrated DC-DC Converter

General Description

Benefits and Features

The MAX5986A/MAX5987A provide a complete power-

supply solution as IEEE 802.3af-compliant Class 1

S IEEE 802.3af Compliant

®

S PoE Class 1 Classification

Powered Devices (PDs) in a Power-over-Ethernet (PoE)

system. The MAX5986A/MAX5987A integrate the PD

interface with an efficient DC-DC converter, offering a low

external part count PD solution. The MAX5987A includes

a low-dropout regulator and the MAX5986A includes

sleep and ultra-low power modes.

S Simplified Wall Adapter Interface

S Efficient, Integrated DC-DC Converter (with

Integrated Switches)

S 8.7V to 60V Wide Input Voltage Range

S 3.0V to 5.6V Programmable Output Voltage Range

S Internal Compensation

The PD interface provides a detection signature and a

Class 1 classification signature with a single external

resistor. The PD interface also provides an isolation

power MOSFET, a 60mA (max) inrush current limit, and a

201mA (typ) operating current limit.

S Fixed 275kHz Switching Frequency

S Frequency Foldback for High-Efficiency Light-

Load Operation

The integrated step-down DC-DC converter uses a peak

current-mode control scheme and provides an easy-to-

implement architecture with a fast transient response.

The step-down converter operates in a wide input volt-

age range from 8.7V to 60V and supports up to 3.84W

of input power at 1.15A load. The DC-DC converter

operates at a fixed 275kHz switching frequency, with an

efficiency-boosting frequency foldback that reduces the

switching frequency by half at light loads.

S Built-In Output-Voltage Monitoring

S Open-Drain RESET Output (MAX5987A)

S Protects Against Overload, Output Short Circuit,

Output Overvoltage, and Overtemperature

S Hiccup-Mode Runaway Current Limit

S Back-Bias Capability to Optimize the Efficiency

S Integrated TVS Diode Withstands Cable Discharge

Event (CDE)

The devices feature an input undervoltage-lockout

(UVLO) with wide hysteresis and long deglitch time to

compensate for twisted-pair cable resistive drop and to

assure glitch-free transition during power-on/-off condi-

tions. The devices also feature overtemperature shut-

down, short-circuit protection, output overvoltage protec-

tion, and hiccup current limit for enhanced performance

and reliability.

S Internal LDO Regulator with Up to 100mA Load

(MAX5987A)

S Fixed 3.3V or Adjustable Output Voltage Through

an External Resistive Divider

S 49mA (typ) Inrush Current Limit

S Pass 2kV, 200m CAT-6 Cable Discharge Event

The MAX5986A/MAX5987A are available in a 16-pin,

5mm x 5mm, TQFN power package and operate over the

-40°C to +85°C temperature range.

Applications

IEEE 802.3af-Powered Devices

IP Phones

Wireless Access Nodes

IP Security Cameras

Ordering Information appears at end of data sheet.

®

WiMAX Base Stations

IEEE is a registered service mark of the Institute of Electrical

and Electronics Engineers, Inc.

For related parts and recommended products to use with this part,

refer to www.maxim-ic.com/MAX5986A/MAX5987A.related.

WiMAX is a registered certification mark and registered service

mark of WiMAX Forum.

�� Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Devices with Integrated DC-DC Converter

ABSOLUTE MAXIMUM RATINGS

(All voltages referenced to GND, unless otherwise noted.)

PGND to GND ......................................................-0.3V to +0.3V

LX Total RMS Current...........................................................1.6A

V

to GND...........................................................-0.3V to +70V

DD

Continuous Power Dissipation (T = + 70NC)

(100V, 100ms, R

= 3.3kω) (Note 1)

A

TEST

TQFN (derate 28.6mW/NC above +70NC)..............2285.7mW

Operating Temperature Range.......................... -40NC to +85NC

Junction Temperature .....................................................+150NC

Storage Temperature Range............................ -65NC to +150NC

Lead Temperature (soldering, 10s) ................................+300NC

Soldering Temperature (reflow) ......................................+260NC

V

, WAD, RREF to GND ........................ -0.3V to (V

+ 0.3V)

CC

DD

AUX, LDO_IN, LED to GND .................................... -0.3V to 16V

LDO_OUT to GND.............................. -0.3V to (LDO_IN + 0.3V)

LDO_FB to GND......................................................-0.3V to +6V

LX to GND ................................................ -0.3V to (V

LDO_OUT, VDRV, FB, RESET, WK, SL, ULP,

+ 0.3V)

CC

to GND..............................................................-0.3V to +6V

VDRV to V ............................................ -0.3V to (V

+ 0.3V)

DD

Note 1: See Figure 1, Test Circuit.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-

tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

PACKAGE THERMAL CHARACTERISTICS (Note 2)

Junction-to-Ambient Thermal Resistance (q )..............35°C/W

JA

Junction-to-Case Thermal Resistance (q )..................2.7°C/W

JC

Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-

layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

ELECTRICAL CHARACTERISTICS

(V

= 48V, R

= 24.9kω, LED, V , SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,

DD

SIG CC

C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), V = V

= 0V, LX unconnected. All voltages are referenced to GND, unless

FB

AUX

otherwise noted. T = T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 3)

A

J

A

PARAMETER

POWER DEVICE (PD) INTERFACE

DETECTION MODE

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input Offset Current

I

V

= 1.4V to 10.1V (Note 4)

10

FA

kI

OFFSET

dR

VDD

Effective Differential Input

Resistance

= 1.4V to 10.1V with 1V step,

VDD

23.95

25.5

(Note 5)

CLASSIFICATION MODE

Classification Enable Threshold

Classification Disable Threshold

Classification Stability Time

Classification Current

V

rising

10.2

22

11.42

23

12.5

23.8

V

TH,CLS,EN

DD

V

TH,CLS,DIS

DD

2

ms

mA

I

V

= 12.6V to 20V

9.12

11.88

CLASS

DD

POWER MODE

V

Supply Voltage Range

Supply Current

V

60

4.5

V

DD

I

V

= 60V

rising

falling

3.6

mA

DD

MAX5986A

MAX5987A

34.3

30

35.7

38.7

31.4

37.6

V

Turn-On Voltage

Turn-Off Voltage

V

DD

ON

V

OFF

�� Maxim Integrated Products

2

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Devices with Integrated DC-DC Converter

ELECTRICAL CHARACTERISTICS (continued)

(V

= 48V, R

= 24.9kω, LED, V , SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,

DD

SIG CC

C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), V = V

= 0V, LX unconnected. All voltages are referenced to GND, unless

FB

AUX

otherwise noted. T = T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 3)

A

J

A

PARAMETER

Turn-On/Off Hysteresis

Deglitch Time

SYMBOL

CONDITIONS

MIN

TYP

4.2

MAX

UNITS

V

MAX5986A

MAX5987A

3.4

V

(Note 6)

DD

HYST_UVLO

7.2

t

V

falling from 40V to 20V (Note 5)

100

Fs

DD

OFF_DLY

DD

t

= time from a (V

- V ) 1.5V

DELAY

DD CC

Inrush to Operating Mode Delay

t

75

90

110

2.2

60

ms

DELAY

to 0V step to DC-DC converter turn-on

T = +25NC

1.2

1.5

Isolation Power MOSFET

On-Resistance

J

I

R

I

= 100mA

VCC

ON_ISO

T = +85NC

J

CURRENT LIMIT

During initial turn-on period,

- V = 4V, measured at V

CC

Inrush Current Limit

I

39

49

mA

INRUSH

V

DD

CC

Current Limit During Normal

Operation

After inrush completed,

I

175

201

226

8.8

mA

V

LIM

V

= V

- 1.5V, measured at V

CC

DD CC

WAD Detection Rising Threshold

V

WAD_RISE

WAD_FALL

WAD Detection Falling

Threshold

V

5.8

V

WAD Detection Hysteresis

WAD Input Current

0.6

V

I

V

= 24V

125

FA

WAD

INTERNAL REGULATOR WITH BACK BIAS

V

Input Voltage Range

Input Current

V

Inferred from V input current

AUX

4.75

0.65

4.2

14

3.1

5.5

V

mA

V

AUX

DRV

AUX

V

from 4.75V to 14V

AUX

Output Voltage

SLEEP MODE (MAX5986A)

WK and ULP Logic Threshold

SL Logic Threshold

V

falling and V rising and falling

ULP

1.6

2.9

0.8

V

TH

WK

Falling

0.55

SL Current

V

R

= 0V

62.5

10.6

21.2

FA

SL

= 60.4kI, V

= 30.2kI, V

= 6.5V

= 3.5V

9.2

12

LED

LED Current Amplitude

I

19.2

23.5

mA

LED

LED Current Programmable

Range

10

20

mA

LED Current with Grounded SL

LED Current Frequency

V

= 0V

20.6

26.4

250

25

31.4

mA

Hz

%

SL

f

Sleep and ultra-low power modes

ILED

LED Current Duty Cycle

D

ILED

�� Maxim Integrated Products

3

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Devices with Integrated DC-DC Converter

ELECTRICAL CHARACTERISTICS (continued)

(V

= 48V, R

= 24.9kω, LED, V , SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,

DD

SIG CC

C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), V = V

= 0V, LX unconnected. All voltages are referenced to GND, unless

FB

AUX

otherwise noted. T = T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 3)

A

J

A

PARAMETER

SYMBOL

CONDITIONS

Sleep mode, V = 6.5V

MIN

TYP

12

MAX

UNITS

mA

%

V

Current Amplitude

I

10

14.5

DD

VDD

LED

Internal Current Duty Cycle

Internal Current Enable Time

Internal Current Disable Time

THERMAL SHUTDOWN

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

LDO (MAX5987A)

D

Sleep and ultra-low power modes

Ultra-low power mode

75

IVDD

MPS

t

76

87

98

ms

t

Ultra-low power mode

205

235

265

ms

MPDO

T

T rising

J

143

16

NC

SD

T

SD,HYS

Input Voltage Range

Inferred from line regulation

4.5

14

V

Output Voltage

LDO_FB = V

3.3

DRV

Max Output Voltage Setting

LDO FB Regulation Voltage

LDO FB Leakage Current

With external divider to LDO_FB

5.5

V

1.224

1

V

FA

V

= 5V, V

= 80mA

= V

,

LDO_IN

LDO_FB

DRV

Dropout

500

mV

I

LOAD

Load Regulation

Line Regulation

I

from 1mA to 80mA

0.4

3

mV/mA

mV/V

LOAD

VLDO_IN from 4.5V to 14V

Overcurrent Protection

Threshold

I

100

mA

OVC

LDO_FB Rising Threshold

LDO_FB Hysteresis

2

1

V

DC-DC CONVERTER INPUT SUPPLY

V

= V

+ 0.3V, rising

+ 0.3V, falling

8.7

7.6

60

DD,RISING

CC

DD

WAD

V

Voltage Range

V

DD

V

DD,FALLING

CC

DD

WAD

WAD Detection Rising Threshold

V

(Note 9)

8.8

V

WAD,RISE

WAD Detection Falling

Threshold

V

5.8

WAD,FALL

WAD Detection Hysteresis

POWER MOSFETs

0.6

I

High-Side pMOS On-Resistance

Low-Side nMOS On-Resistance

R

I

= 0.5A (sourcing)

= 0.5A (sinking)

0.65

0.16

1.01

0.33

DSON-H

LX

R

DSON-L

V

= V

= (V

= 28V,

DD

LX

CC

LX Leakage Current

I

-5

+5

FA

LX-LKG

+ 1V) to (V

- 1V)

PGND

CC

SOFT-START (SS)

Soft-Start Time

t

7.45

ms

SS-TH

�� Maxim Integrated Products

4

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Devices with Integrated DC-DC Converter

ELECTRICAL CHARACTERISTICS (continued)

(V

= 48V, R

= 24.9kω, LED, V , SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,

DD

SIG CC

C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), V = V

= 0V, LX unconnected. All voltages are referenced to GND, unless

FB

AUX

otherwise noted. T = T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 3)

A

J

A

PARAMETER

FEEDBACK (FB)

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

FB Regulation Voltage

FB Input Bias Current

OUTPUT VOLTAGE

Output Voltage Range

V

1.203

1.225

10

1.252

200

V

FB-RG

I

V

= 1.224V

nA

FB

V

3.0

101.5

98.2

5.6

107.8

104

V

OUT

Rising (Note 7)

Falling (Note 7)

105

Cycle by Cycle Overvoltage

Protection

V

%

OUT-OV

101.1

INTERNAL COMPENSATION NETWORK

Compensation Network Zero-

Resistance

R

200

150

kI

ZERO

Compensation Network Zero-

Capacitance

C

pF

CURRENT LIMIT

Peak Current-Limit Threshold

I

1.45

A

PEAK-LIMIT

Runaway Current-Limit

Threshold

I

RUNAWAY-

LIMIT

1.9

I

VALLEY-

LIMIT

Valley Current-Limit Threshold

1.5

25

A

ZX Threshold

I

mA

ZX

TIMINGS

Switching Frequency

Frequency Foldback

f

245

275

305

kHz

SW

f

122.5

137.5

152.5

SW-FOLD

Consecutive ZX Events for

Entering Foldback

8

Events

%

Consecutive ZX Events for

Exiting Foldback

V

Undervoltage Trip Level to

OUT

V

After soft-start completed (Note 7)

55

60

65

OUT-HICF

Cause HICCUP

HICCUP Timeout

Minimum On-Time

LX Dead Time

120

97

ms

ns

t

126

ON-MIN

14

RESET (MAX5987A)

V

Threshold for RESET

FB

V

falling (Note 7)

rising (Note 7)

90

95

%

FB-OKF

FB

Assertion

V

Threshold for RESET

FB

V

FB-OKR

Deassertion

�� Maxim Integrated Products

5

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Devices with Integrated DC-DC Converter

ELECTRICAL CHARACTERISTICS (continued)

(V

= 48V, R

= 24.9kω, LED, V , SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,

DD

SIG CC

C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), V = V

= 0V, LX unconnected. All voltages are referenced to GND, unless

FB

AUX

otherwise noted. T = T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 3)

A

J

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V

Threshold for RESET

V

falling, LDO_FB = V

DRV

LDO_FB

V

90

%

LDO_FB-OKF

Assertion

(Note 8)

RESET Deassertion Delay After

FB Reaches 95% Regulation

3.72

ms

RESET Output Voltage Low

RESET Leakage Current

I

= 1mA

0.1

10

V

SINK

FA

Note 3: All devices are 100% production tested at T = +25°C. Limits over temperature are guaranteed by design.

A

Note 4: The input offset current is illustrated in Figure 2.

Note 5: Effective differential input resistance is defined as the differential resistance between V

and GND, see Figure 2.

DD

Note 6: A 20V glitch on input voltage, which takes V

exit power-on mode.

below V

shorter than or equal to t

does not cause the device to

DD

ON

OFF_DLY

Note 7 Referred to feedback regulation voltage.

Note 8: Referred to LDO feedback regulation voltage.

Note 9: The WAD Detection Rising and Falling Thresholds control the isolation power MOS transistor. To turn the DC-DC on in

WAD mode, the WAD must be detected and the V

must be within the V

voltage range.

DD

I

IN

(V

(I

- V

)

1V

R

INi + 1

INi

TEST

dR =

i

=

- I

)

(I

- I

)

INi + 1 INi

V

INi

I

= I

-

OFFSET INi

dR

i

1ms/10ms/100ms

MAX5986A

I

INi + 1

100V

EVALUATION

BOARD

dR

i

I

INi

I

OFFSET

V

IN

V

INi

1V

V

INi + 1

Figure 1. MAX5986A/MAX5987A Internal TVS Test Setup

Figure 2. Effective Differential Resistance and Offset Current

�� Maxim Integrated Products

6

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Device with Integrated DC-DC Converter

Typical Operating Characteristics

(T = +25°C, unless otherwise noted.)

A

QUIESCENT CURRENT vs. SUPPLY

VOLTAGE (ULTRA-LOW POWER MODE)

SIGNATURE RESISTANCE

vs. SUPPLY VOLTAGE

DETECTION CURRENT vs. INPUT VOLTAGE

0.50

4.00

3.75

3.50

3.25

3.00

2.75

2.50

28

27

26

25

24

23

22

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

1.4

2.9

4.4

5.9

7.4

8.9 10.1

35

40

45

50

55

60

1.4

2.9

4.4

5.9

7.4

8.9 10.1

INPUT VOLTAGE (V)

SUPPLY VOLTAGE (V)

INPUT OFFSET CURRENT

vs. INPUT VOLTAGE

CLASSIFICATION CURRENT

vs. INPUT VOLTAGE

3

2

10.60

10.58

10.56

10.54

10.52

10.50

10.48

10.46

10.44

10.42

10.40

1

0

-1

-2

-3

1.4

2.9

4.4

5.9

7.4

8.9 10.1

12.6

14.1

15.6

17.1

18.6

20.0

SUPPLY VOLTAGE (V)

INPUT VOLTAGE (V)

INRUSH CURRENT LIMIT vs. V VOLTAGE

CC

CLASSIFICATION SETTLING TIME

60

56

52

48

44

40

MAX5986A toc06

V

DD

10V/div

GND

I

DD

10mA/div

0mA

0

6

12 18 24 30 36 42 48

(V)

400µs/div

V

CC

�� Maxim Integrated Products

7

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Device with Integrated DC-DC Converter

Typical Operating Characteristics (continued)

(T = +25°C, unless otherwise noted.)

A

EFFICIENCY vs. LOAD CURRENT

(V = 5V)

LED CURRENT vs. R

SL

LED CURRENT vs. LED VOLTAGE

OUT

28

24

20

18

12

8

100

95

90

85

80

75

70

65

60

55

50

25

20

15

10

5

V

DD

= 48V

R

= 30.2kI

SL

V

= 12V

WAD

V

DD

= 57V

R

= 60.4kI

SL

AUX CONNECTED TO V

OUT

10

20

30

40

R

50

60

70

80

0

100 200 300 400 500 600 700 800

LOAD CURRENT (mA)

0

1.75

3.50

5.25

7.00

(kI)

LED VOLTAGE (V)

SL

5V LOAD TRANSIENT

(0% TO 50%)

5V LOAD TRANSIENT

(50% TO 100%)

MAX5986A toc11

MAX5986A toc12

V

OUT

V

OUT

AC-COUPLED

50mV/div

AC-COUPLED

50mV/div

I

OUT

I

OUT

500mA/div

0A

100µs/div

DC-DC CONVERTER STARTUP

= 0A

DC-DC CONVERTER STARTUP

= 6.67I

I

R

OUT

MAX5986A toc13

MAX5986A toc14

V

OUT

1V/div

V

GND

2ms/div

�� Maxim Integrated Products

8

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Devices with Integrated DC-DC Converter

Pin Configurations

TOP VIEW

12

11

10

9

12

11

10

9

SL

LDO_FB

8

7

6

5

8

7

6

5

V

13

14

15

16

V

13

14

15

16

DD

VDRV

GND

FB

VDRV

GND

FB

CC

MAX5986A

MAX5987A

PGND

RREF

PGND

RREF

*EP

+

1

2

3

4

1

2

3

4

TQFN

*EXPOSED PAD, CONNECT TO GND

Pin Description

MAX5986A MAX5987A

NAME

FUNCTION

Auxiliary Voltage Input. Auxiliary input to the internal regulator V

. Connect AUX

DRV

1

AUX

to output of buck converter if the output voltage greater than 4.75V to back bias the

internal circuitry and increase efficiency. Connect to a clean ground when not used.

2

3

2

LX

Inductor Connection. Inductor connection for the internal DC-DC converter.

LED Driver Output. In sleep mode, LED sources a periodic current (I

25% duty cycle.

) at 250Hz with

LED

—

LED

Wake Mode Enable Input. WK has an internal 50kIpullup resistor to the internal 5V

bias rail. A falling edge on WK brings the device out of sleep mode and into the normal

operating mode (wake mode).

4

—

WK

LDO Input Voltage. Connect LDO_IN to output when used, otherwise connect to GND.

Connect a minimum 1FF bypass capacitor between LDO_IN and GND.

—

3

4

LDO_IN

LDO Output Voltage. Connect a minimum 1FF output capacitor between LDO_OUT and

GND.

LDO_OUT

�� Maxim Integrated Products

9

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Devices with Integrated DC-DC Converter

Pin Description (continued)

NAME

FB

FUNCTION

MAX5986A MAX5987A

Feedback. Feedback input for the DC-DC buck converter. Connect FB to a resistive

divider from the output to GND to adjust the output voltage.

5

Ground. Reference Rail for the Device. It is also the “quiet” ground for all voltage

reference (e.g. FB is referenced to this GND).

6, 10, 11

6, 9, 10

GND

Internal 5V Regulator Voltage Output. The internal voltage regulator provides 5V to the

7

8

7

VDRV

MOSFET driver and other internal circuits. V

drive external circuits. Connect a 1Ff bypass capacitor between V

is referenced to GND. Do not use V

to

DRV

and GND.

DRV

Sleep Mode Enable Input. A falling edge on SL brings the device into sleep mode. An

external resistor (R ) connected between SL and GND sets the LED current (I ).

—

SL

LED

Ultra-Low Power-Mode Enable Input. ULP has an internal 50kIpullup resistor to the

internal 5V bias rail. A falling edge on SL while ULP is asserted low enables ultra-low

power mode. When ultra-low power mode is enabled, the power consumption of the

device is reduced even lower than sleep mode to comply with ultra-low power sleep

power requirements while still supporting MPS.

9

—

ULP

Wall Power Adapter Detector Input. Wall adapter detection is enabled when the voltage

from WAD to GND is greater than 8.8V. When a wall power adapter is present, the

isolation p-channel power MOSFET turns off. Connect WAD directly to GND when the

wall power adapter or other auxiliary power source is not used.

12

WAD

13

14

13

14

V

Positive Supply Input. Connect a 68nF (min) bypass capacitor between V

and PGND.

DD

DC-DC Converter Power Input. V

is connected to V

by an isolation p-channel

DD

CC

MOSFET. Connect a 10FF capacitor in parallel with a 1FF ceramic capacitor between

CC

V

and PGND.

CC

Power Ground. Power ground of the DC-DC converter power stage. Connect PGND

to GND with a star connection. Do not use PGND as reference for sensitive feedback

circuit.

15

16

—

15

16

8

PGND

RREF

Signature Resistor Connection. Connect a 24.9kIresistor (R ) to GND.

SIG

LDO Regulator Feedback Input. Connect to V

to get the preset LDO output voltage

DRV

LDO_FB

of 3.3V, or connect to a resistive divider from the LDO_OUT to GND for an adjustable

LDO output voltage.

Open-Drain RESET Output. The RESET output is driven low if either LDO_OUT or FB

drops below 90% of its set value. RESET goes high 100Fs after both LDO_OUT and FB

rise above 95% of their set values. Leave unconnected when not used.

—

11

—

RESET

EP

Exposed Pad. Connect the exposed pad to ground.

�� Maxim Integrated Products 10

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Devices with Integrated DC-DC Converter

tion current at 10.5mA. The PSE uses this to determine

the maximum power to deliver. The classification cur-

Detailed Description

rent includes current drawn by the supply current of

the device so the total current drawn by the PD is within

PD Interface

The MAX5986A/MAX5987A include complete interface

the IEEE 802.3af standard. The classification current is

functions for a PD to comply with the IEEE 802.3af stan-

turned off when the device leaves classification mode.

dard as a Class 1 PD. The devices provide the detection

and classification signatures using a single external sig-

nature resistor. An integrated MOSFET provides isolation

from the buck converter when the PSE has not applied

power. The MAX5986A/MAX5987A guarantee a leakage

current offset of less than 10µA during the detection

phase. The devices feature power-mode undervoltage-

lockout (UVLO) with wide hysteresis and long deglitch

time to compensate for twisted-pair-cable resistive drop

and to ensure glitch-free transitions between detection,

classification, and power-on/-off modes.

Power Mode (V

> V

)

DD

ON

In power mode, the MAX5986A/MAX5987A have the

isolation MOSFET between V and V fully on. The

DD

CC

MAX5987A has the buck regulator enabled and the LDO

enabled. The MAX5986A can be in either wake mode,

sleep mode, or ultra-low power mode. The buck regulator

is enabled when the MAX5986A is in wake mode.

The devices enter power mode when V

rises above

DD

the undervoltage lockout threshold (V ). When V

ON

DD

rises above V , the device turns on the internal p-chan-

ON

nel isolation MOSFET to connect V

to V

with inrush

Operating Modes

The MAX5986A/MAX5987A operate in three different

CC

DD

current limit internally set to 49mA (typ). The isolation

MOSFET is fully turned on when V is near V and the

modes depending on V . The three modes are detec-

CC

DD

inrush current is below the inrush limit. Once the isola-

tion MOSFET is fully turned on, the device changes the

current limit to 201mA (typ). The buck converter turns on

100ms after the isolation MOSFET turns on fully.

tion mode, classification mode, and power mode. The

device is in detection mode when V

and 10.1V, classification mode when V

is between 1.4V

DD

is between

DD

12.6V and 20V, and power mode when the input voltage

exceeds V

.

ON

Undervoltage Lockout

The MAX5986A/MAX5987A operate with up to a 60V

supply voltage with a turn-on UVLO threshold (V ) at

35.4V/38.7V (typ), and a turn-off UVLO threshold (V

Detection Mode (1.4V < V

< 10.1V)

DD

In detection mode, the MAX5986A/MAX5987A provide

ON

OFF

a signature differential resistance to V . During detec-

)

DD

tion, the power-sourcing equipment (PSE) applies two

at 31.4V (typ). When the input voltage is above V

,

ON

voltages to V , both between 1.4V and 10.1V with a

the device enters power mode and the internal isolation

MOSFET is turned on. When the input voltage is below

DD

minimum 1V increment. The PSE computes the differ-

ential resistance to ensure the presence of the 24.9kω

signature resistor. Connect the 24.9kω signature resistor

V

for more than t

, the MOSFET and the buck

OFF_DLY

OFF

converter are off.

(R ) from RREF to GND for proper signature detec-

SIG

LED Driver (MAX5986A)

tion. The device applies V

to RREF when in detection

DD

The MAX5986A drives an LED, or multiple LEDs in series,

with a maximum LED voltage of 6.5V. In sleep mode and

ultra-low power mode, the LED current is pulse width

modulated with a duty cycle of 25% and the amplitude

mode, and the V

offset current due to the device is

DD

less than 10µA. The DC offset due to protection diodes

does not significantly affect the signature resistance

measurement.

is set by R . The LED driver current amplitude is pro-

SL

Classification Mode (12.6V < V

< 20V)

grammable from 10mA to 20mA using R according to

DD

SL

In classification mode, the MAX5986A/MAX5987A sink

a Class 1 classification current. The PSE applies a clas-

sification voltage between 12.6V and 20V, and measures

the classification current. The MAX5986A/MAX5987A use

the formula:

I

= 646/R (mA)

SL

LED

where R is in kω.

SL

the external 24.9kω resistor (R ) to set the classifica-

SIG

�� Maxim Integrated Products 11

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Devices with Integrated DC-DC Converter

The application circuit must ensure that the auxiliary

power source can provide power to V and V by

Sleep and Ultra-Low Power Modes

(MAX5986A)

The MAX5986A features a sleep mode and an ultra-low

power mode in which the internal p-channel isolation

MOSFET is kept on and the buck regulator is off. In sleep

mode, the LED driver output (LED) pulse width modu-

lates the LED current with a 25% duty cycle. The peak

DD

CC

means of external diodes. The voltage on V

must be

DD

within the V

voltage range to allow the DC-DC to oper-

DD

ate. To allow operation of the DC-DC converter, the V

DD

and V

voltage must be greater than 8.7V, on the rising

CC

edge, while on the falling edge the V

and V

may fall

DD

CC

down to 7.3V keeping the DC-DC converter on.

LED current (I

) is set by an external resistor R . To

LED

SL

enable sleep mode, apply a falling edge to SL with ULP

disconnected or high impedance. Sleep mode can only

be entered from wake mode.

Note: When operating solely with a wall power adapter,

the WAD voltage must be able to meet the condition V

> 8.7V, that likely results in WAD > 9.4V.

DD

Ultra-low power mode allows the MAX5986A to reduce

power consumption lower than sleep mode, while main-

taining the power signature of the IEEE standard. The

ultra-low power-mode enable input ULP is internally held

high with a 50kω pullup resistor to the internal 5V bias of

the device. To enable ultra-low power mode, apply a fall-

ing edge to SL with ULP = LOW. Ultra-low power mode

can only be entered from wake mode.

Internal Linear Regulator and Back Bias

An internal voltage regulator provides VDRV to internal

circuitry. The VDRV output is filtered by a 1µF capaci-

tor connected from VDRV to GND. The regulator is for

internal use only and cannot be used to provide power to

external circuits. VDRV can be powered by either V

or

DD

V

, depending on V

AUX

. The internal regulator is used

AUX

for both PD and buck converter operations.

To exit from sleep mode or ultra-low power mode and

resume normal operation, apply a falling edge on the

wake-mode enable input (WK).

V

can be used to back bias the VDRV voltage regu-

OUT

lator if V

is greater than 4.75V. Back biasing VDRV

OUT

increases device efficiency by drawing current from

instead of V . If V is used as back bias,

V

Thermal-Shutdown Protection

If the MAX5986A/MAX5987A die temperature reaches

143°C, an overtemperature fault is generated and the

device shuts down. The die temperature must cool down

below +127°C to remove the overtemperature fault con-

dition. After a thermal shutdown condition clears, the

device is reset.

OUT

DD

OUT

connect AUX directly to V

V

converter’s output has reached its regulation voltage.

. In this configuration, the

source switches from V

to V

after the buck

DRV

DD

AUX

Cable Discharge Event Protection (CDE)

A 70V voltage clamp is integrated to protect the internal

circuits from a cable discharge event.

WAD Description

For applications where an auxiliary power source such

as a wall power adapter is used to power the PD,

the MAX5986A/MAX5987A feature wall power adapter

detection.

DC-DC Buck Converter

The DC-DC buck converter uses a PWM, peak current-

mode, fixed-frequency control scheme providing an

easy-to-implement architecture without sacrificing a fast

transient response. The buck converter operates in a

wide input voltage range from 8.7V to 60V and supports

up to 3.84W of output power at 1.15A load. The devices

provide a wide array of protection features including

UVLO, overtemperature shutdown, short-circuit protec-

tion with hiccup runaway current limit, cycle-by-cycle

peak current protection, and cycle-by-cycle output over-

voltage protection, for enhanced performance and reli-

ability. A frequency foldback scheme is implemented to

reduce the switching frequency to half at light loads to

increase the efficiency.

The wall power adapter is connected from WAD to

PGND. The MAX5986A/MAX5987A detect the wall power

adapter when the voltage from WAD to PGND is greater

than 8.8V. When a wall power adapter is detected, the

internal isolation MOSFET is turned off, classification cur-

rent is disabled.

Connect the auxiliar power source to WAD, connect a

diode from WAD to V , and connect a diode from WAD

DD

to V . See the typical application circuit in Figure 2.

CC

�� Maxim Integrated Products 12

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Devices with Integrated DC-DC Converter

Frequency Foldback Protection for

High-Efficiency Light-Load Operation

auxiliary power source through V . Connect the auxil-

iary power source to WAD, connect a diode from WAD to

CC

The MAX5986A/MAX5987A enter frequency foldback

mode when eight consecutive inductor current zero-

crossings occur. The switching frequency is 275kHz

under loads large enough that the inductor current does

not cross zero. In frequency foldback mode, the switch-

ing frequency is reduced to 137.5kHz to increase power

conversion efficiency. The device returns to normal

mode when the inductor current does not cross zero for

eight consecutive switching periods. Frequency foldback

mode is forced during startup until 50% of the soft-start

is completed.

V

. See the typical application circuit in Figure 2.

CC

Adjusting LDO Output Voltage (MAX5987A)

An uncommitted LDO regulator is available to provide

a supply voltage to external circuits. A preset voltage

of 3.3V is set by connecting LDO_FB directly to VDRV.

For different output voltages connect a resistor divider

from LDO_OUT and LDO_FB to GND. The total feedback

resistance should be in the range of 100kω. The maxi-

mum output current is 85mA and thermal considerations

must be taken to prevent triggering thermal shutdown.

The LDO regulator can be powered by VOUT, a differ-

ent power supply, or grounded when not used. The LDO

is enabled once the buck converter has reached the

regulation voltage. The LDO is disabled when the buck

converter is turned off or not regulating.

Hiccup Mode

The MAX5986A/MAX5987A include a hiccup protection

feature. When hiccup protection is triggered, the devices

turn off the high-side and turn on the low-side MOSFET

until the inductor current reaches the valley current limit.

The control logic waits 120ms until attempting a new soft-

start sequence. Hiccup mode is triggered if the current

in the high-side MOSFET exceeds the runaway current-

limit threshold, both during soft-start and during normal

operating mode. Hiccup mode can also be triggered in

normal operating mode in the case of an output under-

voltage event. This happens if the regulated feedback

voltage drops below 60% (typ).

Adjusting Buck Converter Output Voltage

The buck converter output voltage is set by changing the

feedback resistor-divider ratio. The output voltage can

be set from 3.0V to 5.6V. The FB voltage is regulated to

1.225V. Keep the trace from the FB pin to the center of

the resistive divider short, and keep the total feedback

resistance around 100kω.

Inductor Selection

Choose an inductor with the following equation:

RESET Output (MAX5987A)

The MAX5987A features an open-drain RESET output

that indicates if either the LDO or the switching regula-

tor drop out of regulation. The RESET output goes low if

either regulator drops below 92% of its regulated feed-

back value. RESET goes high impedance 100µs after

both regulators are above 95% of their value.

where LIR is the ratio of the inductor ripple current to

full load current at the minimum duty cycle. Choose LIR

between 20% to 40% for best performance and stability.

Use an inductor with the lowest possible DC resistance

that fits in the allotted dimensions. Powdered iron ferrite

core types are often the best choice for performance.

With any core material, the core must be large enough

not to saturate at the current limit of the MAX5986A.

Applications Information

Operation with Wall Adapter

For applications where an auxiliary power source such

as a wall power adapter is used to power the PD, the

MAX5986A features wall power adapter detection. The

V

Input Capacitor Selection

CC

device gives priority to the WAD supply over V

supply,

DD

The input capacitor reduces the current peaks drawn

from the input power supply and reduces switching noise

in the IC. The total input capacitance must be equal or

greater than the value given by the following equation

to keep the input-ripple voltage within specification and

minimize the high-frequency ripple current being fed

back to the input source:

and smoothly switches the power supply to WAD when

it is detected. The wall power adapter is connected from

WAD to PGND. The MAX5986A detects the wall power

adapter when the voltage from WAD to PGND is greater

than 8.8V. When a wall power adapter is detected, the

internal isolation MOSFET is turned off, classification

current is disabled and the device draws power from the

�� Maxim Integrated Products 13

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Devices with Integrated DC-DC Converter

where V

is the maximum allowed input ripple

IN-RIPPLE

voltage across the input capacitors and is recommended

to be less than 2% of the minimum input voltage. D is the

duty cycle (V

f ).

S

/V ) and T is the switching period (1/

OUT IN

S

The impedance of the input capacitor at the switching

frequency should be less than that of the input source so

high-frequency switching currents do not pass through

the input source, but are instead shunted through the

input capacitor. The input capacitor must meet the ripple

current requirement imposed by the switching currents.

The RMS input ripple current is given by:

or whichever is larger. The peak-to-peak inductor current

(I

)

P-P

Use these equations for initial output capacitor selec-

tion. Determine final values by testing a prototype or an

evaluation circuit. A smaller ripple current results in less

output-voltage ripple. Since the inductor ripple current is

a factor of the inductor value, the output-voltage ripple

decreases with larger inductance. Use ceramic capaci-

tors for low ESR and low ESL at the switching frequency

of the converter. The ripple voltage due to ESL is negli-

gible when using ceramic capacitors.

where I

is the input RMS ripple current.

RIPPLE

Output Capacitor Selection

The key selection parameters for the output capacitor are

capacitance, ESR, ESL, and voltage-rating requirements.

These affect the overall stability, output ripple voltage,

and transient response of the DC-DC converter. The out-

put ripple occurs due to variations in the charge stored in

the output capacitor, the voltage drop due to the capaci-

tor’s ESR, and the voltage drop due to the capacitor’s

ESL. Estimate the output-voltage ripple due to the output

capacitance, ESR, and ESL:

Load-transient response depends on the selected output

capacitance. During a load transient, the output instantly

changes by ESR x I

. Before the controller can

LOAD

respond, the output deviates further, depending on the

inductor and output capacitor values. After a short time,

the controller responds by regulating the output voltage

back to its predetermined value. The controller response

time depends on the closed-loop bandwidth. A higher

bandwidth yields a faster response time, preventing the

output from deviating further from its regulating value.

V

= V

+ V

+V

RIPPLE

RIPPLE(C)

RIPPLE(ESR) RIPPLE(ESL)

where the output ripple due to output capacitance, ESR,

and ESL is:

�� Maxim Integrated Products 14

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Devices with Integrated DC-DC Converter

4) Connect V , V , and PGND separately to a large

PCB Layout

Careful PCB layout is critical to achieve clean and stable

operation. It is highly recommended to duplicate the

MAX5986A EV kit layout for optimum performance. If

deviation is necessary, follow these guidelines for good

PCB layout:

DD CC

copper area to help cool the IC to further improve

efficiency and long-term reliability.

5) Ensure all feedback connections are short and direct.

Place the feedback resistors and compensation com-

ponents as close as possible to the IC.

1) Connect input and output capacitors to the power

ground plane; connect all other capacitors to the sig-

nal ground plane.

6) Route high-speed switching nodes, such as LX, away

from sensitive analog areas (FB).

7) Place enough vias in the pad for the EP of the

MAX5986A/MAX5987A so that heat generated inside can

be effectively dissipated by the PCB copper. The recom-

mended spacing for the vias is 1mm to 1.2mm pitch. The

thermal vias should be plated (1oz copper) and have a

small barrel diameter (0.3mm to 0.33mm).

2) Place capacitors on V , V , AUX, V

as close

DRV

DD CC

as possible to the IC and its corresponding pin using

direct traces. Keep power ground plane (connected

to PGND) and signal ground plane (connected to

GND) separate.

3) Keep the high-current paths as short and wide as

possible. Keep the path of switching current short

and minimize the loop area formed by LX, the output

capacitors, and the input capacitors.

�� Maxim Integrated Products 15

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Devices with Integrated DC-DC Converter

Typical Application Circuits

C1

68nF

C2

10µF

RJ-45 AND

BRIDGE

1µF

RECTIFIER

V

WAD

AUX

DD CC

VDRV

L0

47µH

5V

OUTPUT

C3

1µF

LX

C4

47µF

R1

75kI

WK

ULP

SL

MAX5986A

TO µP OPEN-DRAIN OUTPUTS

OR PULLDOWN SWITCHES

FB

R2

24.9kI

R

SL

60.4kI

LED

RREF

GND

PGND

R

SIG

24.9kI

0I

Figure 3. MAX5986A 5V Output with Back Bias

�� Maxim Integrated Products 16

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Devices with Integrated DC-DC Converter

Typical Application Circuits (continued)

C1

68nF

C2

10µF

RJ-45 AND

BRIDGE

1µF

RECTIFIER

V

WAD

AUX

DD CC

LDO_FB

VDRV

L0

47µH

5V

OUTPUT

C3

1µF

LX

C4

47µF

R1

75kI

LDO_IN

TO 5V OUTPUT

MAX5987A

LDO_OUT

FB

C5

1µF

C6

1µF

R2

24.9kI

LED

RREF

GND

PGND

R

SIG

24.9kI

0I

Figure 4. MAX5987A 5V Buck Regulator Output and 3.3V LDO Output

�� Maxim Integrated Products 17

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Devices with Integrated DC-DC Converter

Functional Diagram

V

DD

CC

5V

TVS

HOT-SWAP

CONTROLLER

DETECTION

GND

CLASSIFICATION

5V

RREF

WAD

PD VOLTAGE

MONITOR

AUX

5V

1.5V

VDRV

1

5V

REGULATOR

0

CLK

LX

CONTROL

DRIVER

VREF

LDO_IN

VREF

LDO_OUT

LDO

PGND

FB

LDO_FB

(MAX5987A ONLY)

OPEN DRAIN

RESET

V

5V

DD

MAX5986A

MAX5987A

50kI

5V

WK

SL

VREF

BANDGAP

LOGIC

ULP

LED

(MAX5986A ONLY)

�� Maxim Integrated Products 18

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Devices with Integrated DC-DC Converter

Chip Information

Package Information

For the latest package outline information and land patterns

(footprints), go to www.maxim-ic.com/packages. Note that a

“+”, “#”, or “-” in the package code indicates RoHS status only.

Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

PROCESS: BiCMOS

PACKAGE

TYPE

PACKAGE OUTLINE

LAND

PATTERN NO.

CODE

NO.

16 TQFN-EP

T1655-4

21-0140

90-0121

Ordering Information

SLEEP/ULP

PART

PIN-PACKAGE

LDO

UVLO (V)

RESET

MODE

MAX5986AETE+

16 TQFN-EP*

YES

NO

35.7

38.7

NO

MAX5987AETE+**

NO

YES

+Denotes a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

**Future product—contact factory for availability.

�� Maxim Integrated Products 19

MAX5986A/MAX5987A

IEEE 802.3af-Compliant, High-Efficiency, Class 1,

Powered Devices with Integrated DC-DC Converter

Revision History

REVISION

NUMBER

REVISION

DATE

PAGES

CHANGED

DESCRIPTION

0

4/12

Initial release

—

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.

Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical

Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

20

©

2012 Maxim Integrated Products

Maxim is a registered trademark of Maxim Integrated Products, Inc.


型号：	MAX5987AETE
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	IEEE 802.3af-Compliant, High-Efficiency, Class 1,Powered Devices with Integrated DC-DC Converter 符合IEEE 802.3af标准，高效率， 1级，具有集成DC -DC转换器供电设备转换器
文件：	总20页 (文件大小：1817K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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