MAX6324CUT44-T [MAXIM]
Analog IC ; 模拟IC\n
| 型号： | MAX6324CUT44-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Analog IC
|
| 文件： | 总12页 (文件大小：236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1838; Rev 1; 1/01
µP Supervisory Circuits with Windowed
(Min/Max) Watchdog and Manual Reset
General Description
Features
The MAX6323/MAX6324 microprocessor (µP) supervi-
sory circuits monitor power supplies and µP activity in
digital systems. A watchdog timer looks for activity out-
side an expected window of operation. Six laser-
trimmed reset thresholds are available with 2.ꢀ5
accuracy from +2.32V to +4.63V. Valid RESET output is
ꢀ Min/Max (Windowed) Watchdog,
8 Factory-Trimmed Timing Options
ꢀ Pulsed Open-Drain, Active-Low Watchdog Output
ꢀ Power-On Reset
ꢀ Precision Monitoring of +2.5V, +3.0V, +3.3V,
guaranteed down to V
= +1.2V.
CC
and +5.0V Power Supplies
The RESET output is either push-pull (MAX6323) or
open-drain (MAX6324). RESET is asserted low when
CC
ꢀ Open-Drain or Push-Pull RESET Outputs
ꢀ Low-Power Operation (23µA typ)
ꢀ Debounced Manual Reset Input
V
falls below the reset threshold, or when the manual
reset input (MR) is asserted low. RESET remains assert-
ed for at least 100ms after V rises above the reset
CC
threshold or MR is deasserted.
ꢀ Guaranteed Reset Valid to V
= +1.2V
CC
The watchdog pulse output (WDPO) utilizes an open-
drain configuration. It can be triggered either by a fast
timeout fault (watchdog input pulses are too close to
each other) or a slow timeout fault (no watchdog input
pulse is observed within the timeout period). The
watchdog timeout is measured from the last falling
edge of watchdog input (WDI) with a minimum pulse
width of 300ns. WDPO is asserted for 1ms when a fault
is observed. Eight laser-trimmed timeout periods are
available.
Ordering Information
TEMP.
PIN-
RESET
PART*
RANGE
PACKAGE OUTPUT
MAX6323_UT__-T -40°C to +12ꢀ°C 6 SOT23-6 Push-Pull
MAX6324_UT__-T -40°C to +12ꢀ°C 6 SOT23-6 Open Drain
*These devices are factory trimmed to one of eight watchdog-
timeout windows and one of six reset voltage thresholds. Insert
the letter corresponding to the desired watchdog-timeout window
(A, B, C, D, E, F, G, or H) into the blank following the number
6323 or 6324 (see Watchdog Timeout table). Insert the two-digit
code (46, 44, 31, 29, 26, or 23) after the letters UT for the desired
nominal reset threshold (see Reset Threshold Range table at end
of data sheet).
The MAX6323/MAX6324 are offered in a 6-pin SOT23
package and operate over the extended temperature
range (-40°C to +12ꢀ°C).
Applications
Note: There are eight standard versions of each device available
(see Standard Versions table). Sample stock is generally held on
standard versions only. Standard versions have an order incre-
ment requirement of 2500 pieces. Nonstandard versions have an
order increment requirement of 10,000 pieces. Contact factory for
availability of nonstandard versions.
Automotive
Industrial
Medical
Embedded Control Systems
Watchdog Timeout
Pin Configuration
WATCHDOG TIMEOUT*
TOP VIEW
FAST
SLOW
UNITS
SUFFIX
MAX
1.ꢀ
1ꢀ
UNITS
ms
MIN
10
MR
GND
WDI
1
2
3
6
5
4
RESET
WDPO
A
B
C
D
E
ms
100
300
10
ms
s
MAX6323
MAX6324
1ꢀ
ms
1ꢀ
ms
V
CC
1ꢀ
ms
60
F
23
ms
47
ms
s
SOT23
G
H
39
719
ms
ms
82
1.3
Typical Operating Circuit appears at end of data sheet.
*See Figure 1 for operation.
________________________________________________________________ Maxim Integrated Products
1
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
µP Supervisory Circuits with Windowed
(Min/Max) Watchdog and Manual Reset
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND)
Continuous Power Dissipation (T = +70°C)
A
V
..................................................................-0.3V to +6.0V
6-Pin SOT23 (derate 8.7mW/°C above +70°C)..........696mW
Operating Temperature Range .........................-40°C to +12ꢀ°C
Junction Temperature......................................................+1ꢀ0°C
Storage Temperature Range.............................-6ꢀ°C to +1ꢀ0°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
MR, RESET (MAX6323), WDI .............-0.3V to (V
WDPO, RESET (MAX6324)..............................-0.3V to +6.0V
+ +0.3V)
CC
Input Current, V , WDI, MR ..............................................20mA
Output Current, RESET, WDPO ..........................................20mA
CC
Rate of Rise, V
............................................................100V/µs
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= full range, T = -40°C to +12ꢀ°C, unless otherwise noted. Typical values are at V
= 3V, T = +2ꢀ°C.) (Note 1)
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
ꢀ.ꢀ
UNITS
Operating Voltage Range
V
CC
1.2
V
V
V
= 2.ꢀV or 3.3V
= ꢀ.ꢀV
23
4ꢀ
CC
No load, RESET
deasserted
Supply Current
I
µA
CC
27
ꢀ7
CC
MAX632_ _UT46
MAX632_ _UT44
MAX632_ _UT31
MAX632_ _UT29
MAX632_ _UT26
MAX632_ _UT23
RESET deasserted
4.ꢀ0
4.2ꢀ
3.00
2.8ꢀ
2.ꢀꢀ
2.2ꢀ
100
4.63
4.38
3.08
2.93
2.63
2.32
180
20
4.7ꢀ
4.ꢀ0
3.1ꢀ
3.00
2.70
2.38
280
Reset Threshold Voltage
Reset Timeout Delay
V
t
V
TH
ms
µs
RP
10mV/ms, V +100mV to V -100mV
V
CC
to RESET Delay
TH
TH
I
= 1.2mA, V
= 2.2ꢀV (MAX632_ _UT23,
CC
SINK
MAX632_ _UT26, MAX632_ _UT29,
MAX632_ _UT31)
0.4
V
OL
V
WDPO, RESET Output Voltage
I
= 3.2mA, V
= 4.2ꢀV (MAX632_ _UT44,
SINK
CC
0.4
0.4
MAX632_ _UT46)
I
= 100µA, V > 1.2V, RESET asserted
CC
SINK
I
= ꢀ00µA, V = 3.1ꢀV, RESET
CC
SOURCE
0.8 x V
deasserted (MAX632_ _UT23, MAX632_ _UT26,
MAX632_ _UT29, MAX632_ _UT31)
CC
RESET Output Voltage
(MAX6323)
V
I
V
OH
I
= 800µA, V = 4.7ꢀV, RESET
CC
SOURCE
V
CC
- 1.ꢀ
deasserted, (MAX632_ _UT44, MAX632_ _UT46)
V
= V = +ꢀ.ꢀV, RESET, WDPO
RESET
WDPO
1
µA
WDPO, RESET Output Leakage
LKG
deasserted
2
_______________________________________________________________________________________
µP Supervisory Circuits with Windowed
(Min/Max) Watchdog and Manual Reset
ELECTRICAL CHARACTERISTICS (continued)
(V
= full range, T = -40°C to +12ꢀ°C, unless otherwise noted. Typical values are at V
= 3V, T = +2ꢀ°C.) (Note 1)
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
WATCHDOG INPUT AND OUTPUT
MAX632_AUT_ _
1
1.ꢀ
1ꢀ
MAX632_BUT_ _
MAX632_CUT_ _
MAX632_DUT_ _
MAX632_EUT_ _
MAX632_FUT_ _
MAX632_GUT_ _
MAX632_HUT_ _
MAX632_AUT_ _
MAX632_BUT_ _
MAX632_CUT_ _
MAX632_DUT_ _
MAX632_EUT_ _
MAX632_FUT_ _
MAX632_GUT_ _
MAX632_HUT_ _
10
10
1ꢀ
10
1ꢀ
Watchdog Timeout (Fast)
(Notes 2, 3)
t
ms
WD1
10
1ꢀ
17
23
29
39
ꢀ43
10
719
1ꢀ
100
300
10
1ꢀ0
4ꢀ0
1ꢀ
ms
s
Watchdog Timeout (Slow)
(Note 4)
t
WD2
60
90
47
63
ms
s
82
108
1.8
1.3
Minimum Watchdog Input
Pulse Width
300
ns
ns
V
WDI Glitch Immunity
V
= ꢀ.ꢀV
100
CC
V
0.7ꢀ x V
-1.ꢀ
IH
CC
WDI Input Voltage
V
0.8
IL
WDI = 0
WDI = V
-1
1
WDI Input Current
µA
ms
1.ꢀ
3
CC
V
IL
= 0.8V, V = 0.7ꢀV x V
IH
0.ꢀ
1
WDPO Pulse Width
CC
MANUAL RESET INPUT
V
0.7 x V
1
IH
CC
V
MR Input Voltage
V
0.3 x V
CC
IL
µs
ns
ns
k
MR Minimum Pulse Width
MR Glitch Immunity
MR to Reset Delay
V
V
= 2.ꢀV
100
120
8ꢀ
CC
= 2.ꢀV
CC
ꢀ0
MR Pullup Resistance
Note 1: Devices are tested at T = +2ꢀ°C and guaranteed by design for T = T
to T
, as specified.
MAX
A
A
MIN
Note 2: WDPO will pulse low if a falling edge is detected on WDI before this timeout period expires.
Note 3: To avoid a potential fake fault, the first WDI pulse after the rising edge of RESET or WDPO will not create a fast watchdog
timeout fault.
Note 4: WDPO will pulse low if no falling edge is detected on WDI after this timeout period expires.
_______________________________________________________________________________________
3
µP Supervisory Circuits with Windowed
(Min/Max) Watchdog and Manual Reset
Typical Operating Characteristics
(V
= full range, T = +2ꢀ°C, unless otherwise noted.)
A
CC
POWER-DOWN RESET DELAY
vs. TEMPERATURE
MR TO RESET DELAY
vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
40
35
30
25
20
160
140
120
100
80
V
CC
= 5.5V
V
V
= 20mV
OD
30
25
20
15
10
5
15
10
V
CC
= 3.3V
60
= 100mV
OD
20
40
V
CC
= 1.0V
5
0
20
0
0
-40
-20
0
20
40
60
80
-40
-20
0
40
60
80
-40
-20
0
20
40
60
80
TEMPERATURE ( C)
TEMPERATURE ( C)
TEMPERATURE ( C)
NORMALIZED RESET THRESHOLD
vs. TEMPERATURE
NORMALIZED POWER-UP RESET TIMEOUT
vs. TEMPERATURE
NORMALIZED WATCHDOG TIMEOUT
PERIOD (FAST) vs. TEMPERATURE
1.0005
1.0000
1.008
1.006
1.004
1.002
1.000
0.998
1.008
1.006
1.004
1.002
1.000
0.998
0.9995
0.9990
0.9985
0.9980
0.996
0.994
0.992
0.996
0.994
-40
-20
0
20
40
60
80
-40 -20
0
20
40
60
80
-40
-20
0
20
40
60
80
TEMPERATURE ( C)
TEMPERATURE ( C)
TEMPERATURE ( C)
NORMALIZED WATCHDOG OUTPUT
PULSE WIDTH vs. TEMPERATURE
MAXIMUM TRANSIENT DURATION
vs. RESET THRESHOLD OVERDRIVE
NORMALIZED WATCHDOG TIMEOUT
PERIOD (SLOW) vs. TEMPERATURE
1.008
1.006
1.004
1.002
1.000
0.998
400
350
300
1.003
1.002
1.001
1.000
0.999
0.998
V
= V - V
TH CC
OD
250
200
RESET ASSERTED
ABOVE THIS LINE
150
100
50
0.996
0.994
0.992
0.997
0.996
0.995
MAX632_AUT23
100
0
-40
-20
0
20
40
60
80
1
10
1000
-40
-20
0
20
40
60
80
TEMPERATURE ( C)
RESET COMPARATOR OVERDRIVE (mV)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
µP Supervisory Circuits with Windowed
(Min/Max) Watchdog and Manual Reset
Typical Operating Characteristics (continued)
(V
= full range, T = +2ꢀ°C, unless otherwise noted.)
A
CC
SLOW WATCHDOG TIMEOUT PERIOD
FAST WATCHDOG TIMEOUT PERIOD
MAX6323/24-11
MAX6323/24-10
WDI
2V/div
2V/div
WDI
2V/div
2V/div
WDPO
WDPO
MAX6323AUT23
500 s/div
MAX6323AUT23
5ms/div
Pin Description
PIN
NAME
MR
FUNCTION
Active-Low, Manual Reset Input. When MR is asserted low, RESET is asserted low, the internal watchdog
timer is reset to zero, and WDPO is reset to high impedance (open drain). After the rising edge of MR,
RESET is asserted for at least 100ms. Leave MR unconnected or connect to V
1
2
3
if unused.
CC
GND
WDI
Ground
Watchdog Input. The internal watchdog timer is reset to zero and begins to count at the falling edge of WDI
if RESET is high. If WDI sees another falling edge within the factory-trimmed watchdog window, WDPO will
remain unasserted. Transitions outside this window, either faster or slower, will cause WDPO to pulse low for
1ms (typ).
Supply Voltage for the Device. Input for V
(min) capacitor.
reset monitor. For noisy systems, bypass V
with a ꢀ00pF
CC
CC
4
ꢀ
V
CC
Watchdog Pulse Output. The open-drain WDPO output is pulsed low for 1ms (typ) upon detection of a fast
or slow watchdog fault. WDPO is only active when RESET is high.
WDPO
RESET
Active-Low. Reset is asserted when V
drops below V and remains asserted until V
rises above V
CC
TH
CC TH
for the duration of the reset timeout period. The MAX6323 has a push-pull output and the MAX6324 has an
6
open-drain output. Connect a pullup resistor from RESET to any supply voltage up to +6V.
_______________________________________________________________________________________
5
µP Supervisory Circuits with Windowed
(Min/Max) Watchdog and Manual Reset
t
(min)
)
t
(max)
t
(min)
t
(max)
WD1
WD1
WD2
WD2
POSSIBLE STATES
GUARANTEED TO
ASSERT WDPO
GUARANTEED NOT TO
ASSERT WDPO
GUARANTEED TO
ASSERT WDPO
*
*
UNDETERMINED
UNDETERMINED
CONDITION 1
FAST FAULT
CONDITION 2
CONDITION 3
NORMAL OPERATION
SLOW FAULT
*
UNDETERMINED STATES MAY OR MAY NOT GENERATE A FAULT CONDITION.
Figure 1. Detailed Watchdog Input Timing Relationship
other (faster than t
) (Figure 2) or falling edges that
WD1
Detailed Description
are too far apart (slower than t
) (Figure 3), WDPO is
WD2
The MAX6323/MAX6324 µP supervisory circuits main-
tain system integrity by alerting the µP to fault condi-
pulsed low. Normal watchdog operation is displayed in
Figure 4 (WDPO is not asserted). The internal watch-
dog timer is cleared when a WDI falling edge is detect-
ed within the valid watchdog window or when the
device’s RESET or WDPO outputs are deasserted. All
WDI input pulses are ignored while either RESET or
WDPO is asserted. Figure 1 identifies the input timing
regions where WDPO fault outputs will be observed
tions. In addition to a standard V
monitor (for
CC
power-on reset, brownout detect, and power-down
reset), the devices include a sophisticated watchdog
timer that detects when the processor is running out-
side an expected window of operation for a specific
application. The watchdog signals a fault when the
input pulses arrive too early (faster than the selected
with respect to t
and t
. After RESET or WDPO
WD2
WD1
t
timeout period) or too late (slower than the select-
WD1
ed t
deasserts, the first WDI falling edge is ignored for the
fast fault condition (Figure 2).
timeout period) (Figure 1). Incorrect timing can
WD2
lead to poor or dangerous system performance in tight-
ly controlled operating environments. Incorrect timing
could be the result of improper µP clocking or code
execution errors. If a timing error occurs, the
MAX6323/MAX6324 issue a watchdog pulse output,
independent from the reset output, indicating that sys-
tem maintenance may be required.
Upon detecting a watchdog fault, the WDPO output will
pulse low for 1ms. WDPO is an open-drain output.
Connect a pullup resistor on WDPO to any supply up to
+6V.
V
CC
Reset
The MAX6323/MAX6324 also include a standard V
CC
reset monitor to ensure that the µP is started in a known
state and to prevent code execution errors during
power-up, power-down, or brownout conditions.
Watchdog Function
A pulse on the watchdog output WDPO can be trig-
gered by a fast fault or a slow fault. If the watchdog
input (WDI) has two falling edges too close to each
RESET is asserted whenever the V
supply voltage
CC
6
_______________________________________________________________________________________
µP Supervisory Circuits with Windowed
(Min/Max) Watchdog and Manual Reset
t
< t
(min)
WDI WD1
RESET
WDI
WDPO
FAST FAULT
Figure 2. Fast Fault Timing
t
< t
(max)
WDI WD2
RESET
WDI
WDPO
SLOW FAULT
Figure 3. Slow Fault Timing
t
(max) < t < t
(min)
WD1
WDI WD2
RESET
WDI
H
WDPO
L
NORMAL OPERATION (NO PULSING, OUTPUT STAYS HIGH)
Figure 4. Normal Operation, WDPO Not Asserted
_______________________________________________________________________________________
7
µP Supervisory Circuits with Windowed
(Min/Max) Watchdog and Manual Reset
V
TH
V
CC
100ms (min)
100ms (min)
120ns (typ)
20 s (typ)
RESET
MR
1 s (min)
Figure 5. RESET Timing Relationship
falls below the preset threshold or when the manual
Applications Information
reset input (MR) is asserted. The RESET output remains
Negative-Going V
Transients
asserted for at least 100ms after V
has risen above
CC
The MAX6323/MAX6324 are relatively immune to short-
duration negative-going V transients (glitches),
CC
the reset threshold and MR is deasserted (Figure ꢀ).
For noisy environments, bybass V with a ꢀ00pF (min)
CC
CC
which usually do not require the entire system to shut
down. Typically, 200ns large-amplitude pulses (from
capacitor to ensure correct operation.
The MAX6323 has a push-pull output stage, and the
MAX6324 utilizes an open-drain output. Connect a pull-
up resistor on the RESET output of the MAX6324 to any
supply up to +6V. Select a resistor value large enough
to register a logic low (see Electrical Characteristics)
and small enough to register a logic high while supply-
ing all input leakage currents and leakage paths con-
nected to the RESET line. A 10k pullup is sufficient in
most applications.
ground to V ) on the supply will not cause a reset.
CC
Lower amplitude pulses result in greater immunity.
Typically, a V
transient that falls 100mV below the
CC
reset threshold and lasts less than 20µs will not trigger
a reset (see Typical Operating Characteristics). An
optional 0.1µF bypass capacitor mounted close to V
provides additional transient immunity.
CC
Ensuring a Valid Reset Output
Down to V = 0
CC
falls below +1.2V, the MAX6323 RESET out-
Manual Reset Input
Many µP-based products require manual reset capabil-
ity to allow an operator or external logic circuitry to initi-
ate a reset. The manual reset input (MR) can connect
directly to a switch without an external pullup resistor or
When V
CC
put no longer sinks current; it becomes an open circuit.
Therefore, high-impedance CMOS logic inputs con-
nected to RESET can drift to undetermined voltages.
This does not present a problem in most applications,
since most µPs and other circuitry are inoperative with
debouncing network. MR is internally pulled up to V
CC
and, therefore, can be left unconnected if unused. MR
is designed to reject fast, negative-going transients
(typically 100ns pulses), and it must be held low for a
minimum of 1µs to assert the reset output (Figure ꢀ). A
0.1µF capacitor from MR to ground provides additional
noise immunity. After MR transitions from low to high,
reset will remain asserted for the duration of the reset
timeout period, at least 100ms.
V
below +1.2V. However, in applications where
CC
RESET must be valid down to 0, adding a pulldown
resistor to RESET causes any stray leakage currents to
flow to ground, holding RESET low (Figure 6). R1’s
value is not critical; 100k is large enough not to load
RESET and small enough to pull RESET to ground. This
scheme does not work with the open-drain output of the
MAX6324.
8
_______________________________________________________________________________________
µP Supervisory Circuits with Windowed
(Min/Max) Watchdog and Manual Reset
V
CC
V
CC
V
CC
V
CC
V
CC
P
MAX6324
MAX6323
RESET
INPUT
RESET
RESET
R1
100k
GND
GND
GND
Figure 7. Interfacing to µPs with Bidirectional Reset Pins
Figure 6. RESET Valid to V
= Ground Circuit
CC
technique avoids a “stuck” loop in which the watchdog
time would continue to be reset within the loop, keeping
the watchdog from timing out.
Interfacing to µPs with
Bidirectional Reset Pins
Since the RESET output on the MAX6324 is open-drain,
this device easily interfaces with µPs that have bidirec-
tional reset pins, such as the Motorola 68HC11.
Connecting the µP supervisor’s RESET output directly
to the microcontroller’s (µC’s) RESET pin with a single
pullup resistor allows either device to assert reset
(Figure 7).
Figure 9 shows an example of a flow diagram where
the I/O driving the watchdog input is set high at the
beginning of the program, set low at the beginning of
every subroutine or loop, then set high again when the
program returns to the beginning. If the program should
“hang” in any subroutine, the problem would be quickly
corrected, since the I/O is continually set low and the
watchdog time is allowed to time out, causing a reset or
interrupt to be issued.
MAX6324 Open-Drain RESET Output
Allows Use with Multiple Supplies
Generally, the pullup resistor connected to the
MAX6324 will connect to the supply voltage that is
WDPO to MR Loopback
An error detected by the watchdog often indicates that
a problem has occurred in the µP code execution. This
could be a stalled instruction or a loop from which the
processor cannot free itself. If the µP will still respond to
a nonmaskable input (NMI), the processor can be redi-
rected to the proper code sequence by connecting the
WDPO output to an NMI input. Internal RAM data
should not be lost, but it may have been contaminated
by the same error that caused the watchdog to time
out.
being monitored at the IC’s V
pin. However, some
CC
systems may use the open-drain output to level-shift
from the monitored supply to reset circuitry powered by
some other supply (Figure 8). Keep in mind that as the
MAX6324’s V
decreases below +1.2V, so does the
CC
IC’s ability to sink current at RESET. Also, with any pull-
up resistor, RESET will be pulled high as V decays
CC
toward 0. The voltage where this occurs depends on
the pullup resistor value and the voltage to which it is
connected.
If the processor will not recognize NMI inputs, or if the
internal data is considered potentially corrupted when a
watchdog error occurs, the processor should be
restarted with a reset function. To obtain proper reset
timing characteristics, the WDPO output should be con-
nected to the MR input, and the RESET output should
Watchdog Software Considerations
To help the watchdog timer monitor software execution
more closely, set and reset the watchdog input at dif-
ferent points in the program, rather than “pulsing” the
watchdog input high-low-high or low-high-low. This
_______________________________________________________________________________________
9
µP Supervisory Circuits with Windowed
(Min/Max) Watchdog and Manual Reset
+3.3V
+5.0V
START
R
PULLUP
SET WDI
LOW
V
CC
V
CC
5V SYSTEM
MAX6324
SUBROUTINE OR
PROGRAM LOOP
SET WDI HIGH
RESET
INPUT
RESET
GND
GND
RETURN
END
Figure 8. MAX6324 Open-Drain RESET Output Allows Use with
Multiple Supplies
drive the µP RESET input (Figure 10). The short 1ms
WDPO pulse output will assert the manual reset input
and force the RESET output to assert for the full reset
timeout period (100ms min). All internal RAM data is
lost during the reset period, but the processor is guar-
anteed to begin in the proper operating state.
Figure 9. Watchdog Flow Diagram
Reset Threshold Range
(-40°C to +125°C)
Standard Versions
SUFFIX
46
MIN
4.ꢀ0
4.2ꢀ
3.00
2.8ꢀ
2.ꢀꢀ
2.2ꢀ
TYP
4.63
4.38
3.08
2.93
2.63
2.32
MAX
4.7ꢀ
4.ꢀ0
3.1ꢀ
3.00
2.70
2.38
UNITS
MAX6323AUT29
MAX6323AUT46
MAX6323CUT29
MAX6323CUT46
MAX6323DUT29
MAX6323DUT46
MAX6323HUT29
MAX6323HUT46
MAX6324AUT29
MAX6324AUT46
MAX6324BUT29
MAX6324BUT46
MAX6324EUT29
MAX6324EUT46
MAX6324HUT29
MAX6324HUT46
44
31
V
29
26
23
Chip Information
TRANSISTOR COUNT: 1371
PROCESS: BiCMOS
10 ______________________________________________________________________________________
µP Supervisory Circuits with Windowed
(Min/Max) Watchdog and Manual Reset
V
CC
500pF
V
CC
V
CC
*R
PULLUP
P
MAX6323
MAX6324
RESET
WDI
RESET
I/O
MR
WDPO
GND
*MAX6324 ONLY
Figure 10. WDPO to MR Loopback Circuit
Typical Operating Circuit
V
CC
500pF
V
CC
V
CC
*R
PULLUP
P
MAX6323
MAX6324
RESET
WDI
RESET
I/O
MR
WDPO
NMI
GND
*MAX6324 ONLY
______________________________________________________________________________________ 11
µP Supervisory Circuits with Windowed
(Min/Max) Watchdog and Manual Reset
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明