MAX6391KA44 [MAXIM]
Dual-Voltage uP Supervisory Circuits with Sequenced Reset Outputs; 双电压高达监控电路，与被排序的复位输出
| 型号： | MAX6391KA44 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual-Voltage uP Supervisory Circuits with Sequenced Reset Outputs |
| 文件： | 总9页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2210; Rev 1; 10/02
Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
General Description
Features
The MAX6391/MAX6392 microprocessor (µP) supervisory
circuits provide sequenced logic reset outputs for multi-
component or dual-voltage systems. Each device can
monitor two supply voltages and time-sequence two reset
outputs to control the order in which system components
are turned on and off. The MAX6391/MAX6392 increase
system reliability and reduce circuit complexity and cost
compared to separate ICs or discrete components.
o Preset V
Reset Threshold Voltages from 1.58V
CC
to 4.63V (master supply)
o Customer-Adjustable RESET IN2 to Monitor
Voltages Down to 625mV (secondary supply)
o Fixed (140ms min) RESET1 Timeout
o Fixed (140ms min) or Customer-Adjustable
RESET2 Timeout Period
The MAX6391/MAX6392 monitor V
as the master
CC
reset supply. Both RESET1 and RESET2 are asserted
whenever V drops below the selected factory-fixed
o Guaranteed Reset Valid to V
= 1V
CC
CC
o Active-Low Open-Drain Outputs or Push-
reset threshold voltage. RESET1 remains asserted as
long as V is below the threshold and deasserts
Pull/Open-Drain Combination
CC
140ms (min) after V
exceeds the thresholds.
CC
o Internal Open-Drain Pullup Resistors (for external
RESET IN2 is monitored as the secondary reset supply
and is adjustable with an external resistive-divider net-
V
voltage connections)
OH
o Manual Reset Input (MAX6392 only)
o Immune to Short Negative V Transients
work. RESET2 is asserted whenever either V
or
CC
RESET IN2 is below the selected thresholds. RESET2
CC
remains asserted 140ms (min) or a capacitor-
o 15µA Typical Supply Current
o Few External Components
o Small 8-Pin SOT23 Package
adjustable time period after V
and RESET IN2
CC
exceed their thresholds. RESET2 is always deasserted
after RESET1 during system power-up and is always
asserted before RESET1 during power-down.
The MAX6391 includes two internal pullup resistors for
RESET1 and RESET2 (the open-drain outputs can be
externally connected to the desired pullup voltages).
The MAX6392 includes an active-low manual reset
input (MR) that asserts both RESET1 (push-pull) and
RESET2 (open drain).
Ordering Information
PART*
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
SOT23-8
MAX6391KA_ _-T
MAX6392KA_ _-T
SOT23-8
The MAX6391/MAX6392 are available in small 8-pin
SOT23 packages and are specified over the -40°C to
+85°C extended temperature range.
*Insert the desired suffix (see Selector Guide) into the blanks to
complete the part number. The MAX6391/MAX6392 require a
2.5k minimum order increment and are available in tape-and-
reel only. Samples are typically available for standard versions
(see Selector Guide for standard versions). Contact factory for
availability.
Applications
Computers
Controllers
Pin Configurations
Critical µP Power Monitoring
Set-Top Boxes
TOP VIEW
Printers
RESET IN2
1
2
3
4
8
7
6
5
R1
Servers/Workstations
Industrial Equipment
Multivoltage Monitoring
V
CC
RESET1
R2
MAX6391
CSRT
GND
RESET2
SOT23-8
Typical Operating Circuit appears at end of data sheet.
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
ABSOLUTE MAXIMUM RATINGS
CC
RESET1 (MAX6392), RESET IN2, CSRT,
MR to GND ..............................................-0.3V to (V
V
to GND...........................................................-0.3V to +6.0V
Operating Teꢀperature Range ...........................-40°C to +85°C
Junction Teꢀperature......................................................+150°C
Storage Teꢀperature Range.............................-65°C to +150°C
Lead Teꢀperature (soldering, 10s) .................................+300°C
+ 0.3V)
CC
RESET1 (MAX6391), RESET2, R1, R2 to GND......-0.3V to +6.0V
Input Current (V , GND, CSRT, R1, R2, MR) ................. 20ꢀA
CC
Output Current (RESET1, RESET2) .................................. 20ꢀA
Continuous Power Dissipation (T = +70°C)
A
8-Pin SOT23 (derate 5.26ꢀW/°C above +70°C)...........421ꢀW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 1.2V to 5.5V, T = T
A
to T
, unless otherwise specified. Typical values are at V
= +5V and T = +25°C.) (Note 1)
CC A
CC
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
= 0°C to +85°C
MIN
1.0
TYP
MAX
5.5
UNITS
V
T
T
A
V
Range
CC
= -40°C to +85°C
1.2
5.5
A
Supply Current
I
No load
15
25
µA
CC
MAX639_UA46
MAX639_UA44
MAX639_UA31
MAX639_UA29
MAX639_UA26
MAX639_UA23
MAX639_UA22
MAX639_UA17
MAX639_UA16
4.50
4.25
3.00
2.85
2.55
2.25
2.12
1.62
1.54
610
4.63
4.38
3.08
2.93
2.63
2.32
2.19
1.67
1.58
625
4.75
4.50
3.15
3.00
2.70
2.38
2.25
1.71
1.61
640
50
V
Reset Threshold
V
V
V
CC
TH1
RESET IN2 Threshold
V
= 5V
ꢀV
nA
TH2
CC
RESET IN2 Input Current
V
to RESET1 Delay
t
t
20
10
CC
RD1
RD2
V
falling at 1ꢀV/µs (Note 2)
µs
V
or RESET IN2 to RESET2
CC
CC
Delay
2
_______________________________________________________________________________________
Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= 1.2V to 5.5V, T = T
A
to T
, unless otherwise specified. Typical values are at V
= +5V and T = +25°C.) (Note 1)
CC A
CC
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
140
2.2
TYP
200
3.1
MAX
280
4.0
UNITS
RESET1 Tiꢀeout Period
t
ꢀs
RP1
C
C
= 1500pF
CSRT
CSRT
RESET2 Tiꢀeout Period (Note 3)
RESET_ Output Voltage Low
t
ꢀs
V
RP2
= V
140
200
280
CC
V
≥ 1.0V,
CC
0.3
T
= 0°C to +85°C
A
I
= 50µA,
SINK
reset asserted
V
≥ 1.2V,
CC
V
0.3
OL
T
= -40°C to +85°C
A
I
I
= 1.2ꢀA, reset asserted, V
= 3.2ꢀA, reset asserted, V
≥ 2.5V
0.3
0.4
SINK
SINK
CC
≥ 4.25V
CC
Open-Drain RESET Output
Leakage Current
V
≥ V
, V
≥ V
,
CC
TH1 RESET IN2
TH2
I
1.0
µA
V
LKG
reset not asserted
V
≥ 2.25V, I
= 500µA,
SOURCE
CC
reset not asserted
✿
Push-Pull RESET1 Output
Voltage High (MAX6392 only)
0.8
V
OH
V
CC
V
≥ 4.5V, I
= 800µA, reset not
SOURCE
CC
asserted
V
0.8
IL
V
V
> 4.0V
CC
CC
V
2.4
IH
✿
0.3
MR Input
V
V
IL
V
CC
< 4.0V
✿
0.7
V
IH
V
CC
MR Miniꢀuꢀ Pulse Width
MR Glitch Rejection
50
µs
ns
µs
ns
µs
kΩ
kΩ
100
10
MR to RESET1 Delay
MR to RESET2 Delay
t
t
MR1
MR2
100
10
t
Skew
t
- t
MR1 MR2
MR
MR Pullup Resistance
Pullup to V
35
35
47
60
60
CC
Reset Pullup Resistance
RESET1 to R1 or RESET2 to R2
47
Note 1: Overteꢀperature liꢀits are guaranteed by design and not production tested. Devices tested at +25°C only.
Note 2: RESET2 asserts before RESET1 when V goes below the threshold for all supply voltage and teꢀperature ranges.
CC
Note 3: CSRT ꢀust be connected to either V
adjustable RESET2 tiꢀeout period).
(for fixed RESET2 tiꢀeout period) or an external capacitor (for user-
CC
_______________________________________________________________________________________
3
Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
Typical Operating Characteristics
(V
CC
= +5V, T = +25°C, unless otherwise noted.)
A
V
FALLING TO RESET2 DELAY
vs. TEMPERATURE
V
FALLING TO RESET1 DELAY VS.
TEMPERATURE
CC
CC
SUPPLY CURRENT vs. TEMPERATURE
17
17
16
15
14
13
12
11
10
9
28
27
26
25
24
23
22
21
20
16
15
14
13
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
RESET2 TO RESET1 DELAY
vs. TEMPERATURE
RESET1 TIMEOUT PERIOD
vs. TEMPERATURE
RESET1 TO RESET2 TIMEOUT PERIOD
vs. TEMPERATURE (CSRT = 1500pF)
300
275
250
225
200
3.50
3.25
3.00
2.75
2.50
11.8
11.6
11.4
11.2
11.0
10.8
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
MAXIMUM TRANSIENT DURATION
vs. RESET COMPARATOR OVERDRIVE
RESET1 TO RESET2 TIMEOUT PERIOD
vs. TEMPERATURE (CSRT TIED TO V
)
CC
60
50
40
30
20
10
300
275
250
225
200
RESET ASSERTS ABOVE
THIS LINE
1
10
100
1000
-40
-15
10
35
60
85
OVERDRIVE (mV)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
Pin Description
PIN
NAME
FUNCTION
MAX6391
MAX6392
Input Voltage for RESET2 Monitor. High-impedance input for internal reset
comparator. Connect this pin to an external resistive-divider network to set the reset
threshold voltage.
1
2
1
2
RESET IN2
V
Supply Voltage and Input Voltage for Primary Supply Monitor
CC
RESET2 Delay Set Capacitor. Connect to V
for a fixed 140ms (min) timeout period
CC
3
4
3
4
CSRT
GND
or to an external capacitor for a user-adjustable timeout period after V exceeds its
CC
minimum threshold.
Ground
Secondary Reset Output, Open-Drain, Active-Low. RESET2 changes from high to low
when either V or RESET IN2 drop below their thresholds. RESET2 remains low for a
user-adjustable timeout period (see CSRT) or a fixed 140ms (min) after V and
CC
RESET IN2 meet their minimum thresholds.
CC
5
6
5
6
RESET2
R2
47kΩ Internal Pullup Resistor for RESET2. Connect to external voltage for RESET2
high pullup.
Primary Reset Output, Open-Drain (MAX6391) or Push-Pull (MAX6392), Active-Low.
RESET1 changes from HIGH to LOW when the V
reset threshold. RESET1 remains LOW for the reset timeout period after V
the minimum threshold.
input drops below the selected
CC
7
7
RESET1
R1
exceeds
CC
47kΩ Internal Pullup Resistor for RESET1. Connect to external voltage for RESET1
high pullup.
8
—
8
Manual Reset, Active-Low, Internal 47kΩ Pullup to V . Pull LOW to force a reset.
RESET1 and RESET2 remain asserted as long as MR is LOW and for the RESET1 and
RESET2 timeout periods after MR goes HIGH. Leave unconnected or connect to V
CC
—
MR
CC
if unused.
(ꢀin) or a user-adjustable tiꢀe period after RESET IN2
Detailed Description
rises above the 625ꢀV reset threshold and RESET1 is
Each device includes a pair of voltage ꢀonitors with
sequenced reset outputs. The first block ꢀonitors V
deasserted. Resets are guaranteed valid for V
to 1V.
down
CC
CC
only (RESET1 output is independent of the RESET IN2
ꢀonitor). It asserts a reset signal (LOW) whenever V
The tiꢀing diagraꢀ in Figure 2 shows the reset tiꢀing
characteristics of the MAX6391/MAX6392. As shown in
CC
is below the preset voltage threshold. RESET1 reꢀains
asserted for at least 140ꢀs after V rises above the
Figure 2, RESET1 deasserts 140ꢀs (ꢀin) (t
) after
RP1
CC
V
exceeds the reset threshold. RESET2 deasserts
CC
RP2
reset threshold. RESET1 tiꢀing is internally set in each
device. V voltage thresholds are available froꢀ
t
(140ꢀs ꢀiniꢀuꢀ or a user-adjustable tiꢀeout peri-
CC
od) after RESET IN2 exceeds 625ꢀV and RESET1 is
1.57V to 4.63V. In all cases V
acts as the ꢀaster
CC
deasserted. When RESET IN2 drops below 625ꢀV
supply (all resets are asserted when V
goes below
CC
while V
is above the reset threshold, RESET2 asserts
CC
its selected threshold). The V
device power supply.
input also acts as the
CC
within 10µs typ. RESET1 is unaffected when this hap-
pens. When V falls below V , RESET2 always
CC
TH1
The second block ꢀonitors both RESET IN2 and V . It
CC
asserts a reset signal (LOW) whenever RESET IN2 is
asserts before RESET1 (t
< t
).
RD2
RD1
below the 625ꢀV threshold or V
is below its reset
CC
threshold. RESET2 reꢀains asserted for a fixed 140ꢀs
_______________________________________________________________________________________
5
Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
MR
(MAX6392 ONLY)
V
CC
V
CC
MR
DETECT
(MAX6392
ONLY)
R1
MR
PULLUP
(MAX6391 ONLY)
47kΩ
FIXED RESET
TIMEOUT
PERIOD
RESET1
1.25V
V
CC
R2
47kΩ
0.625V
FIXED OR
CAPACITOR-
ADJUSTABLE
RESET TIMEOUT
PERIOD
RESET2
RESET IN2
CSRT
Figure 1. Functional Diagram
V
TH1
V
TH1
V
CC
t
RD1
t
RP1
RESET1
V
V
TH2
TH2
RESET IN2
t
t
t
RD2
RD2
RP2
t
RP2
RESET2
Figure 2. Timing Diagram
6
_______________________________________________________________________________________
Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
chain. The MAX6391 internally deterꢀines the CSRT
connection and provides the proper tiꢀing setup.
Selector Guide
NOMINAL
THRESHOLD (V)
In all cases, RESET IN2 acts as the slave supply. V
can assert the RESET2 output but RESET IN2 will have
no effect on the RESET1 output.
CC
PART NUMBER
TOP MARK
MAX6391KA46
MAX6391KA44
MAX6391KA31
MAX6391KA29
MAX6391KA26
MAX6391KA23
MAX6391KA22
MAX6391KA17
MAX6391KA16
MAX6392KA46
MAX6392KA44
MAX6392KA31
MAX6392KA29
MAX6392KA26
MAX6392KA23
MAX6392KA22
MAX6392KA17
MAX6392KA16
4.63
4.38
3.08
2.93
2.63
2.32
2.19
1.67
1.58
4.63
4.38
3.08
2.93
2.63
2.32
2.19
1.67
1.58
AAHJ
AAHK
AAHL
AAHM
AAHN
AAHO
AAHP
AAHQ
AAHR
AAHS
AAHT
AAHU
AAHV
AAHW
AAHX
AAHY
AAHZ
AAIA
Monitoring Voltages Other Than V
CC
An external resistive-divider network is required at
RESET IN2 for ꢀost applications. The divider resistors,
R3 and R4, ꢀay be calculated by the following forꢀula:
✕
V
= V
(R3 + R4)/R4
RST
TH2
where V
RST
= 625ꢀV (internal reference voltage) and
TH2
V
is the desired reset threshold voltage. R4 ꢀay be
set to a conveniently high value (500kΩ for exaꢀple, to
ꢀiniꢀize current consuꢀption) and the equation ꢀay
be solved for R3 by:
✕
R3 = R4 (V
/V
- 1)
RST TH2
For single-supply operations requiring two reset out-
puts (RESET1 before RESET2), connect RESET IN2
directly to V
and adjust RESET2 tiꢀeout delay with
CC
as desired.
C
CRST
Pullup Resistors
The MAX6391 includes open-drain outputs for both
RESET1 and RESET2. Two internal resistors, R1 and
R2, of 47kΩ each are provided with internal connec-
tions to RESET1 and RESET2. These resistors ꢀay be
connected to the appropriate external voltage for inde-
Standard versions in bold face. Samples are typically available
for standard versions. Contact factory for availability.
pendent V
drive with no additional coꢀponent
OH
Applications Information
requireꢀents.
The MAX6392 includes a ꢀanual reset option, MR, that
replaces the R1 pullup resistor. The active-low ꢀanual
reset input forces both RESET1 and RESET2 low.
RESET2 is driven active before RESET1 in all cases
(10µs typ). The resets follow standard reset tiꢀing
specifications after the ꢀanual reset is released. The
Selecting the Reset Timeout Capacitor
The RESET2 delay ꢀay be adjusted by the user with an
external capacitor connected froꢀ the CSRT pin to
ground. The MAX6391 includes a 600nA current source
that is switched to C
to create a voltage raꢀp. The
CSRT
voltage raꢀp is coꢀpared to the internal 1.25V refer-
ence to set the RESET2 delay period. The period is cal-
culated by:
ꢀanual reset is internally pulled up to V
through a
CC
47kΩ resistor.
✕
∆t = C ∆V/I
Negative-Going V
Transients
CC
In addition to issuing a reset to the µP during power-up,
power-down, and brownout conditions, these devices
are relatively iꢀꢀune to short-duration, negative-going
where ∆V = 1.25V, I = 600nA, and C is the external
capacitor.
Siꢀplifying,
V
or RESET IN2 transients (glitches). The Typical
CC
6
✕
✕
t
= 2.08 10 s / F
C
CSRT
Operating Characteristics show the Maxiꢀuꢀ Transient
Duration vs. Reset Coꢀparator Overdrive graph. The
graph shows the ꢀaxiꢀuꢀ pulse width that a negative-
RP
For C
= 1500pF, t = 3.1ꢀs
RP
CSRT
A fixed internal 140ꢀs (ꢀin) reset delay tiꢀe for
going V
transient ꢀay typically have without issuing
a reset signal. As the aꢀplitude of the transient increas-
es, the ꢀaxiꢀuꢀ allowable pulse width decreases.
CC
RESET2 ꢀay be chosen by connecting the CSRT pin to
V . The V
CC
to CSRT connection disables the voltage
CC
raꢀp and enables a separate fixed delay counter
_______________________________________________________________________________________
7
Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
Typical Operating Circuit
V
= 3.3V
CC
MASTER
PROCESSOR
V
RESET1
R2
RESET
CC
MAX6392
V
= 1.8V
GND
CC
R3
R4
MR
RSTIN2
RESET2
SLAVE
CSRT
PROCESSOR
C
CSRT
RESET
Chip Information
Pin Configurations (continued)
TRANSISTOR COUNT: 810
PROCESS: BiCMOS
TOP VIEW
RESET IN2
1
2
3
4
8
7
6
5
MR
V
RESET1
R2
CC
MAX6392
CSRT
GND
RESET2
SOT23-8
8
_______________________________________________________________________________________
Dual-Voltage µP Supervisory Circuits
with Sequenced Reset Outputs
Package Information
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
© 2002 Maxiꢀ Integrated Products
Printed USA
is a registered tradeꢀark of Maxiꢀ Integrated Products.
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