MAX6444US [MAXIM]
uP Reset Circuits with Long Manual Reset Setup Period; 上电复位电路，带有长手动复位初始化期间
| 型号： | MAX6444US |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | uP Reset Circuits with Long Manual Reset Setup Period |
| 文件： | 总13页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2656; Rev 3; 6/10
µP Reset Circuits with Long Manual Reset
Setup Period
3–MAX6452
General Description
Features
o Single- or Dual-Supply Voltage Monitors
o Precision Factory-Set Reset Thresholds from
The MAX6443–MAX6452 low-current microprocessor
reset circuits feature single or dual manual reset inputs
with an extended setup period. Because of the extend-
ed setup period, short switch closures (nuisance resets)
are ignored.
1.6V to 4.6V
o Adjustable Threshold to Monitor Voltages Down
to 0.63V (MAX6449–MAX6452)
On all devices, the reset output asserts when any of the
monitored supply voltages drops below its specified
threshold. The reset output remains asserted for the
reset timeout period (210ms typ) after all monitored
supplies exceed their reset thresholds. The reset output
is one-shot pulse asserted for the reset timeout period
(140ms min) when selected manual reset input(s) are
held low for an extended setup timeout period. These
devices ignore manual reset transitions of less than the
extended setup timeout period.
o Single or Dual Manual Reset Inputs with Extended
Setup Period
o Optional Short Setup Time Manual Reset Input
(MAX6447/MAX6448 and MAX6451/MAX6452)
o Immune to Short Voltage Transients
o Low 6µA Supply Current
o Guaranteed Valid Reset Down to V
= 1.0V
CC
The MAX6443–MAX6448 are single fixed-voltage µP
supervisors. The MAX6443/MAX6444 have a single
extended manual reset input. The MAX6445/MAX6446
have two extended manual reset inputs. The MAX6447/
MAX6448 have one extended and one immediate manual
reset input.
o Active-Low RESET (Push-Pull or Open-Drain)
Outputs
o 140ms (min) Reset Timeout Period
o Small SOT143 and SOT23 Packages
Ordering Information
The MAX6449–MAX6452 have one fixed-threshold µP
supervisor and one adjustable-threshold µP supervisor.
The MAX6449/MAX6450 have two delayed manual
reset inputs. The MAX6451/MAX6452 have one delayed
and one immediate manual reset input.
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
4 SOT143
MAX6443US_ _ _-T
MAX6444US_ _ _-T
4 SOT143
Note: The first “_ _ ” is a placeholder for the threshold voltage
level of the devices. A desired threshold level is set by the two-
number suffix found in Table 1. The third "_" is a placeholder
for the manual reset setup period of the devices. A desired
setup period is set by the letter suffix found in Table 2. All
devices are available in tape-and-reel only. There is a 2500-
piece minimum order increment for standard versions (Table
2). Sample stock is typically held on standard versions only.
Nonstandard versions require a minimum order increment of
10,000 pieces. Contact factory for availability.
The MAX6443–MAX6452 have an active-low RESET
with push-pull or open-drain output logic options. These
devices, offered in small SOT packages, are fully guar-
anteed over the extended temperature range (-40°C to
+85°C).
Applications
Set-Top Boxes
Consumer Electronics
DVD Players
Devices are available in both leaded and lead-free packaging.
Specify lead-free by replacing “-T” with “+T” when ordering.
Cable/DSL Modems
MP3 Players
Pin Configurations
TOP VIEW
Industrial Equipment
Automotive
4
3
1
2
GND
V
CC
Medical Devices
MAX6443
MAX6444
RESET
MR1
SOT143
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
µP Reset Circuits with Long Manual Reset
Setup Period
ABSOLUTE MAXIMUM RATINGS
All Voltages Referenced to GND
Operating Temperature Range .......................... -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow)
V
CC
..........................................................................-0.3V to +6V
Open-Drain RESET ..................................................-0.3V to +6V
Push-Pull RESET ........................................-0.3V to (V + 0.3V)
MR1, MR2, MR2, RSTIN ..........................................-0.3V to +6V
CC
Input Current, All Pins....................................................... 20mA
Lead(Pb)-free……………………………………………..+260°C
Containing lead………………………………………… +240°C
Continuous Power Dissipation (T = +70°C)
A
4-Pin SOT143 (derate 4.0mW/°C above +70°C)...........320mW
5-Pin SOT23 (derate 7.1mW/°C above +70°C).............571mW
6-Pin SOT23 (derate 8.7mW/°C above +70°C).............696mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 1.0V to 5.5V, T = -40°C to +85°C, unless otherwise specified. Typical values are at T = +25°C.) (Note 1)
CC
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
5.5
UNITS
3–MAX6452
Operating Voltage Range
V
1.0
V
CC
V
V
= 5.5V, no load
7
20
CC
CC
V
Supply Current
I
µA
CC
CC
= 3.6V, no load
6
16
46
44
31
29
26
23
22
17
16
4.50
4.25
3.00
2.85
2.55
2.25
2.12
1.62
1.52
4.63
4.38
3.08
2.93
2.63
2.32
2.19
1.67
1.58
60
4.75
4.50
3.15
3.00
2.70
2.38
2.25
1.71
1.62
V
Reset Threshold
V
V
CC
TH
Reset Threshold Tempco
Reset Threshold Hysteresis
ppm/°C
mV
2 × V
TH
T
T
= 0°C to +85°C
0.615
0.610
0.630
0.645
0.650
A
RSTIN Threshold
V
MAX6449–MAX6452
V
TH-RSTIN
= -40°C to +85°C
A
RSTIN Threshold Hysteresis
RSTIN Input Current
V
MAX6449–MAX6452
MAX6449–MAX6452
2.5
mV
nA
HYST
I
-25
+25
280
RSTIN
MAX6449–MAX6452, V
1mV/µs
falling at
RSTIN
RSTIN to Reset Output Delay
15
µs
Reset Timeout Period
t
140
210
20
ms
µs
RP
V
to RESET Output Delay
t
V
falling at 1mV/µs
CC
CC
RD
K
L
S
T
6.72
4.48
2.24
1.12
10.08
13.44
8.96
4.48
2.24
6.72
3.36
1.68
Manual Reset Minimum Setup
Period Pulse Width
t
s
MR
2
_______________________________________________________________________________________
µP Reset Circuits with Long Manual Reset
Setup Period
3–MAX6452
ELECTRICAL CHARACTERISTICS (continued)
(V
= 1.0V to 5.5V, T = -40°C to +85°C, unless otherwise specified. Typical values are at T = +25°C.) (Note 1)
CC
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MR2 Minimum Setup Period
Pulse Width
MAX6447/MAX6448/MAX6451/MAX6452
1
µs
MR2 Glitch Rejection
MAX6447/MAX6448/MAX6451/MAX6452
MAX6447/MAX6448/MAX6451/MAX6452
100
200
210
50
ns
ns
MR2 to RESET Delay
Manual Reset Timeout Period
t
140
25
280
75
ms
kΩ
kΩ
MRP
MR1 to V
MR2 to V
Pullup Impedance
Pullup Impedance
CC
CC
MAX6445/MAX6446/MAX6449/MAX6450
25
50
75
V
≥ 1.00V, I
= 50µA, RESET asserted
0.3
0.3
0.3
0.4
CC
SINK
V
≥ 1.20V, I
= 100µA, RESET
= 1.2mA, RESET
= 3.2mA, RESET
CC
SINK
asserted
≥ 2.55V, I
RESET Output Low
(Open Drain or Push-Pull)
V
V
OL
V
CC
SINK
asserted
V
≥ 4.25V, I
CC
SINK
asserted
V
≥ 1.80V, I
= 200µA, RESET
= 500µA, RESET
= 800µA, RESET
CC
SOURCE
SOURCE
SOURCE
0.8 × V
0.8 × V
0.8 × V
CC
CC
CC
deasserted
V ≥ 3.15V, I
CC
RESET Output High
(Push-Pull)
V
V
OH
deasserted
V
≥ 4.75V, I
CC
deasserted
RESET Open-Drain Leakage
Current
I
RESET deasserted
1
µA
V
LKG
MR1, MR2, MR2
Input Low Voltage
V
0.3 × V
CC
IL
MR1, MR2, MR2
Input High Voltage
V
0.7 × V
V
IH
CC
Note 1: Devices production tested at T = +25°C. Overtemperature limits are guaranteed by design.
A
_______________________________________________________________________________________
3
µP Reset Circuits with Long Manual Reset
Setup Period
Typical Operating Characteristics
(V
= 3.3V, T = +25°C, unless otherwise noted.)
A
CC
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED RESET TIMEOUT PERIOD
vs. TEMPERATURE
MAXIMUM TRANSIENT DURATION
vs. RESET THRESHOLD OVERDRIVE
9
8
7
6
5
4
3
2
1
0
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
250
200
150
100
50
T
= +85°C
A
T
= +25°C
A
RESET OCCURS
ABOVE THE CURVE
T
= -40°C
A
V
= 4.4V
800
TH
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
-40
-15
10
35
60
85
0
200
400
600
1000
TEMPERATURE (°C)
RESET THRESHOLD OVERDRIVE (mV)
3–MAX6452
NORMALIZED V RESET THRESHOLD
CC
RSTIN TO RESET DELAY
vs. TEMPERATURE (RSTIN FALLING)
V
TO RESET DELAY
vs. TEMPERATURE
CC
vs. TEMPERATURE
1.03
1.02
1.01
1.00
0.99
0.98
0.97
24.0
23.6
23.2
22.8
22.4
22.0
21.6
21.2
20.8
20.4
20.0
24.0
23.6
23.2
22.8
22.4
22.0
21.6
21.2
20.8
20.4
20.0
V
= FALLING AT 1mV/µs
RSTIN FALLING AT 1mV/µs
CC
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
MANUAL RESET TO RESET DELAY
(MAX6445L/MAX6446L/MAX6449L/MAX6450L)
V
CC
TO RESET DELAY
MAX6443/52 toc08
MAX6443/52 toc07
V
= 5V
CC
MR1
(5V/div)
V
= 4.5V
CC
V
= 4.392V
TH
V
(100mV/div)
CC
V
= 4.3V
CC
MR2
(5V/div)
RESET
RESET
(2V/div)
(5V/div)
TIME (100µs/div)
TIME (1s/div)
4
_______________________________________________________________________________________
µP Reset Circuits with Long Manual Reset
Setup Period
3–MAX6452
Pin Description
PIN
NAME
FUNCTION
MAX6443 MAX6445 MAX6447 MAX6449 MAX6451
MAX6444 MAX6446 MAX6448 MAX6450 MAX6452
1
2
2
1
2
2
GND
Ground
Active-Low Push-Pull or Open-Drain Output. RES ET
changes from high to low when V or RSTIN drops below
CC
its selected reset threshold and remains low for the 210ms
reset timeout period after all monitored power-supply inputs
2
1
1
1
RESET exceed their selected reset thresholds. RES ET is one-shot
pulsed low for the reset timeout period (140ms min) after
selected manual reset inputs are asserted longer than the
specified setup period. For the open-drain output, use a
minimum 20kΩ pullup resistor to V
.
CC
Manual Reset Input, Active Low. Internal 50kΩ pullup to
Pull MR1 low for the typical input pulse width (t
V
)
MR
3
—
3
—
3
CC.
to one-shot pulse RESET for the reset timeout period.
MR1
Manual Reset Input, Active Low. Pull both MR1 and
MR2 low for the typical input pulse width (t ) to one-
shot pulse RESET for the reset timeout period.
—
4
3
4
—
4
3
4
—
4
MR
V
Voltage Input. Power supply and input for the
CC
V
CC
primary microprocessor voltage reset monitor.
Manual Reset Input, Active Low. Internal 50kΩ pullup to
V
. Pull both MR1 and MR2 low for the typical input
CC
—
5
—
6
—
MR2
pulse width (t ) to one-shot pulse RESET for the reset
MR
timeout period.
Manual Reset Input. Pull the MR2 high to immediately
one-shot pulse RESET for the reset timeout period.
—
—
—
—
5
—
5
6
5
MR2
Reset Input. High-impedance input to the adjustable
reset comparator. Connect RSTIN to the center point of
an external resistor-divider to set the threshold of the
externally monitored voltage.
—
RSTIN
threshold voltages. Once V
and V
exceed their
CC
RSTIN
Detailed Description
respective reset threshold voltages, RESET remains low
for the reset timeout period and then goes high. RESET
is one-shot pulsed whenever selected manual reset
inputs are asserted. RESET stays asserted for the nor-
mal reset timeout period (140ms min).
Reset Output
The reset output is typically connected to the reset
input of a microprocessor (µP). A µP’s reset input starts
or restarts the µP in a known state. The MAX6443–
MAX6452 µP supervisory circuits provide the reset
logic to prevent code-execution errors during power-
up, power-down and brownout conditions (see the
Typical Operating Circuit).
RESET is guaranteed to be in the proper output logic
state for V
inputs ≥ 1V. For applications requiring valid
CC
reset logic when V
is less than 1V, see the Ensuring a
CC
Valid RESET Output Down to V
= 0V section.
CC
RESET changes from high to low whenever the moni-
tored voltages (RSTIN or V ) drop below the reset
CC
_______________________________________________________________________________________
5
µP Reset Circuits with Long Manual Reset
Setup Period
Manual Reset Input Options
RESET TIMEOUT PERIOD
210ms
Unlike typical manual reset functions associated with
supervisors, each device in the MAX6443–MAX6452
family includes at least one manual reset input, which
must be held logic-low for an extended setup period
MR1 SETUP PERIOD
t
MR
(t ) before the RESET output asserts. When valid
MR
MR1
manual reset input conditions/setup periods are met,
the RESET output is one-shot pulse asserted low for a
fixed reset timeout period (140ms min). Existing front-
panel pushbutton switches (i.e., power on/off, channel
up/down, or mode select) can be used to drive the
manual reset inputs. The extended manual reset setup
period prevents nuisance system resets during normal
front-panel usage or resulting from inadvertent short-
term pushbutton closure.
RESET
Figure 1. MAX6443/MAX6444 Manual Reset Timing Diagram
The MAX6443/MAX6444, MAX6447/MAX6448, and
MAX6451/MAX6452 include a single manual reset input
with extended setup period (MR1). The MAX6445/
MAX6446 and MAX6449/MAX6450 include two manual
reset inputs (MR1 and MR2) with extended setup peri-
ods. For dual MR1, MR2 devices, both inputs must be
held low simultaneously for the extended setup period
210ms
MR1
3–MAX6452
t
MR
MR2
(t ) before the reset output is pulse asserted. The
MR
dual extended setup provides greater protection from
nuisance resets. (For example, the user or service tech-
nician is informed to simultaneously push both the
on/off button and the channel-select button for 6.72s
(L suffix) to reset the system.)
RESET
Figure 2. MAX6445/MAX6446/MAX6449/MAX6450 Manual
Reset Timing Diagram
The MAX6443–MAX6452 RESET output is pulse asserted
once for the reset timeout period after each valid manual
reset input condition. At least one manual reset input
must be released (go high) and then be driven low for the
extended setup period before RESET asserts again.
Internal timing circuitry debounces low-to-high manual
reset logic transitions, so no external circuitry is required.
Figure 1 illustrates the single manual reset function of the
MAX6443/MAX6444 single-voltage monitors, and Figure
2 represents the dual manual reset function of the
MAX6445/MAX6446 and MAX6449/MAX6450.
there are no false RESET assertions when MR2 is dri-
ven from high to low (Figure 4). The MR2 input can be
used for system test purposes or smart-card-detect
applications (see the Applications Information section).
Adjustable Input Voltage (RSTIN)
The MAX6449–MAX6452 monitor the voltage on RSTIN
using an adjustable reset threshold set with an external
resistor voltage-divider (Figure 5). Use the following for-
mula to calculate the externally monitored voltage
The MAX6447/MAX6448 and MAX6451/MAX6452
include both an extended setup period and immediate
setup period manual reset inputs. A low-to-high MR2
rising edge transition immediately pulse asserts the
RESET output for the reset timeout period (140ms min).
If the MAX6447/MAX6448 and MAX6451/MAX6452
MR2 input senses another rising edge before the end
of the 140ms timeout period (Figure 3), the internal
timer clears and begins counting again. If no rising
edges are detected within the 210ms timeout period,
RESET deasserts. The high-to-low transition on MR2
input is internally debounced for 210ms to ensure that
(V
):
MON-TH
V
= V
ꢀ (R1+ R2)/R2
MON-TH
TH-RSTIN
where V
is the desired reset threshold voltage
is the reset input threshold (0.63V).
MON-TH
and V
TH-RSTIN
Resistors R1 and R2 can have very high values to mini-
mize current consumption because of low leakage cur-
rents. Set R2 to some conveniently high value (250kΩ,
for example), and calculate R1 based on the desired
reset threshold voltage, using the following formula:
R1 = R2 ꢀ (V
/V
- 1) Ω
MON-TH TH-RSTIN
6
_______________________________________________________________________________________
µP Reset Circuits with Long Manual Reset
Setup Period
3–MAX6452
t < 210ms
COUNTER RESET
210ms
DEBOUNCING PERIOD
t = 210ms
POSITIVE EDGE
210ms
TIMEOUT PERIOD
MR2
MR2
NO RESET
OUTPUT
RESET
ASSERTED
RESET
Figure 3. MAX6447/MAX6448/MAX6451/MAX6452 MR2
Assertion DebouncingTiming Diagram
Figure 4. MAX6447/MAX6448/MAX6451/MAX6452 MR2
Deassertion Debouncing Timing Diagram
+3.3V
V
V
CC
MON_TH
MAX6449
MAX6451
R1
R2
V
CC
V
RESET
RESET
CC
RSTIN
GND
V
CC
µ
P
MAX6443L
LED
RESET
GND
MR1
NMI
V
= 0.63 x (R1 + R2) / R2
MON_TH
Figure 5. Calculating the Monitored Threshold Voltages
PUSHBUTTON SWITCH:
CLOSE FOR < 4.48s
FOR SYSTEM INTERRUPT;
CLOSE FOR > 6.72s FOR
SYSTEM RESET
Applications Information
Interrupt Before Reset
To minimize data loss and speed system recovery,
many applications interrupt the processor or reset only
portions of the system before a processor hard reset is
asserted. The extended setup time of the MAX6443–
MAX6452 manual reset inputs allows the same push-
button (connected to both the processor interrupt and
the extended MR1 input, as shown in Figure 6) to con-
trol both the interrupt and hard reset functions. If the
Figure 6. Interrupt Before Reset Application Circuit
closed long enough for a hard reset (the same LED
might be used as the front-panel power-on display).
Smart Card Insertion/Removal
The MAX6447/MAX6448/MAX6451/MAX6452 dual manu-
al resets are useful in applications in which both an
extended and immediate setup periods are needed.
Figure 7 illustrates the insertion and removal of a smart
card. MR1 monitors a front-panel pushbutton. When
pushbutton is closed for less than t , the processor is
MR
only interrupted. If the system still does not respond
properly, the pushbutton (or two buttons for the dual
manual reset) can be closed for the full extended setup
period to hard reset the processor. If desired, connect
an LED to the RESET output to blink off (or on) for the
reset timeout period to signify when the pushbutton is
closed for t , RESET one-shot pulses low for 140ms
MR
min. Because MR1 is internally pulled to V
through a
CC
50kΩ resistor, the front-panel switch can be connected to
_______________________________________________________________________________________
7
µP Reset Circuits with Long Manual Reset
Setup Period
+3.3V
3.3V
5V
+1.5V
CORE SUPPLY I/O SUPPLY
RESET
V
CC
V
CC
RESET
MAX6444
MAX6446
MAX6448
MAX6450
MAX6452
100kΩ
µP
MAX6451
µP
DIGITAL INPUT
RSTIN
MR1
MR2
RESET
RESET
GND
N
SMART CARD DETECT:
IMMEDIATE ONE-SHOT
WHEN MANUAL
3–MAX6452
GND
RESET CLOSES
FRONT-PANEL SWITCH
STANDARD µP INPUT
AND t MANUAL
MR
RESET DELAY
Figure 8. Interfacing to Other Voltage Levels
Figure 7. MAX6451/MAX6452 Application Circuit
a microprocessor for general-purpose I/O control. MR2
monitors a switch to detect when a smart card is inserted.
When the switch is closed high (card inserted), RESET
one-shot pulses low for 140ms. MR2 is internally
debounced for 210ms to prevent false resets when the
smart card is removed.
Ensuring a Valid RESET Down to
= 0V (Push-Pull RESET)
V
CC
When V
falls below 1V, RESET current-sinking capa-
CC
bilities decline drastically. The high-impedance CMOS-
logic inputs connected to RESET can drift to
undetermined voltages. This presents no problems in
most applications, because most µPs and other circuitry
Interfacing to Other Voltages
for Logic Compatibility
do not operate with V
below 1V.
CC
In applications in which RESET must be valid down to
0V, add a pulldown resistor between RESET and GND
for the push-pull outputs. The resistor sinks any stray
leakage currents, holding RESET low (Figure 9). The
value of the pulldown resistor is not critical; 100kΩ is
large enough not to load RESET and small enough to
pull RESET to ground. The external pulldown cannot be
used with the open-drain reset outputs.
The open-drain RESET output can be used to interface
to a µP with other logic levels. As shown in Figure 8, the
open-drain output can be connected to voltages from 0
to 6V.
Generally, the pullup resistor connected to the RESET
connects to the supply voltage that is being monitored
at the IC’s V
pin. However, some systems may use
CC
the open-drain output to level-shift from the monitored
supply to reset circuitry powered by some other supply
Transient Immunity
In addition to issuing a reset to the µP during power-up,
power-down, and brownout conditions, these supervi-
sors are relatively immune to short-duration falling tran-
sients (glitches). The graph Maximum Transient Duration
vs. Reset Threshold Overdrive in the Typical Operating
Characteristics section shows this relationship.
(Figure 8). Keep in mind that as the supervisor’s V
CC
decreases toward 1V, so does the IC’s ability to sink
current at RESET. RESET is pulled high as V decays
CC
toward 0. The voltage where this occurs depends on
the pullup resistor value and the voltage to which it is
connected.
8
_______________________________________________________________________________________
µP Reset Circuits with Long Manual Reset
Setup Period
3–MAX6452
The area below the curves of the graph is the region in
V
CC
which these devices typically do not generate a reset
pulse. This graph was generated using a falling pulse
applied to V , starting above the actual reset thresh-
CC
old (V ) and ending below it by the magnitude indicat-
TH
MAX6443
MAX6445
MAX6447
MAX6449
MAX6451
V
CC
ed (reset threshold overdrive). As the magnitude of the
transient increases (V
goes further below the reset
CC
threshold), the maximum allowable pulse width
decreases. Typically, a V transient that goes 100mV
below the reset threshold and lasts 20µs or less does
not cause a reset pulse to be asserted.
CC
RESET
100kΩ
GND
Figure 9. Ensuring RESET Valid to V
= 0V
CC
Table 1. Reset Voltage Threshold
Table 3. Standard Versions Table
TOP
TOP
MARK
V
CC
NOMINAL
PART
PART
PART NO. SUFFIX
( _ _ )
MARK
VOLTAGE
THRESHOLD (V)
MAX6443US16L
MAX6443US23L
MAX6443US26L
MAX6443US29L
MAX6443US46L
MAX6444US16L
MAX6444US23L
MAX6444US26L
MAX6444US29L
MAX6444US46L
MAX6445UK16L
MAX6445UK23L
MAX6445UK26L
MAX6445UK29L
MAX6445UK46L
MAX6446UK16L
MAX6446UK23L
MAX6446UK26L
MAX6446UK29L
MAX6446UK46L
MAX6447UK16L
MAX6447UK23L
MAX6447UK26L
MAX6447UK29L
MAX6447UK46L
KAFW
KAFX
KAFY
KAFK
KAFZ
KAGA
KAGB
KAGC
KAGD
KAFL
AEEF
AEEG
AEEH
AEEI
MAX6448UK16L
MAX6448UK23L
MAX6448UK26L
MAX6448UK29L
MAX6448UK46L
MAX6449UT16L
MAX6449UT23L
MAX6449UT26L
MAX6449UT29L
MAX6449UT46L
MAX6450UT16L
MAX6450UT23L
MAX6450UT26L
MAX6450UT29L
MAX6450UT46L
MAX6451UT16L
MAX6451UT23L
MAX6451UT26L
MAX6451UT29L
MAX6451UT46L
MAX6452UT16L
MAX6452UT23L
MAX6452UT26L
MAX6452UT29L
MAX6452UT46L
AEER
AEES
AEET
46
44
31
29
26
23
22
17
16
4.625
4.375
3.075
2.925
2.625
2.313
2.188
1.665
1.575
AEEU
AEEV
ABEL
ABNP
ABNQ
ABNR
ABNS
ABEM
ABNX
ABNY
ABNZ
ABOA
ABNT
ABEN
ABNU
ABNV
ABNW
ABOB
ABOC
ABOD
ABOE
ABOF
Table 2. Manual Reset Setup Period (t
)
MR
PART NO. SUFFIX
( _ )
MANUAL RESET SETUP
PERIOD (s)
AEAO
AEEN
AEEO
AEEP
AEAP
AEEQ
AEEJ
AEEK
AEAQ
AEEL
AEEM
K
L
S
T
10.08
6.72
3.36
1.68
_______________________________________________________________________________________
9
µP Reset Circuits with Long Manual Reset
Setup Period
Pin Configurations (continued)
TOP VIEW
RESET
1
2
3
5
4
MR2
RESET
GND
1
2
3
5
4
MR2
MAX6445
MAX6446
MAX6447
MAX6448
GND
MR1
V
MR1
V
CC
CC
SOT23-5
SOT23-5
RESET
GND
1
2
3
6
5
4
MR2
RESET
GND
1
2
3
6
MR2
3–MAX6452
MAX6451
MAX6452
MAX6449
MAX6450
RSTIN
5
4
RSTIN
MR1
V
CC
MR1
V
CC
SOT23-6
SOT23-6
Typical Operating Circuit
Ordering Information (continued)
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
5 SOT23
5 SOT23
5 SOT23
5 SOT23
6 SOT23
6 SOT23
6 SOT23
6 SOT23
+3.3V
MAX6445UK_ _ _-T
MAX6446UK_ _ _-T
MAX6447UK_ _ _-T
MAX6448UK_ _ _-T
MAX6449UT_ _ _-T
MAX6450UT_ _ _-T
MAX6451UT_ _ _-T
MAX6452UT_ _ _-T
V
CC
V
CC
MAX6444
µP
MR1
RESET
RESET
GND
GND
Note: The first “_ _ ” is a placeholder for the threshold voltage
level of the devices. A desired threshold level is set by the two-
number suffix found in Table 1. The third "_" is a placeholder
for the manual reset setup period of the devices. A desired
setup period is set by the letter suffix found in Table 2. All
devices are available in tape-and-reel only. There is a 2500-
piece minimum order increment for standard versions (Table
2). Sample stock is typically held on standard versions only.
Nonstandard versions require a minimum order increment of
10,000 pieces. Contact factory for availability.
RESET TIMEOUT PERIOD
210ms
MR1 SETUP PERIOD
t
MR
MR1
RESET
Devices are available in both leaded and lead-free packaging.
Specify lead-free by replacing “-T” with “+T” when ordering.
10 ______________________________________________________________________________________
µP Reset Circuits with Long Manual Reset
Setup Period
3–MAX6452
Selector Guide
MR1 EXT.
SETUP
MR2
(NO SETUP)
MR2 EXT.
SETUP
PART
RSTIN
PUSH-PULL RESET OPEN-DRAIN RESET
MAX6443
MAX6444
MAX6445
MAX6446
MAX6447
MAX6448
MAX6449
MAX6450
MAX6451
MAX6452
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
—
—
—
—
✔
—
—
✔
—
—
—
—
—
—
✔
✔
—
✔
—
✔
—
✔
—
✔
—
—
✔
—
✔
—
✔
—
✔
—
✔
✔
—
—
✔
✔
—
—
✔
✔
✔
—
—
✔
✔
✔
Functional Diagram
V
CC
MAX6443–
MAX6452
RESET
TIMEOUT PERIOD
(210ms typ)
RESET
RSTIN
MAX6449–
MAX6452
MAX6447
MAX6448
MAX6451
MAX6452
V
MR2 ONE-SHOT
DEBOUNCE
CIRCUIT
MANUAL RESET
SETUP PERIOD
CC
MR2
0.63V
t
MR
1.23V
V
CC
V
CC
GND
MR1
MR2
MAX6445
MAX6446
MAX6449
MAX6450
______________________________________________________________________________________ 11
µP Reset Circuits with Long Manual Reset
Setup Period
Package Information
Chip Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PROCESS: BiCMOS
LAND
PACKAGE
PACKAGE
OUTLINE NO.
PATTERN NO.
TYPE
CODE
90-0183
90-0174
90-0175
4 SOT143
5 SOT23
6 SOT23
U4-1
U5-1
U6-1
21-0052
21-0057
21-0058
3–MAX6452
12 ______________________________________________________________________________________
µP Reset Circuits with Long Manual Reset
Setup Period
3–MAX6452
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
10/02
Initial release
—
Revised the General Description, Features, Applications, Ordering Information,
Absolute Maximum Ratings, Electrical Characteristics, Typical Operating
Characteristics, Pin Description, the Manual Reset Input Options, Interrupt Before
Reset, and Smart Card Insertion/Removal sections, Functional Diagram, Typical
Operating Circuit, Selector Guide, Figures 1, 6, and 7, as well as Tables 2 and 3
to add extended setup timeout specifications.
3
6/10
1, 2, 4, 5–12
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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