MAX6727AKATGD4+T [MAXIM]
Power Supply Management Circuit, Fixed, 1 Channel, BICMOS, PDSO8, LEAD FREE, MO-178BA, SOT-23, 8 PIN;
| 型号： | MAX6727AKATGD4+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Power Supply Management Circuit, Fixed, 1 Channel, BICMOS, PDSO8, LEAD FREE, MO-178BA, SOT-23, 8 PIN 信息通信管理 光电二极管 |
| 文件： | 总18页 (文件大小：1688K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX6715A–MAX6729A/
MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 μP
Supervisory Circuits
General Description
Features
● V
(Primary Supply) Reset Threshold Voltages
The MAX6715A–MAX6729A/MAX6797A are ultra-low-volt-
age microprocessor (μP) supervisory circuits designed to
monitor two or three system power-supply voltages. These
devices assert a system reset if any monitored supply falls
below its factory-trimmed or adjustable threshold and main-
tain reset for a minimum timeout period after all supplies rise
above their thresholds. The integrated dual/triple superviso-
ry circuits significantly improve system reliability and reduce
size compared to separate ICs or discrete components.
CC1
from 1.58V to 4.63V
● V
(Secondary Supply) Reset Threshold Voltages
CC2
from 0.79V to 3.08V
● Externally Adjustable RSTIN Threshold for Auxiliary/
Triple-Voltage Monitoring (0.62V Internal Reference)
● Watchdog Timer Option
• 35s (min) Long Startup Period
• 1.12s (min) Normal Timeout Period
● Manual-Reset Input Option
These devices monitor primary supply voltages (V
)
CC1
● Power-Fail Input/Power-Fail Output Option
(Push-Pull and Open-Drain Active-Low)
from 1.8V to 5.0V and secondary supply voltages (V 2)
CC
from 0.9V to 3.3V with factory-trimmed reset threshold
voltage options (see the Reset Voltage Threshold Suffix
Guide). An externally adjustable RSTIN input option
allows customers to monitor a third supply voltage down
to 0.62V. These devices are guaranteed to be in the cor-
● Guaranteed Reset Valid Down to V
or
CC1
V
CC2
= 0.8V
● Reset Output Logic Options
● Immune to Short V Transients
CC
rect reset output logic state when either V
remains greater than 0.8V.
or V
CC1
CC2
● Low Supply Current 14μA (typ) at 3.6V
● Watchdog Disable Feature
A variety of push-pull or open-drain reset outputs along
with watchdog input, manual-reset input, and power-fail
input/output features are available (see the Selector
Guide). Select reset timeout periods from 1.1ms to
1120ms (min) (see the Reset Timeout Period Suffix
Guide). The MAX6715A–MAX6729A/MAX6797A are
available in small 5-, 6-, and 8-pin SOT23 packages and
operate over the -40°C to +125°C temperature range.
● Small 5-, 6-, and 8-Pin SOT23 Packages
Ordering Information
PIN-
PACKAGE
PART
TEMP RANGE
MAX6715AUT_ _D_+T
MAX6716AUT_ _D_+T
MAX6717AUK_ _D_+T
MAX6718AUK_ _D_+T
MAX6719AUT_ _D_+T
-40°C to +125°C 6 SOT23
-40°C to +125°C 6 SOT23
-40°C to +125°C 5 SOT23
-40°C to +125°C 5 SOT23
-40°C to +125°C 6 SOT23
Applications
● Multivoltage Systems
● Telecom/Networking
Equipment
● Industrial Equipment
● Printers/Fax Machines
● Set-Top Boxes
MAX6719AUT_ _D_/V+T* -40°C to +125°C 6 SOT23
● Computers/Servers
● Portable/Battery-
Operated Equipment
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
/V denotes an automotive qualified part.
*Future product—contact factory for availability.
Typical Operating Circuit
Note: The first “_ _” are placeholders for the threshold voltage
levels of the devices. Desired threshold levels are set by the part
number suffix found in the Reset Voltage Threshold Suffix Guide.
The “_” after the D is a placeholder for the reset timeout delay
time. Desired delay time is set using the timeout period suffix
found in the Reset Timeout Period Suffix Guide. For example,
OUT2
DC-DC
CONVERTER
UNREGULATED
DC
IN
OUT1
1.8V
I/O
0.9V
CORE
V
V
CC2
CC1
MAX6715A-
MAX6729A/
MAX6797A
SUPPLY SUPPLY
R1
R2
the MAX6716AUTLTD3-T is a dual-voltage supervisor V
=
TH1
4.625V, V
= 3.075V, and 210ms (typ) timeout period.
RESET
RST
TH2
µP
RSTIN/PFI
I/O
WDI
Ordering Information continued at end of data sheet.
MR
PFO
NMI
Pin Configurations and Selector Guide appear at end of
data sheet.
MAX67_ _
PUSHBUTTON
SWITCH
19-0536; Rev 4; 3/14
MAX6715A–MAX6729A/
MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 μP
Supervisory Circuits
Absolute Maximum Ratings
Terminal Voltage (with respect to GND)
Continuous Power Dissipation (T = +70°C)
A
V
, V
.........................................................-0.3V to +6V
5-Pin SOT23-5 (derate 7.1mW/°C above +70°C) .......571mW
6-Pin SOT23-6 (derate 8.7mW/°C above +70°C) .......696mW
8-Pin SOT23-8 (derate 8.9mW/°C above +70°C) .......714mW
Operating Temperature Range......................... -40°C to +125°C
Storage Temperature Range............................ -65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC1 CC2
Open-Drain RST, RST1, RST2, PFO, RST ............-0.3V to +6V
Push-Pull RST, RST1, PFO, RST .......... -0.3V to (V
Push-Pull RST2...................................... -0.3V to (V
RSTIN, PFI, MR, WDI .............................................-0.3V to +6V
Input Current/Output Current (all pins)...............................20mA
+ 0.3V)
+ 0.3V)
CC1
CC2
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(V
= 0.8V to 5.5V, V
= 0.8V to 5.5V, GND = 0V, T = -40°C to +125°C, unless otherwise noted. Typical values are at T =
CC1
CC2 A A
+25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
Supply Current
V
0.8
5.5
V
CC
V
< 5.5V all I/O connections open,
CC1
15
10
4
39
28
11
9
outputs not asserted
I
CC1
V
< 3.6V all I/O connections open,
CC1
outputs not asserted
µA
V
< 3.6V all I/O connections open,
CC2
outputs not asserted
I
CC2
V
< 2.75V all I/O connections open,
CC2
3
outputs not asserted
L (falling)
M (falling)
T (falling)
S (falling)
R (falling)
Z (falling)
Y (falling)
W (falling)
V (falling)
T (falling)
S (falling)
R (falling)
Z (falling)
Y (falling)
W (falling)
V (falling)
I (falling)
4.500
4.250
3.000
2.850
2.550
2.250
2.125
1.620
1.530
3.000
2.850
2.550
2.250
2.125
1.620
1.530
1.350
1.275
1.080
1.020
0.810
0.765
4.625
4.375
3.075
2.925
2.625
2.313
2.188
1.665
1.575
3.075
2.925
2.625
2.313
2.188
1.665
1.575
1.388
1.313
1.110
1.050
0.833
0.788
4.750
4.500
3.150
3.000
2.700
2.375
2.250
1.710
1.620
3.150
3.000
2.700
2.375
2.250
1.710
1.620
1.425
1.350
1.140
1.080
0.855
0.810
V
Reset Threshold
V
V
CC1
TH1
V
Reset Threshold
V
V
CC2
TH2
H (falling)
G (falling)
F (falling)
E (falling)
D (falling)
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MAX6715A–MAX6729A/
MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 μP
Supervisory Circuits
Electrical Characteristics (continued)
(V
= 0.8V to 5.5V, V
= 0.8V to 5.5V, GND = 0V, T = -40°C to +125°C, unless otherwise noted. Typical values are at T
=
CC1
CC2
A
A
+25°C.) (Note 1)
PARAMETER
SYMBOL
ΔV /°C
CONDITIONS
MIN
TYP
20
MAX
UNITS
ppm/°C
%
Reset Threshold Tempco
TH
Reset Threshold Hysteresis
V
Referenced to V typical
0.5
HYST
TH
V
V
= (V
= (V
+ 100mV) to (V
- 100mV) or
- 75mV)
CC1
CC2
TH1
TH2
TH1
V
to Reset Output Delay
t
20
µs
CC
RD
+ 75mV) to (V
TH2
D1
D2
1.1
8.8
1.65
13.2
26.25
52.5
210
2.2
17.6
35
D7 (MAX6797A only)
17.5
35
D8 (MAX6797A only)
70
Reset Timeout Period
t
ms
RP
D3
D5
D6
D4
140
280
560
1120
280
560
1120
2240
420
840
1680
ADJUSTABLE RESET COMPARATOR INPUT (MAX6719A/MAX6720A/MAX6723A–MAX6727A)
RSTIN Input Threshold
RSTIN Input Current
V
611
626.5
642
mV
nA
mV
µs
RSTIN
I
-100
+100
RSTIN
RSTIN Hysteresis
3
RSTIN to Reset Output Delay
t
V
to (V - 30mV)
RSTIN
22
RSTIND
RSTIN
POWER-FAIL INPUT (MAX6728A/MAX6729A)
PFI Input Threshold
PFI Input Current
PFI Hysteresis
V
611
626.5
642
mV
nA
mV
µs
PFI
I
V
t
-100
+100
PFI
3
PFH
PFI to PFO Delay
(V
+ 30mV) to (V - 30mV)
PFI
2
DPF
PFI
MANUAL-RESET INPUT (MAX6715A–MAX6722A/MAX6725A–MAX6729A)
V
0.3 x V
CC1
IL
MR Input Voltage
V
V
0.7 x V
IH
CC1
MR Minimum Pulse Width
MR Glitch Rejection
MR to Reset Delay
1
µs
ns
ns
kΩ
100
200
50
t
MR
MR Pullup Resistance
25
80
WATCHDOG INPUT (MAX6721A–MAX6729A)
First watchdog period after reset timeout
period
35
54
72
Watchdog Timeout Period
t
s
WD
Normal mode
(Note 2)
1.12
50
1.68
2.24
WDI Pulse Width
WDI Input Voltage
WDI Input Current
t
ns
V
WDI
V
0.3 x V
0.7 x V
-1
IL
CC1
V
IH
CC1
I
V
= 0V or V
CC1
+1
µA
WDI
WDI
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MAX6715A–MAX6729A/
MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 μP
Supervisory Circuits
Electrical Characteristics (continued)
(V
= 0.8V to 5.5V, V
= 0.8V to 5.5V, GND = 0V, T = -40°C to +125°C, unless otherwise noted. Typical values are at T =
CC1
CC2 A A
+25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RESET/POWER-FAIL OUTPUTS
V
or V
≥ 0.8V, I
= 1µA,
CC1
CC2
SINK
SINK
SINK
SINK
SINK
0.3
0.3
0.3
0.3
0.4
output asserted
V
or V ≥ 1.0V, I
= 50µA,
= 100µA,
= 1.2mA,
= 3.2mA,
CC1
CC2
output asserted
RST/RST1/RST2/PFO
Output Low
V
or V ≥ 1.2V, I
CC1
CC2
V
V
OL
output asserted
(Push-Pull or Open-Drain)
V
or V ≥ 2.7V, I
CC1
CC2
output asserted
V
or V ≥ 4.5V, I
CC1
CC2
output asserted
V
≥ 1.8V, I
= 200µA, output not
= 500µA, output not
= 800µA, output not
= 200µA, output not
= 500µA, output not
= 800µA, output not
CC1
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
0.8 x V
0.8 x V
0.8 x V
0.8 x V
0.8 x V
0.8 x V
CC1
CC1
CC1
CC2
CC2
asserted
RST/RST1/PFO
Output High
(Push-Pull Only)
V
≥ 2.7V, I
CC1
V
V
V
V
OH
asserted
V
≥ 4.5V, I
CC1
asserted
V
≥ 1.8V, I
CC1
asserted
RST2
Output High
V
≥ 2.7V, I
CC1
OH
asserted
(Push-Pull Only)
V
≥ 4.5V, I
CC1
CC2
CC1
CC1
asserted
V
≥ 1.0V, I
= 1µA, reset asserted 0.8 x V
CC1
SOURCE
SOURCE
V
≥ 1.8V, I
= 150µA,
0.8 x V
CC1
reset asserted
RST
Output High
(Push-Pull Only)
V
V
V
V
≥ 2.7V, I
= 500µA,
0.8 x V
OH
CC1
SOURCE
CC1
CC1
reset asserted
V
≥ 4.5V, I
= 800µA,
0.8 x V
CC1
SOURCE
≥ 1.8V, I
reset asserted
V
or V
= 500µA,
= 1.2mA,
= 3.2mA,
CC1
CC2
SINK
SINK
SINK
0.3
0.3
0.4
0.5
0.5
reset not asserted
RST
Output Low
(Push-Pull or Open Drain)
V
or V ≥ 2.7V, I
CC1
CC2
V
OL
reset not asserted
V
or V ≥ 4.5V, I
CC1
CC2
reset not asserted
RST/RST1/RST2/PFO Output
Open-Drain Leakage Current
Output not asserted
µA
µA
RST Output Open-Drain
Leakage Current
Output asserted
Note 1: Devices tested at T = +25°C. Overtemperature limits are guaranteed by design and not production tested.
A
Note 2: Parameter guaranteed by design.
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MAX6715A–MAX6729A/
MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 μP
Supervisory Circuits
Typical Operating Characteristics
(V
= 5V, V
= 3.3V, T = +25°C, unless otherwise noted.)
CC1
CC2 A
SUPPLY CURRENT vs. TEMPERATURE
(V 1 = +5V, V 2 = +3.3V)
SUPPLY CURRENT vs. TEMPERATURE
(V 1 = +3.3V, V 2 = +2.5V)
SUPPLY CURRENT vs. TEMPERATURE
(V 1 = +2.5V, V 2 = +1.8V)
CC
CC
CC
CC
CC
CC
20
18
16
14
12
10
8
20
18
16
14
12
10
8
20
18
16
14
12
10
8
TOTAL
I
1
CC
TOTAL
TOTAL
I
1
CC
I
1
CC
6
6
6
4
I
2
CC
4
4
I
2
CC
I 2
CC
2
2
2
0
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY CURRENT vs. TEMPERATURE
(V 1 = +1.8V, V 2 = +1.2V)
NORMALIZED/RESET WATCHDOG
TIMEOUT PERIOD vs. TEMPERATURE
MAXIMUM V TRANSIENT DURATION
CC
vs. RESET THRESHOLD OVERDRIVE
CC
CC
20
18
16
14
12
10
8
1.020
1.016
1.012
1.008
1.004
1.000
0.996
0.992
0.988
0.984
0.980
10,000
1000
RESET OCCURS ABOVE
THIS LINE
TOTAL
I
1
CC
100
10
6
4
I
2
CC
2
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
1
10
100
1000
TEMPERATURE (°C)
TEMPERATURE (°C)
RESET THRESHOLD OVERDRIVE (mV)
NORMALIZED V RESET THRESHOLD
CC
RESET INPUT AND POWER-FAIL INPUT
THRESHOLD vs. TEMPERATURE
V
TO RESET DELAY
vs. TEMPERATURE
CC
vs. TEMPERATURE
1.008
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1.000
0.999
0.998
638
637
636
635
634
633
632
631
630
629
628
20
19
18
17
16
15
14
13
12
11
10
75mV OVERDRIVE
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
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MAX6715A–MAX6729A/
MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 μP
Supervisory Circuits
Typical Operating Characteristics (continued)
(V
= 5V, V
= 3.3V, T = +25°C, unless otherwise noted.)
CC1
CC2 A
RSTIN INPUT TO RESET OUTPUT DELAY
vs. TEMPERATURE
POWER-FAIL INPUT TO POWER-FAIL
OUTPUT DELAY vs. TEMPERATURE
MR TO RESET OUTPUT DELAY
MAX6715A-29A toc12
24
22
20
18
16
14
12
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
30mV OVERDRIVE
30mV OVERDRIVE
V
MR
2V/div
0V
0V
V
RST
2V/div
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
50ns/div
TEMPERATURE (°C)
TEMPERATURE (°C)
Pin Description
PIN
MAX6728A/
MAX6727A MAX6729A/
MAX6797A
NAME
FUNCTION
MAX6715A/ MAX6717A/ MAX6719A/ MAX6721A/ MAX6723A/ MAX6725A/
MAX6716A MAX6718A MAX6720A MAX6722A MAX6724A MAX6726A
Active-Low Reset Output,
Open-Drain or Push-Pull.
RST/RST1 changes from
high to low when V
CC1
or V
drops below the
CC2
selected reset thresholds,
RSTIN is below threshold,
MR is pulled low, or the
watchdog triggers a reset.
RST/ RST/RST1 remains low for
RST1 the reset timeout period
1
1
1
1
1
1
1, 4
1
after V
/V
/RSTIN
CC1 CC2
exceed the device reset
thresholds, MR goes low
to high, or the watchdog
triggers a reset. Open-
drain outputs require an
external pullup resistor.
Push-pull outputs are
referenced to V
.
CC1
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MAX6715A–MAX6729A/
MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 μP
Supervisory Circuits
Pin Description (continued)
PIN
MAX6728A/
NAME
FUNCTION
MAX6715A/ MAX6717A/ MAX6719A/ MAX6721A/ MAX6723A/ MAX6725A/
MAX6716A MAX6718A MAX6720A MAX6722A MAX6724A MAX6726A
MAX6727A MAX6729A/
MAX6797A
Active-Low Reset Output,
Open-Drain or Push-Pull.
RST2 changes from high
to low when V
or V
CC1
CC2
drops below the selected
reset thresholds or MR is
pulled low. RST2 remains
low for the reset timeout
5
—
—
—
—
—
—
—
RST2
period after V
/V
CC1 CC2
exceed the device reset
thresholds or MR goes
low to high. Open-drain
outputs require an external
pullup resistor. Push-pull
outputs are referenced to
V
.
CC2
2
2
2
2
2
2
5
2
5
2
5
GND Ground
Active-Low Manual-Reset
Input. Internal 50kΩ pullup
to V . Pull low
CC1
to force a reset. Reset
remains active as long
as MR is low and for the
reset timeout period after
MR goes high. Leave
3
3
3
3
—
MR
unconnected or connect to
V
if unused.
CC1
Secondary Supply Voltage
Input. Powers
the device when it is
4
6
4
5
4
6
4
6
4
6
6
6
6
V
CC2
above V
and input
CC1
for secondary reset
threshold monitor.
Primary Supply Voltage
Input. Powers the device
when it is above V
input for prim
and
CC2
8
8
8
V
CC1
ary reset threshold
monitor.
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MAX6715A–MAX6729A/
MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 μP
Supervisory Circuits
Pin Description (continued)
PIN
MAX6728A/
NAME
FUNCTION
MAX6715A/ MAX6717A/ MAX6719A/ MAX6721A/ MAX6723A/ MAX6725A/
MAX6716A MAX6718A MAX6720A MAX6722A MAX6724A MAX6726A
MAX6727A MAX6729A/
MAX6797A
Watchdog Input. If WDI
remains high or low for
longer than the watchdog
timeout period, the
internal watchdog timer
runs out and the reset
output asserts for the
reset timeout period. The
internal watchdog timer
clears whenever a reset
is asserted or WDI sees
a rising or falling edge.
The watchdog has a long
—
—
—
5
3
3
3
3
WDI startup period (35s min)
after each reset event
and a short watchdog
timeout period (1.12s min)
after the first valid WDI
transition. Leave WDI
unconnected to disable
the watchdog timer. The
WDI unconnected-state
detector uses a small
200nA current source.
Therefore, do not connect
WDI to anything that will
source more than 50nA.
Undervoltage Reset
Comparator Input. High-
impedance input for
adjustable reset monitor.
The reset output is
asserted when RSTIN falls
RSTIN below the 0.626V internal
reference voltage. Set the
monitored voltage reset
threshold with an external
resistor-divider network.
—
—
5
—
5
7
7
—
Connect RSTIN to V
CC1
or V
if not used.
CC2
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MAX6715A–MAX6729A/
MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 μP
Supervisory Circuits
Pin Description (continued)
PIN
MAX6728A/
NAME
FUNCTION
MAX6715A/ MAX6717A/ MAX6719A/ MAX6721A/ MAX6723A/ MAX6725A/
MAX6716A MAX6718A MAX6720A MAX6722A MAX6724A MAX6726A
MAX6727A MAX6729A/
MAX6797A
Power-Fail Voltage
Monitor Input. High-
impedance input for
internal power-fail monitor
comparator. Connect PFI
to an external resistor-
divider network to set
the power-fail threshold
voltage (0.626V typical
internal reference voltage).
—
—
—
—
—
—
—
7
PFI
Connect to GND, V
, or
CC1
V
if not used.
CC2
Active-Low Power-Fail
Monitor Output, Open-
Drain or Push-Pull. PFO
is asserted low when PFI
is less than 0.626V. PFO
—
—
—
—
—
—
—
4
PFO deasserts without a reset
timeout period. Open-drain
outputs require an external
pullup resistor. Push-pull
outputs are referenced to
V
.
CC1
Active-High Reset Output,
Open-Drain or Push-Pull.
RST changes from low to
high when V
or V
CC1
CC2
drops below selected
reset thresholds, RSTIN
is below threshold, MR
is pulled low, or the
watchdog triggers a reset.
RST remains HIGH for
the reset timeout period
—
—
—
—
—
4
—
—
RST
after V
/V
/RSTIN
CC1 CC2
exceed the device reset
thresholds, MR goes low
to high, or the watchdog
triggers a reset. Open-
drain outputs require an
external pullup resistor.
Push-pull outputs are
referenced to V
.
CC1
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MAX6715A–MAX6729A/
MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 μP
Supervisory Circuits
Adjustable Input Voltage
Detailed Description
The MAX6719A/MAX6720A and MAX6723A–MAX6727A
provide an additional input to monitor a third system volt-
age. The threshold voltage at RSTIN is typically 626mV.
Connect a resistor-divider network to the circuit as shown
in Figure 1 to establish an externally controlled threshold
Supply Voltages
The MAX6715A–MAX6729A/MAX6797A μP supervisory
circuits maintain system integrity by alerting the μP to
fault conditions. These ICs are optimized for systems that
monitor two or three supply voltages. The outputreset
voltage, V
.
EXT_TH
state is guaranteed to remain valid while either V
or
CC1
V
CC2
is above 0.8V.
V
= 626mV((R1 + R2)/R2)
EXT_TH
Threshold Levels
Low-leakage current at RSTIN allows the use of largeval-
ued resistors resulting in reduced power consumption of
the system.
Input-voltage threshold level combinations are indicated
by a two-letter code in the Reset Voltage Threshold Suffix
Guide (Table 1). Contact factory for availability of other
voltage threshold combinations.
Watchdog Input
The watchdog monitors μP activity through the watchdog
input (WDI). To use the watchdog function, connect WDI
to a bus line or μP I/O line. When WDI remains high or
low for longer than the watchdog timeout period, the reset
output asserts.
Reset Outputs
The MAX6715A–MAX6729A/MAX6797A provide an
active-low reset output (RST) and the MAX6725A/
MAX6726A also provide an active-high (RST) output.
RST, RST, RST1, and RST2 are asserted when the
voltage at either V
threshold level, RSTIN drops below threshold, or MR is
pulled low. Once reset is asserted, it stays low for the
The MAX6721A–MAX6729A/MAX6797A include a dual-
mode watchdog timer to monitor μP activity. The flexible
timeout architecture provides a long period initial watch-
dog mode, allowing complicated systems to complete
lengthy boots, and a short period normal watchdog mode,
allowing the supervisor to provide quick alerts when pro-
or V
falls below the voltage
CC1
CC2
reset timeout period (see Table 2). If V
, V
, or
CC1
CC2
RSTIN goes below the reset threshold before the reset
timeout period is completed, the internal timer restarts.
The MAX6715A/MAX6717A/MAX6719A/MAX6721A/
MAX6723A/MAX6725A/MAX6727A/MAX6728A con-
tain open-drain reset outputs, while the MAX6716A/
MAX6718A/MAX6720A/MAX6722A/MAX6724A/
MAX6726A/MAX6729A/MAX6797A contain push-pull
reset outputs. The MAX6727A provides two separate
open-drain RST outputs driven by the same internal logic.
cessor activity fails. After each reset event (V
power-
CC
up/brownout, manual reset, or watchdog reset), there is
a long initial watchdog period of 35s minimum. The long
watchdog period mode provides an extended time for the
system to power-up and fully initialize all μP and system
components before assuming responsibility for routine
watchdog updates.
Manual-Reset Input
Many μP-based products require manual-reset capability,
allowing the operator, a test technician, or external logic
circuitry to initiate a reset. A logic-low on MR asserts the
reset output. Reset remains asserted while MR is low for
MAX6719A/
V
EXT_TH
MAX6720A/
MAX6723A–
MAX6727A
R1
R2
the reset timeout period (t ) after MR returns high. This
RP
input has an internal 50kΩ pullup resistor to V
and
CC1
RSTIN
can be left unconnected if not used. MR can be driven
with CMOS logic levels, or with open-drain/collector out-
puts. Connect a normally open momentary switch from
MR to GND to create a manualreset function; external
debounce circuitry is not required. If MR is driven from
long cables or if the device is used in a noisy environment,
connect a 0.1μF capacitor from MR to GND to provide
additional noise immunity.
GND
Figure 1. Monitoring a Third Voltage
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MAX6715A–MAX6729A/
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Dual/Triple, Ultra-Low-Voltage, SOT23 μP
Supervisory Circuits
The normal watchdog timeout period (1.12s min) begins
after the first transition on WDI before the conclusion of
the long initial watchdog period (Figure 2). During the
normal operating mode, the supervisor will issue a reset
pulse for the reset timeout period if the μP does not
update the WDI with a valid transition (high-to-low or low-
to-high) within the standard timeout period (1.12s min).
Ensuring a Valid Reset Output
Down to V
= 0V
CC
The MAX6715A–MAX6729A/MAX6797A are guaranteed
to operate properly down to V = 0.8V. In applica-
CC
tions that require valid reset levels down to V
use a pulldown resistor at RST to ground. The resistor
value used is not critical, but it must be large enough
= 0V,
CC
not to load the reset output when V
is above the reset
Leave WDI unconnected to disable the watchdog timer.
The WDI unconnected-state detector uses a small (200nA
typ) current source. Therefore, do not connect WDI to
anything that will source more than 50nA.
CC
threshold. For most applications, 100kΩ is adequate. This
configuration does not work for the open-drain outputs
of the MAX6715A/MAX6717A/MAX6719A/MAX6721A/
MAX6723A/MAX6725A/MAX6727A/MAX6728A. For
pushpull, active-high RST output connect the external
Power-Fail Comparator
PFI is the noninverting input to a comparator. If PFI is less
resistor as a pullup from RST to V
.
CC1
than V
(626.5mV), PFO goes low. Common uses for
PFI
the power-fail comparator include monitoring preregulated
input of the power supply (such as a battery) or providing
an early power-fail warning so software can conduct an
orderly system shutdown. It can also be used to monitor
A)
V
MAX6728A/
MAX6729A/
MAX6797A
IN
R1
R2
R1 + R2
R2
supplies other than V
or V
by setting the power-
CC1
CC2
V = V
TRIP PFI
(
)
fail threshold with a resistor-divider, as shown in Figure 3.
PFI is the input to the power-fail comparator. The typical
comparator delay is 2μs from PFI to PFO. Connect PFI to
PFI
PFO
ground of V
if unused.
CC1
GND
B)
V
TH
V
MAX6728A/
MAX6729A/
MAX6797A
CC
V
CC
t
WDI-NORMAL
1.12s MAX
R1
R2
V
CC
R1
1
1
+
-
(V
)
PFI
V
= R2
t
TRIP
WDI-STARTUP
( )
[
]
R1 R2
PFI
PFO
35s MAX
WDI
V
= 626.5mV
PFI
1.12s MAX
V
IN
GND
t
RP
RST
Figure 3. Using Power-Fail Input to Monitor an Additional
Power-Supply a) V is Positive b) V is Negative
Figure 2. Normal Watchdog Startup Sequence
IN
IN
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MAX6715A–MAX6729A/
MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 μP
Supervisory Circuits
The current through R2 should be at least 2.5μA to ensure
that the 100nA (max) PFI input current does not signifi-
Applications Information
Interfacing to μPs with Bidirectional
Reset Pins
cantly shift the trip points. Therefore, R2 < V /10μA <
PFI
62kΩ for most applications. R3 will provide additional
Most μPs with bidirectional reset pins can interface directly
to open-drain RST output options. Systems simultane-
ously requiring a push-pull RST output and a bidirectional
reset interface can be in logic contention. To prevent con-
tention, connect a 4.7kΩ resistor between RST and the
μP’s reset I/O port as shown in Figure 4.
hysteresis for PFO push-pull (V
= V
) or open-drain
OH
CC1
(V
= V
) applications.
OH
PULLUP
Monitoring an Additional Power Supply
These μP supervisors can monitor either positive or nega-
tive supplies using a resistor voltage-divider to PFI. PFO
can be used to generate an interrupt to the μP or cause
reset to assert (Figure 3).
Adding Hysteresis to the Power-Fail
Comparator
Monitoring a Negative Voltage
The power-fail comparator has a typical input hysteresis
of 3mV. This is sufficient for most applications where a
power-supply line is being monitored through an external
voltage-divider (see the Power-Fail Comparator section).
If additional noise margin is desired, connect a resistor
between PFO and PFI as shown in Figure 5. Select the
The power-fail comparator can be used to monitor a neg-
ative supply voltage using the circuit shown in Figure 3.
When the negative supply is valid, PFO is low. When the
negative supply voltage drops, PFO goes high. The cir-
cuit’s accuracy is affected by the PFI threshold tolerance,
V
, R1, and R2.
values of R1, R2, and R3 so PFI sees V
(626mV)
CC
PFI
when V
falls to its power-fail trip point (V
) and
). The
EXT
FAIL
Negative-Going V
Transients
CC
The MAX6715A–MAX6729A/MAX6797A supervisors are
relatively immune to short-duration negative-going V
when V rises to its power-good trip point (V
IN
GOOD
hysteresis window extends between the specified V
FAIL
CC
and V
thresholds. R3 adds the additional hysteresis
GOOD
transients (glitches). It is usually undesirable to reset
by sinking current from the R1/R2 divider network when
PFO is logic-low and sourcing current into the network
when PFO is logic-high. R3 is typically an order of magni-
tude greater than R1 or R2.
the μP when V experiences only small glitches.
CC
The Typical Operating Characteristics show Maximum
Transient Duration vs. Reset Threshold Overdrive, for
which reset pulses are not generated. The graph was
produced using negative-going V
pulses, starting
CC
above V
and ending below the reset threshold by the
TH
RESET TO OTHER SYSTEM COMPONENTS
R3
V
V
CC1 CC2
A
V
V
GOOD
FAIL
V
IN
MAX6715A–
MAX6729A/
MAX6797A
MAX6729A
PFO
V
EXT
µP
4.7kΩ
R1
R2
V
V
RESET
RST
CC2
CC1
PFI
PFO
V
V
V
= DESIRED V
GOOD VOLTAGE THRESHOLD
FAIL VOLTAGE THRESHOLD
GOOD
EXT
= DESIRED V
FAIL
EXT
= V
(FOR PUSH-PULL PFO)
OH
CC1
R2 = 50kΩ (FOR > 10µA R2 CURRENT)
R1 = R2 ((V
R3 = (R1 x V )/(V
- V ) - (V )(V
- V )/V )/V
GOOD
PFI
PFI GOOD FAIL OH PFI
GND
GND
GND
- V
)
OH
GOOD
FAIL
Figure 4. Interfacing to μPs with Bidirectional Reset I/O
Figure 5. Adding Hysteresis to Power-Fail for Push-Pull PFO
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MAX6715A–MAX6729A/
MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 μP
Supervisory Circuits
magnitude indicated (reset threshold overdrive). The
graph shows the maximum pulse width that a negative-
going V
transient may typically have without causing a
CC
START
reset pulse to be issued. As the amplitude of the transient
increases (i.e., goes farther below the reset threshold),
the maximum allowable pulse width decreases. A 0.1μF
bypass capacitor mounted close to the V
additional transient immunity.
SET WDI
HIGH
pin provides
CC
PROGRAM
CODE
Watchdog Software Considerations
Setting and resetting the watchdog input at different points
in the program, rather than “pulsing” the watchdog input
high-low-high or low-high-low, helps the watchdog timer to
closely monitor software execution. This technique avoids
a “stuck” loop where the watchdog timer continues to be
reset within the loop, keeping the watchdog from timing
out. Figure 6 shows an example flow diagram where the
I/O driving the watchdog input is set high at the begin-
ning of the program, set low at the beginning of every
subroutine or loop, then set high again when the program
returns to the beginning. If the program should “hang”
in any subroutine, the I/O is continually set low and the
watchdog timer is allowed to time out, causing a reset or
interrupt to be issued.
SUBROUTINE OR
PROGRAM LOOP
SET WDI LOW
HANG IN
SUBROUTINE
SUBROUTINE
COMPLETED
RETURN
Figure 6. Watchdog Flow Diagram
Maxim Integrated
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MAX6715A–MAX6729A/
MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 μP
Supervisory Circuits
Functional Diagram
V
CC1
V
CC1
MR
MR
PULLUP
V
CC1
V
CC1
V
CC2
V
REF
RST
RESET
TIMEOUT
PERIOD
RESET
OUTPUT
DRIVER
V
CC2
RST
RSTIN/PFI
PFO
V
CC1
V
REF
V
CC1
WATCHDOG
TIMER
WDI
V
REF/2
Maxim Integrated
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MAX6715A–MAX6729A/
MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 μP
Supervisory Circuits
Selector Guide
NUMBER OF
VOLTAGE
MONITORS
OPEN-
DRAIN
RESET
OPEN-
DRAIN
RESET
PUSH-
PULL
RESET
PUSH-
PULL
RESET
WATCH-
DOG
INPUT
POWER-FAIL
INPUT/
OUTPUT
PART
NUMBER
MANUAL
RESET
MAX6715A
MAX6716A
MAX6717A
MAX6718A
MAX6719A
MAX6720A
MAX6721A
MAX6722A
MAX6723A
MAX6724A
MAX6725A
MAX6726A
MAX6727A
MAX6728A
MAX6729A
MAX6797A
2
2
2
2
3
3
2
2
3
3
3
3
3
2
2
2
2
—
1
—
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
—
—
—
—
—
1
√
√
—
—
—
—
—
—
√
—
2
—
—
1
√
—
—
1
√
—
—
1
√
—
—
1
√
—
—
1
√
—
—
1
√
√
—
—
1
—
—
√
√
—
—
1
√
—
—
1
√
—
—
—
2
—
—
—
—
—
√
√
—
—
1
—
—
—
—
√
√
—
1
√
√
√ (open drain)
√ (push-pull)
√ (open drain)
—
—
√
√
1
√
√
Ordering Information (continued)
PIN-
PACKAGE
PART
TEMP RANGE
MAX6720AUT_ _D_+T
MAX6721AUT_ _D_+T
MAX6722AUT_ _D_+T
MAX6723AUT_ _D_+T
MAX6724AUT_ _D_+T
MAX6725AKA_ _D_+T
MAX6726AKA_ _D_+T
MAX6727AKA_ _D_+T
MAX6728AKA_ _D_+T
MAX6729AKA_ _D_+T
MAX6797AKA_ _D_+T
-40°C to +125°C 6 SOT23
-40°C to +125°C 6 SOT23
-40°C to +125°C 6 SOT23
-40°C to +125°C 6 SOT23
-40°C to +125°C 6 SOT23
-40°C to +125°C 8 SOT23
-40°C to +125°C 8 SOT23
-40°C to +125°C 8 SOT23
-40°C to +125°C 8 SOT23
-40°C to +125°C 8 SOT23
-40°C to +125°C 8 SOT23
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Note: The first “_ _” are placeholders for the threshold voltage
levels of the devices. Desired threshold levels are set by the part
number suffix found in the Reset Voltage Threshold Suffix Guide.
The “_” after the D is a placeholder for the reset timeout delay
time. Desired delay time is set using the timeout period suffix
found in the Reset Timeout Period Suffix Guide. For example,
the MAX6716AUTLTD3-T is a dual-voltage supervisor V
=
TH1
4.625V, V
= 3.075V, and 210ms (typ) timeout period.
TH2
Maxim Integrated
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MAX6715A–MAX6729A/
MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 μP
Supervisory Circuits
Table 1. Reset Voltage Threshold Suffix
Guide**
Table 2. Reset Timeout Period Suffix
Guide
ACTIVE TIMEOUT PERIOD
TIMEOUT
PART NUMBER
SUFFIX
V
NOMINAL
V
NOMINAL
CC1
VOLTAGE
CC2
VOLTAGE
PERIOD SUFFIX
MIN (ms)
1.1
MAX (ms)
2.2
(_ _)
THRESHOLD (V)
4.625
4.375
4.375
3.075
2.925
2.625
3.075
2.925
2.625
3.075
2.925
2.625
3.075
2.925
2.625
3.075
2.925
2.625
2.313
2.188
2.313
2.188
2.313
2.188
2.313
2.188
1.665
1.575
1.665
1.575
1.665
1.575
THRESHOLD (V)
3.075
2.925
2.625
2.313
2.188
2.188
1.665
1.575
1.575
1.388
1.313
1.313
1.110
1.050
1.050
0.833
0.788
0.788
1.665
1.575
1.388
1.313
1.110
1.050
0.833
0.788
1.388
1.313
1.110
1.050
0.833
0.788
D1
D2
LT
MS
MR
TZ
8.8
17.6
†
†
D7
D8
17.5
35.0
140
35.0
70.0
D3
D5
D6
D4
280
SY
RY
TW
SV
RV
TI
280
560
560
1120
2240
1120
†D7 and D8 timeout periods are only available for the MAX6797A.
SH
RH
TG
SF
RF
TE
SD
RD
ZW
YV
ZI
YH
ZG
YF
ZE
YD
WI
VH
WG
VF
WE
VD
Note: Standard versions are shown in bold and are available in
a D3 timeout option only. Standard versions require 2500-piece-
order increments and are typically held in sample stock. There is a
10,000 order increment on nonstandard versions. Other thresh-
old voltages may be available; contact factory for availability.
Maxim Integrated
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MAX6715A–MAX6729A/
MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 μP
Supervisory Circuits
Pin Configurations
TOP VIEW
+
+
+
RST1
GND
MR
1
2
3
6
5
4
V
RST
GND
MR
1
2
3
5
4
V
V
V
RST
GND
MR
1
2
3
6
5
4
V
CC1
CC1
CC1
CC2
CC1
MAX6715A/
MAX6716A
MAX6717A/
MAX6718A
MAX6719A/
MAX6720A
RST2
RSTIN
V
V
CC2
CC2
SOT23
+
SOT23
+
SOT23
+
RST
GND
WDI
RST
1
2
3
4
8
7
6
5
V
RST
GND
MR
1
2
3
6
5
4
V
CC1
RST
GND
WDI
1
2
3
6
5
4
CC1
RSTIN
MAX6721A/
MAX6722A
MAX6723A/
MAX6724A
MAX6725A/
MAX6726A
WDI
RSTIN
V
CC2
MR
V
V
CC2
CC2
SOT23
SOT23
SOT23
+
+
RST
1
2
3
4
8
7
6
5
V
RST
1
2
3
4
8
7
V
CC1
CC1
GND
WDI
RST
RSTIN
GND
WDI
PFO
PFI
MAX6727A
MAX6728A/
MAX6729A/
MAX6797A
V
CC2
6
5
V
CC2
MR
MR
SOT23
SOT23
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
5 SOT23
6 SOT23
8 SOT23
U5+1
U6+1
21-0057
21-0058
21-0078
90-0174
90-0175
90-0176
K8SN+1
Maxim Integrated
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MAX6715A–MAX6729A/
MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 μP
Supervisory Circuits
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
DESCRIPTION
CHANGED
0
4/06
7/06
Initial release
—
1
Updated Ordering Information
1, 15
Added the MAX6797A to Ordering Information, Electrical Characteristics, Pin
Description, Detailed Description, Figures 4 and 5, Selector Guide, Table 2,
Pin Configurations
2
6/08
1, 2, 6–11, 12, 15–17
3
9/08
3/14
Updated Selector Guide
15
1
4
Added automotive part to the Ordering Information table
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2014 Maxim Integrated Products, Inc.
│ 18
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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