MAX6727AKAZID6+T [MAXIM]
Power Supply Management Circuit, Adjustable, 3 Channel, BICMOS, PDSO8, SOT-23, 8 PIN;
| 型号： | MAX6727AKAZID6+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Power Supply Management Circuit, Adjustable, 3 Channel, BICMOS, PDSO8, SOT-23, 8 PIN 输入元件 信息通信管理 光电二极管 |
| 文件： | 总18页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0536; Rev 3; 9/08
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
15–2/MX697A
General Description
Features
The MAX6715A–MAX6729A/MAX6797A are ultra-low-volt-
age microprocessor (µP) supervisory circuits designed to
monitor two or three system power-supply voltages. These
devices assert a system reset if any monitored supply falls
below its factory-trimmed or adjustable threshold and main-
tain reset for a minimum timeout period after all supplies rise
above their thresholds. The integrated dual/triple supervisory
circuits significantly improve system reliability and reduce
size compared to separate ICs or discrete components.
o V 1 (Primary Supply) Reset Threshold Voltages
CC
from 1.58V to 4.63V
o V 2 (Secondary Supply) Reset Threshold
CC
Voltages from 0.79V to 3.08V
o Externally Adjustable RSTIN Threshold for
Auxiliary/Triple-Voltage Monitoring
(0.62V Internal Reference)
o Watchdog Timer Option
35s (min) Long Startup Period
1.12s (min) Normal Timeout Period
These devices monitor primary supply voltages (V 1)
CC
from 1.8V to 5.0V and secondary supply voltages (V 2)
CC
o Manual-Reset Input Option
from 0.9V to 3.3V with factory-trimmed reset threshold
voltage options (see the Reset Voltage Threshold Suffix
Guide). An externally adjustable RSTIN input option
allows customers to monitor a third supply voltage down
to 0.62V. These devices are guaranteed to be in the cor-
o Power-Fail Input/Power-Fail Output Option
(Push-Pull and Open-Drain Active-Low)
o Guaranteed Reset Valid Down to V 1 or
CC
V 2 = 0.8V
CC
rect reset output logic state when either V 1 or V
CC
2
CC
o Reset Output Logic Options
o Immune to Short V
remains greater than 0.8V.
Transients
CC
A variety of push-pull or open-drain reset outputs along
with watchdog input, manual-reset input, and power-fail
input/output features are available (see the Selector
Guide). Select reset timeout periods from 1.1ms to
1120ms (min) (see the Reset Timeout Period Suffix
Guide). The MAX6715A–MAX6729A/MAX6797A are avail-
able in small 5-, 6-, and 8-pin SOT23 packages and oper-
ate over the -40°C to +125°C temperature range.
o Low Supply Current 14µA (typ) at 3.6V
o Watchdog Disable Feature
o Small 5-, 6-, and 8-Pin SOT23 Packages
Ordering Information
PIN-
PACKAGE
PART
TEMP RANGE
Applications
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
MAX6715AUT_ _D_+T
MAX6716AUT_ _D_+T
MAX6717AUK_ _D_+T
MAX6718AUK_ _D_+T
MAX6719AUT_ _D_+T
MAX6720AUT_ _D_+T
6 SOT23
Multivoltage Systems
Telecom/Networking
Equipment
Computers/Servers
Portable/Battery-
Operated Equipment
Industrial Equipment
Printers/Fax Machines
Set-Top Boxes
6 SOT23
5 SOT23
5 SOT23
6 SOT23
6 SOT23
+Denotes a lead-free/RoHS-compliant package.
T = Tape and reel.
Typical Operating Circuit
Note: The first “_ _” are placeholders for the threshold voltage
levels of the devices. Desired threshold levels are set by the part
number suffix found in the Reset Voltage Threshold Suffix Guide.
The “_” after the D is a placeholder for the reset timeout delay
time. Desired delay time is set using the timeout period suffix
found in the Reset Timeout Period Suffix Guide. For example, the
OUT2
DC-DC
CONVERTER
OUT1
UNREGULATED
DC
IN
1.8V
I/O
0.9V
CORE
V
1
V
2
CC
CC
SUPPLY SUPPLY
MAX6716AUTLTD3-T is a dual-voltage supervisor V 1 =
MAX6715A-
MAX6729A/
MAX6797A
TH
R1
4.625V, V 2 = 3.075V, and 210ms (typ) timeout period.
TH
RESET
RST
WDI
PFO
µP
RSTIN/PFI
MR
I/O
NMI
Ordering Information continued at end of data sheet.
R2
MAX67_ _
PUSHBUTTON
SWITCH
Pin Configurations and Selector Guide appear at end of
data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND)
Continuous Power Dissipation (T = +70°C)
A
V
1, V 2 ..........................................................-0.3V to +6V
5-Pin SOT23-5 (derate 7.1mW/°C above +70°C) ........571mW
6-Pin SOT23-6 (derate 8.7mW/°C above +70°C) ........696mW
8-Pin SOT23-8 (derate 8.9mW/°C above +70°C) ........714mW
Operating Temperature Range .........................-40°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
CC
Open-Drain RST, RST1, RST2, PFO, RST ................-0.3V to +6V
Push-Pull RST, RST1, PFO, RST...............-0.3V to (V 1 + 0.3V)
Push-Pull RST2.........................................-0.3V to (V 2 + 0.3V)
RSTIN, PFI, MR, WDI................................................-0.3V to +6V
Input Current/Output Current (all pins) ...............................20mA
CC
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V 1 = 0.8V to 5.5V, V 2 = 0.8V to 5.5V, GND = 0V, T = -40°C to +125°C, unless otherwise noted. Typical values are at T =
A
CC
CC
A
+25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
Supply Current
V
0.8
5.5
V
CC
V
1 < 5.5V all I/O connections open,
CC
15
10
4
39
28
11
9
outputs not asserted
I
CC1
V
1 < 3.6V all I/O connections open,
CC
outputs not asserted
V
outputs not asserted
µA
2 < 3.6V all I/O connections open,
CC
I
CC2
V
2 < 2.75V all I/O connections open,
CC
3
outputs not asserted
L (falling)
M (falling)
T (falling)
S (falling)
R (falling)
Z (falling)
Y (falling)
W (falling)
V (falling)
T (falling)
S (falling)
R (falling)
Z (falling)
Y (falling)
W (falling)
V (falling)
I (falling)
4.500
4.250
3.000
2.850
2.550
2.250
2.125
1.620
1.530
3.000
2.850
2.550
2.250
2.125
1.620
1.530
1.350
1.275
1.080
1.020
0.810
0.765
4.625
4.375
3.075
2.925
2.625
2.313
2.188
1.665
1.575
3.075
2.925
2.625
2.313
2.188
1.665
1.575
1.388
1.313
1.110
1.050
0.833
0.788
4.750
4.500
3.150
3.000
2.700
2.375
2.250
1.710
1.620
3.150
3.000
2.700
2.375
2.250
1.710
1.620
1.425
1.350
1.140
1.080
0.855
0.810
V
1 Reset Threshold
V
V
CC
TH1
15–2/MX697A
V
2 Reset Threshold
CC
V
V
TH2
H (falling)
G (falling)
F (falling)
E (falling)
D (falling)
2
_______________________________________________________________________________________
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
15–2/MX697A
ELECTRICAL CHARACTERISTICS (continued)
(V 1 = 0.8V to 5.5V, V 2 = 0.8V to 5.5V, GND = 0V, T = -40°C to +125°C, unless otherwise noted. Typical values are at T =
A
CC
CC
A
+25°C.) (Note 1)
PARAMETER
SYMBOL
∆V /°C
CONDITIONS
MIN
TYP
20
MAX
UNITS
ppm/°C
%
Reset Threshold Tempco
Reset Threshold Hysteresis
TH
V
Referenced to V typical
0.5
HYST
TH
V
CC
V
CC
1 = (V 1+ 100mV) to (V 1 - 100mV) or
TH TH
V
to Reset Output Delay
t
20
µs
CC
RD
2 = (V 2 + 75mV) to (V 2 - 75mV)
TH
TH
D1
D2
1.1
8.8
1.65
13.2
26.25
52.5
210
2.2
17.6
35
D7 (MAX6797A only)
17.5
35
D8 (MAX6797A only)
70
Reset Timeout Period
t
ms
RP
D3
D5
D6
D4
140
280
560
1120
280
560
1120
2240
420
840
1680
ADJUSTABLE RESET COMPARATOR INPUT (MAX6719A/MAX6720A/MAX6723A–MAX6727A)
RSTIN Input Threshold
RSTIN Input Current
V
611
626.5
642
mV
nA
RSTIN
RSTIN
I
-100
+100
RSTIN Hysteresis
3
mV
µs
RSTIN to Reset Output Delay
t
V
to (V - 30mV)
RSTIN
22
RSTIND
RSTIN
POWER-FAIL INPUT (MAX6728A/MAX6729A)
PFI Input Threshold
PFI Input Current
PFI Hysteresis
V
611
626.5
642
mV
nA
mV
µs
PFI
PFI
I
-100
+100
V
3
2
PFH
DPF
PFI to PFO Delay
t
(V + 30mV) to (V - 30mV)
PFI PFI
MANUAL-RESET INPUT (MAX6715A–MAX6722A/MAX6725A–MAX6729A)
V
0.3 ✕ V
1
CC
IL
MR Input Voltage
V
V
0.7 ✕ V
1
CC
IH
MR Minimum Pulse Width
MR Glitch Rejection
MR to Reset Delay
1
µs
ns
ns
kΩ
100
200
50
t
MR
MR Pullup Resistance
25
35
80
WATCHDOG INPUT (MAX6721A–MAX6729A)
First watchdog period after reset timeout
period
54
72
Watchdog Timeout Period
t
s
WD
Normal mode
(Note 2)
1.12
50
1.68
2.24
WDI Pulse Width
WDI Input Voltage
WDI Input Current
t
ns
V
WDI
V
0.3 ✕ V
1
CC
IL
V
0.7 ✕ V
1
CC
IH
I
WDI = 0V or V
1
CC
-1
+1
µA
WDI
_______________________________________________________________________________________
3
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)
(V 1 = 0.8V to 5.5V, V 2 = 0.8V to 5.5V, GND = 0V, T = -40°C to +125°C, unless otherwise noted. Typical values are at T =
A
CC
CC
A
+25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RESET/POWER-FAIL OUTPUTS
V
1 or V 2 ≥ 0.8V, I
= 1µA,
CC
CC
SINK
SINK
SINK
SINK
SINK
0.3
0.3
0.3
0.3
0.4
output asserted
V
1 or V 2 ≥ 1.0V, I
= 50µA,
= 100µA,
= 1.2mA,
= 3.2mA,
CC
CC
output asserted
RST/RST1/RST2/PFO
Output LOW
V
1 or V 2 ≥ 1.2V, I
CC
CC
V
V
OL
output asserted
(Push-Pull or Open-Drain)
V
1 or V 2 ≥ 2.7V, I
CC
CC
output asserted
V
1 or V 2 ≥ 4.5V, I
CC
CC
output asserted
V
1 ≥ 1.8V, I
= 200µA, output not
= 500µA, output not
= 800µA, output not
= 200µA, output not
= 500µA, output not
= 800µA, output not
CC
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
0.8 ✕ V
0.8 ✕ V
0.8 ✕ V
0.8 ✕ V
0.8 ✕ V
0.8 ✕ V
1
1
1
2
2
CC
CC
CC
CC
CC
asserted
RST/RST1/PFO
Output HIGH
(Push-Pull Only)
V
1 ≥ 2.7V, I
CC
V
V
V
OH
asserted
V
1 ≥ 4.5V, I
CC
asserted
V
1 ≥ 1.8V, I
CC
asserted
RST2
Output HIGH
(Push-Pull Only)
V
1 ≥ 2.7V, I
CC
V
OH
asserted
V
1 ≥ 4.5V, I
CC
2
1
1
CC
CC
CC
asserted
V
V
1 ≥ 1.0V, I
1 ≥ 1.8V, I
= 1µA, reset asserted 0.8 ✕ V
CC
SOURCE
15–2/MX697A
= 150µA,
CC
SOURCE
0.8 ✕ V
reset asserted
RST
Output HIGH
(Push-Pull Only)
V
V
V
V
1 ≥ 2.7V, I
= 500µA,
OH
CC
SOURCE
0.8 ✕ V
1
CC
CC
reset asserted
V
1 ≥ 4.5V, I
= 800µA,
CC
SOURCE
0.8 ✕ V
1
reset asserted
V
1 or V 2 ≥ 1.8V, I
= 500µA,
= 1.2mA,
= 3.2mA,
CC
CC
SINK
SINK
SINK
0.3
0.3
0.4
0.5
0.5
reset not asserted
RST
Output LOW
(Push-Pull or Open Drain)
V
1 or V 2 ≥ 2.7V, I
CC
CC
V
OL
reset not asserted
V
1 or V 2 ≥ 4.5V, I
CC
CC
reset not asserted
RST/RST1/RST2/PFO Output
Open-Drain Leakage Current
Output not asserted
µA
µA
RST Output Open-Drain
Leakage Current
Output asserted
Note 1: Devices tested at T = +25°C. Overtemperature limits are guaranteed by design and not production tested.
A
Note 2: Parameter guaranteed by design.
4
_______________________________________________________________________________________
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
15–2/MX697A
Typical Operating Characteristics
(V 1 = 5V, V 2 = 3.3V, T = +25°C, unless otherwise noted.)
CC
CC
A
SUPPLY CURRENT vs. TEMPERATURE
(V 1 = +5V, V 2 = +3.3V)
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
(V 1 = +3.3V, V 2 = +2.5V)
CC
CC
CC
CC
(V 1 = +2.5V, V 2 = +1.8V)
CC
CC
20
18
16
14
12
10
8
20
18
16
14
12
10
8
20
18
16
14
12
10
8
TOTAL
I
1
CC
TOTAL
TOTAL
I
1
CC
I
1
CC
6
6
6
4
I
2
CC
4
4
I
2
CC
I
2
CC
2
2
2
0
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
NORMALIZED/RESET WATCHDOG
TIMEOUT PERIOD vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
(V 1 = +1.8V, V 2 = +1.2V)
MAXIMUM V TRANSIENT DURATION
CC
vs. RESET THRESHOLD OVERDRIVE
CC
CC
1.020
1.016
1.012
1.008
1.004
1.000
0.996
0.992
0.988
0.984
0.980
20
18
16
14
12
10
8
10,000
1000
RESET OCCURS ABOVE
THIS LINE
TOTAL
I
1
CC
100
10
6
4
I
2
CC
2
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
1
10
100
1000
TEMPERATURE (°C)
TEMPERATURE (°C)
RESET THRESHOLD OVERDRIVE (mV)
NORMALIZED V RESET THRESHOLD
CC
RESET INPUT AND POWER-FAIL INPUT
THRESHOLD vs. TEMPERATURE
V
TO RESET DELAY
CC
vs. TEMPERATURE
vs. TEMPERATURE
1.008
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1.000
0.999
0.998
638
637
636
635
634
633
632
631
630
629
628
20
19
18
17
16
15
14
13
12
11
10
75mV OVERDRIVE
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
Typical Operating Characteristics (continued)
(V 1 = 5V, V 2 = 3.3V, T = +25°C, unless otherwise noted.)
CC
CC
A
RSTIN INPUT TO RESET OUTPUT DELAY
vs. TEMPERATURE
POWER-FAIL INPUT TO POWER-FAIL
OUTPUT DELAY vs. TEMPERATURE
MR TO RESET OUTPUT DELAY
MAX6715A-29A toc12
24
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
30mV OVERDRIVE
30mV OVERDRIVE
22
20
18
16
14
12
V
MR
2V/div
0V
0V
V
RST
2V/div
50ns/div
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Pin Description
PIN
MAX6728A/
MAX6729A/
MAX6797A
NAME
FUNCTION
MAX6715A/ MAX6717A/ MAX6719A/ MAX6721A/ MAX6723A/ MAX6725A/
MAX6716A MAX6718A MAX6720A MAX6722A MAX6724A MAX6726A
MAX6727A
Active-Low Reset Output,
Open-Drain or Push-Pull.
RST/RST1 changes from
15–2/MX697A
high to low when V 1 or
CC
V
2 drops below the
CC
selected reset thresholds,
RSTIN is below threshold,
MR is pulled low, or the
watchdog triggers a reset.
RST/RST1 remains low for
the reset timeout period
RST/
RST1
1
1
1
1
1
1
1, 4
1
after V 1/ V 2/RSTIN
CC
CC
exceed the device reset
thresholds, MR goes low
to high, or the watchdog
triggers a reset. Open-
drain outputs require an
external pullup resistor.
Push-pull outputs are
referenced to V 1.
CC
6
_______________________________________________________________________________________
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
15–2/MX697A
Pin Description (continued)
PIN
MAX6728A/
MAX6729A/
MAX6797A
NAME
FUNCTION
MAX6715A/ MAX6717A/ MAX6719A/ MAX6721A/ MAX6723A/MAX6725A/
MAX6716A MAX6718A MAX6720A MAX6722A MAX6724A MAX6726A
MAX6727A
Active-Low Reset Output,
Open-Drain or Push-Pull.
RST2 changes from high
to low when V 1 or V
2
CC
CC
drops below the selected
reset thresholds or MR is
pulled low. RST2 remains
low for the reset timeout
5
—
—
—
—
—
—
—
RST2
period after V 1/V
2
CC
CC
exceed the device reset
thresholds or MR goes low
to high. Open-drain
outputs require an external
pullup resistor. Push-pull
outputs are referenced to
V
2.
CC
2
3
2
3
2
3
2
3
2
2
5
2
5
2
5
GND
Ground
Active-Low Manual-Reset
Input. Internal 50kΩ pullup
to V 1. Pull low
CC
to force a reset. Reset
remains active as long as
MR is low and for the reset
timeout period after MR
goes high. Leave
—
MR
unconnected or connect
to V 1 if unused.
CC
Secondary Supply Voltage
Input. Powers
the device when it is
above V 1 and input
CC
for secondary reset
threshold monitor.
Primary Supply Voltage
Input. Powers the device
4
6
4
5
4
6
4
6
4
6
6
8
6
8
6
8
V
V
2
1
CC
when it is above V
2
CC
CC
and input for primary reset
threshold monitor.
_______________________________________________________________________________________
7
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
Pin Description (continued)
PIN
MAX6728A/
MAX6727A MAX6729A/
MAX6797A
NAME
FUNCTION
MAX6715A/ MAX6717A/ MAX6719A/ MAX6721A/ MAX6723A/ MAX6725A/
MAX6716A MAX6718A MAX6720A MAX6722A MAX6724A MAX6726A
Watchdog Input. If WDI
remains high or low for
longer than the watchdog
timeout period, the internal
watchdog timer runs out
and the reset output
asserts for the reset
timeout period. The
internal watchdog timer
clears whenever a reset is
asserted or WDI sees a
rising or falling edge. The
watchdog has a long
—
—
—
5
3
3
3
3
WDI
startup period (35s min)
after each reset event and
a short watchdog timeout
period (1.12s min) after
the first valid WDI
transition. Leave WDI
unconnected to disable
the watchdog timer. The
WDI unconnected-state
detector uses a small
200nA current source.
Therefore, do not connect
WDI to anything that will
source more than 50nA.
15–2/MX697A
Undervoltage Reset
Comparator Input. High-
impedance input for
adjustable reset monitor.
The reset output is
asserted when RSTIN falls
—
—
5
—
5
7
7
—
RSTIN below the 0.626V internal
reference voltage. Set the
monitored voltage reset
threshold with an external
resistor-divider network.
Connect RSTIN to V
1
CC
or V 2 if not used.
CC
8
_______________________________________________________________________________________
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
15–2/MX697A
Pin Description (continued)
PIN
MAX6728A/
MAX6727A MAX6729A/
MAX6797A
NAME
FUNCTION
MAX6715A/ MAX6717A/ MAX6719A/ MAX6721A/ MAX6723A/ MAX6725A/
MAX6716A MAX6718A MAX6720A MAX6722A MAX6724A MAX6726A
Power-Fail Voltage
Monitor Input. High-
impedance input for
internal power-fail monitor
comparator. Connect PFI
to an external resistor-
divider network to set the
power-fail threshold
—
—
—
—
—
—
—
7
PFI
voltage (0.626V typical
internal reference
voltage). Connect to GND,
V
1, or V 2 if not used.
CC CC
Active-Low Power-Fail
Monitor Output, Open-
Drain or Push-Pull. PFO is
asserted low when PFI is
less than 0.626V. PFO
deasserts without a reset
timeout period. Open-
drain outputs require an
external pullup resistor.
Push-pull outputs are
—
—
—
—
—
—
—
4
PFO
referenced to V 1.
CC
Active-High Reset Output,
Open-Drain or Push-Pull.
RST changes from low to
high when V 1 or V
2
CC
CC
drops below selected
reset thresholds, RSTIN is
below threshold, MR is
pulled low, or the
watchdog triggers a reset.
RST remains HIGH for the
reset timeout period after
—
—
—
—
—
4
—
—
RST
V
1/V 2/RSTIN exceed
CC CC
the device reset
thresholds, MR goes low
to high, or the watchdog
triggers a reset. Open-
drain outputs require an
external pullup resistor.
Push-pull outputs are
referenced to V 1.
CC
_______________________________________________________________________________________
9
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
Adjustable Input Voltage
Detailed Description
The MAX6719A/MAX6720A and MAX6723A–MAX6727A
provide an additional input to monitor a third system volt-
age. The threshold voltage at RSTIN is typically 626mV.
Connect a resistor-divider network to the circuit as shown
in Figure 1 to establish an externally controlled threshold
Supply Voltages
The MAX6715A–MAX6729A/MAX6797A µP supervisory
circuits maintain system integrity by alerting the µP to
fault conditions. These ICs are optimized for systems
that monitor two or three supply voltages. The output-
reset state is guaranteed to remain valid while either
voltage, V
.
EXT_TH
V
CC
1 or V 2 is above 0.8V.
CC
V
= 626mV((R1 + R2)/R2)
EXT_TH
Threshold Levels
Input-voltage threshold level combinations are indicat-
ed by a two-letter code in the Reset Voltage Threshold
Suffix Guide (Table 1). Contact factory for availability of
other voltage threshold combinations.
Low-leakage current at RSTIN allows the use of large-
valued resistors resulting in reduced power consump-
tion of the system.
Watchdog Input
The watchdog monitors µP activity through the watch-
dog input (WDI). To use the watchdog function, con-
nect WDI to a bus line or µP I/O line. When WDI
remains high or low for longer than the watchdog time-
out period, the reset output asserts.
Reset Outputs
The MAX6715A–MAX6729A/MAX6797A provide an
active-low reset output (RST) and the MAX6725A/
MAX6726A also provide an active-high (RST) output.
RST, RST, RST1, and RST2 are asserted when the volt-
age at either V 1 or V 2 falls below the voltage
CC
CC
threshold level, RSTIN drops below threshold, or MR is
pulled low. Once reset is asserted, it stays low for the
reset timeout period (see Table 2). If V 1, V 2, or
The MAX6721A–MAX6729A/MAX6797A include a dual-
mode watchdog timer to monitor µP activity. The flexi-
ble timeout architecture provides a long period initial
watchdog mode, allowing complicated systems to
complete lengthy boots, and a short period normal
watchdog mode, allowing the supervisor to provide
quick alerts when processor activity fails. After each
CC
CC
RSTIN goes below the reset threshold before the reset
timeout period is completed, the internal timer restarts.
The MAX6715A/MAX6717A/MAX6719A/MAX6721A/
MAX6723A/MAX6725A/MAX6727A/MAX6728A contain
open-drain reset outputs, while the MAX6716A/
MAX6718A/MAX6720A/MAX6722A/MAX6724A/
MAX6726A/MAX6729A/MAX6797A contain push-pull
reset outputs. The MAX6727A provides two separate
open-drain RST outputs driven by the same internal logic.
reset event (V
power-up/brownout, manual reset, or
CC
watchdog reset), there is a long initial watchdog period
of 35s minimum. The long watchdog period mode pro-
vides an extended time for the system to power-up and
fully initialize all µP and system components before
assuming responsibility for routine watchdog updates.
15–2/MX697A
Manual-Reset Input
Many µP-based products require manual-reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic-low on MR
asserts the reset output. Reset remains asserted while
V
MR is low for the reset timeout period (t ) after MR
EXT_TH
RP
MAX6719A/
returns high. This input has an internal 50kΩ pullup
MAX6720A/
MAX6723A–
R1
resistor to V 1 and can be left unconnected if not
CC
used. MR can be driven with CMOS logic levels, or with
open-drain/collector outputs. Connect a normally open
momentary switch from MR to GND to create a manual-
reset function; external debounce circuitry is not
required. If MR is driven from long cables or if the
device is used in a noisy environment, connect a 0.1µF
capacitor from MR to GND to provide additional noise
immunity.
MAX6727A
RSTIN
R2
GND
Figure 1. Monitoring a Third Voltage
10 ______________________________________________________________________________________
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
15–2/MX697A
The normal watchdog timeout period (1.12s min)
Ensuring a Valid Reset Output
Down to V = 0V
begins after the first transition on WDI before the con-
clusion of the long initial watchdog period (Figure 2).
During the normal operating mode, the supervisor will
issue a reset pulse for the reset timeout period if the µP
does not update the WDI with a valid transition (high-to-
low or low-to-high) within the standard timeout period
(1.12s min).
CC
The MAX6715A–MAX6729A/MAX6797A are guaranteed
to operate properly down to V = 0.8V. In applications
CC
that require valid reset levels down to V
= 0V, use a
CC
pulldown resistor at RST to ground. The resistor value
used is not critical, but it must be large enough not to
load the reset output when V is above the reset thresh-
CC
old. For most applications, 100kΩ is adequate. This con-
figuration does not work for the open-drain outputs of the
MAX6715A/MAX6717A/MAX6719A/MAX6721A/
MAX6723A/MAX6725A/MAX6727A/MAX6728A. For push-
pull, active-high RST output connect the external resistor
Leave WDI unconnected to disable the watchdog timer.
The WDI unconnected-state detector uses a small
(200nA typ) current source. Therefore, do not connect
WDI to anything that will source more than 50nA.
Power-Fail Comparator
as a pullup from RST to V 1.
CC
PFI is the noninverting input to a comparator. If PFI is
less than V
(626.5mV), PFO goes low. Common uses
PFI
A)
for the power-fail comparator include monitoring prereg-
ulated input of the power supply (such as a battery) or
providing an early power-fail warning so software can
conduct an orderly system shutdown. It can also be
V
IN
MAX6728A/
MAX6729A/
MAX6797A
R1
R2
R1 + R2
R2
V
= V
PFI
TRIP
(
)
used to monitor supplies other than V 1 or V 2 by
CC
CC
PFI
PFO
setting the power-fail threshold with a resistor-divider, as
shown in Figure 3. PFI is the input to the power-fail com-
parator. The typical comparator delay is 2µs from PFI to
PFO. Connect PFI to ground of V 1 if unused.
CC
GND
B)
V
TH
V
CC
MAX6728A/
MAX6729A/
MAX6797A
V
CC
t
WDI-NORMAL
1.12s MAX
R1
R2
V
CC
R1
1
1
R2
+
-
(V
= R2
)
PFI
V
TRIP
(R1 )
[
]
t
WDI-STARTUP
35s MAX
PFI
PFO
V
= 626.5mV
PFI
WDI
RST
1.12s MAX
V
IN
GND
t
RP
Figure 3. Using Power-Fail Input to Monitor an Additional
Power-Supply a) V is Positive b) V is Negative
Figure 2. Normal Watchdog Startup Sequence
IN
IN
______________________________________________________________________________________ 11
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
The current through R2 should be at least 2.5µA to ensure
Applications Information
Interfacing to µPs with Bidirectional
Reset Pins
that the 100nA (max) PFI input current does not signifi-
cantly shift the trip points. Therefore, R2 < V /10µA <
PFI
62kΩ for most applications. R3 will provide additional hys-
Most µPs with bidirectional reset pins can interface
directly to open-drain RST output options. Systems
simultaneously requiring a push-pull RST output and a
bidirectional reset interface can be in logic contention.
To prevent contention, connect a 4.7kΩ resistor
between RST and the µP’s reset I/O port as shown in
Figure 4.
teresis for PFO push-pull (V
= V 1) or open-drain
CC
OH
(V
= V
) applications.
OH
PULLUP
Monitoring an Additional Power Supply
These µP supervisors can monitor either positive or
negative supplies using a resistor voltage-divider to
PFI. PFO can be used to generate an interrupt to the µP
or cause reset to assert (Figure 3).
Adding Hysteresis to the Power-Fail
Comparator
Monitoring a Negative Voltage
The power-fail comparator can be used to monitor a
negative supply voltage using the circuit shown in
Figure 3. When the negative supply is valid, PFO is low.
When the negative supply voltage drops, PFO goes
high. The circuit’s accuracy is affected by the PFI
The power-fail comparator has a typical input hysteresis
of 3mV. This is sufficient for most applications where a
power-supply line is being monitored through an external
voltage-divider (see the Power-Fail Comparator section).
If additional noise margin is desired, connect a resistor
between PFO and PFI as shown in Figure 5. Select the
threshold tolerance, V , R1, and R2.
CC
values of R1, R2, and R3 so PFI sees V
(626mV) when
PFI
Negative-Going V
Transients
CC
V
EXT
falls to its power-fail trip point (V
) and when V
FAIL
IN
The MAX6715A–MAX6729A/MAX6797A supervisors are
rises to its power-good trip point (V
). The hysteresis
GOOD
relatively immune to short-duration negative-going V
CC
window extends between the specified V
and V
GOOD
FAIL
transients (glitches). It is usually undesirable to reset
the µP when V experiences only small glitches. The
thresholds. R3 adds the additional hysteresis by sinking
current from the R1/R2 divider network when PFO is
logic-low and sourcing current into the network when PFO
is logic-high. R3 is typically an order of magnitude greater
than R1 or R2.
CC
Typical Operating Characteristics show Maximum
Transient Duration vs. Reset Threshold Overdrive, for
which reset pulses are not generated. The graph was
produced using negative-going V
pulses, starting
CC
above V and ending below the reset threshold by the
TH
RESET TO OTHER SYSTEM COMPONENTS
R3
V
CC
1 V 2
CC
15–2/MX697A
A
V
GOOD
V
FAIL
V
IN
MAX6715A–
MAX6729A/
MAX6797A
PFO
V
EXT
MAX6729A
µP
4.7kΩ
R1
V
V
2
1
RESET
RST
CC
PFI
PFO
V
V
V
= DESIRED V GOOD VOLTAGE THRESHOLD
EXT
CC
GOOD
FAIL
OH
R2
= DESIRED V FAIL VOLTAGE THRESHOLD
EXT
= V 1 (FOR PUSH-PULL PFO)
CC
R2 = 50kΩ (FOR > 10µA R2 CURRENT)
R1 = R2 ((V
- V ) - (V )(V
- V )/V )/V
GOOD
PFI
PFI GOOD FAIL OH PFI
GND
R3 = (R1 x V )/(V
- V
FAIL
)
GND
GND
OH
GOOD
Figure 4. Interfacing to µPs with Bidirectional Reset I/O
Figure 5. Adding Hysteresis to Power-Fail for Push-Pull PFO
12 ______________________________________________________________________________________
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
15–2/MX697A
magnitude indicated (reset threshold overdrive). The
graph shows the maximum pulse width that a negative-
going V transient may typically have without causing
CC
START
a reset pulse to be issued. As the amplitude of the tran-
sient increases (i.e., goes farther below the reset
threshold), the maximum allowable pulse width
decreases. A 0.1µF bypass capacitor mounted close to
SET WDI
HIGH
the V
pin provides additional transient immunity.
CC
Watchdog Software Considerations
PROGRAM
CODE
Setting and resetting the watchdog input at different
points in the program, rather than “pulsing” the watch-
dog input high-low-high or low-high-low, helps the
watchdog timer to closely monitor software execution.
This technique avoids a “stuck” loop where the watch-
dog timer continues to be reset within the loop, keeping
the watchdog from timing out. Figure 6 shows an exam-
ple flow diagram where the I/O driving the watchdog
input is set high at the beginning of the program, set low
at the beginning of every subroutine or loop, then set
high again when the program returns to the beginning. If
the program should “hang” in any subroutine, the I/O is
continually set low and the watchdog timer is allowed to
time out, causing a reset or interrupt to be issued.
SUBROUTINE OR
PROGRAM LOOP
SET WDI LOW
HANG IN
SUBROUTINE
SUBROUTINE
COMPLETED
RETURN
Figure 6. Watchdog Flow Diagram
______________________________________________________________________________________ 13
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
Functional Diagram
V
CC
1
V
CC
1
MR
MR
PULLUP
V
CC
1
V
CC
1
V 2
CC
V
REF
RST
RST
RESET
TIMEOUT
PERIOD
RESET
OUTPUT
DRIVER
V
CC
2
RSTIN/PFI
PFO
V
CC
1
15–2/MX697A
V
REF
V 1
CC
WATCHDOG
TIMER
WDI
V
REF/2
14 ______________________________________________________________________________________
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
15–2/MX697A
Selector Guide
POWER-
FAIL
INPUT/
OUTPUT
NUMBER OF
VOLTAGE
MONITORS
OPEN-
DRAIN
RESET
OPEN-
DRAIN
RESET
PUSH-
PULL
RESET
PUSH-
PULL
RESET
WATCH-
DOG
INPUT
PART
NUMBER
MANUAL
RESET
MAX6715A
MAX6716A
MAX6717A
MAX6718A
MAX6719A
MAX6720A
MAX6721A
MAX6722A
MAX6723A
MAX6724A
MAX6725A
MAX6726A
MAX6727A
MAX6728A
MAX6729A
MAX6797A
2
2
2
2
3
3
2
2
3
3
3
3
3
2
2
2
2
—
1
—
—
—
—
—
—
—
—
—
—
1
—
2
—
—
—
—
—
—
—
—
—
—
—
1
√
√
—
—
—
—
—
—
√
—
—
—
1
√
—
—
1
√
—
—
1
√
—
—
1
√
—
—
1
√
—
—
1
√
√
—
—
1
—
—
√
√
—
—
1
√
—
—
1
√
—
—
—
2
—
—
—
—
—
√
√
—
—
1
—
—
—
—
√
√
—
1
√
√
√ (open drain)
√ (push-pull)
√ (open drain)
—
—
√
√
1
√
√
Ordering Information (continued)
PIN-
PART
TEMP RANGE
PACKAGE
6 SOT23
6 SOT23
6 SOT23
6 SOT23
8 SOT23
8 SOT23
8 SOT23
8 SOT23
8 SOT23
8 SOT23
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
MAX6721AUT_ _D_+T
MAX6722AUT_ _D_+T
MAX6723AUT_ _D_+T
MAX6724AUT_ _D_+T
MAX6725AKA_ _D_+T
MAX6726AKA_ _D_+T
MAX6727AKA_ _D_+T
MAX6728AKA_ _D_+T
MAX6729AKA_ _D_+T
MAX6797AKA_ _D_+T
+Denotes a lead-free/RoHS-compliant package.
T = Tape and reel.
Note: The first “_ _” are placeholders for the threshold voltage
levels of the devices. Desired threshold levels are set by the part
number suffix found in the Reset Voltage Threshold Suffix Guide.
The “_” after the D is a placeholder for the reset timeout delay
time. Desired delay time is set using the timeout period suffix
found in the Reset Timeout Period Suffix Guide. For example, the
MAX6716AUTLTD3-T is a dual-voltage supervisor V 1 =
TH
4.625V, V 2 = 3.075V, and 210ms (typ) timeout period.
TH
______________________________________________________________________________________ 15
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
Table 1. Reset Voltage Threshold Suffix
Table 2. Reset Timeout Period Suffix
Guide**
Guide
PART NUMBER
SUFFIX
V
CC
1 NOMINAL
VOLTAGE
V
CC
2 NOMINAL
VOLTAGE
ACTIVE TIMEOUT PERIOD
TIMEOUT
PERIOD SUFFIX
MIN (ms)
1.1
MAX (ms)
2.2
(_ _)
THRESHOLD (V)
4.625
4.375
4.375
3.075
2.925
2.625
3.075
2.925
2.625
3.075
2.925
2.625
3.075
2.925
2.625
3.075
2.925
2.625
2.313
2.188
2.313
2.188
2.313
2.188
2.313
2.188
1.665
1.575
1.665
1.575
1.665
1.575
THRESHOLD (V)
3.075
2.925
2.625
2.313
2.188
2.188
1.665
1.575
1.575
1.388
1.313
1.313
1.110
1.050
1.050
0.833
0.788
0.788
1.665
1.575
1.388
1.313
1.110
1.050
0.833
0.788
1.388
1.313
1.110
1.050
0.833
0.788
D1
D2
LT
MS
MR
TZ
8.8
17.6
†
D7
17.5
35.0
140
35.0
†
D8
70.0
D3
D5
D6
D4
280
SY
RY
TW
SV
RV
TI
280
560
560
1120
2240
1120
†
D7 and D8 timeout periods are only available for the MAX6797A.
SH
RH
TG
SF
RF
TE
SD
RD
ZW
YV
ZI
6
YH
ZG
YF
ZE
YD
WI
VH
WG
VF
WE
VD
**Standard versions are shown in bold and are available in a D3
timeout option only. Standard versions require 2,500 piece order
increments and are typically held in sample stock. There is a
10,000 order increment on nonstandard versions. Other thresh-
old voltages may be available, contact factory for availability.
16 ______________________________________________________________________________________
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
15–2/MX697A
Pin Configurations
TOP VIEW
RST1
1
2
3
6
5
4
V
1
RST
GND
MR
1
2
3
5
4
V
V
V
1
2
1
RST
GND
MR
1
2
3
6
5
4
V 1
CC
CC
CC
CC
CC
MAX6715A/
MAX6716A
MAX6717A/
MAX6718A
MAX6719A/
MAX6720A
GND
MR
RST2
RSTIN
V
2
V 2
CC
CC
CC
SOT23
SOT23
SOT23
RST
1
2
3
4
8
7
6
5
V 1
CC
RST
GND
MR
1
2
3
6
5
4
V
1
RST
GND
WDI
1
2
3
6
5
4
GND
WDI
RST
RSTIN
MAX6721A/
MAX6722A
MAX6723A/
MAX6724A
MAX6725A/
MAX6726A
WDI
RSTIN
V
CC
2
MR
V
2
V 2
CC
CC
SOT23
SOT23
SOT23
RST
1
2
3
4
8
7
6
5
V
1
RST
GND
WDI
PFO
1
2
3
4
8
7
V
1
2
CC
CC
GND
WDI
RST
RSTIN
PFI
MAX6727A
MAX6728A/
MAX6729A/
MAX6797A
V
2
6
5
V
CC
CC
MR
MR
SOT23
SOT23
Chip Information
Package Information
For the latest package outline information and land patterns, go
TRANSISTOR COUNT: 1072
to www.maxim-ic.com/packages.
PROCESS: BiCMOS
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
5 SOT23
6 SOT23
8 SOT23
U5-1
21-0057
21-0058
21-0078
U6-1
K8SN-1
______________________________________________________________________________________ 17
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
4/06
7/06
Initial release
—
Updated Ordering Information.
1, 15
Added the MAX6797A to Ordering Information, Electrical Characteristics,
Pin Description, Detailed Description, Figures 4 and 5, Selector Guide,
Table 2, Pin Configurations.
2
3
6/08
9/08
1, 2, 6–11, 12, 15–17
15
Updated Selector Guide.
15–2/MX697A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
Heaney
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Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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