MAX6753KA43/V+T [MAXIM]
Power Supply Management Circuit, Adjustable, 1 Channel, BICMOS, PDSO8, SOT-23, 8 PIN;
| 型号： | MAX6753KA43/V+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Power Supply Management Circuit, Adjustable, 1 Channel, BICMOS, PDSO8, SOT-23, 8 PIN 信息通信管理 光电二极管 |
| 文件： | 总14页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX6746–MAX6753
µP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
General Description
Features
The MAX6746–MAX6753 low-power microprocessor
(µP) supervisory circuits monitor single/dual system
supply voltages from 1.575V to 5V and provide maxi-
mum adjustability for reset and watchdog functions.
o Factory-Set Reset Threshold Options from 1.575V
to 5V in ~100mV Increments
o Adjustable Reset Threshold Options
o Single/Dual Voltage Monitoring
These devices assert a reset signal whenever the V
CC
supply voltage or RESET IN falls below its reset thresh-
old or when manual reset is pulled low. The reset output
o Capacitor-Adjustable Reset Timeout
o Capacitor-Adjustable Watchdog Timeout
o Min/Max (Windowed) Watchdog Option
o Manual Reset Input Option
remains asserted for the reset timeout period after V
CC
and RESET IN rise above the reset threshold. The reset
function features immunity to power-supply transients.
The MAX6746–MAX6753 have ±±2 factory-trimmed
reset threshold voltages in approximately 100mV incre-
ments from 1.575V to 5.0V and/or adjustable reset
threshold voltages using external resistors.
o Guaranteed RESET Valid for V
o 3.7µA Supply Current
≥ 1V
CC
o Push-Pull or Open-Drain RESET Output Options
o Power-Supply Transient Immunity
o Small 8-Pin SOT23 Packages
The reset and watchdog delays are adjustable with
external capacitors. The MAX6746–MAX6751 contain a
watchdog select input that extends the watchdog time-
out period by 1±8x. The MAX675±/MAX6753 contain a
window watchdog timer that looks for activity outside an
expected window of operation.
Ordering Information
PART
TEMP RANGE
-40°C to +1±5°C
-40°C to +1±5°C
-40°C to +1±5°C
-40°C to +1±5°C
-40°C to +1±5°C
-40°C to +1±5°C
-40°C to +1±5°C
-40°C to +1±5°C
-40°C to +1±5°C
-40°C to +1±5°C
-40°C to +1±5°C
-40°C to +1±5°C
-40°C to +1±5°C
PIN-PACKAGE
8 SOT±3
8 SOT±3
8 SOT±3
8 SOT±3
8 SOT±3
8 SOT±3
8 SOT±3
8 SOT±3
8 SOT±3
8 SOT±3
8 SOT±3
8 SOT±3
8 SOT±3
MAX6746KA_ _-T
MAX6746KA_ _/V+T
MAX6747KA_ _-T
MAX6747KA_ _/V+T
MAX6748KA-T
The MAX6746–MAX6753 are available with a push-pull
or open-drain active-low RESET output. The MAX6746–
MAX6753 are available in an 8-pin SOT±3 package and
are fully specified over the automotive temperature
range (-40°C to +1±5°C).
MAX6749KA-T
Applications
MAX6750KA_ _-T
MAX6750KA_ __/V+T
MAX6751KA_ _-T
MAX6751KA_ _/V+T*
MAX6752KA_ _-T
MAX6753KA_ _-T
MAX6753KA_ _/V+T
Medical Equipment
Automotive
Embedded Controllers
Critical µP Monitoring
Set-Top Boxes
Intelligent Instruments
Portable Equipment
Computers
Battery-Powered
Computers/Controllers
Note: “_ _” represents the two number suffix needed when
ordering the reset threshold voltage value for the
Pin Configurations
MAX6746/MAX6747 and MAX6750–MAX6753. The reset
threshold voltages are available in approximately 100mV incre-
ments. Table ± contains the suffix and reset factory-trimmed
voltages. All devices are available in tape-and-reel only. There
is a ±500-piece minimum order increment for standard ver-
sions (see Table 3). Sample stock is typically held on standard
versions only. Nonstandard versions require a minimum order
increment of 10,000 pieces. Contact factory for availability.
TOP VIEW
+
RESET IN (MR)
SWT
1
2
3
4
8
7
6
5
V
CC
RESET
WDI
MAX6746–
MAX6751
SRT
Devices are available in both leaded and lead-free packaging.
Specify lead-free by replacing “-T” with “+T” when ordering.
GND
WDS
+ Denotes a lead (Pb)-Free/RoHs-compliant package.
T = Tape and reel
/V denotes an automotive qualified part.
*Future product—contact factory for availability.
SOT23
( ) ARE FOR MAX6746 AND MAX6747 ONLY.
Selector Guide appears at end of data sheet.
Typical Operating Circuit appears at end of data sheet.
Pin Configurations continued at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-±530; Rev 8; ±/14
MAX6746–MAX6753
µP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
ABSOLUTE MAXIMUM RATINGS
CC
V
to GND...........................................................-0.3V to +6.0V
Continuous Power Dissipation (T = +70°C)
A
SRT, SWT, SET0, SET1, RESET IN, WDS, MR,
WDI, to GND .......................................…-0.3V to (V
RESET (Push-Pull) to GND......................…-0.3V to (V
RESET (Open Drain) to GND.............................…-0.3V to +6.0V
Input Current (All Pins) .....................................................±±0mA
Output Current (RESET) ...................................................±±0mA
8-Pin SOT±3 (derate 8.9mW/°C above +70°C)............714mW
Operating Temperature Range .........................-40°C to +1±5°C
Storage Temperature Range ............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+±60°C
+ 0.3V)
+ 0.3V)
CC
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +1.±V to +5.5V, T = T
A
to T
, unless otherwise specified. Typical values are at V
= +5V and T = +±5°C.) (Note 1)
CC A
CC
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
= 0°C to +1±5°C
MIN
1.0
TYP
MAX
5.5
5.5
10
9
UNITS
T
T
A
Supply Voltage
V
V
CC
= -40°C to 0°C
1.±
A
V
V
V
≤ 5.5V
≤ 3.3V
≤ ±.0V
5
CC
CC
CC
Supply Current
I
µA
4.±
3.7
CC
8
See V
selection table
V
±2
-
V
±2
+
TH
TH
TH
V
Reset Threshold
V
T = -40°C to+1±5°C
A
V
CC
TH
Hysteresis
to Reset Delay
V
0.8
±0
2
µs
HYST
V
falling from V + 100mV to V
-
CC
TH
TH
V
CC
100mV at 1mV/µs
C
C
= 1500pF
5.69±
7.590
0.506
±50
9.487
SRT
SRT
SRT
Reset Timeout Period
t
ms
RP
= 100pF
SRT Ramp Current
I
V
= 0 to 1.±3V; V
= 1.6V to 5V
±00
300
nA
V
RAMP
CC
SRT Ramp Threshold
V
V
= 1.6V to 5V (V
= 1500pF
= 100pF
rising)
RAMP
1.173
5.69±
1.±35
7.590
0.506
1.±97
9.487
RAMP
CC
C
C
C
C
C
C
SWT
SWT
SWT
SWT
SWT
SWT
Normal Watchdog Timeout Period
(MAX6746–MAX6751)
t
t
ms
ms
ms
WD
WD
= 1500pF
= 100pF
7±8.6
7±8.6
971.5 1±14.4
64.77
Extended Watchdog Timeout
(MAX6746–MAX6751)
= 1500pF
= 100pF
971.5 1±14.4
64.77
Slow Watchdog Period
(MAX675±/MAX6753)
t
WD±
WD1
Fast Watchdog Timeout Period,
SET Ratio = 8,
(MAX675±/MAX6753)
C
C
C
C
= 1500pF
= 100pF
= 1500pF
= 100pF
91.08 1±1.43 151.80
8.09
SWT
SWT
SWT
SWT
t
ms
ms
Fast Watchdog Timeout Period,
SET Ratio = 16,
(MAX675±/MAX6753)
45.53
60.71
4.05
75.89
t
WD1
±
Maxim Integrated
MAX6746–MAX6753r
µP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
ELECTRICAL CHARACTERISTICS (continued)
(V
= +1.±V to +5.5V, T = T
A
to T
, unless otherwise specified. Typical values are at V
= +5V and T = +±5°C.) (Note 1)
CC A
CC
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
= 1500pF
MIN
TYP
MAX
UNITS
Fast Watchdog Timeout Period,
SET Ratio = 64,
(MAX675±/MAX6753)
C
C
11.38
15.18
18.98
SWT
SWT
t
ms
WD1
= 100pF
1.01
Fast Watchdog Minimum Period
(MAX675±/MAX6753)
±000
ns
SWT Ramp Current
I
V
V
V
V
V
V
V
V
= 0 to 1.±3V, V = 1.6V to 5V
±00
±50
300
1.±97
0.3
nA
V
RAMP
SWT
CC
SWT Ramp Threshold
V
= 1.6V to 5V (V
rising)
1.173
1.±35
RAMP
CC
CC
CC
CC
CC
CC
CC
RAMP
≥ 1.0V, I
≥ ±.7V, I
≥ 4.5V, I
≥ 1.8V, I
= 50µA
SINK
SINK
SINK
RESET Output-Voltage LOW
Open-Drain, Push-Pull
(Asserted)
V
V
= 1.±mA
= 3.±mA
0.3
OL
0.4
= ±00µA
= 500µA
0.8 x V
0.8 x V
0.8 x V
SOURCE
CC
CC
CC
RESET Output-Voltage HIGH,
Push-Pull (Not Asserted)
V
V
≥ ±.±5V, I
OH
SOURCE
≥ 4.5V, I
= 800µA
SOURCE
RESET Output Leakage Current,
Open Drain
V
V
> V , reset not asserted,
CC TH
I
1.0
0.8
µA
LKG
= 5.5V
RESET
DIGITAL INPUTS (MR, SET0, SET1, WDI, WDS)
V
IL
V
V
≥ 4.0V
CC
CC
V
±.4
IH
Input Logic Levels
V
V
< 4.0V
0.3 x V
CC
IL
V
0.7 x V
1
IH
CC
MR Minimum Pulse Width
MR Glitch Rejection
µs
ns
ns
kΩ
ns
100
±00
±0
MR to RESET Delay
MR Pullup Resistance
WDI Minimum Pulse Width
RESET IN
Pullup to V
1±
±8
CC
300
RESET IN Threshold
RESET IN Leakage Current
RESET IN to RESET Delay
V
T
= -40°C to +1±5°C
A
1.±16
-50
1.±35
1
1.±54
+50
V
RESET IN
I
nA
µs
RESET IN
RESET IN falling at 1mV/µs
±0
Note 1: Production testing done at T = +±5°C. Over temperature limits are guaranteed by design.
A
Maxim Integrated
3
MAX6746–MAX6753
µP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
Typical Operating Characteristics
(V
= +5V, T = +±5°C, unless otherwise noted.)
A
CC
SUPPLY CURRENT
RESET TIMEOUT PERIOD vs. C
WATCHDOG TIMEOUT PERIOD vs. C
vs. SUPPLY VOLTAGE
SRT
SWT
6
1000
100,000
10,000
1000
100
MAX6746–MAX6751
5
4
3
EXTENDED MODE
100
10
1
NORMAL MODE
2
1
10
1
0
0.1
0.1
1
2
3
4
5
6
1000
6
100
1000
10,000
100,000
100
1000
10,000
100,000
SUPPLY VOLTAGE (V)
C
(pF)
C
(pF)
SWT
SRT
NORMALIZED RESET TIMEOUT PERIOD
vs. TEMPERATURE
NORMALIZED WATCHDOG TIMEOUT PERIOD
vs. TEMPERATURE
MAXIMUM TRANSIENT DURATION
vs. RESET THRESHOLD OVERDRIVE
1.20
1.15
1.10
1.05
1.00
0.95
0.90
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
175
150
125
100
75
C
SRT
= 100pF
C
= 100pF
SWT
RESET OCCURS
ABOVE THE CURVE
C
= 1500pF
SWT
50
C
= 1500pF
SRT
25
V
= 2.92V
800
TH
0
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
0
200
400
600
TEMPERATURE (°C)
TEMPERATURE (°C)
RESET THRESHOLD OVERDRIVE (mV)
NORMALIZED RESET IN THRESHOLD VOLTAGE
vs. TEMPERATURE
RESET IN THRESHOLD
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
1.010
1.008
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.992
1.240
1.239
1.238
1.237
1.236
1.235
6
5
4
3
V
= 5V
CC
V
= 5V
CC
V
CC
= 1.8V
V
= 3.3V
CC
2
1
0.990
0
-50 -25
0
25
50
75 100 125
1
2
3
4
5
-50 -25
0
25
50
75 100 125
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Maxim Integrated
4
MAX6746–MAX6753r
µP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
Typical Operating Characteristics (continued)
(V
= +5V, T = +±5°C, unless otherwise noted.)
A
CC
RESET AND WATCHING TIMEOUT
PERIOD vs. SUPPLY VOLTAGE
V
TO RESET DELAY
RESET AND WATCHDOG
TIMEOUT PERIOD vs. SUPPLY VOLTAGE
CC
vs. TEMPERATURE (V FALLING)
CC
9.0
8.5
8.0
7.5
7.0
6.5
6.0
27.0
0.60
0.56
0.52
0.48
0.44
0.40
C
= C = 1500pF
SRT
C
= C = 100pF
SRT
V
FALLING AT 1mV/μs
SWT
SWT
CC
26.6
26.2
25.8
25.4
25.0
RESET
WATCHDOG
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
(V)
-50 -25
0
25
50
75 100 125
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
(V)
V
TEMPERATURE (°C)
V
CC
CC
Pin Description
PIN
NAME
FUNCTION
MAX6746
MAX6747
MAX6748–
MAX6751
MAX6752
MAX6753
Manual Reset Input. Pull MR low to manually reset the device. Reset
remains asserted for the reset timeout period after MR is released.
1
—
—
—
1
MR
Reset Input. High-impedance input to the adjustable reset comparator.
RESET IN Connect RESET IN to the center point of an external resistor-divider to
set the threshold of the externally monitored voltage.
—
—
1
Logic Input. SET0 selects watchdog window ratio or disables the
watchdog timer. See Table 1.
—
SET0
Watchdog Timeout Input.
MAX6746–MAX6751: Connect a capacitor between SWT and ground to
set the basic watchdog timeout period (t ). Determine the period by
WD
the formula t
= 5.06 x 106 x C
with t
in seconds and C
in
SWT
WD
SWT
WD
Farads. Extend the basic watchdog timeout period by using the WDS
input. Connect SWT to ground to disable the watchdog timer function.
±
±
±
SWT
MAX675±/MAX6753: Connect a capacitor between SWT and ground to
set the slow watchdog timeout period (t
). Determine the slow
WD±
watchdog period by the formula: t
= 0.65 x 109 x C
with t
in
WD±
SWT
WD±
seconds and C
in Farads. The fast watchdog timeout period is set
SWT
by pinstrapping SET0 and SET1 (Connect SET0 high and SET1 low to
disable the watchdog timer function.) See Table 1.
Reset Timeout Input. Connect a capacitor from SRT to GND to select
3
4
3
4
3
4
SRT
the reset timeout period. Determine the period as follows: t = 5.06 x
RP
106 x C
with t in seconds and C
in Farads.
SRT
SRT
RP
GND
Ground
5
Maxim Integrated
MAX6746–MAX6753
µP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
Pin Description (continued)
PIN
NAME
FUNCTION
MAX6746
MAX6747
MAX6748–
MAX6751
MAX6752
MAX6753
Watchdog Select Input. WDS selects the watchdog mode. Connect
WDS to ground to select normal mode and the watchdog timeout
5
5
—
5
WDS
SET1
period. Connect WDS to V
basic timeout period by a factor of 1±8. A change in the state of WDS
clears the watchdog timer.
to select extended mode, multiplying the
CC
Logic Input. SET1 selects the watchdog window ratio or disables the
watchdog timer. See Table 1.
—
—
Watchdog Input.
MAX6746–MAX6751: A falling transition must occur on WDI within the
selected watchdog timeout period or a reset pulse occurs. The
watchdog timer clears when a transition occurs on WDI or whenever
RESET is asserted. Connect SWT to ground to disable the watchdog
timer function.
6
6
6
WDI
MAX675±/MAX6753: WDI falling transitions within periods shorter than
t
or longer than t
force RESET to assert low for the reset timeout
WD±
WD1
period. The watchdog timer begins to count after RESET is deasserted.
The watchdog timer clears when a valid transition occurs on WDI or
whenever RESET is asserted. Connect SET0 high and SET1 low to
disable the watchdog timer function. See the Watchdog Timer section.
Push/Pull or Open-Drain Reset Output. RESET asserts whenever V
or
CC
RESET IN drops below the selected reset threshold voltage (V or
TH
V
, respectively) or manual reset is pulled low. RESET remains
RESET IN
7
8
7
8
7
8
RESET
low for the reset timeout period after all reset conditions are deasserted,
and then goes high. The watchdog timer triggers a reset pulse (t
whenever a watchdog fault occurs.
)
RP
Supply Voltage. V
threshold V monitor.
is the power-supply input and the input for fixed
CC
V
CC
CC
6
Maxim Integrated
MAX6746–MAX6753r
µP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
t
(MIN)
t
(MAX)
t
(MIN)
t (MAX)
WD2
WD1
WD1
WD2
GUARANTEED
TO ASSERT
GUARANTEED TO
NOT ASSERT
GUARANTEED TO
ASSERT
RESET
RESET
RESET
*UNDETERMINED
*UNDETERMINED
WDI CONDITION 1
WDI CONDITION 2
FAST FAULT
NORMAL OPERATION
SLOW FAULT
WDI CONDITION 3
*UNDETERMINED STATES MAY OR MAY NOT GENERATE A FAULT CONDITION
Figure 1. MAX675±/MAX6753 Detailed Watchdog Input Timing Relationship
RESET is guaranteed to be in the correct logic state for
greater than 1V. For applications requiring valid
Detailed Description
V
CC
The MAX6746–MAX6753 assert a reset signal whenever
reset logic when V
is less than 1V, see the section
CC
the V
supply voltage or RESET IN falls below its reset
CC
Ensuring a Valid RESET Output Down to V
= 0V.
CC
threshold. The reset output remains asserted for the
reset timeout period after V and RESET IN rise above
CC
RESET IN Threshold
its respective reset threshold. A watchdog timer triggers
a reset pulse whenever a watchdog fault occurs.
The MAX6748–MAX6751 monitor the voltage on RESET IN
using an adjustable reset threshold (V ) set with
RESET IN
an external resistor voltage-divider (Figure ±). Use the
following formula to calculate the externally monitored
The reset and watchdog delays are adjustable with
external capacitors. The MAX6746–MAX6751 contain a
watchdog select input that extends the watchdog time-
out period to 1±8x.
voltage (V
):
MON_TH
V
= V
x (R1 + R±) / R±
MON_TH
RESET IN
The MAX675± and MAX6753 have a sophisticated
watchdog timer that detects when the processor is run-
ning outside an expected window of operation. The
watchdog signals a fault when the input pulses arrive too
V
MON_TH
early (faster that the selected t
late (slower than the selected t
Figure 1).
timeout period) or too
WD±
WD1
timeout period) (see
R1
V
CC
V
CC
Reset Output
RESET IN
The reset output is typically connected to the reset input
of a µP. A µP’s reset input starts or restarts the µP in a
known state. The MAX6746–MAX6753 µP supervisory
circuits provide the reset logic to prevent code-execu-
tion errors during power-up, power-down, and
brownout conditions (see theTypical Operating Circuit).
RESET changes from high to low whenever the moni-
MAX6748
MAX6749
MAX6750
MAX6751
R2
GND
tored voltage, RESET IN and/or V
drop below the
CC
V
= 1.235 x (R1 + R2) / R2
MON_TH
reset threshold voltages. Once V
and/or V
CC
RESET IN
exceeds its respective reset threshold voltage(s),
RESET remains low for the reset timeout period, then
goes high.
Figure ±. Calculating the Monitored Threshold Voltage
(V
)
MON_TH
Maxim Integrated
7
MAX6746–MAX6753
µP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
guarantee RESET IN threshold accuracy and timing
V
MON_TH
performance. The MAX6748 and MAX6749 can be con-
figured to monitor V
V
voltage by connecting V
to
CC
CC
MON_TH.
Dual-Voltage Monitoring
(MAX6750/MAX6751)
R1
V
CC
The MAX6750 and MAX6751 contain both factory-
trimmed threshold voltages and an adjustable reset
threshold input, allowing the monitoring of two voltages,
V
CC
RESET IN
MAX6748
MAX6749
MAX6750
MAX6751
V
and V
(see Figure ±). RESET is asserted
MON_TH
when either of the voltages falls below it respective
threshold voltages.
CC
R2
GND
Manual Reset (MAX6746/MAX6747)
Many µP-based products require manual reset capabil-
ity, to allow an operator or external logic circuitry to initi-
ate a reset. The manual reset input (MR) can connect
directly to a switch without an external pullup resistor or
debouncing network. MR is internally pulled up to V
CC
and, therefore, can be left unconnected if unused.
Figure 3. Adding an External Manual Reset Function to the
MAX6748–MAX6751
MR is designed to reject fast, falling transients (typically
100ns pulses) and it must be held low for a minimum of
1µs to assert the reset output. A 0.1µF capacitor from
MR to ground provides additional noise immunity. After
MR transitions from low to high, reset remains asserted
for the duration of the reset timeout period.
where V
is the desired reset threshold voltage
MON_TH
and V is the reset input threshold (1.±35V). Resistors
TH
R1 and R± can have very high values to minimize cur-
rent consumption due to low leakage currents. Set R±
to some conveniently high value (500kΩ, for example)
and calculate R1 based on the desired reset threshold
voltage, using the following formula:
A manual reset option can easily be implemented
with the MAX6748–MAX6751 by connecting a normally
open momentary switch in parallel with R± (Figure 3).
When the switch is closed, the voltage on RESET IN
goes to zero, initiating a reset. Similar to the MAX6746/
MAX6747 manual reset, reset remains asserted while
the voltage at RESET IN is zero and for the reset time-
out period after the switch is opened.
R1 = R± x (V
/V
- 1) (Ω)
MON_TH RESET IN
The MAX6748 and MAX6749 do not monitor V
sup-
CC
ply voltage, therefore, V
must be greater than 1.5V to
CC
V
CC
t
t
RP
WD
WDI
OV
V
CC
RESET
OV
NORMAL MODE (WDS = GND)
Figure 4a. Watchdog Timing Diagram, WDS = GND
8
Maxim Integrated
MAX6746–MAX6753r
µP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
V
CC
t
t
x 128
RP
WD
WDI
OV
V
CC
RESET
OV
EXTENDED MODE (WDS = V
)
CC
Figure 4b. Watchdog Timing Diagram, WDS = V
CC
Watchdog Timer
Table 1. Min/Max Watchdog Setting
MAX6746–MAX6751
The watchdog’s circuit monitors the µP’s activity. It the
µP does not toggle the watchdog input (WDI) within
SET0
LOW
LOW
HIGH
HIGH
SET1
LOW
HIGH
LOW
HIGH
RATIO
8
16
t
(user-selected), RESET asserts for the reset time-
WD
out period. The internal watchdog timer is cleared by
any event that asserts RESET, by a falling transition at
WDI (which can detect pulses as short as 300ns) or by
a transition at WDS. The watchdog timer remains
cleared while reset is asserted; as soon as reset is
released, the timer starts counting.
Watchdog Disabled
64
where HIGH is V
and LOW is GND. Table 1 illus-
CC
trates the SET0 and SET1 configuration for the 8, 16,
and 64 window ratio ( t
/t
).
WD± WD1
The MAX6746–MAX6751 feature two modes of watch-
dog operation: normal mode and extended mode. In nor-
mal mode (Figure 4a), the watchdog timeout period is
determined by the value of the capacitor connected
between SWT and ground. In extended mode (Figure
4b), the watchdog timeout period is multiplied by 1±8.
For example, in extended mode, a 0.1µF capacitor gives
a watchdog timeout period of 65s (see the Extended-
For example, if C
is 1500pF, and SET0 and SET1 are
SWT
low, then t
is 975ms (typ) and t
is 1±±ms (typ).
WD±
WD1
RESET asserts if the watchdog input has two falling
edges too close to each other (faster than t ) (Figure
WD1
5a) or falling edges that are too far apart (slower than
) (Figure 5b). Normal watchdog operation is dis-
t
WD±
played in (Figure 5c). The internal watchdog timer is
cleared when a WDI falling edge is detected within the
valid watchdog window or when RESET is deasserted.
All WDI inputs are ignored while RESET is asserted.
Mode Watchdog Timeout Period vs. C
graph in the
SWT
Typical Operating Characteristics). To disable the watch-
dog timer function, connect SWT to ground.
The watchdog timer begins to count after RESET is
deasserted. The watchdog timer clears and begins to
count after a valid WDI falling logic input. WDI falling
MAX6752/MAX6753
The MAX675± and MAX6753 have a windowed watch-
dog timer that asserts RESET for the adjusted reset
timeout period when the watchdog recognizes a fast
transitions within periods shorter than t
or longer
WD1
than t
force RESET to assert low for the reset time-
WD±
watchdog fault (t
< t
), or a slow watchdog fault
WDI
WD1
out period. WDI falling transitions within the t
and
WD1
(period > t
). The reset timeout period is adjusted
independently of the watchdog timeout period.
WD±
t
window do not assert RESET. WDI transitions
WD±
between t
and t
or t
and
WD±(min)
WD1(min)
WD1(max)
The slow watchdog period, t is calculated as follows:
WD±
t
are not guaranteed to assert or deassert the
WD±(max)
t
= 0.65 x 109 x C
SWT
RESET. To guarantee that the window watchdog does
not assert the RESET, strobe WDI between t
WD±
WD1(max)
with t
in seconds and C
in Farads.
WD±
SWT
and t
. The watchdog timer is cleared when
WD±(min)
The fast watchdog period, t
, is selectable as a ratio
WD1
RESET is asserted or after a falling transition on WDI or
after a state change on SET0 or SET1. Disable the
watchdog timer by connecting SET0 high and SET1 low.
from the slow watchdog fault period (t
). Select the
WD±
fast watchdog period by pinstrapping SET0 and SET1,
Maxim Integrated
9
MAX6746–MAX6753
µP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
t
< t
(MIN)
5V
3.3V
WDI WD1
V
CC
MAX6747
MAX6749
MAX6451
MAX6753
100kΩ
WDI
RESET
V
CC
RESET
(a) FAST FAULT
μP
RESET
N
t
> t
(MAX)
WDI WD2
GND
GND
WDI
Figure 6. Interfacing to Other Voltage Levels
RESET
normal mode operation, calculate the watchdog time-
out capacitor as follows:
(b) SLOW FAULT
C
SWT
= t /(5.06 x 106)
WD
t
(MAX) < t < t
(MIN)
WD1
WDI WD2
with t in seconds and C
in Farads.
RP
SRT
For the MAX675± and MAX6753 windowed watchdog
function, calculate the slow watchdog period, t
follows:
as
WD±
WDI
t
= 0.65 x 109 x C
RESET
WD±
SWT
C
and C
must be a low-leakage (< 10nA) type
SRT
SWT
capacitor. Ceramic capacitors are recommended.
(c) NORMAL OPERATION (NO PULSING, OUTPUT STAYS HIGH)
Transient Immunity
In addition to issuing a reset to the µP during power-up,
power-down, and brownout conditions, these supervi-
sors are relatively immune to short-duration supply tran-
sients (glitches). The Maximum Transient Duration vs.
Reset Threshold Overdrive graph in the Typical
Operating Characteristics shows this relationship.
Figure 5. MAX675±/MAX6753 Window Watchdog Diagram
Applications Information
Selecting Reset/Watchdog
Timeout Capacitor
The reset timeout period is adjustable to accommodate
a variety of µP applications. Adjust the reset timeout
The area below the curves of the graph is the region
in which these devices typically do not generate a reset
pulse. This graph was generated using a falling pulse
period (t ) by connecting a capacitor (C
) between
RP
SRT
SRT and ground. Calculate the reset timeout capacitor
as folllows:
applied to V , starting above the actual reset threshold
CC
(V ) and ending below it by the magnitude indicated
TH
C
SRT
= t / (5.06 x 106)
RP
(reset-threshold overdrive). As the magnitude of the tran-
sient increases (farther below the reset threshold), the
maximum allowable pulse width decreases. Typically, a
with t in seconds and C
in Farads.
RP
SRT
The watchdog timeout period is adjustable to accom-
modate a variety of µP applications. With this feature,
the watchdog timeout can be optimized for software
execution. The programmer can determine how often
the watchdog timer should be serviced. Adjust the
V
transient that goes 100mV below the reset threshold
CC
and lasts 50µs or less does not cause a reset pulse to be
issued.
watchdog timeout period (t ) by connecting a specif-
WD
ic value capacitor (C
) between SWT and GND. For
SWT
10
Maxim Integrated
MAX6746–MAX6753r
µP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
Interfacing to Other Voltages for
Logic Compatibility
The open-drain RESET output can be used to interface
to a µP with other logic levels. As shown in Figure 6, the
open-drain output can be connected to voltages from 0
to 6V.
Ensuring a Valid RESET Down to V
= 0V
CC
(Push-Pull RESET)
When V falls below 1V, RESET current sinking capabil-
CC
ities decline drastically. The high-impedance CMOS-
logic inputs connected to RESET can drift to undeter-
mined voltages. This presents no problems in most
applications, since most µPs and other circuitry do not
Generally, the pullup resistor connected to the RESET
operate with V
below 1V.
connects to the supply voltage that is being monitored
CC
at the IC’s V
pin. However, some systems can use
CC
In those applications where RESET must be valid down
to 0V, add a pulldown resistor between RESET and
GND for the MAX6746/MAX6748/MAX6750/MAX675±
push/pull outputs. The resistor sinks any stray leakage
currents, holding RESET low (Figure 7). The value of the
pulldown resistor is not critical; 100kΩ is large enough
not to load RESET and small enough to pull RESET to
ground. The external pulldown can not be used with
the open-drain reset outputs.
the open-drain output to level-shift from the monitored
supply to reset circuitry powered by some other supply.
Keep in mind that as the supervisor’s V
decreases
CC
towards 1V, so does the IC’s ability to sink current at
RESET. Also, with any pullup resistor, RESET is pulled
high as V
decays toward zero. The voltage where
CC
this occurs depends on the pullup resistor value and
the voltage to which it is connected.
V
CC
V
CC
MAX6746
MAX6748
MAX6450
MAX6752
RESET
100kΩ
GND
Figure 7. Ensuring RESET Valid to V
= 0V
CC
Maxim Integrated
11
MAX6746–MAX6753
µP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
Table 2. Reset Threshold Voltage Suffix
(T = -40°C to +125°C)
Table 3. Standard Version Table
A
PART
TOP MARK
AEDI
MAX6746KA16
MAX6746KA±3
MAX6746KA±6
MAX6746KA±9
MAX6746KA46
MAX6747KA16
MAX6747KA±3
MAX6747KA±6
MAX6747KA±9
MAX6747KA46
MAX6748KA
SUFFIX
50
49
48
47
46
45
44
43
4±
41
40
39
38
37
36
35
34
33
3±
31
30
29
±8
±7
26
±5
±4
23
±±
±1
±0
19
18
17
16
MIN
TYP
MAX
5.100
4.998
4.896
4.794
4.718
4.590
4.463
4.386
4.±84
4.18±
4.080
3.978
3.876
3.774
3.67±
3.570
3.468
3.366
3.±64
3.137
3.060
2.984
±.856
±.754
2.678
±.550
±.448
2.359
±.±3±
±.14±
±.040
1.938
1.836
1.698
1.607
AEDJ
AEDK
AALN
AEDL
AALO
AEDM
AEDN
AEDO
AEDP
AALP
AALQ
AEDQ
AALR
AEDR
AEDS
AEDT
AEDU
AEDV
AEDW
AEDX
AEDY
AEDZ
AEEA
AALT
4.900
4.80±
4.704
4.606
4.533
4.410
4.±88
4.±14
4.116
4.018
3.9±0
3.8±±
3.7±4
3.6±6
3.5±8
3.430
3.33±
3.±34
3.136
3.014
±.940
2.867
±.744
±.646
2.573
±.450
±.35±
2.267
±.144
±.058
1.960
1.86±
1.764
1.63±
1.544
5.000
4.900
4.800
4.700
4.625
4.500
4.375
4.300
4.±00
4.100
4.000
3.900
3.800
3.700
3.600
3.500
3.400
3.300
3.±00
3.075
3.000
2.925
±.800
±.700
2.625
±.500
±.400
2.313
±.188
±.100
±.000
1.900
1.800
1.665
1.575
MAX6749KA
MAX6750KA16
MAX6750KA±3
MAX6750KA±6
MAX6750KA±9
MAX6750KA46
MAX6751KA16
MAX6751KA±3
MAX6751KA±6
MAX6751KA±9
MAX6751KA46
MAX675±KA16
MAX675±KA±3
MAX675±KA±6
MAX675±KA±9
MAX675±KA46
MAX6753KA16
MAX6753KA±3
MAX6753KA±6
MAX6753KA±9
MAX6753KA46
AEEB
AEEC
AEED
AEEE
AEEF
AEEG
AEEH
Note: Standard versions are shown in bold. There is a ±500-
piece minimum order increment for standard versions.
Sample stock is typically held on standard versions only.
Nonstandard versions require a minimum order increment of
10,000 pieces. Contact factory for availability.
1±
Maxim Integrated
MAX6746–MAX6753r
µP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
Selector Guide
FIXED V
RESET
THRESHOLD
ADJUSTABLE
RESET
THRESHOLD
STANDARD
WATCHDOG WATCHDOG
MIN/MAX
MANUAL
RESET
INPUT
CC
PUSH/ PULL OPEN-DRAIN
PART
RESET
RESET
TIMER
TIMER
MAX6746
MAX6747
MAX6748
MAX6749
MAX6750
MAX6751
MAX675±
MAX6753
X
X
—
—
X
X
X
—
—
—
—
—
—
X
X
—
X
—
X
X
X
—
—
X
X
—
X
—
—
—
—
—
—
X
X
—
X
X
X
—
X
X
X
X
—
X
X
—
—
—
—
—
X
X
X
—
Typical Operating Circuit
Pin Configurations (continued)
V
IN
TOP VIEW
MAX6749
MAX4751
V
CC
SET0
SWT
SRT
1
2
3
4
8
7
6
5
V
CC
R1
R2
RESET
WDI
MAX6752
MAX6753
RESET IN
V
CC
μP
MAX6748
MAX6749
MAX6750
MAX6751
GND
SET1
RESET
RESET
GND
SOT23
SRT
C
SRT
I/O
WDI
Chip Information
SWT
WDS
PROCESS: BiCMOS
C
SWT
WDS = 0 FOR NORMAL MODE
WDS = V FOR EXTENDED MODE
Package Information
CC
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
LAND
PATTERN NO.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
21-0078
90-0176
8 SOT±3
K8-5
Maxim Integrated
13
MAX6746–MAX6753
µP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
3
7/0±
Initial release
—
1
1±/05
Added the lead-free notation
Added the automotive version of the MAX6746 and the MAX6753 and
revised the Typical Operating Characteristics
4
9/10
1, 4
5
6
7
8
1±/10
4/11
Added the automotive version of the MAX6750
Added the automotive version of the MAX6747
Added the automotive version of the MAX6751
Added a future product reference to MAX6751KA_ _ /V+T
1
1
1
1
1±/13
±/14
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
14 _________________________________Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© ±014 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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