MAX6876ETX-T [MAXIM]
Power Supply Support Circuit, Fixed, 1 Channel, BICMOS, 6 X 6 MM, 0.80 MM HEIGHT, MO-220WJJD-1, TQFN-36;
| 型号： | MAX6876ETX-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Power Supply Support Circuit, Fixed, 1 Channel, BICMOS, 6 X 6 MM, 0.80 MM HEIGHT, MO-220WJJD-1, TQFN-36 信息通信管理 |
| 文件： | 总39页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3479; Rev 0; 10/04
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
General Description
Features
ꢀ Tracking/Sequencing for Up to Four Supply
The MAX6876 EEPROM-configurable, multivoltage
power tracker/supervisor monitors four system voltages
and ensures proper power-up and power-down condi-
tions for systems requiring voltage tracking and/or
sequencing. The MAX6876 provides a highly config-
urable solution as key thresholds and timing parame-
ters are programmed through an I2C* interface and
these values are stored in internal EEPROM. The
MAX6876 also provides supervisory functions and an
overcurrent detection circuit.
Voltages (With One MAX6876 Device) and
Tracking for Up to 16 Supply Voltages (Using
Four MAX6876 Devices)
ꢀ EEPROM-Configurable Tracking/Sequencing
Control
ꢀ Bus Voltage Independent Operation (MAX6876 Is
Powered from the Tracked Supply Voltages or
Always-On Supply)
The MAX6876 features programmable undervoltage and
overvoltage thresholds for each input supply. When all
voltages are within specifications, the device turns on the
external n-channel MOSFETs to either sequence or track
the voltages to the system. All of the voltages can be
sequenced or tracked or powered up with a combination
of the two options. During tracking, the voltage at the
GATE of each MOSFET is increased to slowly turn on
each supply. The voltages at the source of each MOSFET
are compared to each other to ensure that the voltage dif-
ferential between each monitored supply does not
exceed 250mV (typ). Tracking is dynamically adjusted to
force all outputs to track within a ±±25mV window from a
reference ramp; if, for any reason, any supply fails to
track within ±250mV from the reference ramp, a FAULT
output is asserted, the power-up mode is terminated, and
all outputs are powered off. Power-up mode is also termi-
nated if the controlled voltages fail to complete the ramp-
up within a programmable FAULT timeout. The MAX6876
features latch-off and autoretry modes to power on again
after a fault condition has been detected.
ꢀ EEPROM-Selectable Undervoltage/Overvoltage-
Lockout Thresholds for Each Input Supply
ꢀ EEPROM-Selectable Power-Up/Down Slew Rate
ꢀ Programmable Power-Good Output Thresholds
and Timing
ꢀ Global Adjustable Undervoltage Lockout or Logic
ENABLE Input
ꢀ Independent Internal Charge Pumps to Enhance
External n-Channel FETs (V
= 5V)
GATE_SOURCE
ꢀ Post Power-Up Selectable Overcurrent Detection
ꢀ 0.5V to 5.5V IN_ Threshold Range
ꢀ
1.5ꢀ Threshold Accuracy
ꢀ I2C/SMBus™-Compatible Serial Interface
ꢀ Small 6mm x 6mm, 36-Pin Thin QFN Package
Ordering Information
PIN-
PACKAGE
PKG
CODE
PART
TEMP RANGE
Other features of the MAX6876 include a reset circuit, a
manual reset input (MR), and a margin disable input
(MARGIN). The device also features outputs for indicat-
ing a power-good condition (PG_) and an overcurrent
condition (OC), and a bus-removal (REM) output.
MAX6876ETX
-40°C to +85°C
36 Thin QFN
T3666-3
Pin Configuration
The MAX6876 is available in a small 6mm x 6mm, 36-
pin thin QFN package and is fully specified over the
extended -40°C to +85°C temperature range.
TOP VIEW
36 35 34 33 32 31 30 29 28
V
1
2
3
4
5
6
7
8
9
27 IN4
Applications
CC
GND
ABP
26 GATE4
25 OUT4
24 REFIN
23 N.C.
22 PG4
21 PG3
Multivoltage Systems
Networking Systems
Telecom
Storage Equipment
TRKEN
SYNCH
HOLD
OC
Servers/Workstations
MAX6876
PG2
REM
20
EP*
*Purchase of I2C components from Maxim Integrated Products,
Inc., or one of its sublicensed Associated Companies, conveys
a license under the Philips I2C Patent Rights to use these com-
ponents in an I2C system, provided that the system conforms
to the I2C Standard Specification as defined by Philips.
FAULT
19 PG1
10 11 12 13 14 15 16 17 18
6mm x 6mm
THIN QFN
*EXPOSED PADDLE
SMBus is a trademark of Intel Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
ABSOLUTE MAXIMUM RATINGS
(All voltages are referenced to GND, unless otherwise noted.)
GATE_.............................................................-0.3V to (IN_ + 6V)
OUT_, GND Current..........................................................±50mA
Continuous Power Dissipation (T = +70°C)
A
IN1–IN4, V ............................................................-0.3V to +6V
36-Pin, 6mm x 6mm Thin QFN
CC
OUT1–OUT4, SYNCH, ABP,
REFIN...............................-0.3V to Max (IN1–IN4, V
(derate ±6.3mW/°C above +70°C)..............................±105mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
) + 0.3V
CC
ENABLE, TRKEN, HOLD, FAULT, MR, MARGIN......-0.3V to +6V
RESET, PG1–PG4, OC, REM....................................-0.3V to +6V
SDA, SCL, A0, A1.....................................................-0.3V to +6V
Input/Output Current (all pins except OUT_ and GND) ...±±0mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V , IN1–IN4 = +±.7V to +5.5V; ENABLE = MARGIN = MR = ABP = TRKEN; T = -40°C to +85°C, unless otherwise specified.
CC
A
Typical values are at T = +±5°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
5.5
UNITS
GATE_ = PG_ = RESET = 0
1.4
Operating Voltage Range
(Note ±)
V
V
CC
Voltage on ABP (from V
or IN1–IN4) to
CC
±.7
ensure the device is fully operational
Minimum voltage on ABP (from V or
CC
Undervoltage Lockout
V
IN1–IN4) to ensure the device is EEPROM
±.5
V
UVLO
configured
V
= 5.5V, IN1–IN4 = 3.3V, no load
1.8
±.5
3
4
CC
Supply Current
I
mA
V
CC
Configuration registers or memory access,
no load
IN1–IN4 (in ±0mV increments)
IN1–IN4 (in 10mV increments)
1.00
0.50
5.50
3.05
IN_ Threshold Range
V
TH
0.5V < IN_ < 5.5V, IN_
T
= 0°C to +85°C
-1.5
-±.5
-50
+1.5
+±.5
+50
%
falling for UV, rising for
OV
A
±V < IN_ < 5.5V, IN_
falling for UV, rising for
OV (±0mV increments)
%
mV
%
1V < IN_ < ±V, IN_
falling for UV, rising for
OV (±0mV increments)
Threshold Accuracy
T
A
= -40°C to
+85°C
1V < IN_ < 3.05V, IN_
falling for UV, rising for
OV (10mV increments)
-±.5
+±.5
0.5V < IN_ < 1V, IN_
falling for UV, rising for
OV (10mV increments)
mV
-±5
+±5
Threshold Hysteresis
V
0.5
50
%V
TH
TH_HYS
RESET Threshold Tempco
∆V
ppm/°C
TH/C
2
_______________________________________________________________________________________
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
ELECTRICAL CHARACTERISTICS (continued)
(V , IN1–IN4 = +±.7V to +5.5V; ENABLE = MARGIN = MR = ABP = TRKEN; T = -40°C to +85°C, unless otherwise specified.
CC
A
Typical values are at T = +±5°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Tracking-Differential-Voltage Hold
Ramp (Note 3)
V
V
> V
< V
OUT_
OUT_
TH_PL
V
95
1±5
155
mV
TRK
TH_PG
Tracking-Differential-Voltage
Hysteresis
±5
mV
mV
Tracking-Differential FAULT
Voltage (Note 3)
V
V
> V
< V
OUT_
OUT_
TH_PL
TH_PG
V
±00
±50
300
TRK_F
00
01
10
11
±0
40
±5
50
30
60
Register
contents
(Table 16)
t
,
FAULTUP
FAULT Timeout Period (Note 4)
ms
t
FAULTDOWN
80
100
±00
±
1±0
±40
160
FAULT to GATE Delay
IN1–IN4 Input Impedance
OUT1–OUT4 Input Impedance
Power-On Delay
t
µs
kΩ
kΩ
ms
µs
FG
R
For IN_ voltages < the highest IN_ supply
OUT_ pulldown disabled
55
70
90
145
130
3
IN1-4
R
100
OUT1-4
t
V
≥ V
ABP UVLO
PO
D-GATE
IN_ to GATE_ Delay
t
IN_ falling/rising, 100mV overdrive
6
OUT_ rising, 100mV overdrive
3
ms
µs
OUT_ to PG_ Delay
t
POK
OUT_ falling, 100mV overdrive
±5
000
001
010
±5
µs
10
±0
1±.5
±5
15
30
t
t
Register
contents
(Table 16)
RESET,
011
40
50
60
GATE, RESET, Autoretry Timeout
Period (Notes 5, 6)
AUTO,
100
80
100
±00
400
1600
1±.5
50
1±0
±40
480
19±0
15
ms
ms
t
GATE
101
110
111
00
160
3±0
1±80
10
Register
contents
(Table 16)
01
40
60
OC Timeout Period
t
OC
10
80
100
±00
800
800
400
400
±00
±00
100
100
97.5
95
1±0
±40
1040
11±0
5±0
560
±60
±80
130
140
98.75
96.±5
93.75
91.±5
11
160
560
480
±80
±40
140
1±0
70
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
= 0°C to +85°C
= -40°C to 0°C
= 0°C to +85°C
= -40°C to 0°C
= 0°C to +85°C
= -40°C to 0°C
= 0°C to +85°C
= -40°C to 0°C
00
01
10
11
Register
contents
(Table 16)
Track/Sequence Slew Rate Rising
or Falling
TRK
V/s
SLEW
60
00
01
10
11
96.±5
93.75
91.±5
88.75
Register
contents
(Table 16),
OUT_ falling
IN_ to OUT_ Overcurrent
Threshold
V
%
TH_OC
9±.5
90
_______________________________________________________________________________________
3
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
ELECTRICAL CHARACTERISTICS (continued)
(V , IN1–IN4 = +±.7V to +5.5V; ENABLE = MARGIN = MR = ABP = TRKEN; T = -40°C to +85°C, unless otherwise specified.
CC
A
Typical values are at T = +±5°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
95
MAX
96.±5
93.75
91.±5
88.75
UNITS
00
01
10
11
93.75
91.±5
88.75
86.±5
Register
contents
(Table 16),
OUT_ rising
9±.5
90
IN_ to OUT_ Power-Good
Threshold
V
%
TH_PG
87.5
0.5
14±
10
V
V
Hysteresis
V
%
TH_PG and TH_OC
OUT_HYS
Power Low Threshold
Power Low Hysteresis
V
OUT_ falling
1±5
165
mV
mV
TH_PL
TH_PL_HYS
V
OUT_ to GND Pulldown
Impedance (When Enabled)
ABP ≥ ±.5V
100
Ω
ABP ≥ ±.5V, I
ABP ≥ 4.0V, I
= 4mA
0.3
0.4
SINK
SINK
SINK
REM Output Low
V
V
OL_REM
= 15mA
ABP ≥ 1.4V, I
only)
= 50µA (PG_, RESET
0.3
Output Low PG1–PG4, HOLD,
FAULT, OC, RESET (Note ±)
V
V
V
OL
ABP ≥ ±.5V, I
ABP ≥ 4.0V, I
ABP ≥ 1.4V, I
ABP ≥ ±.5V, I
ABP ≥ 4.0V, I
= 1mA
= 4mA
= 50µA
= 1mA
= 4mA
0.3
0.4
0.3
0.3
0.8
SINK
SINK
SINK
GATE1–GATE4 Output Low
V
GOL
SINK
SINK
PG1–PG4, HOLD, FAULT, OC ,
RESET, REM Output Open-Drain
Leakage Current
I
Output deasserted
-1
+1
µA
V
LKG
IN_ +
4.4
IN_ +
5.8
GATE_ Output-Voltage High
V
I
= 0.5µA
IN_ + 5
GOH
GATE_
GATE_ Pullup Current
I
During power-up/down, V
During power-up/down, V
= 1V
= 4V
±.5
±.5
4.5
4.5
µA
µA
GATEUP
GATE_
GATE_ Pulldown Current
I
GATEDOWN
GATE_
0.3 x
ABP
V
IL
MARGIN, FAULT, HOLD, MR,
ENABLE Input Voltage
V
0.6 x
ABP
V
IH
MR Input Pulse Width
t
±
µs
ns
MR
FAULT, HOLD, MARGIN, MR,
ENABLE Glitch Rejection
100
Digital Input to Logic Delay,
FAULT, HOLD, MARGIN, MR,
ENABLE
t
D
1
µs
MARGIN, MR Digital Input to ABP
Pullup Resistance
R
P
70
100
130
kΩ
4
_______________________________________________________________________________________
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
ELECTRICAL CHARACTERISTICS (continued)
(V , IN1–IN4 = +±.7V to +5.5V; ENABLE = MARGIN = MR = ABP = TRKEN; T = -40°C to +85°C, unless otherwise specified.
CC
A
Typical values are at T = +±5°C.) (Note 1)
A
PARAMETER
TRKEN Input Delay
SYMBOL
CONDITIONS
TRKEN falling, 100mV overdrive
Input rising
MIN
TYP
±
MAX
UNITS
t
µs
EN
1.±45
1.±±5
-100
1.±85
1.±5
1.3±0
1.±75
+100
1.±75
TRKEN Reference Voltage Range
V
V
TRKEN
Input falling
TRKEN Input Current
I
V
= 1.±5V
nA
V
TRKEN
TRKEN
REFIN
Reference Input Voltage Range
Reference Input Resistance
V
R
1.±±5
1.±5
500
REFIN
V
= 1.±5V
kΩ
REFIN
SERIAL INTERFACE LOGIC (SDA, SCL, A0, A1)
0.3 x
ABP
Logic-Input Low Voltage
Logic-Input High Voltage
V
V
V
IL
0.6 x
ABP
V
IH
Input Leakage Current
Output-Voltage Low
I
1
0.4
1
µA
V
ILKG
V
I
= 3mA
OL
SINK
Output Leakage Current
Input/Output Capacitance
I
µA
pF
OLKG
C
10
I/O
SERIAL INTERFACE TIMING (SDA, SCL)
Serial Clock Frequency
Clock Low Period
Clock High Period
Bus Free Time
f
400
kHz
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
SCL
t
1.3
0.6
1.3
0.6
0.6
0.6
0.1
50
LOW
t
HIGH
t
BUF
START Setup Time
START Hold Time
STOP Setup Time
Clock Low to Valid Output
Data Out Hold Time
Data In Setup Time
Data In Hold Time
SCL/SDA Rise Time
SCL/SDA Fall Time
t
SU:STA
HD:STA
SU:STO
t
t
t
0.9
AA
DH
t
t
100
0
SU:DAT
HD:DAT
t
t
300
300
R
t
F
F
±0 +
0.1 x
Transmit SDA Fall Time
t
C
= 400pF
300
ns
BUS
C
BUS
SCL/SDA Noise Suppression Time
Byte Write Cycle Time
t
50
ns
I
t
11
ms
WR
Note 1: Specifications guaranteed for the stated global conditions. 100% production tested at T = +±5°C and T = +85°C.
A
A
Specifications at T = -40°C are guaranteed by design.
A
Note 2: The internal supply voltage, measurable on ABP, is equal to the maximum of IN1–IN4 and V
supplies.
CC
Note 3: Differential between each of the OUT_ and the SYNCH ramp voltage during power-up/down measured as V
- ± x
OUT_
V
.
SYNCH
Note 4: FAULT timeout starts to count at the beginning of each sequence of power-up/down and clears when the programmed
OUT_ voltages track successfully.
_______________________________________________________________________________________
5
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
ELECTRICAL CHARACTERISTICS (continued)
(V , IN1–IN4 = +±.7V to +5.5V; ENABLE = MARGIN = MR = ABP = TRKEN; T = -40°C to +85°C, unless otherwise specified.
CC
A
Typical values are at T = +±5°C.) (Note 1)
A
Note 5: The MAX6876 programmed as a single device; GATE timeout has counted prior to beginning each sequence of power-up.
GATE timeout is not enabled during power-down or when the device is programmed as a master/slave.
Note 6: The MAX6876 programmed as a single device, the autoretry time begins to count at the assertion of the FAULT signal.
The MAX6876 programmed as a master/slave device; the autoretry time begins to count at the deassertion of the
common FAULT signal.
Timing Diagrams
V
V
TRKEN
TRKEN
BUS VOLTAGE MONITORED THROUGH TRKEN INPUT
GND
GND
GND
IN1 = 3.3V
IN2 = 2.5V
IN3 = 1.8V
IN4 = 1.5V
MONITORED THROUGH SET THRESHOLDS ON IN_
INPUTS (EEPROM-SELECTABLE)
OUT1 = 3.3V
EEPROM-
ADJUSTED
SLEW RATE
OUT2 = 2.5V
OUT3 = 1.8V
OUT4 = 1.5V
t
GATE
>t
FAULTDOWN
<t
FAULTUP
RESET
t
RESET
GND
FAULT
GND
Figure 1. Tracking Timing Diagram
6
_______________________________________________________________________________________
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Timing Diagrams (continued)
V
V
TRKEN
BUS VOLTAGE MONITORED THROUGH TRKEN INPUT
TRKEN
GND
IN1 = 3.3V
IN2 = 2.5V
IN3 = 1.8V
IN4 = 1.5V
MONITORED THROUGH SET THRESHOLDS ON IN_ INPUTS
(EEPROM-SELECTABLE)
GND
EEPROM-
ADJUSTED
SLEW RATE
OUT1 = 3.3V
OUT2 = 2.5V
OUT3 = 1.8V
OUT4 = 1.5V
t
t
t
t
GATE
GATE
GATE
GATE
GND
GND
t
RESET
RESET
Figure 2. Sequencing Timing Diagram
_______________________________________________________________________________________
7
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Timing Diagrams (continued)
V
V
TRKEN
TRKEN
BUS VOLTAGE MONITORED THROUGH TRKEN INPUT
GND
IN1 = 2.5V
IN2 = 1.8V
IN3 = 0.9V
IN4 = 0.7V
MONITORED THROUGH SET THRESHOLDS ON IN_ INPUTS
(EEPROM-SELECTABLE)
GND
EEPROM-
SELECTED
SLEW RATE
OUT1 = 2.5V
EEPROM-
SELECTED
SLEW RATE
(FORCED INTO
QUICK SHUTDOWN
WHEN IN1 FAILS)
OUT2 = 1.8V
OUT3 = 0.9V
OUT4 = 0.7V
GND
GND
GATE
t
RESET
RESET
Figure 3. Voltage Tracking with Forced Shutdown (IN1 UV Failure)
FULL TRK
FULL SEQ
ENABLE
SYNCH
MIX WITH 3 RAMP
(FAST SHUTDOWN BIT SET)
OUT1 = 4V
OUT2 = 3V
OUT3 = 2V
OUT4 = 1V
MIX WITH 2 RAMP
Figure 5. Mixed-Mode Tracking/Sequencing Examples
Figure 4. Sequencing Ramp Down Diagram
8
_______________________________________________________________________________________
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Typical Operating Characteristics
(V
= 3.3V, ENABLE = MARGIN = MR = ABP = TRKEN, T = +±5°C, unless otherwise noted.)
CC
A
NORMALIZED TIMEOUT PERIOD
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED IN_ THRESHOLD
vs. TEMPERATURE
vs. TEMPERATURE
2.00
1.90
1.015
1.100
1.050
1.000
0.950
0.900
1.010
1.005
1.000
0.995
0.990
0.985
0.980
0.975
1.80
1.70
1.60
1.50
1.40
1.30
1.20
1.10
1.00
0.90
2.7
3.4
4.1
4.8
5.5
-40
-15
10
35
60
85
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
MAXIMUM IN_ TRANSIENT DURATION
vs. IN_ THRESHOLD OVERDRIVE
GATE OUTPUT-VOLTAGE LOW
vs. SINK CURRENT
NORMALIZED PG AND OC THRESHOLD
vs. TEMPERATURE
130
120
110
100
90
80
70
60
50
40
30
20
10
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.010
1.005
1.000
0.995
0.990
0.985
0
1
10
100
1000
0
3
6
9
12 15 18 21 24 27 30 33
(mA)
-40
-15
10
35
60
85
IN_ THRESHOLD OVERDRIVE (mV)
I
SINK
TEMPERATURE (°C)
TRACKING MODE WITH
FAST SHUTDOWN
SEQUENCING MODE
TRACKING MODE
MAX6876 toc08
MAX6876 toc09
MAX6876 toc07
OUT4
OUT4
OUT3
OUT4
OUT3
OUT3
OUT2
OUT_
1V/div
OUT_
1V/div
OUT_
1V/div
OUT2
OUT1
OUT2
OUT1
OUT1
0V
0V
0V
20ms/div
10ms/div
10ms/div
_______________________________________________________________________________________
9
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Typical Operating Characteristics (continued)
(V
= 3.3V, ENABLE = MARGIN = MR = ABP = TRKEN, T = +±5°C, unless otherwise noted.)
A
CC
MIXED MODE
MIXED MODE WITH FAST SHUTDOWN
MAX6876 toc10
MAX6876 toc11
OUT4
OUT4
OUT3
OUT2
OUT1
OUT3
OUT2
OUT_
1V/div
OUT_
1V/div
OUT1
0V
0V
20ms/div
20ms/div
Pin Description
PIN
NAME
FUNCTION
Optional Supply Voltage Input. Connect V
to an alternate (i.e., always-on) supply if desired. V
CC
CC
supports operation/communication when the monitored supplies are not powered or are below the
minimum required operating voltage. In a master/slave application, connect all V pins to a common
CC
1
V
CC
supply line.
±
3
GND
ABP
Ground
Internal Analog Bypass. Bypass ABP with a 1µF capacitor to GND. ABP maintains the device supply
voltage during rapid power-down conditions.
Tracking Enable Input. TRKEN must be higher than 1.±85V to enable voltage tracking power-up
operation. When TRKEN falls below 1.±5V (3% hysteresis), OUT_ tracks down. Connect TRKEN to an
external resistor-divider network to set the desired monitor threshold. Connect TRKEN to ABP if not
used.
4
5
TRKEN
SYNCH
Selectable Tracking Synchronization Output/Input. SYNCH allows multiple MAX6876 devices to
±
control tracking of multiple power supplies (up to 16 voltages on the same I C bus). One device is
programmed as SYNCH master and all other devices are programmed as slaves. SYNCH on the
master outputs the common ramp voltage to which all OUT_ voltages are tracked (with active control
loops). SYNCH of the slave devices is input for the ramp control voltage (no internal ramp is
generated in the slaves) (see the SYNCH section). Connect SYNCH to other SYNCH pins only.
Active-Low, Open-Drain Synchronization Hold Output/Input. HOLD communicates synchronization
status between master/slave devices in multiple MAX6876 applications. The HOLD output remains
asserted while selected tracking IN_ inputs are below their selected thresholds (the slave device can
delay tracking start until its inputs are at their required stable voltage levels) or held low by the master
when it is counting the autoretry time after a detected fault condition (see the Synchronization Hold
Output (HOLD) section). Slave device SYNCH are inputs for the ramp control voltage.
6
HOLD
10 ______________________________________________________________________________________
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Pin Description (continued)
PIN
NAME
FUNCTION
Active-Low, Open-Drain Overcurrent Output. OC asserts low if any monitored IN_ to OUT_ voltage
falls out of the selected percentage of the IN_ voltage range (V
) for more than the programmed
TH_OC
7
OC
t
OC monitoring begins only after supply tracking or sequencing has been completed and is
OC.
disabled during power-down operation.
Open-Drain Bus Removal Output. REM signals when it is safe to remove the card after a controlled
track/sequence-down operation. REM goes high impedance when all V < V . REM requires
OUT_
TH_PL
8
9
REM
an external pullup resistor. In master/slave mode, REM can be ORed together (the common REM
connection remains low if any V > V threshold) (see the Typical Application Circuit and the
Bus Removal Output (REM) section).
OUT_
TH_PL
Active-Low, Open-Drain Tracking Fault Alert Output or Input. FAULT asserts low if a tracking failure is
present for longer than the specified fault period or if tracking voltages fails by more than ±±50mV
(see the FAULT section).
FAULT
Active-Low, Open-Drain Reset or Power-Good Output. RESET is low during power-up and power-
down tracking. RESET goes high after all selected OUT_ outputs exceed their selected thresholds
10
11
RESET
and the reset timeout period t
has expired. The reset timeout period is internally selectable.
RESET
RESET requires an external pullup resistor.
Logic ENABLE Input. ENABLE must be high to enable voltage tracking/sequencing power-up
operation. OUT_ begins tracking down when ENABLE is low. Connect to ABP if not used.
ENABLE
Active-Low Margin Input. The MARGIN function allows systems to be tested with supply voltages
outside their normal ranges without affecting supply tracking/sequencing or reset states. MARGIN
functionality is usually enabled after systems have powered up in normal mode. The MARGIN
functionality is disabled (returns to normal monitoring mode) after MARGIN returns high. MARGIN is
internally pulled up to ABP through a 100kΩ resistor.
1±
MARGIN
13, ±3
14
N.C.
No Connection. Not internally connected.
Active-Low Manual Reset Input. When MR is low, RESET goes low and remains asserted for the
selected timeout period after MR is pulled high. MR is internally pulled up to ABP through a 100kΩ
resistor.
MR
15
16
17
18
19
SDA
SCL
A0
Serial-Interface Data Input/Output (Open-Drain). SDA requires an external pullup resistor.
Serial-Interface Clock Input. SCL requires an external pullup resistor.
Serial-Interface Address Inputs. The inputs allow up to four MAX6876 devices to be addressed when
sharing a common data bus. A1 and A0 should be connected to GND or ABP.
A1
PG1
Power-Good Output, Open-Drain. Each PG_ output signals when its monitored OUT_ voltage is within
±0
±1
±±
PG±
PG3
PG4
the selected percentage of the IN_ voltage range (V
). PG_ is low until OUT_ exceeds the
. PG_ outputs are open-drain and require
TH_PG
programmable threshold (V
external pullups if used.
) for more than t
TH_PG
POK
______________________________________________________________________________________ 11
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Pin Description (continued)
PIN
NAME
FUNCTION
Reference Voltage Input. The MAX6876 can be configured to use the internal 1.±5V reference or an
external voltage reference. REFIN is tri-stated when using the internal reference. REFIN provides the
threshold voltage for the voltage detectors when using an external voltage reference. Use an external
voltage reference when tighter voltage-detector accuracy is desired. When configured to an internal
reference, leave REFIN unconnected. When configured for an external reference, connect a 1.±±5V to
1.±75V reference to REFIN.
±4
REFIN
Monitored Output Voltage. The OUT4 output is monitored to control the supply slew rate and tracking
performance. OUT1–OUT4 begin to track up after the internal supply (ABP) exceeds the minimum
voltage requirements, V
> 1.±85V threshold, ENABLE is logic high, and IN1–IN4 are all within
TRKEN
±5
±6
OUT4
their selected thresholds. The OUT4 output falls out of the tracking equation as OUT4 approaches
IN4; other OUT_ supplies continue tracking up without signaling a system fault. OUT_ outputs are
tracked down during power-off conditions.
Gate Drive for External n-Channel FETs. GATE4 begins enhancing the external n-channel FETs when
all monitored inputs are within their selected thresholds (0.5V to 5.5V), at least one IN_ input or V
above the minimum operating voltage, V
high. During power-up mode, GATE_ voltages are enhanced with internal control loops forcing all
OUT_ voltages to track the reference ramp (SYNCH) at a programmed slew rate. An internal charge
is
CC
> 1.±85V threshold, and the ENABLE input is logic
TRKEN
GATE4
pump boosts GATE4 to V
complete.
+ 5V to fully enhance the external n-channel FET when power-up is
IN4
Supply Voltage and Tracked Input Voltage. Nominal supply range is 0.5V to 5V. IN1, IN±, IN3, IN4, or
must be greater than the internal UVLO (V = ±.7V) to enable the tracking functionality. The
IN4 input is monitored with internally selected thresholds to ensure all supplies have stabilized before
tracking (or sequencing) is enabled.
V
CC
ABP
±7
±8
IN4
Monitored Output Voltage. OUT3 is monitored to control the supply slew rate and tracking
performance. OUT1–OUT4 begin to track up after the internal supply (ABP) exceeds the minimum
voltage requirements, V
> 1.±85V threshold, ENABLE is logic high, and IN1–IN4 are all within
TRKEN
OUT3
their selected thresholds. The OUT3 output falls out of the tracking equation as OUT3 approaches
IN3; other OUT_ supplies continue tracking up without signaling a system fault. OUT_ outputs are
tracked down during power-off conditions.
Gate Drive for External n-Channel FETs. GATE3 begins enhancing the external n-channel FETs when
all monitored inputs are within their selected thresholds (0.5V to 5.5V), at least one IN_ input or V
is
CC
above the minimum operating voltage, V
> 1.±85V threshold, and the ENABLE input is logic
TRKEN
±9
GATE3
high. During power-up mode, GATE_ voltages are enhanced with internal control loops forcing all
OUT_ voltages to track the reference ramp (SYNCH) at a programmed slew rate. An internal charge
pump boosts GATE3 to V
complete.
+ 5V to fully enhance the external n-channel FET when power-up is
IN3
Supply Voltage and Tracked Input Voltage. Nominal supply range is 0.5V to 5V. IN1, IN±, IN3, IN4, or
must be greater than the internal UVLO (V = ±.7V) to enable the tracking functionality. IN3 is
monitored with internally selected thresholds to ensure all supplies have stabilized before tracking (or
sequencing) is enabled.
V
CC
ABP
30
31
IN3
Monitored Output Voltage. OUT± is monitored to control the supply slew rate and tracking
performance. OUT1–OUT4 begin to track up after the internal supply (ABP) exceeds the minimum
voltage requirements, V
> 1.±85V threshold, ENABLE is logic high, and IN1–IN4 are all within
TRKEN
OUT±
their selected thresholds. OUT± output falls out of the tracking equation as OUT± approaches IN±;
other OUT_ supplies continue tracking up without signaling a system fault. OUT_ outputs are tracked
down during power-off conditions.
12 ______________________________________________________________________________________
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Pin Description (continued)
PIN
NAME
FUNCTION
Gate Drive for External n-Channel FETs. GATE± begins enhancing the external n-channel FETs when
all monitored inputs are within their selected thresholds (0.5V to 5.5V), at least one IN_ input or V
is
CC
above the minimum operating voltage, V
> 1.±85V threshold, and the ENABLE input is logic
TRKEN
3±
GATE±
high. During power-up mode, GATE_ voltages are enhanced with internal control loops forcing all
OUT_ voltages to track the reference ramp (SYNCH) at a programmed slew rate. An internal charge
pump boosts GATE± to V
complete.
+ 5V to fully enhance the external n-channel FET when power-up is
IN±
Supply Voltage and Tracked Input Voltage. Nominal supply range is 0.5V to 5V. IN1, IN±, IN3, IN4, or
must be greater than the internal UVLO (V = ±.7V) to enable the tracking functionality. IN± is
monitored with internally selected thresholds to ensure all supplies have stabilized before tracking (or
sequencing) is enabled.
V
CC
ABP
33
34
IN±
Monitored Output Voltage. Each OUT1 is monitored to control the supply slew rate and tracking
performance. OUT1–OUT4 begin to track up after the internal supply (ABP) exceeds the minimum
voltage requirements, V
> 1.±85V threshold, ENABLE is logic high, and IN1–IN4 are all within
TRKEN
OUT1
their selected thresholds. The OUT1 output falls out of the tracking equation as OUT1 approaches
IN1; other OUT_ supplies continue tracking up without signaling a system fault. OUT_ outputs are
tracked down during power-off conditions.
Gate Drive for External n-Channel FETs. GATE1 begins enhancing the external n-channel FETs when
all monitored inputs are within their selected thresholds (0.5V to 5.5V), at least one IN_ input or V
is
CC
above the minimum operating voltage, V
> 1.±85V threshold, and the ENABLE input is logic
TRKEN
35
GATE1
high. During power-up mode, GATE_ voltages are enhanced with internal control loops forcing all
OUT_ voltages to track the reference ramp (SYNCH) at a programmed slew rate. An internal charge
pump boosts GATE1 to V
complete.
+ 5V to fully enhance the external n-channel FET when power-up is
IN1
Supply Voltage and Tracked Input Voltage. Nominal supply range is 0.5V to 5V. IN1, IN±, IN3, IN4, or
must be greater than the internal UVLO (V = ±.7V) to enable the tracking functionality. IN1 is
monitored with internally selected thresholds to ensure all supplies have stabilized before tracking (or
sequencing) is enabled.
V
CC
ABP
36
IN1
EP
—
Exposed Paddle. Exposed paddle is internally connected to GND.
The MAX6876 features programmable undervoltage
and overvoltage thresholds for each input supply. The
Detailed Description
The MAX6876 EEPROM-configurable, multivoltage
power tracker/supervisor monitors four system voltages
and ensures proper power-up and power-down condi-
tions for systems requiring voltage tracking and/or
sequencing. The MAX6876 provides a highly config-
urable solution as key thresholds and timing parame-
ters are programmed through an I±C interface and
these values are stored in internal EEPROM. In addition
to tracking and sequencing voltages, the MAX6876
also provides supervisory functions as well as an over-
current detection circuit.
thresholds are EEPROM configured in 10mV (0.5V to
3.05V) or ±0mV (1.0V to 5.5V) increments. When all of
the voltages are within their specifications, the device
turns on the external n-channel MOSFETs to either
sequence or track the voltages to the system. All of the
voltages can be sequenced or tracked or powered up
with a combination of the two options. During voltage
tracking, the voltage at the GATE of each MOSFET is
increased to slowly turn on each OUT_. The GATE
delay is EEPROM-selectable from ±5µs to 1.6s. The
______________________________________________________________________________________ 13
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Functional Diagram
IN1
IN2
IN3
IN4
ABP
V
CC
ABP
GATE1 OUT1
V
= V + 5V
IN1
CP1
INTERNAL
SUPPLY/UVLO
MAX6876
CHARGE
PUMP
IN1
PG1
OVER-
CURRENT
DETECT
UV/OV
IN1
IN1
COMP
COMP
COMP
RAMP
GENERATOR
V
THPG
COMP
IN2
UV/OV
ABP
CONTROL
LOGIC
IN3
UV/OV
GND
GATE2
PG2
OUT2
RAMP
IN2 TO OUT2
CONTROL BLOCK
OUT1
IN4
OUT2
OUT3
OUT4
IN1
IN2
IN3
COMP
1.25V
UV/OV
GATE3
PG3
OUT3
IN3 TO OUT3
CONTROL BLOCK
TRACKING
MONITORS
EEPROM/
CONFIGURATION
REGISTERS
GATE4
PG4
OUT4
REF
IN4 TO OUT4
CONTROL BLOCK
IN4
voltages at the sources of the MOSFETs are compared
to each other to ensure that the voltage differential
between each monitored supply does not exceed
±50mV (typ). Tracking is dynamically adjusted to force
all outputs to track within a ±1±5mV window from a ref-
erence ramp; if, for any reason, any supply fails to track
within ±±50mV from the reference ramp, the FAULT
output is asserted, the power-up mode is terminated,
and all outputs are powered off. Power-up mode is in
the same way terminated if the controlled voltages fail
to complete the ramp up within a programmable FAULT
timeout. The MAX6876 generates all required voltages
(with internal charge pumps) and timing to control up to
four external n-channel MOSFETs for the OUT1–OUT4
supply voltages.
A synchronization feature allows up to 16 voltages to
be tracked simultaneously. In addition, HOLD and
SYNCH communicate synchronization status between
master/slave devices in multiple MAX6876 applications.
Other features of the MAX6876 include a reset circuit
with an I±C-programmable timeout feature. A manual
reset input (MR) and a margin disable input (MARGIN)
allow for more control during the manufacturing process.
The device also features four power-good outputs (PG_),
an overcurrent output (OC), and a bus-removal safe
(REM) output. The device has an accurate internal 1.±5V
reference; for greater accuracy, connect an external
+1.±5V reference to REFIN.
14 ______________________________________________________________________________________
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Table 1. Master/Slave Settings
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
If “00,” the device configuration is a single device.
If “01,” the device configuration is multiple devices, slave.
If “10,” the device configuration is multiple devices, slave.
If “11,” the device configuration is multiple devices, master.
09h
±9h
[7:6]
Modes of Operation
RAMP 1
RAMP 2
RAMP 3
RAMP 4
The MAX6876 provides three different modes of opera-
tion: tracking, sequencing, and mixed modes. The
mixed mode is a combination of both tracking and
sequencing modes (see the Mixed Mode (Tracking/
Sequencing) section).
OUT1
OUT2
OUT3
OUT4
BIT 0
BIT 4
BIT 0
BIT 4
Tracking
When all selected inputs exceed their selected thresh-
BIT 1
BIT 2
BIT 3
BIT 5
BIT 6
BIT 1
BIT 2
BIT 3
BIT 5
BIT 6
olds, V
> 1.±85V, and ENABLE is logic high, the
TRKEN
tracking process is initialized. The MAX6876 generates
an internal ramp voltage that drives the control loops
for the desired tracked voltage. The tracking functional-
ity is monitored with a comparator control block (see
the Functional Diagram and Figure 5). The comparators
monitor and control each output voltage with respect to
the common tracking ramp voltage to stay within a
±1±5mV differential window, monitor each tracked out-
put voltage with respect to its input voltage, and moni-
tor each output voltage with respect to GND during
power-up/retry cycles. Under normal conditions each
OUT_ voltage will track the ramp voltage until the OUT_
voltage approximates the IN_ voltage (the external
n-channel FET is saturated). The slew rate for the ramp
voltage is selected through EEPROM.
BIT 7
(MSB)
BIT 7
(MSB)
R0Bh[7:0]
R0Ch[7:0]
Figure 6. Mapping Tracking and Sequencing Modes
intended to provide only tracking for the four supplies
(only one ramp is generated). To control one particular
channel, insert a “1” in any of the four possible posi-
tions (one row for each channel contains 4 bits) and the
circuit will generate the proper signals (see Figure 6).
Master/Slave Operation (Tracking Only)
To support voltage tracking for more than four supplies,
combine multiple MAX6876 devices. Two MAX6876
devices (one master/one slave) track up to eight supply
voltages and four MAX6876 devices (one master and
three slaves) track up to 16 supply voltages. Each
device must be programmed to act in master or slave
mode (only one master is allowed); the default state is
single device (see Table 1). The MAX6876 outputs the
ramp control voltage with the SYNCH output when con-
figured as a master device. This ramp allows multiple
devices to synchronize with the master when slave
SYNCHs are configured as inputs. For proper function-
ality control, connect all ENABLE pins together. In mas-
ter/slave mode, all controlled supplies are tracked
up/down (no mixed sequencing/tracking modes are
supported). In master-slave application, the part is
For multiple MAX6876 operations, the ramp control volt-
age is brought out of the master’s SYNCH (programmed
as an output) and into the slave’s SYNCH (programmed
as an input). The highest tracked supply must be con-
nected to one of the master’s IN_ inputs. When all IN_
threshold conditions are met (on master and slaves), the
master ramp begins rising at the selected ramp slew rate.
During normal operation all OUT_ voltages (for master
and slave) track the ramp voltage. If the slave’s OUT_
voltages do not properly follow the ramp voltage (exceed
1±5mV differential), the slave device asserts HOLD low.
The master recognizes the HOLD and holds the ramp
voltage, allowing the slave’s slower OUT_ voltages to
______________________________________________________________________________________ 15
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
catch up. When the slave’s voltages approach the ramp
voltage, the slave releases HOLD and the master allows
the ramp voltage to begin rising again. All tracking must
be completed by the selected tracking fault timeout peri-
od or the supplies are powered down. The slave HOLD
output is asserted low until the selected tracking IN_ volt-
ages are within their selected thresholds. This ensures
that the master does not begin the tracking operation until
the slave’s input voltages (IN_) have properly stabilized.
Configuring Tracking and Sequencing
Modes
To configure tracking and sequencing modes, insert
“1” and “0” into the 0Bh and 0Ch registers (see Table
±). Figure 6 shows how to map for tracking and
sequencing modes. Each OUT_ output can follow one
of the four possible ramps in tracking or sequencing
mode (16 bits are available) and one bit set to “1,”
means that the channel of the interested row is pow-
ered up/down by the corresponding ramp (see Figure
6).
Sequencing
The sequencing operation can be initialized by proper-
ly setting the bit of registers 0Bh and 0Ch. During a
sequencing power-up phase, each OUT_ is indepen-
dently powered on with a controlled slew rate. No more
than one supply is powered on for each generated
ramp. The bits of registers 0Bh and 0Ch establish the
turn-on order. During each phase, the ramp is enabled
1) If the depicted table (in Figure 6) is made by all “1s,”
the part simply generates a single ramp (all channels
in tracking mode since the first column is full of “1s,”)
and it ignores the remaining values of the other 1± bits.
±) If one row contains more than one symbol “1,” only
the first encountered (columns starting with R0Bh
[3:0]) is taken into account and the channel is pow-
ered up/down with the corresponding ramp.
to start only after the t
timeout has been counted.
GATE
The sequencing phase will be considered complete
when all the channels programmed to power on reach
the independently set PG_ thresholds (see Figure 5).
3) If there is one (or more) row in which all 4 bits are
set to “0,” it means that the device will not control
that particular channel.
Mixed Mode (Tracking/Sequencing)
The MAX6876 is fully programmable to generate up to
four ramps during power-up or power-down modes.
Each OUT_ voltage independently is programmed to
follow any of the control ramps generated by the
MAX6876. To do the latter, set the bits on register 0Bh
and 0Ch to “1” for each channel. The following are pro-
gramming examples of different power-up modes (ꢁ =
sequence, / = track):
4) If there is one (or more) column where all 4 bits are
set to “0,” the device skips that ramp and its associ-
ate t
D-GATE.
In master-slave applications, the device is intended to
provide only tracking for the four supplies (only one
ramp can be generated). To control one particular
channel, only insert a “1” in any of the four possible
positions (one row for each channel contains 4 bits)
and the device generates the proper signals. When
three or less ramps are needed, use consecutive
ramps starting with ramp 1.
0Bh = 0000 1111 0Ch = 0000 0000 tracking mode:
OUT1/OUT±/OUT3/OUT4 on Ramp1
0Bh = 1000 0100 0Ch = 0010 0001 sequencing
mode: OUT3 ꢁ OUT4 ꢁ OUT1 ꢁ OUT± on Ramp1,
Ramp±, Ramp3, Ramp4
Power-Down and Power-Up
When all the IN_ inputs are within the selected threshold
range and the internal enable is logic high (Figure 7), the
device initiates a power-up phase. During power-up, the
OUT_ outputs are forced by an internal loop that controls
the GATE_ of the external MOSFET to follow the reference
ramp voltage. This phase for each individual ramp must
be completed within the programmable fault timeout time;
otherwise, the part will force a shutdown on the GATE_.
Once the power-up is completed, a power-down phase
can be initiated by forcing the internal enable low. Two
power-down options are available: a fast-shutdown option
where all GATE_ gates are quickly turned off or a reverse-
order option. This reverse-order option allows the OUT_
voltage to be powered down with a controlled slew rate
and in the reverse order they have been powered up (see
Figure ±).
0Bh = 1100 0001 0Ch = 0010 0000 mix mode*: OUT1
ꢁ OUT4/OUT3 ꢁ OUT± on Ramp1, Ramp±, Ramp4
*(Ramp3 is not considered because no OUT_ outputs
are selected by bit [0:3] of 0Ch.)
Drive ENABLE or TRKEN low or use a software com-
mand to initiate a controlled power-down. The MAX6876
powers down the OUT_ voltages in a reverse sequence
from the one at power-up when this option is selected.
For example, with the following power-up sequence:
OUT1 ꢁ OUT4/OUT3 ꢁ OUT±
then the power-down sequence will be:
OUT± ꢁ OUT4/OUT3 ꢁ OUT1
16 ______________________________________________________________________________________
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Table 2. Configuring Tracking and Sequencing Modes
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
Bit 7—If 1, OUT4 on ramp ±
Bit 6—If 1, OUT3 on ramp ±
Bit 5—If 1, OUT± on ramp ±
Bit 4—If 1, OUT1 on ramp ±
Bit 3—If 1, OUT4 on ramp 1
Bit ±—If 1, OUT3 on ramp 1
Bit 1—If 1, OUT± on ramp 1
Bit 0—If 1, OUT1 on ramp 1
Bit 7—If 1, OUT4 on ramp 4
Bit 6—If 1, OUT3 on ramp 4
Bit 5—If 1, OUT± on ramp 4
Bit 4—If 1, OUT1 on ramp 4
Bit 3—If 1, OUT4 on ramp 3
Bit ±—If 1, OUT3 on ramp 3
Bit 1—If 1, OUT± on ramp 3
Bit 0—If 1, OUT1 on ramp 3
0Bh
±Bh
[7:0]
0Ch
±Ch
[7:0]
To speed up the discharge of the OUT_ voltage, an
optional 100Ω pulldown resistor can be selected (see
Table 3).
ed. Toggle ENABLE, I±C command bit, and TRKEN or
cycle device power to clear the latch. Set bit 5 of regis-
ter 09h to “1” to program the MAX6876 in latch-off
mode, or “0” to program for autoretry mode. The
autoretry time can be programmed with bits ±, 3, and 4
of register 09h (see Table 5). During autoretry, the gate
drive remains off and FAULT remains asserted. In a
master-slave application, FAULT is asserted low until all
the OUT_ outputs of each device are discharged to
GND, and only the master counts the autoretry time
while HOLD remains low (see Table 5).
Slew-Rate Control
The reference ramp voltage slew rate during any con-
trolled power-up/down phase can be programmed in
the 100V/s to 800V/s range. Before any power-up or
retry cycle, the MAX6876 must first ensure that all
OUT_ voltages are near ground (below the V
TH_PL
power low threshold). An internal programmable track-
ing timeout period can be selected to signal a fault and
shut down the output voltages if tracking takes too long
(see Table 4).
Stability Comment
No external compensation is required for tracking or
slew-rate control.
Power-supply tracking operation should be completed
within the selected fault timeout period. For selected
control ramps of 100V/s the normal tracking time
should be approximately 50ms (5V supply, SR =
100V/s). The total tracking time is extended when the
MAX6876 must vary the control slew rate to allow slow
supplies to catch up. If the external FET is too small
(RDS is too high for the selected load current and IN_
source current), the OUT_ voltage may never reach the
control ramp voltage.
Powering the MAX6876
The MAX6876 derives power from V
or the voltage-
CC
detector inputs: IN1–IN4 (see the Functional Diagram).
V
(if being used) or one of the IN_ inputs must be at
CC
least +±.7V to ensure full device operation.
The highest input voltage on IN1–IN4 or V
supplies
CC
power to the device. Internal hysteresis ensures that
the supply input that initially powers the device contin-
ues to power the device when multiple input voltages
are within 50mV (typ) of each other.
Autoretry and Latch-Off Functions
The MAX6876 features latch-off or autoretry mode to
power on again after a fault condition has been detect-
______________________________________________________________________________________ 17
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Table 3. Program Power-Down and Power-Up
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
Bit 7—If 1, reverse order of track/sequence power-down
If 0, GATE_ fast pulldown
Bit 6—If 1, OUT1 charges with internal pulldown
If 0, no pulldown is allowed
Bit 5—If 1, OUT± charges with internal pulldown
If 0, no pulldown is allowed
13h
33h
[7:3]
Bit 4—If 1, OUT3 charges with internal pulldown
If 0, no pulldown is allowed
Bit 3—If 1, OUT4 charges with internal pulldown
If 0, no pulldown is allowed
“00” fault power-up timer value = ±5ms
“01” fault power-up timer value = 50ms
“10” fault power-up timer value = 100ms
“11” fault power-up timer value = ±00ms
“00” fault power-down timer value = ±5ms
“01” fault power-down timer value = 50ms
“10” fault power-down timer value = 100ms
“11” fault power-down timer value = ±00ms
[7:6]
[5:4]
0Ah
±Ah
Table 4. Setting the Slew Rate
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
“00” track/sequence slew rate (rise or fall) = 800V/s
“01” track/sequence slew rate (rise or fall) = 400V/s
“10” track/sequence slew rate (rise or fall) = ±00V/s
“11” track/sequence slew rate (rise or fall) = 100V/s
1±h
3±h
Bit [7:6]
Inputs
IN1–IN4
V
- 0.5V
TH
x =
0.01V
for +0.5V to +3.05V range.
The IN1–IN4 voltage detectors monitor voltages from
1V to 5.5V in ±0mV increments, or +0.5V to +3.05V in
10mV increments. Use the following equations to set
the threshold voltages for IN_:
where V is the desired threshold voltage and x is the
TH
decimal code for the desired threshold (Table 6). For
the +1V to +5.5V range, x must equal ±±5 or less; oth-
erwise, the threshold exceeds the maximum operating
voltage of IN1–IN4 (Table 6). An overvoltage or under-
voltage failure on an IN_ input immediately shuts down
all the OUT_ outputs and generates a FAULT in the
master/slave condition.
V
-1V
TH
x =
0.0±V
for +1V to +5.5V range.
18 ______________________________________________________________________________________
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Table 5. Program Autoretry/Latch off
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
If 1, latch-on fault
If 0, autoretry
5
“000” autoretry timer value = ±5µs
“001” autoretry timer value = 1±.5ms
“010” autoretry timer value = ±5.0ms
“011” autoretry timer value = 50.0ms
“100” autoretry timer value = 100.0ms
“101” autoretry timer value = ±00.0ms
“110” autoretry timer value = 400.0ms
“111” autoretry timer value = 1600.0ms
09h
±9h
[4:±]
Table 6. IN1–IN4 Threshold Settings
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT
RANGE
DESCRIPTION
IN1 Undervoltage Threshold
V
V
= 1.0 + n x ±0mV (if R08[7] = 0)
= 0.5 + n x 10mV (if R08[7] = 1)
TH
00h
01h
±0h
±1h
[7:0]
[7:0]
TH
where n is the register content decimal representation. Note that V ranges
TH
must be 1V to 5.5V and 0.5V to 3.05V, respectively.
IN± Undervoltage Threshold
V
V
= 1.0 + n x ±0mV (if R08[6] = 0)
= 0.5 + n x 10mV (if R08[6] = 1)
TH
TH
where n is the register content decimal representation. Note that V ranges
TH
must be 1V to 5.5V and 0.5V to 3.05V, respectively.
IN3 Undervoltage Threshold
V
V
= 1.0 + n x ±0mV (if R08[5] = 0)
= 0.5 + n x 10mV (if R08[5] = 1)
TH
TH
0±h
03h
04h
±±h
±3h
±4h
[7:0]
[7:0]
[7:0]
where n is the register content decimal representation. Note that V ranges
TH
must be 1V to 5.5V and 0.5V to 3.05V, respectively.
IN4 Undervoltage Threshold
V
V
where n is the register content decimal representation. Note that V ranges
TH
must be 1V to 5.5V and 0.5V to 3.05V, respectively.
= 1.0 + n x ±0mV (if R08[4] = 0)
= 0.5 + n x 10mV (if R08[4] = 1)
TH
TH
IN1 Overvoltage Threshold
V
V
= 1.0 + n x ±0mV (if R08[7] = 0)
= 0.5 + n x 10mV (if R08[7] = 1)
TH
TH
where n is the register content decimal representation. Note that V ranges
TH
must be 1V to 5.5V and 0.5V to 3.05V, respectively.
______________________________________________________________________________________ 19
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Table 6. IN1–IN4 Threshold Settings (continued)
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT
RANGE
DESCRIPTION
IN± Overvoltage Threshold
V
V
= 1.0 + n x ±0mV (if R08[6] = 0)
= 0.5 + n x 10mV (if R08[6] = 1)
TH
TH
05h
06h
±5h
±6h
[7:0]
[7:0]
where n is the register content decimal representation. Note that V ranges
TH
must be 1V to 5.5V and 0.5V to 3.05V, respectively.
IN3 Overvoltage Threshold
V
V
= 1.0 + n x ±0mV (if R08[5] = 0)
= 0.5 + n x 10mV (if R08[5] = 1)
TH
TH
where n is the register content decimal representation. Note that V ranges
TH
must be 1V to 5.5V and 0.5V to 3.05V, respectively.
IN4 Overvoltage Threshold
V
V
= 1.0 + n x ±0mV (if R08[4] = 0)
= 0.5 + n x 10mV (if R08[4] = 1)
TH
TH
07h
08h
±7h
±8h
[7:0]
[7:4]
where n is the register content decimal representation. Note that V ranges
TH
must be 1V to 5.5V and 0.5V to 3.05V, respectively.
Bit 7—If 0, ±0mV steps in V setting for IN1
If 1, 10mV steps in V setting for IN1
TH
TH
Bit 6—If 0, ±0mV steps in V setting for IN±
If 1, 10mV steps in V setting for IN±
TH
TH
Bit 5—If 0, ±0mV steps in V setting for IN3
TH
If 1, 10mV steps in V setting for IN3
TH
Bit 4—If 0, ±0mV steps in V setting for IN4
TH
If 1, 10mV steps in V setting for IN4
TH
ENABLE low to initiate tracking/sequencing power-down
operation. When ENABLE is not used, connect to ABP.
Manual Reset Input (MR)
The manual reset (MR) input initiates a reset condition.
MR is internally pulled up to ABP through a 100kΩ
resistor. When MR is low, RESET remains low for the
selected reset timeout period after MR transitions from
low to high (see the Reset Output (RESET) section).
When the MAX6876 is configured to use the I±C on/off
command, a valid I±C signal must be received before
the device begins the power-up tracking/sequencing
routine. The internal enable logic is an AND function of
the ENABLE logic, the TRKEN logic, and the I±C con-
trol/command logic (Figure 7). When all three AND gate
input variables are true (and the monitored IN/OUT volt-
ages meet their required thresholds), turn-on is allowed.
When any AND input variable becomes false, the turn-
off cycle (track/sequence down) begins immediately.
Drive ENABLE and TRKEN high if only the I±C com-
mand is to be used to turn on/off the device. The detec-
tors monitoring IN_ and OUT_ voltages, and
overcurrent conditions have a higher priority after a
power-on routine has been initiated by the internal
enable logic. If a fault occurs during the power-up
cycle, the device is powered down immediately, inde-
pendent of ENABLE, TRKEN, and the I±C shutdown
Margin Input (MARGIN)
MARGIN allows system-level testing while power sup-
plies exceed the normal ranges. Drive MARGIN low
before varying system voltages below/above the select-
ed threshold without signaling an error. MARGIN makes
it possible to vary the supplies without a need to repro-
gram the IN_ or PG_ thresholds and prevents
tracker/sequencer alerts or faults. Drive MARGIN high
or leave it floating for normal operating mode.
ENABLE
Drive logic ENABLE input high to initiate voltage track-
ing/sequencing during power-up operation. Drive logic
20 ______________________________________________________________________________________
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Table 7. Program ENABLE
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
±
Bit 1—If 1, check ENABLE with I C enable control bit
±
If 0, ignore ENABLE with I C
09h
±9h
[1:0]
±
±
Bit 0—If 0, enable with I C = 0, I C enable command bit
±
If 1, enable with I C = 1
Table 8. Select External Reference
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
11h
31h
0
Bit 0—If 1, selects external reference; 0 selects internal reference
command (Table 7). If a latch-on fault mode is chosen,
a toggle on the internal enable clears the latch condi-
tion and restarts the device after a fault condition
(Figure 7).
ENABLE
TRKEN
INTERNAL
ENABLE
Reference Voltage Input (REFIN)
The MAX6876 features an internal +1.±5V voltage refer-
ence. The voltage reference sets the threshold of the
voltage detectors. Leave REFIN unconnected when
using the internal reference. REFIN accepts an external
reference in the +1.±±5V to +1.±75V range. Use Table
8 commands to select the external reference.
V
TRKEN
I2C ENABLE CONTROL BIT
(RAM REGISTER)
1 = YES
I2C ENABLE COMMAND BIT
(RAM REGISTER)
0 = OFF
09h[1]
0 = NO
09h[0]
1 = ON
Track Enable Input (TRKEN)
The track enable (TRKEN) monitor input is another fea-
ture of the MAX6876. To enable voltage-tracking
power-up operation, drive TRKEN higher than 1.±85V.
When TRKEN goes below 1.±5V, OUT_ outputs start
tracking down. Connect TRKEN to an external resistor-
divider network to set the desired monitor threshold.
Connect TRKEN to ABP if not used.
Figure 7. Logic ENABLE
Monitored Outputs
OUT1–OUT4
The MAX6876 monitors four OUT_ outputs to control
the tracking/sequencing performance. After the internal
supply (ABP) exceeds the minimum voltage (±.7V)
requirements, TRKEN > 1.±5V, the internal ENABLE
input is logic high, and IN1–IN4 are all within their
selected thresholds, OUT1–OUT4 will begin to track or
sequence.
SYNCH
The MAX6876 provides selectable tracking synchro-
nization output or input (SYNCH). SYNCH allows track-
ing of up to 16 power supplies on the same I±C bus.
One device is programmed as the SYNCH master and
the other devices are programmed as slaves. SYNCH
of the master device outputs the common ramp voltage
to which all OUT_ voltages are tracked. The SYNCH
pins of the slave devices are inputs for the ramp control
voltage (no internal ramp is generated in the slave
devices) (see Table 1).
During power-up mode, the MAX6876 drives the gates
of the external n-channel FETs to force the OUT_ volt-
ages to track the internally set ramp voltage. If OUT_
voltages vary from the ramp voltage by more than
±1±5mV, an internal comparator signals an alert that
dynamically adjusts the ramp voltage (stops the ramp
until the slow OUT_ catches up). During power-down
mode, an internal pulldown resistor (100Ω) on OUT_
can be enabled to help discharge load capacitance.
______________________________________________________________________________________ 21
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Table 9. GATE-Delay Time Settings
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
“000” gate-delay timer value = ±5µs
“001” gate-delay timer value = 1±.5ms
“010” gate-delay timer value = ±5.0ms
“011” gate-delay timer value = 50.0ms
“100” gate-delay timer value = 100.0ms
“101” gate-delay timer value = ±00.0ms
“110” gate-delay timer value = 400.0ms
“111” gate-delay timer value = 1600.0ms
0Fh
±Fh
[7:5]
Table 10. FAULT Power-Up and Power-Down Time Settings
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
Bit [7:6] “00” fault power-up timer value = ±5ms
“01” fault power-up timer value = 50ms
“10” fault power-up timer value = 100ms
“11” fault power-up timer value = ±00ms
[7:6]
0Ah
±Ah
Bit [5:4] “00” fault power-down timer value = ±5ms
“01” fault power-down timer value = 50ms
“10” fault power-down timer value = 100ms
“11” fault power-down timer value = ±00ms
[5:4]
FAULT
Outputs
The MAX6876 offers an open-drain, active-low tracking
fault alarm (FAULT). FAULT asserts low when a power-
up phase is not completed within the specified fault
period or if tracking voltages fail by more than ±±50mV.
For multiple MAX6876 applications, FAULT is an
input/output pin and communicates fault information
between master/slave devices. Connect all FAULT pins
in an ORed configuration to force simultaneous shut-
down on all MAX6876s (Table 10.) See the Typical
Application Circuit.
GATE_
The MAX6876 features four GATE_ outputs to drive four
external n-channel FET gates. The following conditions
must be met before GATE_ begins enhancing the
external n-channel FET_:
1) All monitored inputs (IN1–IN4) are above their
selected thresholds (0.5V to 5.5V)
±) At least one IN_ input or V
3) Drive ENABLE high
4) TRKEN > 1.±5V
is above ±.7V
CC
Power-Good Outputs (PG_)
The MAX6876 features four power-good (PG_) outputs.
PG_ outputs are open-drain and require external
pullups.
At power-up mode, GATE_ voltages are enhanced con-
trol loops so all OUT_ voltages track together at a user-
selected slew rate. Each GATE_ is internally pulled up
to 5V above its relative IN_ voltage to fully enhance the
external n-channel FET when power-up is complete. In
sequencing/tracking mode, a gate delay timeout is
internally counted prior to the start of each control ramp
(see Figures 1 and ± and Table 9).
When the OUT_ output is within the selected percent-
age of the IN_ voltage range (V
), the correspond-
TH_PG
ing PG_ output goes high impedance. PG_ stays low
until the OUT_ voltage exceeds the programmable
V
threshold for more than t
(Table 11).
POK
TH_PG
22 ______________________________________________________________________________________
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Table 11. PG Threshold Settings
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
“00” IN4 to OUT4 power-good threshold = 95%
“01” IN4 to OUT4 power-good threshold = 9±.5%
“10” IN4 to OUT4 power-good threshold = 90%
“11” IN4 to OUT4 power-good threshold = 87.5%
“00” IN3 to OUT3 power-good threshold = 95%
"01" IN3 to OUT3 power-good threshold = 9±.5%
“10” IN3 to OUT3 power-good threshold = 90%
“11” IN3 to OUT3 power-good threshold = 87.5%
“00” IN± to OUT± power-good threshold = 95%
“01” IN± to OUT± power-good threshold = 9±.5%
“10” IN± to OUT± power-good threshold = 90%
“11” IN± to OUT± power-good threshold = 87.5%
“00” IN1 to OUT1 power-good threshold = 95%
“01” IN1 to OUT1 power-good threshold = 9±.5%
“10” IN1 to OUT1 power-good threshold = 90%
“11” IN1 to OUT1 power-good threshold = 87.5%
[7:6]
10h
30h
[5:0]
Bus Removal Output (REM)
Reset Output (RESET)
The reset output, RESET, is an open-drain output that
monitors the selected OUT_ voltages. The selected
OUT_ voltages must exceed their selected PG_ thresh-
The MAX6876 features an open-drain bus removal
(REM) output. REM signals when it is safe to remove
the card after a controlled track/sequence power-down
operation. To initiate a power-down, drive ENABLE low
or send an I±C power-down command. REM monitors
OUT_ and when any of the OUT_ voltages are above
olds for the selected reset timeout period (t ) before
RP
RESET is deasserted. A manual reset input (MR) can
assert RESET. RESET remains low while MR is low.
RESET remains low for the selected reset timeout peri-
the V
threshold, REM stays low. When all OUT_
TH_PL
outputs are below V
, REM goes high impedance.
od (t ) after MR transitions from low to high (Table 13).
TH_PL
RP
Connect REM to an external pullup resistor/LED chain
to visually signal when it is safe to remove a powered
board from the bus.
Synchronization Hold Output (HOLD)
The MAX6876 features an open-drain, active-low syn-
chronization alert output/input. HOLD communicates
synchronization status between master/slave devices in
multiple MAX6876 applications. When a slave device
detects a tracking problem with respect to the master
SYNCH signal, the slave asserts HOLD low. When
tracking is back under control, the slave’s HOLD is
deasserted and goes high again. The HOLD output
remains asserted while selected tracking IN_ inputs are
below their selected thresholds (the slave device can
delay a tracking start until its inputs are at their required
stable voltage levels) or held low by the master when it
is counting the autoretry time after a detected fault con-
dition. Connect HOLD pins only to other MAX6876
HOLD pins.
In tracking mode when REM is used in master/slave
operations, connect all REM pins together. The com-
mon REM connection remains low if any OUT_ supply
is above the V
threshold.
TH_PL
Overcurrent Output (OC)
The open-drain, active-low OC output asserts low if an
overcurrent condition is detected in any selected channel
for longer than t . Overcurrent conditions are deter-
OC
mined as a differential voltage between IN_ and OUT_.
OC monitoring begins only after supply tracking or
sequencing has been completed and is disabled during
power-down operation (Table 1±).
______________________________________________________________________________________ 23
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Table 12. OC Threshold Settings
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
Bit [7:6] “00” IN4 to OUT4 overcurrent threshold = 97.5%
“01” IN4 to OUT4 overcurrent threshold = 95%
“10” IN4 to OUT4 overcurrent threshold = 9±.5%
“11” IN4 to OUT4 overcurrent threshold = 90%
[7:6]
Bit [5:4] “00” IN3 to OUT3 overcurrent threshold = 97.5%
“01” IN3 to OUT3 overcurrent threshold = 95%
“10” IN3 to OUT3 overcurrent threshold = 9±.5%
“11” IN3 to OUT3 overcurrent threshold = 90%
0Dh
±Dh
Bit [3:±] “00” IN± to OUT± overcurrent threshold = 97.5%
“01” IN± to OUT± overcurrent threshold = 95%
“10” IN± to OUT± overcurrent threshold = 9±.5%
“11” IN± to OUT± overcurrent threshold = 90%
[5:0]
Bit [1:0] “00” IN1 to OUT1 overcurrent threshold = 97.5%
“01” IN1 to OUT1 overcurrent threshold = 95%
“10” IN1 to OUT1 overcurrent threshold = 9±.5%
“11” IN1 to OUT1 overcurrent threshold = 90%
Bit [7:6] “00” overcurrent timer value = 1±.5ms
“01” overcurrent timer value = 50ms
“10” overcurrent timer value = 100ms
“11” overcurrent timer value = ±00ms
Bit 5—If 1, overcurrent monitoring on OUT1 is enabled
If 0, no overcurrent monitoring on OUT1
0Eh
±Eh
[7:1]
Bit 4—If 1, overcurrent monitoring on OUT± is enabled
If 0, no overcurrent monitoring on channel 1
Bit 3—If 1, overcurrent monitoring on OUT3 is enabled
If 0, no overcurrent monitoring on OUT3
Bit ±—If 1, overcurrent monitoring on OUT4 is enabled
If 0, no overcurrent monitoring on OUT4
ABP
to ensure the device is configured properly. After com-
pleting the setup procedure, use the read word proto-
col to read back the data from the configuration
registers. Lastly, use the write word protocol to write
this data to the EEPROM registers. After completing the
EEPROM register configuration, apply full power to the
system to begin normal operation. The nonvolatile
EEPROM stores the latest configuration upon removal
of power (Table 14).
ABP powers the analog circuitry. Bypass ABP to GND
with a 1µF ceramic capacitor installed as close to the
device as possible. Do not use ABP to provide power
to external circuitry.
Configuring the MAX6876
The MAX6876 factory-default configuration sets all reg-
isters to 00h. This device requires configuration before
full power is applied to the system. To configure the
MAX6876, first apply an input voltage greater than ±.7V
Software Reboot
A command code of C4h initiates a software reboot. A
software reboot allows the user to restore the EEPROM
configuration to the volatile registers without cycling the
power supplies.
to one of IN1–IN4 or V
(see the Powering the
CC
MAX6876 section). Next, transmit data with the serial
interface. Use the block write protocol to quickly config-
ure the device. Write to the configuration registers first,
24 ______________________________________________________________________________________
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Table 13. Program RESET
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
Bit 7—If 1, OUT1 also controls RESET
If 0, OUT1 does not control RESET
Bit 6—If 1, OUT± also controls RESET
If 0, OUT± does not control RESET
Bit 5—If 1, OUT3 also controls RESET
If 0, OUT3 does not control RESET
Bit 4—If 1, OUT4 also controls RESET
If 0, OUT4 does not control RESET
11h
31h
[7:1]
Bit [3:1] “000” reset timer value = ±5µs
“001” reset timer value = 1±.5ms
“010” reset timer value = ±5.0ms
“011” reset timer value = 50.0ms
“100” reset timer value = 100.0ms
“101” reset timer value = ±00.0ms
“110” reset timer value = 400.0ms
“111” reset timer value = 1600.0ms
SMBus/I2C-Compatible Serial Interface
The MAX6876 features an I±C/SMBus-compatible ±-
wire serial interface consisting of a serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facili-
tate bidirectional communication between the
MAX6876 and the master device at clock rates up to
400kHz. Figure 10 shows the ±-wire interface timing
diagram. The MAX6876 is transmit/receive slave-only,
relying upon a master device to generate a clock sig-
nal. The master device (typically a microcontroller) initi-
ates a data transfer on the bus and generates SCL to
permit that transfer.
Bit Transfer
Each clock pulse transfers one data bit. The data on
SDA must remain stable while SCL is high (Figure 11);
otherwise, the MAX6876 registers a START or STOP
condition (Figure 1±) from the master. SDA and SCL
idle high when the bus is not busy.
Start and Stop Conditions
Both SCL and SDA idle high when the bus is not busy.
A master device signals the beginning of a transmis-
sion with a START (S) condition (Figure 8) by transition-
ing SDA from high to low while SCL is high. The master
device issues a STOP (P) condition (Figure 8) by transi-
tioning SDA from low to high while SCL is high. A STOP
condition frees the bus for another transmission. The
bus remains active if a REPEATED START condition is
generated, such as in the block read protocol (see
Figure 11).
A master device communicates to the MAX6876 by
transmitting the proper address followed by command
and/or data words. Each transmit sequence is framed
by a START (S) or REPEATED START (SR) condition
and a STOP (P) condition. Each word transmitted over
the bus is 8 bits long and is always followed by an
acknowledge pulse.
Early STOP Conditions
The MAX6876 recognizes a STOP condition at any point
during transmission except if a STOP condition occurs in
the same high pulse as a START condition. This condi-
tion is not a legal I±C format; at least one clock pulse
must separate any START and STOP condition.
SCL is a logic input, while SDA is an open-drain
input/output. SCL and SDA both require external pullup
resistors to generate the logic-high voltage. Use 4.7kΩ
for most applications.
______________________________________________________________________________________ 25
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Table 14. Registers Summary
REGISTERS
DESCRIPTIONS
Input Undervoltage Thresholds
(Registers 00h to 03h)
Input undervoltage thresholds (0.5V to 3.04V in 10mV increments or 1.0V to 5.5V in ±0mV
increments). Each channel’s range is selected with register 08h.
Input Overvoltage Thresholds
(Registers 04h to 07h)
Input overvoltage thresholds (0.5V to 3.04V in 10mV increments or 1.0V to 5.5V in ±0mV
increments). Each channel’s range is selected with register 08h.
Selects if outputs are to be sequenced or tracked. Sequencing/tracking modes are defined
by 4 bits for each OUT voltage of register 0Bh and 0Ch (see the Track/Sequence section).
Tracking/Sequencing Modes
Tracking/Sequencing
Power-Up/Down Slew Rate
Selectable output slew rate for power-up/down mode. Selected slew is overwritten during
tracking faults. Power-up/down slew rate is selected by bit [6:7] of register 1±h.
Power-up sequencing delay. Selects delay time for sequencing each supply.
Programmable delays are selected with bit [5:7] of register 0Fh.
Power-Up Delay Period
Selectable power-down operation. Chooses if output voltages should be brought down in
the reverse sequence from power-up mode selections or if power supplies should be
simultaneously fast powered down (selected with bit 7 register 13h).
Power-Down Sequence/Track
Behavior
Selects if OUT_ should be internally pulled to GND when in fast shutdown or tracking fault
mode (selected with bit [6:3] register 13h).
OUT Pulldown Enable
Selects if the device will be used alone or in a master/slave application. If a single
application, the device can be operated in mixed sequencing/tracking modes. If multi-
device application, the device can be operated in tracking mode only (selected with bit
[7:6] register 09h).
Single/Multiple Device Application
00: single device 11: master device 01 or 10: slave device
Overcurrent Threshold
Selects IN_-to-OUT_ threshold voltage for overcurrent monitoring for each channel (register 0Dh).
Selects IN_-to-OUT_ threshold voltage for power-good monitoring for each channel
(register 10h).
Power-Good Threshold
Overcurrent Assert Select
Overcurrent Filter Period
Selects which overcurrent monitors will assert the OC output (selected by bit [5:±] of reg. 0Eh).
Selects the filter time for the overcurrent monitors. OC will not assert until the overcurrent
condition has existed longer than the selected filter period (selected by bit [7:6] of reg. 0Eh).
Selects the timeout period for sequencing/tracking completion. If sequencing/tracking
operation is not complete before the fault timeout period, a FAULT alert will be signaled
and all supplies will be powered down (selected by bit [7:4] of reg. 0Ah).
Fault Timeout Period
Fault Behavior
Selects how the device should operate during faults. Options include latch-off after fault or
autoretry after fault. Autoretry delay is selectable (selected by bit 5 of reg. 09h).
Reset Assert Select
Selects which OUT detectors will assert the RES E T output (selected by bit [7:4] of reg. 11h).
Reset Timeout Period Select
Selects the reset timeout period (selected by bit [3:1] of reg. 11h).
Bit 0 and bit 1 of register 09h allows a micro to turn the MAX6876 on/off with the I±C
interface. While 09h[1] is 0, the part will ignore any enable command from I±C. If 09h[1] is
set to 1, then 09h[0] has to be 1 to enable the part to power on.
Enable the Part with I±C Interface
26 ______________________________________________________________________________________
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
SDA
t
BUF
t
SU:DAT
t
SU:STA
t
t
SU:STO
HD:DAT
t
t
LOW
HD:STA
SCL
t
HIGH
t
HD:STA
t
t
F
R
START
CONDITION
STOP
CONDITION
START
CONDITION
REPEATED START
CONDITION
Figure 10. Serial-Interface Timing Details
SDA
SDA
SCL
SCL
S
P
START
CONDITION
STOP
CONDITION
CHANGE OF
DATA ALLOWED
DATA LINE STABLE,
DATA VALID
Figure 12. Start and Stop Conditions
Figure 11. Bit Transfer
Repeated START Conditions
erates an ACK. The MAX6876 generates an ACK when
receiving an address or data by pulling SDA low during
the 9th clock period (Figure 13). When transmitting
data, such as when the master device reads data back
from the MAX6876, the device waits for the master
device to generate an ACK. Monitoring ACK allows for
detection of unsuccessful data transfers. An unsuc-
cessful data transfer occurs if the receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time. The MAX6876
generates a NACK after the slave address during a
software reboot, while writing to the EEPROM, or when
receiving an illegal memory address.
A REPEATED START (SR) condition may indicate a
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation (see Figure 1±). SR may also be used
when the bus master is writing to several I±C devices
and does not want to relinquish control of the bus. The
MAX6876 serial interface supports continuous write
operations with or without an SR condition separating
them. Continuous read operations require SR condi-
tions because of the change in direction of data flow.
Acknowledge
The acknowledge bit (ACK) is the 9th bit attached to
any 8-bit data word. The receiving device always gen-
______________________________________________________________________________________ 27
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
START
CLOCK PULSE FOR ACKNOWLEDGE
CONDITION
2
1
8
9
SCL
SDA BY
TRANSMITTER
S
SDA BY
RECEIVER
Figure 13. Acknowledge
Slave Address
The MAX6876 slave address conforms to the following
table:
sends C4h, this signifies a software reboot. The send
byte procedure follows:
1) The master sends a start condition.
SA7
(MSB)
SA0
(LSB)
±) The master sends the 7-bit slave address and a
write bit (low).
SA6 SA5 SA4 SA3 SA± SA1
A1 A0
1
0
1
0
X
R/W
3) The addressed slave asserts an ACK on SDA.
4) The master sends an 8-bit data byte.
X = Don’t care.
5) The addressed slave asserts an ACK on SDA.
6) The master sends a stop condition.
SA7–SA4 represent the standard ±-wire interface
address (1010) for devices with EEPROM. SA3 and
SA± correspond to the A1 and A0 address inputs of the
MAX6876 (hardwired as logic low or logic high). SA0 is
a read/write flag bit (0 = write, 1 = read).
Write Byte/Word
The write byte/word protocol allows the master device
to write a single byte in the register bank, preset an
EEPROM (configuration or user) address for a subse-
quent read, or to write a single byte to the configuration
EEPROM (see Figure 15). The write byte/word proce-
dure follows:
The A0 and A1 address inputs allow up to four
MAX6876s to connect to one bus. Connect A0 and A1
to GND or to HBP (see Figure 14).
Send Byte
The send byte protocol allows the master device to send
one byte of data to the slave device (see Figure 15). The
send byte presets a register pointer address for a sub-
sequent read or write. The slave sends a NACK instead
of an ACK if the master tries to send an address that is
not allowed. If the master sends C0h or C1h, the data is
ACK, because this could be the start of the write block
or read block. If the master sends a stop condition, the
internal address pointer does not change. If the master
1) The master sends a start condition.
±) The master sends the 7-bit slave address and a
write bit (low).
3) The addressed slave asserts an ACK on SDA.
4) The master sends an 8-bit command code.
5) The addressed slave asserts an ACK on SDA.
6) The master sends an 8-bit data byte.
7) The addressed slave asserts an ACK on SDA.
28 ______________________________________________________________________________________
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
SDA
1
0
A1
A0
X
R/W
ACK
0
1
START
MSB
LSB
SCL
Figure 14. Slave Address
8) The master sends a stop condition or sends another
8-bit data byte.
4) The master sends the 8-bit command code for
block write (83h).
9) The addressed slave asserts an ACK on SDA.
10) The master sends a stop condition.
5) The addressed slave asserts an ACK on SDA.
6) The master sends the 8-bit byte count (1 to 16
bytes), N.
To write a single byte to the register bank, only the 8-bit
command code and a single 8-bit data byte are sent.
The command code must be in the range of 00h to 13h
to write on RAM or ±0h to 33h to write on EEPROM. The
data byte is written to the register bank if the command
code is valid. The slave generates a NACK at step 5 if
the command code is invalid.
7) The addressed slave asserts an ACK on SDA.
8) The master sends 8 bits of data.
9) The addressed slave asserts an ACK on SDA.
10) Repeat steps 8 and 9 N - 1 times.
11) The master generates a stop condition.
Block Write
The block write protocol allows the master device to
write a block of data (1 to 16 bytes) to the EEPROM or
to the register bank (see Figure 15). The destination
address must already be set by the send byte or write
byte protocol. If the number of bytes to be written caus-
es the address pointer to exceed 13h for the configura-
tion register (or 33h for the configuration EEPROM), the
address pointer stays at 13h (or 33h), overwriting this
memory address with the remaining bytes of data. The
last data byte sent is stored at register address 13h (or
33h). The block write procedure follows:
Block Read
The block read protocol allows the master device to
read a block of 16 bytes from the EEPROM or register
bank (see Figure 15). Read fewer than 16 bytes of data
by issuing an early STOP condition from the master, or
by generating a NACK with the master. The send byte
or write byte protocol predetermines the destination
address with a command code of C1h. The block read
procedure follows:
1) The master sends a start condition.
±) The master sends the 7-bit slave address and a
write bit (low).
1) The master sends a start condition.
3) The addressed slave asserts an ACK on SDA.
±) The master sends the 7-bit slave address and a
write bit (low).
4) The master sends 8 bits of the block read com-
mand (C1h).
3) The addressed slave asserts an ACK on SDA.
5) The slave asserts an ACK on SDA, unless busy.
______________________________________________________________________________________ 29
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
SEND BYTE FORMAT
WRITE WORD FORMAT
ADDRESS WR
S
ADDRESS
WR
0
ACK
DATA
8 bits
ACK
P
S
ACK COMMAND ACK
DATA ACK
8 bits
DATA ACK
8 bits
P
7 bits
7 bits
0
8 bits
Data Byte–
Slave Address–
Data Byte–presets the
internal address pointer.
Slave Address–
Write Address of
Data Byte–
Data goes into
the register you are Data goes into
equivalent to chip-
select line of a 3-
wire interface.
equivalent to chip-
select line of a 3-
wire interface.
the next register set by
the command.
writing to.
the register set by
the command.
WRITE BYTE FORMAT
S
ADDRESS
WR
0
ACK
COMMAND
8 bits
ACK
DATA
8 bits
ACK
P
7 bits
Slave Address–
Command Byte–
selects register
you are writing to.
Data Byte–data goes into the
register set by the command.
equivalent to chip-
select line of a 3-
wire interface.
BLOCK WRITE FORMAT
BYTE
DATA BYTE
1
DATA BYTE
...
DATA BYTE
N
S
ADDRESS
7 bits
WR
0
ACK COMMAND ACK
8 bits
ACK
ACK
ACK
ACK
P
COUNT= N
8 bits
8 bits
8 bits
8 bits
Slave Address–
equivalent to chip-
select line of a 3-
wire interface.
Command Byte–
prepares device
for block
Data Byte–data goes into the register set by the
command byte.
operation.
BLOCK READ FORMAT
ADDRESS WR ACK COMMAND ACK SR ADDRESS WR
BYTE
COUNT= 16
DATA BYTE
1
DATA BYTE
...
DATA BYTE
N
S
ACK
ACK
ACK
ACK
ACK
P
7 bits
0
8 bits
7 bits
0
10h
8 bits
8 bits
8 bits
Slave Address–
equivalent to chip-
select line of a 3-
wire interface.
Command Byte–
prepares device
for block
Slave Address–
Data Byte–data goes into the register set by the
command byte.
equivalent to chip-
select line of a 3-
wire interface.
operation.
S = Start condition.
P = Stop condition.
Shaded = Slave transmission.
SR = Repeated start condition.
Figure 15. SMBus/I2C Protocols
30 ______________________________________________________________________________________
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Table 15. Configuration of Lock Bit
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
If 1, configuration registers are locked
If 0, configuration registers unlocked
13h
33h
±
6) The master generates a repeated start condition.
Configuration EEPROM
The configuration EEPROM addresses range from ±0h
to 33h. Write data to the configuration EEPROM to auto-
matically set up the MAX6876 upon power-up. Data
transfers from the configuration EEPROM to the config-
uration registers when ABP exceeds UVLO during
power-up. After ABP exceeds UVLO, an internal 1MHz
clock starts after a 5µs delay, and data transfer begins.
Data transfer disables access to the configuration reg-
isters and EEPROM. The data transfer from EEPROM to
the configuration registers takes ±ms (max). Read con-
figuration EEPROM data at any time after power-up or
software reboot. Write commands to the configuration
EEPROM are allowed at any time, unless the configura-
tion lock bit is set (see Table 15). The maximum cycle
time to write a single byte is 11ms (max).
7) The master sends the 7-bit slave address and a
read bit (high).
8) The slave asserts an ACK on SDA.
9) The slave sends the 8-bit byte count (16).
10) The master asserts an ACK on SDA.
11) The slave sends 8 bits of data.
1±) The master asserts an ACK on SDA.
13) Repeat steps 8 and 9 fifteen times.
14) The master generates a stop condition.
Address Pointers
Use the send byte protocol to set the register address
pointers before read and write operations. For the con-
figuration registers, valid address pointers range from
00h to 13h. Register addresses outside of this range
result in a NACK being issued from the MAX6876.
When using the block write protocol, the address point-
er automatically increments after each data byte,
except when the address pointer is already at 13h. If
the address pointer is already 13h, and more data
bytes are being sent, these subsequent bytes overwrite
address 13h repeatedly, leaving only the last data byte
sent stored at this register address.
Configuration Register Bank and EEPROM
The configuration registers can be directly modified
with the serial interface without modifying the EEPROM,
after the power-up procedure terminates and the con-
figuration EEPROM data has been loaded into the con-
figuration register bank. Use the write byte or block
write protocols to write directly to the configuration reg-
isters. Changes to the configuration registers are lost
upon power removal.
At device power-up, the register bank loads configura-
tion data from the EEPROM. Configuration data can be
directly altered in the register bank during application
development, allowing maximum flexibility. Transfer the
new configuration data byte-by-byte to the configura-
tion EEPROM with the write byte protocol. The next
device power-up or software reboot automatically loads
the new configuration (Table 16).
For the configuration EEPROM, valid address pointers
range from ±0h to 33h. When using the block write pro-
tocol, the address pointer automatically increments
after each data byte, except when the address pointer
is already at 33h. If the address pointer is already 33h,
and more data bytes are being sent, these subsequent
bytes overwrite address 33h repeatedly, leaving only
the last data byte sent stored at this register address.
______________________________________________________________________________________ 31
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Table 16. Register Map
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
READ/WRITE
DESCRIPTION
IN1 Undervoltage Threshold Value (V ):
TH
V
V
= 1.0 + n x ±0mV (if R08[7] = 0)
= 0.5 + n x 10mV (if R08[7] = 1)
TH
00h
01h
0±h
03h
04h
±0h
±1h
±±h
±3h
±4h
R/W
TH
where n is the register content decimal representation. Note that V
ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively.
TH
TH
IN± Undervoltage Threshold Value (V ):
V
V
where n is the register content decimal representation. Note that V
ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively.
TH
= 1.0 + n x ±0mV (if R08[6] = 0)
= 0.5 + n x 10mV (if R08[6] = 1)
TH
R/W
R/W
R/W
R/W
R/W
R/W
TH
IN3 Undervoltage Threshold Value (V ):
V
V
where n is the register content decimal representation. Note that V
ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively.
TH
= 1.0 + n x ±0mV (if R08[5] = 0)
= 0.5 + n x 10mV (if R08[5] = 1)
TH
TH
TH
TH
TH
TH
TH
IN4 Undervoltage Threshold Value (V ):
V
V
where n is the register content decimal representation. Note that V
ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively.
TH
= 1.0 + n x ±0mV (if R08[4] = 0)
= 0.5 + n x 10mV (if R08[4] = 1)
TH
TH
IN1 Overvoltage Threshold Value (V ):
V
V
where n is the register content decimal representation. Note that V
ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively.
TH
= 1.0 + n x ±0mV (if R08[7] = 0)
= 0.5 + n x 10mV (if R08[7] = 1)
TH
TH
IN± Overvoltage Threshold Value (V ):
V
V
where n is the register content decimal representation. Note that V
ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively.
TH
= 1.0 + n x ±0mV (if R08[6] = 0)
= 0.5 + n x 10mV (if R08[6] = 1)
TH
05h
06h
±5h
±6h
TH
IN3 Overvoltage Threshold Value (V ):
V
V
TH
= 1.0 + n x ±0mV (if R08[5] = 0)
= 0.5 + n x 10mV (if R08[5] = 1)
TH
TH
where n is the register content decimal representation. Note that V
ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively.
32 ______________________________________________________________________________________
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Table 16. Register Map (continued)
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
READ/WRITE
DESCRIPTION
IN4 Overvoltage Threshold Value (V ):
TH
V
V
= 1.0 + n x ±0mV (if R08[4] = 0)
= 0.5 + n x 10mV (if R08[4] = 1)
TH
07h
±7h
R/W
TH
where n is the register content decimal representation. Note that V
ranges must be 1V to 5.5V and 0.5V to 3.05V, respectively.
TH
Bit 7—If 0, ±0mV steps in V setting for IN1
TH
If 1, 10mV steps in V setting for IN1
TH
Bit 6—If 0, ±0mV steps in V setting for IN±
TH
If 1, 10mV steps in V setting for IN±
TH
Bit 5—If 0, ±0mV steps in V setting for IN3
TH
If 1, 10mV steps in V setting for IN3
TH
Bit 4—If 0, ±0mV steps in V setting for IN4
TH
If 1, 10mV steps in V setting for IN4
TH
Bit 3—UV1 or OV1 Fault (read only for register address). If 1, IN1 is under
undervoltage threshold or over overvoltage threshold. If 0, IN1 is over
undervoltage threshold and under overvoltage threshold.
08h
±8h
R/W
Bit ±—UV± or OV± Fault (read only for register address). If 1, IN± is under
undervoltage threshold or over overvoltage threshold. If 0, IN± is over
undervoltage threshold and under overvoltage threshold.
Bit 1—UV3 or OV3 Fault (read only for register address). If 1, IN3 is under
undervoltage threshold or over overvoltage threshold. If 0, IN3 is over
undervoltage threshold and under overvoltage threshold.
Bit 0—UV4 or OV4 Fault (read only for register address). If 1, IN4 is under
undervoltage threshold or over overvoltage threshold. If 0, IN4 is over
undervoltage threshold and under overvoltage threshold.
Bit [7:6] If “00” the device configuration is a single device
If “01” the device configuration is multiple devices, slave
If “10” the device configuration is multiple devices, slave
If “11” the device configuration is multiple devices, master
Bit 5—If 1, latch-on fault
If 0, autoretry
Bit [4:±] “000” autoretry timer value = ±5µs
“001” autoretry timer value = 1±.5ms
“010” autoretry timer value = ±5.0ms
“011” autoretry timer value = 50.0ms
“100” autoretry timer value = 100.0ms
“101” autoretry timer value = ±00.0ms
“110” autoretry timer value = 400.0ms
“111” autoretry timer value = 1600.0ms
09h
±9h
R/W
±
Bit 1—If 1, check I C enable bit
±
If 0, ignore I C enable bit
±
Bit 0—If 1 and 09h[1] = 1, I C enabled
±
If 0 and 09h[1] = 1, I C disabled
______________________________________________________________________________________ 33
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Table 16. Register Map (continued)
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
READ/WRITE
DESCRIPTION
Bit [7:6] “00” fault power-up timer value = ±5ms
“01” fault power-up timer value = 50ms
“10” fault power-up timer value = 100ms
“11” fault power-up timer value = ±00ms
Bit [5:4] “00” fault power-down timer value = ±5ms
“01” fault power-down timer value = 50ms
“10” fault power-down timer value = 100ms
“11” fault power-down timer value = ±00ms
0Ah
±Ah
R/W
Bit 3—Reserved (write 0’s for EEPROM writes)
Bit ±—Reserved (write 0’s for EEPROM writes)
Bit 1—Reserved (write 0’s for EEPROM writes)
Bit 0—Reserved (write 0’s for EEPROM writes)
Bit 7—If 1, OUT4 on ramp ±
Bit 6—If 1, OUT3 on ramp ±
Bit 5—If 1, OUT± on ramp ±
Bit 4—If 1, OUT1 on ramp ±
Bit 3—If 1, OUT4 on ramp 1
0Bh
±Bh
R/W
Bit ±—If 1, OUT3 on ramp 1
Bit 1—If 1, OUT± on ramp 1
Bit 0—If 1, OUT1 on ramp 1
Bit 7—If 1, OUT4 on ramp 4
Bit 6—If 1, OUT3 on ramp 4
Bit 5—If 1, OUT± on ramp 4
Bit 4—If 1, OUT1 on ramp 4
Bit 3—If 1, OUT4 on ramp 3
0Ch
±Ch
R/W
Bit ±—If 1, OUT3 on ramp 3
Bit 1—If 1, OUT± on ramp 3
Bit 0—If 1, OUT1 on ramp 3
Bit [7:6] “00” IN4 to OUT4 overcurrent threshold = 97.5%
“01” IN4 to OUT4 overcurrent threshold = 95%
“10” IN4 to OUT4 overcurrent threshold = 9±.5%
“11” IN4 to OUT4 overcurrent threshold = 90%
Bit [5:4] “00” IN3 to OUT3 overcurrent threshold = 97.5%
“01” IN3 to OUT3 overcurrent threshold = 95%
“10” IN3 to OUT3 overcurrent threshold = 9±.5%
“11” IN3 to OUT3 overcurrent threshold = 90%
0Dh
±Dh
R/W
Bit [3:±] “00” IN± to OUT± overcurrent threshold = 97.5%
“01” IN± to OUT± overcurrent threshold = 95%
“10” IN± to OUT± overcurrent threshold = 9±.5%
“11” IN± to OUT± overcurrent threshold = 90%
Bit [1:0] “00” IN1 to OUT1 overcurrent threshold = 97.5%
“01” IN1 to OUT1 overcurrent threshold = 95%
“10” IN1 to OUT1 overcurrent threshold = 9±.5%
“11” IN1 to OUT1 overcurrent threshold = 90%
34 ______________________________________________________________________________________
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Table 16. Register Map (continued)
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
READ/WRITE
DESCRIPTION
Bit [7:6] “00” overcurrent timer value = 1±.5ms
“01” overcurrent timer value = 50ms
“10” overcurrent timer value = 100ms
“11” overcurrent timer value = ±00ms
Bit 5—If 1, overcurrent monitoring on OUT1 is enabled
If 0, no overcurrent monitoring on OUT1
Bit 4—If 1, overcurrent monitoring on OUT± is enabled
0Eh
±Eh
R/W
If 0, no overcurrent monitoring on OUT±
Bit 3—If 1, overcurrent monitoring on OUT3 is enabled
If 0, no overcurrent monitoring on OUT3
Bit ±—If 1, overcurrent monitoring on OUT4 is enabled
If 0, no overcurrent monitoring on OUT4
Bit [1:0] Not used
Bit [7:5] “000” gate1-delay timer value = ±5µs
“001” gate1-delay timer value = 1±.5ms
“010” gate1-delay timer value = ±5.0ms
“011” gate1-delay timer value = 50.0ms
“100” gate1-delay timer value = 100.0ms
“101” gate1-delay timer value = ±00.0ms
“110” gate1-delay timer value = 400.0ms
“111” gate1-delay timer value = 1600.0ms
Bit 4—Not used
0Fh
±Fh
R/W
Bit 3—OC1 overcurrent fault (read only for register address). If 1, OC1 is
overcurrent. If 0, OC1 is not overcurrent.
Bit ±—OC± overcurrent fault (read only for register address). If 1, OC± is
overcurrent. If 0, OC± is not overcurrent.
Bit 1—OC3 overcurrent fault (read only for register address). If 1, OC3 is
overcurrent. If 0, OC3 is not overcurrent.
Bit 0—OC4 overcurrent fault (read only for register address). If 1, OC4 is
overcurrent. If 0, OC4 is not overcurrent.
Bit [7:6] “00” IN4 to OUT4 power-good threshold = 95%
“01” IN4 to OUT4 power-good threshold = 9±.5%
“10” IN4 to OUT4 power-good threshold = 90%
“11” IN4 to OUT4 power-good threshold = 87.5%
Bit [5:4] “00” IN3 to OUT3 power-good threshold = 95%
“01” IN3 to OUT3 power-good threshold = 9±.5%
“10” IN3 to OUT3 power-good threshold = 90%
“11” IN3 to OUT3 power-good threshold = 87.5%
10h
30h
R/W
Bit [3:±] “00” IN± to OUT± power-good threshold = 95%
“01” IN± to OUT± power-good threshold = 9±.5%
“10” IN± to OUT± power-good threshold = 90%
“11” IN± to OUT± power-good threshold = 87.5%
Bit [1:0] “00” IN1 to OUT1 power-good threshold = 95%
“01” IN1 to OUT1 power-good threshold = 9±.5%
“10” IN1 to OUT1 power-good threshold = 90%
“11” IN1 to OUT1 power-good threshold = 87.5%
______________________________________________________________________________________ 35
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Table 16. Register Map (continued)
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
READ/WRITE
DESCRIPTION
Bit 7—If 1, OUT1 also controls RESET
If 0, OUT1 does not control RESET
Bit 6—If 1, OUT± also controls RESET
If 0, OUT± does not control RESET
Bit 5—If 1, OUT3 also controls RESET
If 0, OUT3 does not control RESET
Bit 4—If 1, OUT4 also controls RESET
If 0, OUT4 does not control RESET
11h
31h
R/W
Bit [3:1] “000” reset timer value = ±5µs
“001” reset timer value = 1±.5ms
“010” reset timer value = ±5.0ms
“011” reset timer value = 50.0ms
“100” reset timer value = 100.0ms
“101” reset timer value = ±00.0ms
“110” reset timer value = 400.0ms
“111” reset timer value = 1600.0ms
Bit 0. If 1, selects external reference, if 0 internal reference selected
Bit [7:6] “00” track/sequence slew rate (rise or fall) = 800V/s
“01” track/sequence slew rate (rise or fall) = 400V/s
“10” track/sequence slew rate (rise or fall) = ±00V/s
“11” track/sequence slew rate (rise or fall) = 100V/s
1±h
3±h
R/W
Bit [5:3] Not used
Bit ±—Reserved (write 0’s for EEPROM writes)
Bit 1—Reserved (write 0’s for EEPROM writes)
Bit 0—Reserved (write 0’s for EEPROM writes)
Bit 7—If 1, reverse order of track/sequence power-down
If 0, GATE_ fast pulldown
Bit 6—If 1, OUT1 pulldown with 100Ω
If 0, OUT1 100Ω pulldown disabled
Bit 5—If 1, it is possible to discharge OUT± with a pulldown
If 0, no pulldown is allowed
13h
33h
R/W
Bit 4—If 1, it is possible to discharge OUT3 with a pulldown
If 0, no pulldown is allowed
Bit 3—If 1, it is possible to discharge OUT4 with a pulldown
If 0, no pulldown is allowed
Bit ±—If 1, configuration registers are locked
If 0, configuration registers unlocked
Bit [1:0] not used
14h
15h
16h
34h
35h
36h
—
—
—
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
36 ______________________________________________________________________________________
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Table 16. Register Map (continued)
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
READ/WRITE
DESCRIPTION
Reserved. Should not be overwritten.
17h
37h
—
—
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
18h
38h
19h
1Ah
1Bh
1Ch
39h
3Ah
3Bh
3Ch
—
—
—
—
1Dh
1Eh
3Dh
3Eh
—
—
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
Reserved. Should not be overwritten.
1Fh
3Fh
—
changes actually take place, unless when changing one
of the voltage detector’s thresholds. Changing a volt-
age-detector threshold typically takes 150µs. When
changing EEPROM contents, software reboot or cycling
of power is required for these changes to transfer to
volatile memory.
Applications Information
Layout and Bypassing
For better noise immunity, bypass each of the voltage-
detector inputs to GND with 0.1µF capacitors installed
as close to the device as possible. Bypass ABP to GND
with 1µF capacitors installed as close to the device as
possible. ABP is an internally generated voltage and
should not be used to supply power to external circuitry.
Chip Information
Configuration Latency Period
A delay of less than 5µs occurs between writing to the
configuration registers and the time when these
PROCESS: BiCMOS
______________________________________________________________________________________ 37
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Typical Application Circuits
IN1
IN2
IN3
IN4
OUT1
OUT2
OUT3
OUT4
IN1
IN2
IN3
IN4 GATE1 GATE2 GATE3 GATE4
OUT1
V
CC
FAULT
HOLD
OUT2
OUT3
OUT4
RESET
REM
MAX6876
SYNCH
TRKEN
V
PULLUP
ENABLE
ABP
GND
SDA
SCL
A0
A1
PG_
OUT5
OUT1
IN5
IN1
IN2
IN3
IN4
3.3V
5V
IN6
IN7
IN8
2.5V
OUT6
OUT7
OUT8
3.0V
OUT2
OUT3
OUT4
1.5V
1.8V
0.75V
1V
OUT4
IN4 GATE1 GATE2 GATE3 GATE4 OUT1 OUT2 OUT3
IN1
IN2
IN3
IN4 GATE1 GATE2 GATE3 GATE4 OUT1
OUT3
OUT4
OUT2
IN1
IN2
IN3
SYNCH (IN)
SYNCH (OUT)
HOLD
HOLD
SLAVE
MASTER
FAULT
FAULT
V
V
CC
CC
ENABLE ABP
ABP
ENABLE
TRKEN
TRKEN
ALWAYS ON
3.3V
NOTE: CONFIGURING THE MAX6876 FOR MASTER/SLAVE OPERATION.
38 ______________________________________________________________________________________
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
D
C
L
b
D/2
D2/2
k
E/2
E2/2
(NE-1) X
e
C
L
E
E2
k
L
e
(ND-1) X
e
e
L
C
C
L
L
L1
L
L
e
e
A
A1
A2
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
1
E
21-0141
2
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
2
E
21-0141
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 39
© ±004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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