MAX6881ETE+ [MAXIM]
Dual-/Triple-Voltage, Power-Supply Sequencers/Supervisors; 双/三电压，电源排序器/监控器
| 型号： | MAX6881ETE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual-/Triple-Voltage, Power-Supply Sequencers/Supervisors |
| 文件： | 总19页 (文件大小：422K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3772; Rev 1; 10/05
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
General Description
Features
The MAX6880–MAX6883 dual-/triple-voltage monitors
are designed to sequence power supplies during
power-up condition. When all of the voltages exceed
their respective thresholds, these devices turn on volt-
ages to the system sequentially, enhancing n-channel
MOSFETs used as switches. The time between each
sequenced voltage is determined by an external
capacitor, thus allowing flexibility in delay timing. The
MAX6880/MAX6881 sequence three voltages and the
MAX6882/MAX6883 sequence two voltages.
♦ Capacitor-Adjustable Power-Up Sequencing
Delay
♦ Internal Charge Pumps to Enhance External
n-Channel FETs
♦ Capacitor-Adjustable Timeout Period Power-Good
Output (MAX6880/MAX6882)
♦ Adjustable Undervoltage Lockout or
Logic-Enable Input
♦ Internal 100Ω Pulldown for Each Output to
These devices initially monitor all of the voltages and
when all of them are within their tolerances, the inter-
nal charge pumps enhance external n-channel
MOSFETs in a sequential manner to apply the volt-
ages to the system. Internal charge pumps drive the
gate voltages 5V above the respective input voltage
thereby ensuring the MOSFETs are fully enhanced to
reduce the on-resistance.
Discharge Capacitive Load Quickly
♦ 0.5V to 5.5V Nominal IN_/OUT_ Range
♦ 2.7V to 5.5V Operating Voltage Range
♦ Immune to Short Voltage Transients
♦ Small 4mm x 4mm 24-Pin or 16-Pin Thin QFN
Packages
The MAX6880–MAX6883 feature capacitor-adjustable
slew-rate control to provide controlled turn-on charac-
teristics. After all of the voltages reach 92.5% of their
final value, a power-good output (MAX6880/MAX6882)
signal is active. The power-good output (PG/RST) can
be delayed with an external capacitor to create a
power-on reset delay. After the initial power-up phase,
the MAX6880–MAX6883 continue to monitor the volt-
ages. If any of the voltages falls below its threshold, the
MOSFETs are quickly turned off and the voltages are
tracked down together. An internal 100Ω pulldown
resistor ensures that the capacitance at the MOSFET’s
source is discharged quickly. The power-good output
goes low to provide a system reset.
Ordering Information
PIN-
PACKAGE
PKG
CODE
PART
TEMP RANGE
MAX6880ETG+
MAX6881ETE+
MAX6882ETE+
MAX6883ETE+
-40°C to +85°C 24 Thin QFN T2444-4
-40°C to +85°C 16 Thin QFN T1644-4
-40°C to +85°C 16 Thin QFN T1644-4
-40°C to +85°C 16 Thin QFN T1644-4
+Denotes lead-free package.
Pin Configurations
TOP VIEW
The MAX6880–MAX6883 are available in small 4mm x
4mm 24-pin and 16-pin thin QFN packages and speci-
fied over the -40°C to +85°C extended operating tem-
perature range.
18
17
16
15
14
13
12
11
10
9
GATE2 19
OUT1 20
GATE1 21
IN3 22
N.C.
Applications
Multivoltage Systems
N.C.
TIMEOUT
MAX6880
Networking Systems
SLEW
DELAY
GND
Telecom
EP*
IN2
IN1
8
23
24
+
Storage Equipment
7
Servers/Workstations
1
2
3
4
5
6
4mm x 4mm THIN QFN
*EXPOSED PADDLE CONNECTED TO GND.
Selector Guide appears at end of data sheet.
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND, unless otherwise noted.)
IN1, IN2, IN3.............................................................-0.3V to +6V
ABP .........................................-0.3V to the highest of V
Input/Output Current (all pins except
OUT_ and GND) ........................................................... 20mA
V
IN1 - IN3
SET1, SET2, SET3 ....................................................-0.3V to +6V
GATE1, GATE2, GATE3 .........................................-0.3V to +12V
OUT1, OUT2, OUT3 .................................................-0.3V to +6V
MARGIN ...................................................................-0.3V to +6V
PG/RST, EN/UV ........................................................-0.3V to +6V
DELAY, SLEW, TIMEOUT.........................................-0.3V to +6V
OUT_ Current.................................................................... 50mA
GND Current..................................................................... 50mA
Continuous Power Dissipation (T = +70°C)
A
16-Pin 4mm x 4mm Thin QFN
(derate 16.9mW/°C above +70°C).............................1349mW
24-Pin 4mm x 4mm Thin QFN
(derate 20.8mW/°C above +70°C).............................1667mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(IN1, IN2, or IN3 = +2.7V to +5.5V, EN/UV = MARGIN = ABP, T = -40°C to +85°C, unless otherwise specified. Typical values are
A
at T = +25°C, unless otherwise noted.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Voltage on the highest of IN_ to ensure that
PG/RST is valid and GATE_ = 0
1.4
Operating Voltage Range
IN_
V
Voltage on the highest of IN_ to ensure the
device is fully operational
2.7
5.5
Supply Current
I
IN1 = 5.5V, IN2 = IN3 = 3.3V, no load
1.1
0.5
0.5
0.5
1.8
mA
V
CC
SET_ falling, T = +25oC
0.4925
0.4875
0.5075
0.5125
A
SET_ Threshold Range
V
TH
SET_ falling, T = -40°C to +85°C
A
SET_ Threshold Hysteresis
SET_ Input Current
V
SET_ rising
SET_ = 0.5V
Input rising
Input falling
%
TH_HYST
I
-100
+100
nA
SET
V
1.286
1.25
EN_R
EN_F
EN/UV Input Voltage
V
V
1.22
-5
1.28
+5
EN/UV Input Current
I
t
µA
µs
EN
EN
EN/UV Input Pulse Width
DELAY, TIMEOUT Output Current
EN/UV falling, 100mV overdrive
7
I
D
(Notes 2, 3)
2.12
2.5
1.25
25
2.88
µA
DELAY, TIMEOUT Threshold
Voltage
V
= 3.3V
V
CC
SLEW Output Current
I
(Note 4)
= 200pF
22.5
-15
27.5
+15
µA
%
S
Sequence Slew-Rate Timebase
Accuracy
SR
C
SLEW
Timebase/C
Ratio
100pF < C
< 1nF
104
kΩ
%
SLEW
SLEW
Slew-Rate Accuracy during Power-
Up and Power-Down
C
= 200pF, V
= 5.5V (Note 4)
-50
+50
SLEW
IN_
2
_______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
ELECTRICAL CHARACTERISTICS (continued)
(IN1, IN2, or IN3 = +2.7V to +5.5V, EN/UV = MARGIN = ABP, T = -40°C to +85°C, unless otherwise specified. Typical values are
A
at T = +25°C, unless otherwise noted.) (Note 1)
A
Power-Good Threshold
V
V
V
falling
rising
91.5
92.5
0.5
93.5
%
%
TH_PG
OUT_
OUT_
Power-Good Threshold Hysteresis
V
HYS_PG
IN_ +
4.2
IN_ +
5.0
IN_ +
5.8
GATE_ Output High
V
I
= 0.5µA
V
GOH
SOURCE
During power-up and power-down,
= 1V
GATE_ Pullup Current
I
2.5
2.5
4
4
µA
µA
GUP
V
GATE_
During power-up and power-down,
= 5V
I
GD
V
GATE_
GATE_ Pulldown Current
When disabled, V
When disabled, V
= 5V, V
= 5V, V
≥ 2.7V
≥ 4V
9.5
20
10
GATE_
GATE_
IN_
IN_
I
mA
µs
V
GDS
SET_ to GATE_ Delay
t
SET falling, 25mV overdrive
D-GATE
V
V
≥ 2.7V, I
≥ 4.0V, I
= 1mA, output asserted
= 4mA, output asserted
0.3
0.4
IN_
IN_
SINK
SINK
PG/RST Output Low
V
OL
Differential between each of the OUT_ and
the ramp voltage during power-up and
power-down, Figure 1 (Note 5)
Tracking Differential Voltage Stop
Ramp
V
75
125
250
180
mV
mV
TRK
Differential between each of the OUT_ and
the ramp voltage, Figure 1 (Note 5)
Tracking Differential Fault Voltage
V
200
125
310
170
TRK_F
TH_PL
Power-Low Threshold
V
OUT_ falling
142
10
mV
mV
Ω
Power-Low Hysteresis
V
OUT_ rising
TH_PLHYS
OUT to GND Pulldown Impedance
MARGIN Pullup Current
IN_ > 2.7V (Note 6)
100
10
I
7
13
µA
IN
V
0.8
IL
MARGIN Input Voltage
V
V
2.0
IH
MARGIN Glitch Rejection
100
ns
Note 1: Specifications guaranteed for the stated global conditions. 100% production tested at T = +25°C and T = +85°C.
A
A
Specifications at T = -40°C to +85°C are guaranteed by design. These devices meet the parameters specified when at
A
least one of IN1/IN2/IN3 is between 2.7V to 5.5V, while the remaining IN1/IN2/IN3 are between 0 and 5.5V.
Note 2: A current I = 2.5µA 15% is generated internally and is used to set the DELAY and TIMEOUT periods and used as a refer-
D
ence for t
and t
.
DELAY
TIMEOUT
Note 3: The total DELAY is t
= 200µs + (500kΩ x C
). Leave DELAY unconnected for 200µs delay. The total TIMEOUT is
DELAY
DELAY
t
= 200µs + (500kΩ x C ). Leave TIMEOUT unconnected for 200µs timeout.
TIMEOUT
TIMEOUT
Note 4: A current I = 25µA 10% is generated internally and used as a reference for t
, t
, and slew rate.
S
FAULT RETRY
Note 5: During power-up, only the condition OUT_ < ramp - V
is checked in order to stop the ramp. However, both conditions
TRK
OUT_ < ramp – V
and OUT_ > ramp + V
cause a fault. During power-down, only the condition OUT > ramp +
TRK_F
TRK_F
V
TRK
is checked in order to stop the ramp. However, both conditions OUT_ < ramp - V
and OUT_ > ramp + V
TRK_F TRK_F
cause a fault (see Figure 10). Therefore, if OUT1, OUT2, and OUT3 (during power-up tracking and power-down) differ by
more than 2 x V , a fault condition is asserted.
TRK_F
Note 6: A 100Ω pulldown to GND activated by a fault condition. See the Internal Pulldown section.
_______________________________________________________________________________________
3
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
250mV UP =
250mV UP =
FAULT THRESHOLD
FAULT THRESHOLD
125mV UP =
STOP RAMP THRESHOLD
125mV DOWN =
STOP RAMP THRESHOLD
250mV DOWN =
FAULT THRESHOLD
250mV DOWN =
FAULT THRESHOLD
REFERENCE RAMP
REFERENCE RAMP
POWER-UP
POWER-DOWN
Figure 1. Stop Ramp/Fault Window During Power-Up and Power-Down
EN/UV
EN/UV
BUS VOLTAGE MONITORED THROUGH EN/UV INPUT
V
EN_R
V
EN_F
IN1 = 3.3V
IN2 = 1.8V
IN3 = 0.7V
IN_
MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS
CAPACITOR-
ADJUSTED
SLEW RATE
OUT1 = 3.3V
OUT2 = 1.8V
OUT3 = 0.7V
OUT_
t
t
DELAY
DELAY
t
DELAY
PG/RST
t
TIMEOUT
Figure 2. Sequencing In Normal Mode
_______________________________________________________________________________________
4
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
EN/UV
EN/UV
BUS VOLTAGE MONITORED THROUGH EN/UV INPUT
V
EN_R
IN1 = 3.3V
IN2 = 1.8V
IN3 = 0.7V
IN_
MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS
OUT_ FORCED
BELOW V
CAPACITOR-
ADJUSTED
SLEW RATE
TH_PG
OUT1 = 3.3V
OUT2 = 1.8V
OUT3 = 0.7V
OUT_
t
t
DELAY
DELAY
t
DELAY
PG/RST
t
TIMEOUT
FORCED INTO QUICK SHUTDOWN WHEN OUT1 FALLS BELOW 92.5% of IN1
Figure 3. Sequencing In Fast Shutdown Mode
_______________________________________________________________________________________
5
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
EN/UV
EN/UV
BUS VOLTAGE MONITORED
THROUGH EN/UV INPUT
V
EN_R
V
EN_F
IN1 = 3.3V
IN2 = 1.8V
IN3 = 0.7V
IN_
MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS
CAPACITOR-
ADJUSTED
SLEW RATE
OUT1 = 3.3V
OUT2 = 1.8V
OUT_
OUT3 = 0.7V
t
t
DELAY
DELAY
t
DELAY
t
TIMEOUT
PG/RST = LOW
Figure 4. Timing Diagram (Aborted Sequencing)
EN/UV
V
EN_R
OUT1
OUT1
OUT2
OUT2
OUT_
OUT3 IS SLOW
OUT3 IS SLOW
t
t
DELAY
t
FAULT
FAULT
t
DELAY
t
DELAY
t
RETRY
t
t
DELAY
DELAY
t
DELAY
t
AND t
NOT TO SCALE
FAULT
RETRY
ALL SET > 0.5V AND IN_ ≥ 2.7V
Figure 5. t
FAULT
and t
Timing Diagram in Sequencing
RETRY
6
_______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
Typical Operating Characteristics
(V
= 2.7V to 5.5V, C
= 200pF, EN = MARGIN = ABP, T = +25°C, unless otherwise noted.)
IN_
SLEW A
V
SUPPLY CURRENT
vs. INPUT VOLTAGE
NORMALIZED POWER-GOOD TIMEOUT
vs. TEMPERATURE
POWER-GOOD TIMEOUT
CC
vs. C
TIMEOUT
1.4
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
1000
100
10
1.3
1.2
1.1
1.0
0.9
0.8
T
= +85°C
A
T
= +25°C
A
1
T
= -40°C
A
0.1
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-15
10
35
60
85
0.0001
0.001
0.01
0.1
1
INPUT VOLTAGE (V)
TEMPERATURE (°C)
C
(µF)
DELAY
NORMALIZED SET_ THRESHOLD
vs. TEMPERATURE
NORMALIZED DELAY TIMEOUT
vs. TEMPERATURE
SLEW RATE
vs. C
SLEW
1.005
1.004
1.003
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.995
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
10,000
1000
100
10
-40
-15
10
35
60
85
-40
-15
10
35
60
85
10
100
1000
10,000
TEMPERATURE (°C)
TEMPERATURE (°C)
C
(pF)
SLEW
DELAY TIMEOUT
NORMALIZED EN/UV THRESHOLD
vs. TEMPERATURE
IN_ TRANSIENT DURATION
vs. IN THRESHOLD OVERDRIVE
vs. C
DELAY
1000
100
10
1.005
1.004
1.003
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.995
30
27
24
21
18
15
12
9
IN_ = 3.3V
PG/RST GOES LOW ABOVE THE CURVE
1
6
3
0.1
0
0.0001
0.001
0.01
(µF)
0.1
1
-40
-15
10
35
60
85
0
50
100
150
200
250
300
C
TEMPERATURE (°C)
IN_ THRESHOLD OVERDRIVE (mV)
DELAY
_______________________________________________________________________________________
7
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
Typical Operating Characteristics (continued)
(V
= 2.7V to 5.5V, C
= 200pF, EN = MARGIN = ABP, T = +25°C, unless otherwise noted.)
IN_
SLEW
A
GATE_ VOLTAGE LOW
vs. SINK CURRENT
GATE_ OUTPUT VOLTAGE HIGH
vs. GATE SOURCE CURRENT
SEQUENCING MODE
MAX6880 toc12
1.6
10
9
8
7
6
5
4
3
2
1
0
EN/UV
2V/div
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
OUT1
1V/div
OUT2
1V/div
OUT3
1V/div
20ms/div
0
1
2
3
4
5
6
7
8
9
10
0
0.5
1.0
1.5
2.0
2.5
3.0
GATE SINK CURRENT (mA)
GATE SOURCE CURRENT (µA)
FAST SHUTDOWN WITH RETRY
FAST SHUTDOWN WITH RETRY
MAX6880 toc13
MAX6880 toc14
EN/UV
2V/div
OUT1
2V/div
OUT2
2V/div
OUT1
1V/div
OUT3 PULLED BELOW
92.5% OF IN3 FOR
OUT2
1V/div
SEQUENCING MODE
OUT3
2V/div
OUT3
1V/div
PG/RST
1V/div
40ms/div
100ms/div
8
_______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
Pin Description
PIN
NAME
FUNCTION
MAX6880 MAX6881 MAX6882 MAX6883
1, 11,
12, 15
—
—
1, 8, 9, 10
N.C.
No Connection. Not internally connected.
Internal Supply Bypass Input. Bypass ABP with a 1µF capacitor to
GND. ABP maintains the device supply voltage during rapid power-
down conditions.
2
—
1
—
ABP
3
4
2
3
—
2
—
2
SET3
SET2
Externally Adjusted IN_ Undervoltage Lockout Threshold. Connect
SET_ to an external resistor-divider network to set the desired
undervoltage threshold for each IN_ supply (see the Typical
Application Circuit). All SET_ inputs must be above the internal
SET_ threshold (0.5V) to enable sequencing functionality.
5
4
3
3
SET1
Logic-Enable Input or Undervoltage Lockout Monitor Input. EN/UV
must be high (EN/UV > V
) to enable voltage sequencing
EN_R
6
7
8
5
6
7
4
5
6
4
5
6
EN/UV
GND
power-up operation. OUT_ begins tracking down when EN/UV <
. Connect EN/UV to an external resistor-divider network to set
the external UVLO threshold.
Ground
V
EN_F
Sequence Delay Select Input. Connect a capacitor from DELAY
to GND to select the desired delay period before sequencing is
enabled (after all SET_ inputs and EN/UV are above their respective
thresholds) or between supply sequences. Leave DELAY
unconnected for the default 200µs delay period.
DELAY
Slew-Rate Adjustment Input. Connect a capacitor from SLEW
to GND to select the desired OUT_ slew rate.
9
8
7
8
7
SLEW
PG/RST Timeout Period Adjust Input. PG/RST asserts high after the
timeout period when all OUT_ exceed their IN_ referenced
TIMEOUT threshold. Connect a capacitor from TIMEOUT to GND to set the
desired timeout period. Leave TIMEOUT unconnected for the
default 200µs delay period.
10
—
—
Margin Input, Active-Low. Drive MARGIN low to enable margin
mode (see the Margin section). The MARGIN functionality is
MARGIN disabled (returns to normal monitoring mode) after MARGIN returns
high. MARGIN is internally pulled up to ABP through a 10µA
current source.
13
—
9
—
_______________________________________________________________________________________
9
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
Pin Description (continued)
PIN
NAME
FUNCTION
MAX6880 MAX6881 MAX6882 MAX6883
Power-Good Output, Open-Drain. PG_RST asserts high t
TIMEOUT
14
—
10
—
PG/RST
after all OUT_ voltages exceed the V
thresholds.
TH_PG
Channel 3 Monitored Output Voltage. Connect OUT3 to the source
of an n-channel FET. A fault condition activates a 100Ω pulldown to
ground.
16
9
—
—
OUT3
GATE3
OUT2
Gate Drive for External n-Channel FET. An internal charge pump
boosts GATE3 to V
+ 5V to fully enhance the external n-channel
17
18
19
20
21
10
11
12
13
14
—
11
12
13
14
—
11
12
13
14
IN3
FET when power-up is complete.
Channel 2 Monitored Output Voltage. Connect OUT2 to the source
of an n-channel FET. A fault condition activates a 100Ω pulldown to
ground.
Gate Drive for External n-Channel FET. An internal charge pump
boosts GATE2 to V
+ 5V to fully enhance the external n-channel
GATE2
OUT1
IN2
FET when power-up is complete.
Channel 1 Monitored Output Voltage. Connect OUT1 to the source
of an n-channel FET. A fault condition activates a 100Ω pulldown to
ground.
Gate Drive for External n-Channel FET. An internal charge pump
GATE1
boosts GATE1 to V
+ 5V to fully enhance the external n-channel
IN1
FET when power-up is complete.
Supply Input Voltage. IN1, IN2, or IN3 must be greater than the
22
23
15
16
—
—
IN3
IN2
internal undervoltage lockout (V
= 2.7V) to enable the
ABP
sequencing functionality. Each IN_ input is simultaneously
monitored by SET_ inputs to ensure all supplies have stabilized
before power-up is enabled. If IN_ is connected to ground or left
unconnected and SET_ is above 0.5V, then no sequencing control
is performed on that channel. Each IN_ is internally pulled down by
a 100kΩ resistor.
15
15
24
EP
1
16
EP
16
EP
IN1
EP
EP
Exposed Paddle. Connect exposed paddle to ground.
10 ______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
Functional Diagram
IN1
TO LOAD
IN2 IN3
OUT1
GATE1
IN1
ABP
INTERNAL
/UVLO
V
IN1
CC
MAX6880
CHARGE
PUMP
SET1
RAMP
GENERATOR
IN2
COMP
GATE
CONTROLLER
SET2
SET3
IN3
COMP
COMP
COMP
CONTROL
LOGIC
GATE2
OUT2
IN2 TO OUT2
CONTROL BLOCK
VBUS
OUT1
OUT2
OUT3
IN1
GATE3
OUT3
IN3 TO OUT3
CONTROL BLOCK
EN/UV
SEQUENCING
MONITOR
IN2
IN3
V
REF
PG CIRCUIT
MARGIN
GND
DELAY
SLEW
TIMEOUT
PG/RST
C
SLEW
C
TIMEOUT
______________________________________________________________________________________ 11
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
when its output voltage exceeds a fixed percentage
(V ) of the corresponding IN_ voltage. When all
Detailed Description
TH_PG
The MAX6880–MAX6883 multivoltage power
sequencers/supervisors monitor three (MAX6880/
MAX6881) and two (MAX6882/MAX6883) system volt-
ages and provide proper power-up and power-down
control for systems requiring voltage sequencing. These
devices ensure the controlled voltages sequence in the
proper order as system power supplies are enabled.
The MAX6880–MAX6883 generate all required voltages
and timing to control up to three external n-channel
pass FETs for the OUT1/OUT2/OUT3 supply voltages.
channels have exceeded these thresholds, PG/RST
asserts high after t
sequence.
, indicating a successful
TIMEOUT
If there is a fault condition during the initial power-up
sequence, the process is aborted.
When powering down, all outputs turn off simultaneous-
ly, tracking each other. No reverse power-down
sequencing occurs.
The power-supply sequencing operation should be
completed within the selected fault timeout period
The MAX6880–MAX6883 feature adjustable undervolt-
age thresholds for each input supply. When all of the
voltages are above the adjusted thresholds these
devices turn on the external n-channel MOSFETs to
sequence the voltages to the system. The outputs are
turned on one after the other, OUT1 first and OUT3 last.
(t
) (see Figure 5). The total sequencing time is
FAULT
extended when the devices must vary the control slew
rate to allow slow supplies to catch up. If the external
FET is too small (R
is too high for the selected load
DS
current and IN_ source current), the OUT_ voltage may
never reach the control ramp voltage. For a slew rate of
935V/s, a fault is signaled if all outputs have not stabi-
lized within 22ms. For a slew rate of 93.5V/s, a fault is
signaled if sequencing takes too long (more than
219ms).
The MAX6880–MAX6883 feature internal charge pumps
to fully enhance the external FETs for low-voltage drops
at highpass currents. The MAX6880/MAX6882 also fea-
ture a power-good output (PG/RST) with a selectable
timeout period that can be used for system reset.
The fault time period (t
) is set through the capaci-
FAULT
The MAX6880–MAX6883 monitor up to three voltages.
Devices may be configured to exclude any IN_. To dis-
able sequencing operation of any IN_, connect the IN_
to ground (or leave unconnected) and connect SET_ to
a voltage greater than 0.5V. The channel exclusion fea-
ture adds more flexibility to the device in a variety of
different applications. As an example, the MAX6880
can sequence two voltages using IN1 and IN2 while
IN3 is left disabled.
tor at SLEW (C
). Use the following formula to esti-
SLEW
mate the fault timeout period:
= 2.191 x 108 x C
t
FAULT
SLEW
Autoretry Function
The MAX6880/MAX6881/MAX6882 feature autoretry
modes to power-on again after a fault condition has been
detected (see the Typical Operating Characteristics).
When a fault is detected, for a period of t
, GATE_
RETRY
Powering the MAX6880–MAX6883
These devices derive power from either IN1, IN2, or IN3
voltage inputs (see the Functional Diagram). In order to
ensure proper operation, at least one of the IN_ inputs
must be at least +2.7V.
remains off and the 100Ω pulldowns are turned on.
After the t period, the device waits t and
RETRY
DELAY
retry sequencing if all power-up conditions are met
(see Figure 5). These include all V
> 0.5V, EN/UV >
SET_
V
, and OUT_ voltages < V
. The autoretry
EN_R
TH_PL
(see Table 1).
SLEW
The highest input voltage on IN1/IN2/IN3 supplies
power to the devices. Internal hysteresis ensures that
the supply input that initially powers these devices con-
tinues to power the MAX6880–MAX6883 when multiple
input voltages are within 100mV (typ) of each other.
period t
is a function of C
RETRY
Power-Up and Power-Down
During power-up, OUT_ is forced to follow the internal
reference ramp voltage by an internal loop that controls
the GATE_ of the external MOSFET. This phase must
be completed within the adjustable fault timeout period
Sequencing
The sequencing operation can be initiated after all
(t
); otherwise, the part forces a shutdown on all
FAULT
input conditions for power-up are met V
> 1.25V
EN/UV
GATE_.
Once the power-up is completed, a power-down phase
can be initiated by forcing V below V . The
and all SET_ inputs are above the internal SET_ thresh-
old (0.5V). In sequencing mode, the outputs are turned
on sequentially, OUT1 first and OUT3 last. Before turn-
ing on each channel, a delay period is waited (pro-
grammable by connecting a capacitor from DELAY to
ground. The power-up phase for each channel ends
EN/UV
EN_F
reference voltage ramp ramps down at the capacitor-
adjusted slew rate. The control-loop comparators moni-
tor each OUT_ voltage with respect to the common
12 ______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
reference ramp voltage. During ramp down, if an OUT_
voltage is greater than the reference ramp voltage by
more than V , the control loop dynamically stops the
control ramp voltage from decreasing until the slow
OUT_ voltage catches up. If an OUT_ voltage is greater
or less than the reference ramp voltage by more than
Margin Input (MARGIN) (MAX6880/MAX6882)
MARGIN allows system-level testing while power sup-
plies are below the normal ranges as adjusted by the
SET_ inputs. Drive MARGIN low before varying system
voltages below the adjusted thresholds to avoid signal-
ing an error. The state of PG/RST does not change
while MARGIN is low. PG/RST and all monitoring func-
tions are disabled while MARGIN is low. MARGIN
makes it possible to vary the supplies without a need to
adjust the thresholds to prevent sequencer alerts. Drive
MARGIN high or leave it unconnected for normal oper-
ating mode.
TRK
V
, a fault is signaled and the fast-shutdown mode
TRK_F
is initiated. In fast-shutdown mode, a 100Ω pulldown
resistor is connected from OUT_ to GND to quickly dis-
charge capacitance at OUT_, and GATE_ is pulled low
with a strong I
current (see Figure 3).
GDS
Figure 4 shows the aborted sequencing mode. When
EN/UV goes low before t
expires, all the out-
TIMEOUT
Slew-Rate Control Input (SLEW)
The reference ramp voltage slew rate during any con-
trolled power-up/down phase can be programmed in
the 90V/s to 950V/s range by connecting a capacitor
puts go low, and the device goes into fast shutdown.
Internal Pulldown
To ensure that the OUT_ voltages are not held high by
a large output capacitance after a fault has occurred,
there is a 100Ω internal pulldown at OUT_. The pull-
(C
) from SLEW to ground. Use the following for-
SLEW
mula to calculate the typical slew rate:
Slew Rate = (9.35 x 10-8)/ C
down ensures that all OUT_ voltages are below V
TH_PL
SLEW
(referenced to GND) before power-up cycling is initiat-
ed. The internal pulldown also ensures a fast discharge
of the output capacitor during fast shutdown and fault
modes. The pulldowns are not present during normal
operation.
where slew rate is in V/s and C
is in farads.
SLEW
The capacitor at C
also sets the retry timeout peri-
SLEW
), see Table 1.
od (t
RETRY
For example, if C
= 100pF, we have t
=
RETRY
SLEW
350ms, t
= 21.91ms, slew rate = 935V/s. For
FAULT
Stability Comment
No external compensation is required for sequencing
or slew-rate control.
example, if C
= 1nF, we have t
= 3.5s, slew
RETRY
SLEW
rate = 93.5V/s.
C
is the capacitor on SLEW pad, and must be
SLEW
Inputs
large enough so the parasitic PC board capacitance is
negligible. C
C
should be in the range of 100pF <
SLEW
< 1nF.
IN1/IN2/IN3
The highest voltage on IN1, IN2, or IN3 supplies power
to the device. The undervoltage threshold for each IN_
supply is set with an external resistor-divider from each
IN_ to SET_ to ground. To disable sequencing on any
IN_, connect IN_ to ground (or leave unconnected) and
connect SET_ to a voltage greater than 0.5V.
SLEW
Undervoltage Lockout Threshold Inputs (SET_)
The MAX6880/MAX6881 feature three and the MAX6882/
MAX6883 feature two externally adjustable IN_ under-
voltage lockout thresholds (SET1/SET2/SET3). The 0.5V
SET_ threshold enables monitoring IN_ voltages as low
as 0.5V. The undervoltage threshold for each IN_ sup-
ply is set with an external resistor-divider from each IN_
to SET_ to ground (see Figure 6). All SET_ inputs must
be above the internal SET_ threshold (0.5V) to enable
sequencing functionality. Use the following formula to
set the UVLO threshold:
V
IN_
IN_
R1
R2
MAX6880–
MAX6883
SET_
V
= V (R1 + R2) / R2
TH
IN_
where V
TH
is the undervoltage lockout threshold and
IN_
Figure 6. Setting the Undervoltage (UVLO) Thresholds
V
is the 500mV SET threshold.
______________________________________________________________________________________ 13
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
ABP Input (MAX6880/MAX6882)
Table 1. CSLEW Timing Formulas
ABP powers the analog circuitry. Bypass ABP to GND
with a 1µF ceramic capacitor installed as close to the
device as possible. ABP takes the highest voltage of
IN_. Do not use ABP to provide power to external cir-
cuitry. ABP maintains the device supply voltage during
rapid power-down conditions.
TIME PERIOD
FORMULAS
(9.35 x 10-8) / C
Slew Rate
SLEW
t
3.506 x 109 x C
2.191 x 108 x C
RETRY
SLEW
SLEW
t
FAULT
OUT1/OUT2/OUT3
The MAX6880/MAX6881 monitor three OUT_ and the
MAX6882/MAX6883 monitor two OUT_ outputs to con-
trol the sequencing performance. After the internal sup-
ply (ABP) exceeds the minimum voltage (2.7V)
Limiting Inrush Current
The capacitor (C
) at SLEW to ground, controls the
SLEW
OUT_ slew rate, thus controlling the inrush current
required to charge the load capacitor at OUT_. Using
the programmed slew rate, limit the inrush current by
using the following formula:
requirements, EN/UV > V
, and IN1/IN2/IN3 are all
EN_R
greater than their adjusted SET_ thresholds, OUT1/
OUT2/OUT3 begin to sequence.
I
= C
x SR
INRUSH
OUT
where I
is in amperes, C
is in farads, and SR
INRUSH
is in V/s.
OUT
During fault conditions, an internal pulldown resistor
(100Ω) on OUT_ is enabled to help discharge load
capacitance (100Ω is connected for fast power-down
control).
Delay Time Input (DELAY)
To adjust the desired delay period (t ) before
DELAY
sequencing is enabled, connect a capacitor (C
)
DELAY
Outputs
between DELAY to ground (see Figures 2 to 5). The
selected delay time is also enforced when EN/UV rises
from low to high when all the input voltages are present.
Use the following formula to calculate the delay time:
GATE_
The MAX6880–MAX6883 feature up to three GATE_ out-
puts to drive up to three external n-channel FET gates.
The following conditions must be met before GATE_
begins enhancing the external n-channel FET_:
t
= 200µs + (500kΩ x C
)
DELAY
DELAY
where t
is in µs and C
is in farads. Leave
DELAY
DELAY
1) All SET_ inputs (SET1/SET2/SET3) are above their
0.5V thresholds.
DELAY unconnected for the default 200µs delay.
Timeout Period Input (TIMEOUT)
(MAX6880/MAX6882)
2) At least one IN_ input is above the minimum operat-
ing voltage (2.7V).
These devices feature a PG/RST timeout period.
3) EN/UV > 1.25V.
Connect a capacitor (C
) from TIMEOUT to
TIMEOUT
At power-up mode, GATE_ voltages are enhanced by
control loops so all OUT_ voltages sequence at a
capacitor-adjusted slew rate. Each GATE_ is internally
pulled up to 5V above its relative IN_ voltage to fully
enhance the external n-channel FET when power-up is
complete.
ground to program the PG/RST timeout period. After all
OUT_ outputs exceed their IN_ referenced thresholds
(V
), PG/RST remains low for the selected timeout
TIMEOUT
TH_PG
period t
(see Figure 3).
t
= 200µs + (500kΩ x C
)
TIMEOUT
TIMEOUT
where t
is in µs and C
is in farads.
TIMEOUT
TIMEOUT
Power-Good Output (PG/RST) (MAX6880/MAX6882)
The MAX6880/MAX6882 include a power-good (PG/RST)
output. PG/RST is an open-drain output and requires an
external pullup resistor.
Leave TIMEOUT unconnected for the default 200µs
timeout delay.
Logic-Enable Input (EN/UV)
Drive logic EN/UV input above V
sequencing during power-up operation. Drive logic
EN/UV below V to initiate tracking power-down
operation. Connect EN/UV to an external resistor-
divider network to set the external undervoltage lockout
threshold.
to initiate voltage
EN_R
All the OUT_ outputs must exceed their IN_ referenced
thresholds (IN_ x V
) for the selected reset timeout
TH_PG
EN_F
period t
(see the TIMEOUT Period Input sec-
TIMEOUT
tion) before PG/RST asserts high. PG/RST stays low for
the selected reset timeout period (t ) after all
TIMEOUT
the OUT_ voltages exceed their IN_ referenced thresh-
olds. PG/RST goes low when V < V or V
<
EN/UV
SET_
TH
V
EN_R
(see Figure 2).
14 ______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
Layout and Bypassing
Applications Information
For better noise immunity, bypass each of the IN_
inputs to GND with 0.1µF capacitors installed as close
to the device as possible. Bypass ABP to GND with a
1µF capacitor installed as close to the device as possi-
ble. ABP is an internally generated voltage and must
not be used to supply power to external circuitry.
MOSFET Selection
The external pass MOSFET is connected in series with
the sequenced power-supply source. Since the load
current and the MOSFET drain-to-source impedance
(R ) determine the voltage drop, the on characteris-
DS
tics of the MOSFET affect the load supply accuracy.
The MAX6880–MAX6883 fully enhance the external
MOSFET out of its linear range to ensure the lowest
drain-to-source on-impedance. For highest supply
accuracy/lowest voltage drop, select a MOSFET with
an appropriate drain-to-source on-impedance with a
gate-to-source bias of 4.5V to 6.0V.
Selector Guide
TIMEOUT
SELECTABLE
PG THRESHOLD
VOLTAGE (%)
PART
CHANNEL
PG/RST
MARGIN
MAX6880
MAX6881
MAX6882
MAX6883
3
3
2
2
Yes
No
Yes
No
Yes
No
92.5
—
Yes
No
Yes
No
Yes
No
92.5
—
Chip Information
PROCESS: BiCMOS
______________________________________________________________________________________ 15
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
Typical Application Circuit
OUT1
IN1
IN2
IN3
OUT2
OUT3
0.1µF
0.1µF
0.1µF
IN1
IN2
IN3
GATE1 GATE2 GATE3
SET1
OUT1
SET2
SET3
EN/UV
OUT2
MAX6880
OUT3
V
BUS
PG/RST
MARGIN
ABP
SLEW
GND
DELAY TIMEOUT
1µF
16 ______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
Pin Configurations (continued)
TOP VIEW
12
11
10
9
12
11
10
9
SLEW
TIMEOUT
8
7
6
5
8
7
6
5
OUT1 13
GATE1 14
OUT1 13
GATE1 14
IN2 15
DELAY
GND
SLEW
DELAY
GND
MAX6881
MAX6882
IN3
IN2
15
16
EP*
EP*
EN/UV
16
IN1
+
+
1
2
3
4
1
2
3
4
4mm x 4mm THIN QFN
4mm x 4mm THIN QFN
12
11
10
9
N.C.
8
7
6
5
OUT1 13
GATE1 14
SLEW
DELAY
GND
MAX6883
IN2
IN1
15
16
EP*
+
1
2
3
4
4mm x 4mm THIN QFN
*EXPOSED PADDLE CONNECTED TO GND.
______________________________________________________________________________________ 17
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
1
E
21-0139
2
18 ______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
2
E
21-0139
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2005 Maxim Integrated Products
Heaney
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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