MAX6917EO50-T [MAXIM]
Timer or RTC, Non-Volatile, CMOS, PDSO20;
| 型号： | MAX6917EO50-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Timer or RTC, Non-Volatile, CMOS, PDSO20 光电二极管 |
| 文件： | 总31页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3702; Rev 0; 5/05
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
General Description
Features
The MAX6917 provides all the features of a real-time
clock (RTC) plus a microprocessor (µP) supervisory cir-
cuit, NV RAM controller, and backup-battery monitor
function. In addition, 96 x 8 bits of static RAM are avail-
able for scratchpad storage. The MAX6917 communi-
♦ Real-Time Clock Counts
Seconds, Minutes, Hours, Date,
Month, Day of Week, and Year
with Leap-Year Compensation Through 2099
†
2
2
cates with a µP through an I C -bus-compatible serial
♦ Fast (400kHz) I C-Bus-Compatible Interface
interface.
♦ 96 x 8 Bits of RAM for Scratchpad Data Storage
The real-time clock/calendar provides seconds, min-
utes, hours, day, date, month, and year information.
The end of the month date is automatically adjusted for
months with fewer than 31 days, including corrections
for leap years through 2099. The clock operates in
either 24hr or 12hr format with an AM/PM indicator. A
time/date-programmable alarm function is provided
with an open-drain, active-low alarm output.
♦ Uses Standard 32.768kHz, 6pF Load, Watch
Crystal
♦ Single-Byte or Multiple-Byte (Burst Mode) Data
Transfer for Read or Write of Clock Registers or
RAM
♦ Battery Monitor and Low-Battery Warning Output
Internal Default for Lithium Backup-Battery
Testing
The µP supervisory circuit features an open-drain,
active-low reset available in three different reset thresh-
olds. A manual reset input and a watchdog function are
included as well.
Pins Available for Other Backup-Battery
Testing Configurations
The NV RAM controller provides power for external SRAM
from a backup battery plus chip-enable gating. The back-
up battery also provides data retention of the on-board 96
x 8 bits of RAM. An open-drain, active-low, battery-on sig-
nal alerts the system when operating from a battery.
♦ Dual Power-Supply Pins for Primary and Backup
Power
♦ Battery-On Output
♦ NV RAM Controller
The battery-test circuitry periodically tests the backup
battery for a low-battery condition. An optional external
resistor network selects different battery thresholds. A
Chip-Enable Gating (Control of CE with Reset
and Power Valid)
VOUT for SRAM Power
freshness seal prevents battery drain until the first V
power-up.
CC
♦ Microprocessor Supervisor with Watchdog Input
♦ Programmable Time/Date Alarm Output
The MAX6917 has a crystal-fail-detect circuit and a
data-valid bit. The MAX6917 is available in a 20-pin
QSOP package and is guaranteed to operate over the
extended (-40°C to +85°C) temperature range.
♦ Data Valid Bit (Loss of All Voltage Alerts User of
Corrupt Data)
♦ Crystal-Fail Detect
Applications
♦ Reference Output Frequencies—1Hz and
Point-of-Sale Equipment
Programmable Logic Controllers
Intelligent Instruments
Fax Machines
32.768kHz
♦ Small, 20-Pin, QSOP Surface-Mount Package
Digital Thermostats
Ordering Information
Industrial Control
PIN-
PACKAGE
PKG
CODE
PART
TEMP RANGE
Pin Configuration and Selector Guide appear at end of data
sheet.
MAX6917EO30
-40°C to +85°C 20 QSOP
E20-2
E20-2
E20-2
†
2
Purchase of I C components from Maxim Integrated Products,
MAX6917EO33* -40°C to +85°C 20 QSOP
MAX6917EO50* -40°C to +85°C 20 QSOP
*Future product—contact factory for availability.
Inc., or one of its sublicensed Associate Companies, conveys a
2
license under the Philips I C Patent Rights to use these com-
2
ponenets in an I C system, provided that the system conforms to
2
the I C Standard Specification as defined by Philips.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
ABSOLUTE MAXIMUM RATINGS
BATT CC
All Other Pins to GND................................-0.3V to (V
All Other Pins to GND ............................-0.3V to (V
Input Currents
V
, V
to GND ...............................................-0.3V to +6.0V
Output Currents
Continuous ..........................................................200mA
All Other Outputs ............................................................20mA
Continuous Power Dissipation
+ 0.3V)
+ 0.3V)
V
OUT
CC
BATT
V
V
..................................................................................200mA
20-Pin QSOP (derate 9.1mW/°C over T = +70°C) .....727mW
CC
A
.................................................................................20mA
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
BATT
GND ....................................................................................20mA
All Other Pins.................................................................... 20mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= V
to V
, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Notes 1, 2)
CC
CC(MIN)
CC(MAX)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
2.7
3.0
4.5
2.0
2.0
2.0
TYP
3.0
MAX
3.3
UNITS
MAX6917EO30
MAX6917EO33
MAX6917EO50
MAX6917EO30
MAX6917EO33
MAX6917EO50
Operating Voltage Range
(Note 3)
V
V
3.3
3.6
CC
5.0
5.5
5.5
Operating Voltage Range BATT
(Note 4)
V
5.5
V
BATT
5.5
V
V
V
V
V
V
V
V
V
V
V
V
= 2V, V
= 3V, V
= 0
= 0
1
BATT
BATT
BATT
BATT
BATT
BATT
BATT
BATT
BATT
BATT
BATT
BATT
CC
1Hz, 32kHz
outputs disabled;
XTAL FAIL
1.4
CC
= 3.6V, V
= 5.5V, V
= 0
1.9
CC
CC
disabled
= 0
3.8
= 2V, V
= 3V, V
= 0
1.23
1.61
2.3
CC
CC
1Hz, 32kHz
outputs disabled;
XTAL FAIL
= 0
Timekeeping Current V
(Note 5)
BATT
I
µA
BATT
= 3.6V, V
= 5.5V, V
= 0
CC
CC
enabled
= 0
4.08
2.82
4.7
= 2V, V
= 3V, V
= 0
CC
CC
1Hz, 32kHz
= 0
enabled, outputs
open; XTAL FAIL
disabled
= 3.6V, V
= 5.5V, V
= 0
6.1
CC
CC
= 0
= 0
= 0
= 0
= 0
= 0
= 0
10.6
1Hz, 32kHz
V
V
V
V
V
V
= 3.3V, V
= 3.6V, V
= 5.5V, V
= 3.3V, V
= 3.6V, V
= 5.5V, V
0.1
0.12
0.2
CC
CC
CC
CC
CC
CC
BATT
BATT
BATT
BATT
BATT
BATT
enabled, outputs
open; XTAL FAIL
enabled
Active Supply Current V
(Note 6)
CC
I
mA
CCA
1Hz, 32kHz
outputs disabled;
XTAL FAIL
0.9
0.11
0.18
disabled
2
_______________________________________________________________________________________
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= V
to V
, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Notes 1, 2)
CC
CC(MIN)
CC(MAX)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
27
UNITS
1Hz, 32kHz
V
V
V
V
V
V
= 3.3V, V
= 3.6V, V
= 5.5V, V
= 3.3V, V
= 3.6V, V
= 5.5V, V
= 0
= 0
= 0
= 0
= 0
= 0
CC
CC
CC
CC
CC
CC
BATT
BATT
BATT
BATT
BATT
BATT
enabled, outputs
open; XTAL FAIL
enabled
30
81
Standby Current V (Note 5)
I
µA
CC
CCS
1Hz, 32kHz
outputs disabled;
XTAL FAIL
20
25
76
disabled
V
OUT
V
0.2
-
CC
V
V
V
V
V
V
= 2.7V, V
= 3.0V, V
= 4.5V, V
= 0, I
= 0, I
= 0, I
= 35mA
CC
BATT
BATT
BATT
OUT
OUT
OUT
V
0.2
-
-
CC
V
V
in V Mode (Note 4)
CC
V
V
= 35mA
= 70mA
V
V
OUT
OUT
CC
V
0.2
CC
CC
V
V
V
-
-
-
BATT
0.02
= 2V, V
= 3V, V
= 0, I
OUT
= 400µA
= 800µA
BATT
BATT
BATT
CC
in Battery-Backup Mode
OUT
BATT
0.03
= 0, I
OUT
CC
OUT
(Notes 4, 7)
BATT
0.05
= 4.5V, V
= 0, I
= 1.5mA
CC
OUT
V
-to-V
Switchover
Switchover
Power-up (V
< V
) switch from V
V
BATT
+ 0.1
BATT
CC
CC
RST
BATT
V
V
V
V
TRU
TRD
Threshold
to V
(Note 7)
CC
V
-to-V
Power-down (V
< V
RST
) switch from V
CC
CC
BATT
CC
RST
,
VBATT
- 0.1
Threshold
to V
(Note 7)
BATT
CE_IN AND CE_OUT (Figures 10, 14, 15, 16)
Disabled, V
< V
CC
CE_IN Leakage Current
IIL, IIH
-1
+1
µA
V
= VCC or GND
CE_IN
V
= V
V
= 0.9V
,
CC
CC(MIN), IH
CC
CE_OUT connected to GND;
CE_IN-to-CE_OUT Resistance
46
140
Ω
VIL = 0.1VCC, CE_OUT connected to VCC
50Ω source-impedance driver,
C
V
= 10pF, V
= V
,
CC(MIN)
LOAD
CC
CE_IN-to-CE_OUT Propagation
Delay
= 0.9V , V = 0.1V
CC
10
10
20
50
t
ns
µs
IH
CC IL
CED
(Note 8); measured from 50% point on
CE_IN to the 50% point of CE_OUT
RESET Active to CE_OUT High
Delay
t
MR high to low
2
RCE
_______________________________________________________________________________________
3
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= V
to V
, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Notes 1, 2)
CC
CC(MIN)
CC(MAX)
A
A
PARAMETER
CE_OUT Active-Low Delay After
> V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
t
RP
140
200
280
ms
V
CC
RST
I
= -100µA, V
= 2V, V = 0,
CC
0.8 x
V
BATT
OH
BATT
CE_OUT High Voltage
MR INPUT (Figure 10)
MR Input Voltage
V
V
OH
RESET = low
V
0.8
IL
V
V
2.0
1
IH
MR Pullup Resistance
MR Minimum Pulse Width
MR Glitch Immunity
Internal pullup resistor
50
kΩ
µs
ns
ns
t
35
GW
MR to RESET Delay
t
V
V
= V
> V
, V = 0
CC(MIN) BATT
450
600
RD
CC
CC
WDI INPUT (Figure 12)
WDI Initial Timeout Period
from rising edge of RESET
1.00
1.00
140
100
1.6
1.6
2.25
2.25
280
s
s
RST
t
Long watchdog timeout period
Short watchdog timeout period
WDL
Watchdog Timeout Period
Minimum WDI Input Pulse Width
WDI Input Threshold
t
200
ms
ns
WDS
t
WDI
V
0.8
+100
450
IL
V
V
2.0
IH
WDI Input-Leakage Current
V
= V
or GND
CC
-100
nA
WDI
Watchdog frequency = 1MHz,
= V , 1Hz, 32kHz outputs
V
Standby Current with WDI
CC
V
I
µA
CC
CC(MAX)
CCSW
Max Frequency
disabled (Note 5)
BATTERY TEST AND TRIP (Figures 17, 18, and 19)
V
Trip Point
V
Internal mode
= V
external mode
2.45
1.14
2.6
2.70
1.31
V
V
BATT
BTP
V
, V
= 2V,
CC
CC(MAX) BATT
TRIP Input Threshold
V
1.24
TRIP
TRIP Input Comparator
Hysteresis
V
10
mV
TRIP_HYST
TRIP Input Current
Battery Test Load
I
External mode
Internal
-100
0.65
+100
1.30
nA
TRIP_LKG
R
0.91
MΩ
LOAD_INT
V
0.3V
-
OUT
TEST Output-High Voltage
V
I
= -5mA
= 5mA
V
V
TEST_HIGH TEST
TEST Output-Low Voltage
V
I
0.3
TEST_LOW
TEST
BATT_LO, ALM OUTPUT
V
V
V
= 2V, V
= 0, I = 5mA
0.5
0.5
BATT
CC
OL
Output Low Voltage
Off-Leakage
V
= 2.7V, V
= 0, I = 10mA
V
OL
CC
CC
BATT
BATT
OL
= 4.5V, V
= 0, I = 20mA
0.5
OL
I
-100
+100
nA
LKG
4
_______________________________________________________________________________________
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= V
to V
, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Notes 1, 2)
CC
CC(MIN)
CC(MAX)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
BATT_ON OUTPUT
V
V
V
= 2V, V
= 0, I = 5mA
0.5
0.5
BATT
BATT
BATT
CC
OL
Output Low Voltage
V
= 2.7V, V
= 0, I = 10mA
V
OL
CC
CC
OL
= 4.5V, V
= 0, I = 20mA
0.5
OL
Off-Leakage
I
-100
+100
nA
LKG
RESET
MAX6917EO30
MAX6917EO33
MAX6917EO50
2.5
2.8
4.1
2.63
2.93
4.38
30
2.7
3.0
4.5
RESET Threshold Voltage
V
V
RST
V
V
Hysteresis
V
mV
RST
CC
HYST
V
falling from V
RST(MAX)
MAX6917EO30
27
37
75
90
CC
to V
, measured
RST(MIN)
Falling-Reset Delay
t
MAX6917EO33
MAX6917EO50
µs
RPD
from the beginning of V
falling to RESET low
CC
50
120
280
Main Reset Active-Timeout Period
RESET Output Voltage
Off-Leakage
t
140
200
ms
V
RP
RESET asserted, I = 1.6mA, V
= 2V,
OL
BATT
V
0.2
OL
V
= 0
CC
I
-100
0.7 x
+100
nA
LKG
2
I C DIGITAL INPUTS SCL, SDA
Input High Voltage
Input Low Voltage
Input Hysteresis
V
V
V
V
IH
V
CC
0.3 x
V
IL
V
CC
0.05 x
V
HYS
V
CC
Input Leakage Current
Input Capacitance
V
= 0 to V
-100
+100
10
nA
pF
V
IN
CC
(Note 8)
= 4mA, V
SDA Output Low Voltage
V
I
= V
CC(MIN)
0.4
OL
OL
CC
FREQUENCY OUTPUTS (32kHz and 1Hz)
V
= 0, V
= 100µA
= 2V,
CC
BATT
0.2
0.4
0.5
I
OL
32kHz and 1Hz
OUT Low Voltage
V
= 2.7V, V
= 1mA
= 0,
CC
BATT
V
V
OL
I
OL
V
= 4.5V, V
= 2mA
= 0,
CC
BATT
I
OL
_______________________________________________________________________________________
5
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= V
to V
, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Notes 1, 2)
CC
CC(MIN)
CC(MAX)
A
A
PARAMETER
SYMBOL
CONDITIONS
= 2V,
BATT
MIN
OUT
TYP
MAX
UNITS
V
I
= 0, V
V
-
-
-
CC
OH
= -100µA
0.1V
32kHz and 1Hz
OUT High Voltage
V
= 2.7V, V
= -1mA
= 0,
V
OUT
0.3V
CC
OH
BATT
V
V
OH
I
V
= 4.5V, V
= -2mA
= 0,
V
OUT
0.4V
CC
OH
BATT
I
AC ELECTRICAL CHARACTERISTICS
(V
= V
to V
, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
CC
CC(MIN)
CC(MAX)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
FAST I C-BUS TIMING (Figure 2 (Note 9))
SCL Clock Frequency
Bus Timeout
f
(Note 10)
800
1
400,000
2
Hz
s
SCL
TIMEOUT
t
Bus Free Time Between STOP
and START Conditions
t
1.3
0.6
0.6
µs
µs
µs
BUF
Hold Time After (Repeated)
START Conditions
t
After this period, the first clock is generated
HD:STA
HD:STA
Repeated START Condition
Setup Time
t
t
STOP Condition Setup Time
Data Hold Time
0.6
0
µs
µs
ns
µs
µs
SU:STO
HD:DAT
t
(Notes 11, 14)
0.9
Data Setup Time
t
100
1.3
0.6
SU:DAT
SCL Low Period
t
LOW
SCL High Period
t
HIGH
20 +
0.1 × C
SCL/SDA Rise Time (Receiving)
SCL/SDA Fall Time (Receiving)
t
(Note 12)
300
300
ns
ns
R
b
b
b
20 +
0.1 × C
t
t
(Notes 12, 13)
(Notes 12, 13)
F
F
20 +
0.1 × C
SCL/SDA Fall Time (Transmitting)
Pulse Width of Spike Suppressed
250
50
ns
ns
pF
t
0
SP
Capacitive Load for Each Bus
Line
C
400
b
BATTERY-TEST TIMING (Figure 18)
Battery Test to BATT_LO Active
Battery-Test Cycle—Normal
Battery-Test Pulse Width
t
(Note 8)
(Note 8)
(Note 8)
1
1
s
hr
s
BL
t
24
BTCN
BTPW
t
Note 1: V
is the reset threshold for V . See the Selector Guide section.
CC
RST
Note 2: All parameters are 100% tested at T = +85°C. Limits overtemperature are guaranteed by design and are not
A
production tested.
6
_______________________________________________________________________________________
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
AC ELECTRICAL CHARACTERISTICS (continued)
(V
= V
to V
, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
CC
CC(MIN)
CC(MAX)
A
A
2
Note 3: I C serial interface is operational for V > V
.
CC
RST
Note 4: See the Detailed Description section (V
function).
, CE_OUT, and MR floatinOgU. T
OUT
Note 5:
I
is specified with SDA = SCL = V , CE_IN = WDI = GND, V
, CE_OUT, and MR floating. I
is specified with SDA =
BATT
CC
CCS
SCL = V , CE_IN = WDI = GND, V
CC
OUT
2
Note 6: I C serial interface operating at 400kHz, SDA pulled high, and WDI = V or GND, V
and CE_OUT floating.
CC
OUT
Note 7: For OUT switchover to BATT, V
must fall below V
and V
. For OUT switchover to V , V
must be above V
or
CC
RST
BATT
CC CC
RST
above V
.
BATT
Note 8: Guaranteed by design. Not subject to production testing.
Note 9: All values are referred to V and V levels.
IH (MIN)
IL(MAX)
Note 10: Minimum SCL clock frequency is limited by the MAX6917 bus timeout feature, which resets the serial bus interface if either
SDA or SCL is held low for 1s to 2s. When using the burst read or write command, all 96 bytes of RAM must be read/written
within the timeout period. See the Timeout Feature section.
Note 11: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
of the SCL signal) to
IH(MIN)
bridge the undefined region of the falling edge of SCL.
Note 12: C is the total capacitance of one bus line in pF.
b
Note 13: The maximum t for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage t is
F
F
specified at 250ns. This allows series-protection resistors to be connected between the SDA/SCL pins and the SDA/SCL bus
lines without exceeding the maximum specified t .
F
Note 14: The maximum t
only has to be met if the device does not stretch the LOW period (t
) of the SCL signal.
LOW
HD:DAT
Typical Operating Characteristics
(V
= 3V, V
= 3V, T = +25°C, unless otherwise noted.)
A
CC
BATT
V
-TO-OUT VOLTAGE vs. TEMPERATURE
CC
BATT-TO-OUT VOLTAGE vs. TEMPERATURE
40
10
9
8
35
30
25
20
15
10
V
V
I
= 0V
CC
V
V
I
= 3V
CC
7
6
5
4
3
2
1
0
= 3V
BATT
= 0V
BATT
= 800µA
OUT
= 35mA
OUT
V
V
I
= 3.3V
CC
= 0V
BATT
V
V
I
= 0V
= 35mA
CC
OUT
= 2V
BATT
= 400µA
OUT
-40
15
10
35
60
85
-40
15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TIMEKEEPING CURRENT
vs. TEMPERATURE
TIMEKEEPING CURRENT
vs. TEMPERATURE
1.6
1.4
1.2
1.0
0.8
0.6
0.4
1.6
1.4
1.2
1.0
0.8
0.6
0.4
V
= 3V
V
= 3V
BATT
BATT
SCL = SDA = V = 0V
CC
1Hz, 32kHz OUTPUTS DISABLED
XTAL FAIL DISABLED
SCL = SDA = V = 0V
CC
1Hz, 32kHz OUTPUTS DISABLED
XTAL FAIL ENABLED
-40
15
10
35
60
85
-40
15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Typical Operating Characteristics (continued)
(V
CC
= 3V, V
= 3V, T = +25°C, unless otherwise noted.)
BATT A
TIMEKEEPING CURRENT
vs. TEMPERATURE
RESET TIMEOUT PERIOD
vs. TEMPERATURE
RESET COMPARATOR DELAY
vs. V FALLING
CC
220
215
210
205
200
195
190
185
180
1000
100
10
3.4
3.2
3.0
2.8
2.6
2.4
2.2
V
= 3V
BATT
SCL = SDA = V = 0V
CC
1Hz, 32kHz OUTPUTS ENABLED
XTAL FAIL DISABLED
1
-40
15
10
35
60
85
-40
15
10
35
60
85
0.1
1
10
100
1000
TEMPERATURE (°C)
TEMPERATURE (°C)
V
FALLING (V/ms)
CC
RESET COMPARATOR DELAY
vs. TEMPERATURE
RESET THRESHOLD vs. TEMPERATURE
(MAX6917EO30)
WATCHDOG TIMEOUT PERIOD
vs. TEMPERATURE
50
45
40
35
30
25
20
15
10
5
2.675
2.670
2.665
2.660
2.655
2.650
2.645
2.640
2.635
2.630
2.625
2.620
2.615
220
215
210
205
200
195
190
185
180
V
FALLING AT 10V/ms
CC
WD TIME BIT SET TO 1
RESET GOES HIGH ABOVE
THIS THRESHOLD
RESET GOES LOW BELOW
THIS THRESHOLD
-40
15
10
35
60
85
-40
15
10
35
60
85
-40
15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
MAXIMUM TRANSIENT DURATION
vs. RESET COMPARATOR OVERDRIVE
CHIP-ENABLED PROPAGATION DELAY
vs. CE_OUT LOAD CAPACITANCE
CHIP-ENABLED PROPAGATION DELAY
vs. CE_OUT LOAD CAPACITANCE
100
90
80
70
60
50
40
30
20
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
RISING EDGE OF CE_IN TO
RISING EDGE OF CE_OUT
FALLING EDGE OF CE_IN TO
FALLING EDGE OF CE_OUT
RESET ASSERTS ABOVE THIS LINE
V
CC
= 3V
V
= 3V
CC
V
= 3.3V
CC
V
= 3.3V
CC
V
= 5V
CC
V
CC
= 5V
100 150 200 250 300 350 400 450 500
OVERDRIVE (mV)
0
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
0
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
8
_______________________________________________________________________________________
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Typical Operating Characteristics (continued)
(V
CC
= 3V, V
= 3V, T = +25°C, unless otherwise noted.)
BATT A
ACTIVE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
ACTIVE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
TIMEKEEPING CURRENT
vs. SUPPLY VOLTAGE
0.085
0.080
0.075
0.070
0.065
0.060
0.055
0.050
0.045
0.040
0.035
0.030
0.025
0.080
0.075
0.070
0.065
0.060
0.055
0.050
0.045
0.040
0.035
0.030
0.025
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
SCL = 400kHz, SDA = V
SCL = 400kHz, SDA = V
CC
1Hz, 32kHz OUTPUTS DISABLED
XTAL FAIL DISABLED
CC
SCL = SDA = V = 0V
CC
1Hz, 32kHz OUTPUTS DISABLED
XTAL FAIL DISABLED
1Hz, 32kHz OUTPUTS ENABLED
XTAL FAIL ENABLED
T
A
= +85°C
T
A
= -40°C, +25°C, +85°C
T = -40°C, +25°C, +85°C
A
T = -40°C
A
T
A
= +25°C
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
(V)
V
BATT
TIMEKEEPING CURRENT
vs. SUPPLY VOLTAGE
V
TO V
vs. OUTPUT CURRENT
OUT
(NORMAL MODE)
TIMEKEEPING CURRENT
vs. SUPPLY VOLTAGE
CC
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
SCL = SDA = V = 0V
CC
1Hz, 32kHz OUTPUTS DISABLED
XTAL FAIL ENABLED
SCL = SDA = V = 0V
CC
1Hz, 32kHz OUTPUTS ENABLED
XTAL FAIL DISABLED
V
CC
= +2.7V
V
CC
= +3.3V
T
= +85°C
V
CC
= +5V
A
T
A
= +85°C
T
A
= -40°C
T
= -40°C
A
T
A
= +25°C
T
A
= +25°C
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
(V)
0
10 20 30 40 50 60 70 80 90 100
OUTPUT CURRENT (mA)
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V
BATT
V
BATT
(V)
V
-TO-V
vs. OUTPUT CURRENT
OUT
BATT
(BATTERY BACKUP MODE)
0.025
0.020
0.015
0.010
0.005
0
V
= +2V
BATT
V
= +3.3V
BATT
V
= +5V
BATT
0
0.4
0.8
1.2
1.6
2.0
2.4
OUTPUT CURRENT (mA)
_______________________________________________________________________________________
9
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Pin Description
PIN
NAME
FUNCTION
Supply Output for External SRAM or Other ICs Requiring Use of Backup-Battery Power. When V rises
CC
above the reset threshold or above V
, V
is connected to V . When V
falls below V
and
RESET
BATT OUT
CC
CC
1
V
OUT
V
, V
is connected to V
. Connect a 0.1µF low-leakage bypass capacitor from V
to GND.
OUT
BATT BATT
OUT
Leave open if not used.
External Battery Test. Active high for 1s during each battery test. Intended to drive an external MOSFET
or bipolar transistor for an external battery-test configuration. External test must be selected in the control
register to use TEST; otherwise, it remains low. Leave open if not used.
2
3
TEST
TRIP
External Trip Set. If a different battery-low threshold is desired other than the internal POR default of
V
, then connect R
between V
and TRIP and R
between TRIP and the drain or collector of
BTP
SET+
BATT
SET-
an external transistor whose base or gate is connected to TEST; Figure 17 (see the Battery Test section).
External test must be selected in the control register to use TRIP. Leave open if not used.
4
5
BATT_ON Open-Drain Battery-On Indicator. BATT_ON is active low when the MAX6917 is powered from V
.
BATT
CE_IN
Chip-Enable Input. The input to the chip-enable gating circuitry. Connect CE_IN to GND if unused.
Manual-Reset Input. A logic low on MR asserts RESET. RESET remains asserted as long as MR is low
and for t after MR returns high. The active-low MR input has an internal pullup resistor. MR can be
driven from a TTL or CMOS-logic line or shorted to ground with a switch. Internal debouncing circuitry
ensures noise immunity. Leave MR open if unused.
RP
6
7
MR
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout period, the
internal watchdog timer runs out and RESET is asserted. The internal watchdog timer clears while RESET
is asserted or when WDI sees a rising or falling edge. The watchdog function can be disabled from the
control register. The timeout period is configurable in the control register for 200ms or 1.6s.
WDI
8
9
GND
X1
Ground
32.768kHz Crystal-Oscillator Input
32.768kHz Crystal-Oscillator Output
10
X2
10 ______________________________________________________________________________________
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Pin Description (continued)
PIN
11
NAME
32KHZ
1HZ
FUNCTION
32.768kHz Output. Buffered push-pull output that is enabled from the FOUT configuration register.
1Hz Output. Buffered push-pull output that is enabled from the FOUT configuration register.
12
2
13
SDA
Open-Drain Data Input/Output. I C bus serial data input/output connection.
2
14
SCL
Serial Clock Input. I C bus clock for input/output data transfers.
Open-Drain, Active-Low Alarm Output. ALM goes low when RTC time matches alarm thresholds set in
the alarm threshold registers. ALM stays low until cleared by reading or writing to the alarm configuration
register or to any of the alarm threshold registers.
15
16
17
ALM
Chip-Enable Output. CE_OUT goes low only when CE_IN is low and RESET is not asserted. If CE_IN is
low when RESET is asserted, CE_OUT remains low for t
or until CE_IN goes high, whichever occurs
CE_OUT
RCE
first. CE_OUT is pulled to V
.
OUT
Open-Drain, Battery-Low Indicator. BATT_LO is active low when the V
input is tested below V
if
BATT
BTP
BATT_LO the internal trip is selected in the control register (POR default). If external trip is selected in the control
register, then BATT_LO is active low when TRIP is less than V
.
TRIP
Open-Drain, Active-Low Reset Output. RESET pulses low for t when triggered, and stays low
RP
whenever V
is below the reset threshold or when MR is logic low. RESET remains low for t after
RP
18
19
RESET
CC
either V
rises above the reset threshold or MR goes from low to high.
CC
V
Main Supply Input. Connect a 0.1µF bypass capacitor from V
to GND.
CC
CC
Backup-Battery Input. When V
falls below the reset threshold and V
, V
switches from V to
CC
BATT OUT CC
V
V
. When V
. Connect V
rises above V
or the reset threshold, V
reconnects to V . V
may exceed
BATT
CC
BATT
OUT
CC BATT
20
V
BATT
to GND if no backup-battery supply is used. Connect a 0.1µF low-leakage bypass
to GND.
CC
BATT
capacitor from V
BATT
Real-Time Clock
Detailed Description
The RTC provides seconds, minutes, hours, day, date,
month, and year information. The end of the months is
automatically adjusted for months with fewer than 31
days, including corrections for leap years through 2099.
Functional Description
The MAX6917 contains eight 8-bit timekeeping registers,
seven 8-bit alarm threshold registers, one status register,
one control register, one alarm-configuration register, and
96 x 8 bits of SRAM. In addition to single-byte reads and
writes to registers and RAM, there is a burst timekeeping
register read/write command, a burst RAM read/write
command, and a battery-test command that allows soft-
ware-commanded testing of the backup battery at any
Crystal Oscillator
The MAX6917 uses an external, standard 6pF load
watch crystal. No other external components are
required for this timekeeping oscillator. Power-up oscil-
lator start time is dependent mainly upon applied V
CC
2
and ambient temperature. The MAX6917, because of
its low timekeeping current, exhibits a typical startup
time of 1s to 2s.
time. An I C-bus-compatible interface allows serial com-
munication with a µP. When V
is less than the reset
CC
threshold, the serial interface is disabled to prevent erro-
neous data from being written to the MAX6917. A µP
supervisory section and an NVRAM controller are provid-
ed for ease of implementation with µP-based systems. A
crystal fail-detect circuit and a data-valid bit can be used
to guarantee RAM data integrity and valid timekeeping
data. Two reference frequencies outputs, 32.768kHz and
1Hz, are provided for external device clocking. Time and
calendar data are stored in a binary-coded decimal
(BCD) format. Figure 1 shows the functional diagram of
the MAX6917.
2
I C-Compatible Interface
The I2C bus allows bidirectional, 2-wire communication
between different ICs. The two lines are serial data line
(SDA) and serial clock line (SCL). Both lines must be
connected to a positive supply through individual
pullup resistors (see the Typical Application Circuit).
Data transfer can only be initiated when the bus is not
busy (both SDA and SCL are high). Figure 2 shows a
timing diagram for I2C communication.
______________________________________________________________________________________ 11
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
WATCHDOG
TIMER
WDI
RESET
MAX6917
RESET
LOGIC
DEBOUNCE
CIRCUIT
MR
CRYSTAL-
FAIL
XTAL FAIL
DETECT
X1
X2
DIVIDERS
OSCILLATOR
32.768kHz
CE
CONTROL
CE_OUT
CE_IN
32KHZ
CLOCK
BURST
1HZ
SECONDS
MINUTES
HOURS
DATE
TEST
TRIP
GND
POWER
CONTROL
AND
V
BATT
V
MONTH
DAY
OUT
MONITOR
V
CC
CONTROL
LOGIC
BATT_LO
BATT_ON
YEAR
CONTROL
CENTURY
SCL
SDA
ALARM
CONFIG
INPUT-
SHIFT
REGISTERS
ADDRESS
REGISTER
BATT
TEST
STATUS
CONFIG
DATA
VALID
LOGIC
96 x 8
RAM
ALARM
THRESHOLDS
FOUT
CONFIG
ALARM
CONTROL
LOGIC
ALM
RAM
BURST
Figure 1. Functional Diagram
12 ______________________________________________________________________________________
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
SDA
t
BUFF
t
F
t
t
R
SU:DAT
t
HD:STA
t
t
SP
R
t
t
LOW
F
SCL
t
t
t
HD:DAT
SU:STA
HD:STA
t
SU:STO
t
HIGH
S
P
Sr
S
S = START CONDITION
P = STOP CONDITION
Sr = REPEATED START CONDITION
2
Figure 2. I C Communication Timing Diagram
To maximize battery life and prevent erroneous data
from being entered into the MAX6917, the serial bus
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data
(Figure 6). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high portion of the clock pulse. A
master receiver must signal an end of data to the trans-
mitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this
case, the transmitter must leave the SDA high to enable
the master to generate a STOP condition. If a STOP
condition is received before the current byte of data
transfer is completed in burst mode, the last incomplete
byte is ignored if it is a burst transaction to RAM or the
whole burst transaction is ignored if it is a burst trans-
action to the timekeeping registers. There is no limit to
the number of bytes that can be transmitted between a
START and a STOP condition.
interface is disabled when V
is below V
. If the
RST
CC
SDA or SCL serial interface lines are held low for longer
than 1s to 2s, the serial bus interface resets and awaits
for a new START condition (see the START and STOP
Conditions section).
I2C System Configuration
A device on the I2C-compatible bus that generates a
message is called a transmitter and a device that
receives the message is called a receiver. The device
that controls the message is the master and the
devices that are controlled by the master are called
slaves (Figure 3). The word message refers to data in
the form of three 8-bit bytes for a single read or write.
The first byte is the slave ID byte, the second byte is
the address/command byte, and the third is the data.
START and STOP Conditions
Data transfer can only be initiated when the bus is not
busy (both SDA and SCL are high). A high-to-low tran-
sition of SDA while SCL is high defines a START (S)
condition; low-to-high transition of SDA while SCL is
high defines a STOP (P) condition (Figures 2, 4). Any
time a START condition occurs, the slave ID must follow
immediately, regardless of completion of a previous
data transfer.
Slave Address
Before any data is transmitted on the I2C-bus-compati-
ble serial interface, the device that is expected to
respond must be addressed first. The first byte sent
after the START (S) condition is the address byte or 7-
bit slave ID. The MAX6917 acts as a slave trans-
mitter/receiver. Therefore, SCL is only an input clock
signal and SDA is a bidirectional data line. The slave
address for the MAX6917 is shown in Figure 7.
Bit Transfer
After the START condition occurs, 1 bit of data is trans-
ferred for each clock pulse. The data on SDA must
remain stable during the high portion of the clock pulse
as changes in data during this time are interpreted as a
control signal (Figure 5).
______________________________________________________________________________________ 13
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Address/Command Byte
The second byte of data sent after the START condition
is the address/command byte (Figure 8). Each data
transfer is initiated by an address/command byte. Bits
7–1 specify the designated register or RAM location to
be read or written to, and the LSB (bit 0) specifies a
write operation if logic zero or a read operation if logic
one. The command byte is always input starting with
the MSB (bit 7).
If single reads are used to read each of the timekeep-
ing registers individually, then it is necessary to do
some error checking on the receiving end. An error can
occur when the seconds counter increments before all
the other registers are read out. For example, suppose
a carry of 13:59:59 to 14:00:00 occurs during single-
read operations of the timekeeping registers. Then the
net data could become 14:59:59, which is erroneous
real-time data. To prevent this with single-read opera-
tions, read the seconds register first (initial seconds)
and store this value for future comparison. When the
remaining timekeeping registers have been read out,
read the seconds register again (final seconds). If the
initial seconds value is 59, check that the final-seconds
value is still 59; if not, repeat the entire single-read
process for the timekeeping registers. A comparison of
the initial-seconds value with the final-seconds value
can indicate if there was a bus-delay problem in read-
ing the timekeeping data (difference should always be
1s or less). Using a 100kHz bus speed, and sequential
single reads, it would take under 2.5ms to read all
seven of the timekeeping registers plus a second read
of the seconds register.
Reading from the Timekeeping Registers
The timekeeping registers (seconds, minutes, hours,
date, month, day, and year) and the control register
can be read either with a single read or a burst read
(Figure 9). Since the RTC runs continuously and a read
takes a finite amount of time, there is the possibility that
the clock counters could change during a read opera-
tion, thereby reporting inaccurate timekeeping data. In
the MAX6917, each clock counter’s data is buffered by
2
a latch. Clock counter data is latched by the I C bus
read command (on the falling edge of SCL when the
slave acknowledge bit is sent, after the address/com-
mand byte has been sent by the master to read a time-
keeping register). Collision-detection circuitry ensures
that this does not happen coincident with a seconds
counter update to ensure accurate time data is being
read. This avoids time-data changes during a read
operation. The clock counters continue to count and
keep accurate time during the read operation.
The most accurate way to read the timekeeping regis-
ters is to perform a burst read. With burst reads, the
main timekeeping registers (seconds, minutes, hours,
date, month, day, year) and the control register are
read sequentially, in the order listed with the seconds
register first. They must be all read out as a group of
SDA
SCL
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
DATA LINE
STABLE;
CHANGE OF
DATA
DATA VALID
ALLOWED
2
Figure 5. Bit Transfer
Figure 3. I C System Configuration
START
CONDITION
CLOCK PULSE FOR
ACKNOWLEDGE
SDA
SCL
1
2
8
9
SCL
S
SDA
P
BY TRANSMITTER
START
CONDITION
STOP
CONDITION
SDA
BY RECEIVER
S
Figure 6. Acknowledge
Figure 4. START and STOP Conditions
14 ______________________________________________________________________________________
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
1
1
0
1
0
0
0
R/W
ACK
SDA
SCL
MSB
LSB
Figure 7. MAX6917 Slave Address
eight registers, with 8 bytes each, for proper execution
of the burst-read function. All seven timekeeping regis-
ters are latched upon the receipt of the burst-read com-
mand. The worst-case error that can occur between the
actual time and the read time is 1s.
BIT 7
BIT 0
A7
A6
A5
A4
A3
A2
A1
R/W
Writing to the Timekeeping Registers
The time and date can be set by writing to the time-
keeping registers (seconds, minutes, hours, date,
month, day, year, and century). To avoid changing the
Figure 8. Address/Command Byte
ACKNOWLEDGE
SINGLE WRITE
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
FROM SLAVE
A
1 0 1 0 0 0 0
A
A
1
S
ADDR
0
8-BIT DATA
P
S
S
S
R/W
START CONDITION
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
NO ACKNOWLEDGE
FROM MASTER
SINGLE READ
A
A
A
A
A
A
M
S
1
1
0
1
0
0
0
0
ADDR
1
0
1
Sr
1
1
0
1
0
0
0
1
8-BIT DATA
P
P
S
S
S
S
R/W
R/W
STOP CONDITION
ACKNOWLEDGE
START CONDITION
REPEATED START CONDITION
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
BURST WRITE
FROM SLAVE
A
A
A
S
1
1
0
1
0
0
0
0
LAST 8-BIT DATA
S
ADDR
FIRST 8-BIT DATA
S
S
S
R/W
STOP CONDITION
ACKNOWLEDGE
START CONDITION
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
BURST READ
FROM MASTER
A
A
A
1
1
0
1
0
0
0
0
1
1
0
1
0
0
0
1
S
ADDR
Sr
FIRST 8-BIT DATA
S
S
M
R/W
R/W
NO ACKNOWLEDGE
FROM MASTER
START CONDITION
REPEATED START CONDITION
ADDR = 7-BIT RAM OR REGISTER ADDRESS
S = START CONDITION
A
LAST 8-BIT DATA
M
P
Sr = REPEATED START CONDITION
P = STOP CONDITION
STOP CONDITION
A
A
A
= ACKNOWLEDGE FROM SLAVE
= ACKNOWLEDGE FROM MASTER
= NOT ACKNOWLEDGE FROM MASTER
S
M
M
Figure 9. Read and Write Operations
______________________________________________________________________________________ 15
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
current time by an incomplete write operation, the cur-
rent time value is buffered from being written directly to
the clock counters. The new data sent replaces the cur-
rent contents of this input buffer. This time update data
is loaded into the clock counters after the stop bit at the
To avoid rollover issues when writing time data to the
MAX6917, the remaining time and date registers must
be written within 1s of updating the seconds register
when using single writes. For burst writes, all eight reg-
isters must be written within this period (1s).
2
end of the I C bus write operation. Collision-detection
The weekday data in the day register increments at
midnight. Values that correspond to the day of the
week are user defined, but must be sequential (i.e., if 1
equals Sunday, then 2 equals Monday, and so on). If
invalid values are written to the timekeeping registers,
the operation becomes undefined.
circuitry ensures that this does not happen coincident
with a seconds-counter update to guarantee that accu-
rate time data is being written. This avoids time data
changes during a write operation. An incomplete write
operation aborts the time-update procedures and the
contents of the input buffer are discarded. The clock
counters reflect the new time data beginning with the
first 1s clock cycle after the stop bit. The clock counter
is reset immediately after a write to the seconds regis-
ter or a burst write to the timekeeping registers. This
ensures that 1s clock tick is synchronous to timekeep-
ing writes.
Timeout Feature
The purpose of the bus timeout feature is to reset the seri-
al bus interface and change the SDA line of the MAX6917
from an output to an input, which puts the SDA line into a
high-impedance state. This is necessary when the
MAX6917 is transmitting data and becomes stuck at a
logic-low level. If the SDA line is stuck low, any other
device on the bus is not able to communicate.
If single-write operations (Figure 9) are used to write to
each of the timekeeping registers, then error checking is
needed. If the seconds register is the one to be updat-
ed, update it first and then read it back and store its
value as the initial seconds. Update the remaining time-
keeping registers and then read the seconds register
again (final seconds). If initial seconds was 59, ensure it
is still 59. If initial seconds was not 59, ensure that final
seconds is within 1s of initial seconds. If the seconds
register is not to be written to, then read the seconds
register first and save it as initial seconds. Write to the
required timekeeping registers and then read the sec-
onds register again (final seconds). If initial seconds
was 59, ensure it is still 59. If initial seconds was not 59,
ensure that final seconds is within 1s of initial seconds.
The timeout feature looks for a valid START and STOP
condition to determine whether SDA has been stuck
low. A valid START condition initiates the timeout
counter in reference to the internal 1Hz clock. Counting
begins on the first rising edge of the 1Hz clock after a
valid START condition. If a valid STOP condition is
detected before the next rising edge of the 1Hz clock,
the timeout counter is stopped and awaits a new valid
START condition. If a valid STOP condition is not
detected before the next rising edge of the 1Hz clock,
the I2C interface resets to the idle state and waits for a
new I2C transaction. Depending on the occurrence of
the START condition, that initiates the timeout counter,
in reference to the internal 1Hz clock, the timeout peri-
od can be 1s to 2s. The lower limit of the timeout period
(1s) imposes a limit on the SCL frequency of the
MAX6917 because a burst read/write requires up to 96
bytes of information to be transmitted in between a
START and STOP condition.
Although both single writes and burst writes are possi-
ble, the most accurate way to write to the timekeeping
counters is to do a burst write (Figure 9). In the burst
write, the main timekeeping registers (seconds, min-
utes, hours, date, month, day, year) and the control
register are written sequentially. They must be all writ-
ten to as a group of eight registers, with 8 bytes each,
for proper execution of the burst-write function. All
seven timekeeping registers and the control register
are simultaneously loaded into the input buffer at the
end of the 2-wire bus write operation. The worst-case
error that can occur between the actual time and the
write time update is 1s.
16 ______________________________________________________________________________________
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
for a read (Table 1). If the write-protect bit is set to one
when a write-clock/calendar-burst mode is specified,
no data transfer occurs to any of the seven timekeeping
registers or the control register. When writing to the
clock/calendar registers in the burst mode, the first
eight registers must be written to for the data to be
transferred.
Registers
Tables 1 and 2 show the register map, as well as the
register descriptions for the MAX6917.
Control Register
The control register contains bits for configuring the
MAX6917 for custom applications. Bit D0 (BATT ON
BLINK) and D1 (BATT LO BLINK) are used to enable a
1Hz blink rate on BATT_ON and BATT_LO when they
are active; see the Battery Test section for details. D2
(WD TIME) and D3 (WD EN) are used to enable the
watchdog function and select its timeout. For details,
see the Watchdog Input section. D5 (INT/EXT TEST)
sets whether the internal resistor ratio or an external
resistor ratio is to be used to check for the low-battery
condition; see the Battery Test section for details. D6
(XTAL EN) enables the crystal-fail-detect circuitry when
set. See the Crystal-Fail Detect section for details. D7
(WP) is the write protect bit. Before any write operation
to the registers (except the control register) or RAM, bit
7 must be zero. When set to one, the write-protect bit
prevents write operations to any register (except the
control register) or RAM location.
RAM
The static RAM consists of 96 x 8 bits addressed con-
secutively in the RAM address/command space. Even
address/commands (3Eh to FCh) are used for RAM
writes and odd address/commands (3Fh to FDh) are
used for RAM reads (Table 2).
RAM-Burst Mode
Sending the RAM-burst address/command (FEh for
write, FFh for read) specifies burst-mode operation. In
this mode, the 96 RAM locations can be consecutively
read or written to starting with bit 7 of address/com-
mand 3Eh for writes, and 3Fh for reads. A burst read
outputs all 96 bytes of RAM. When writing to RAM in
burst mode, it is not necessary to write all 96 bytes for
the data to transfer; each complete byte written is
transferred to the RAM. When reading from RAM, data
are output until all 96 bytes have been read, or until the
Timekeeping and Alarm Thresholds Registers
Time and date data is stored in the timekeeping and
alarm threshold registers in BCD format as shown in Table
1. The weekday data in the day register is user defined (a
common format is 1 = Sunday, 2 = Monday, etc.)
2
data transfer is stopped by the I C master.
Status Register
The status register contains individual bits for monitor-
ing the status of several functions of the MAX6917. Bits
D0–D3 are unused and always read zero (Table 1). D4
(ALM OUT) reflects the state of the alarm function; see
the Alarm-Generation Function section for details. D5
(BATT LO) indicates the state of the battery connected
AM/PM and 12hr/24hr Mode
For both timekeeping and alarm threshold registers
(Table 1), D7 of the hours register is defined as the
12hr or 24hr mode-select bit. When set to one, the 12hr
mode is selected. In the 12hr mode, D5 is the AM/PM
bit with logic one being PM. In the 24hr mode, D5 is the
second 10hr bit (20hr to 23hr).
to V
; see the Battery Test section for more informa-
BATT
tion. D6 (DATA VALID) alerts the user if all power was
lost. See the Data Valid Bit section for details. D7 (XTAL
FAIL) is the output of the crystal-fail detect circuit. See
the Crystal-Fail Detect section for details.
Clock-Burst Mode
Addressing the clock-burst register specifies burst-
mode operation. In this mode, the first eight clock/cal-
endar registers (seven timekeeping and the control
register) can be consecutively read or written to by
using the address/command byte 00h for a write or 01h
______________________________________________________________________________________ 17
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Table 1. Register Map
REGISTER ADDRESS
REGISTER FUNCTION
FUNCTION
A7
A6
A5
A4
A3
A2
A1
A0
VALUE
D7
D6
D5
D4
D3
D2
D1
D0
CLOCK
BURST
R
0
0
0
0
0
0
0
W
0–59
0
0
R
10 SEC
0
1 SEC
SEC
MIN
HR
1
0
0
0
0
0
0
0
0
0
0
POR STATE
0
0
0
0
0
0
0
0
0
0
0
W
0–59
0
0
10 MIN
0
1 MIN
1 HR
R
0
1
1
0
POR STATE
0
W
R
10 HR
00–23
01–12
1
0
0
0
10 HR
0
W
12/24
AM/
PM
POR STATE
0
0
0
0
0
0
0
01–28/29
01–30/31
POR STATE
0
0
R
0
0
10 DATE
1 DATE
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DATE
W
0
0
0
0
1
1
1
0
01–12
R
0
0
0
0
0
0
10 M
0
1 MONTH
MONTH
1
1
0
POR STATE
W
0
0
WEEKDAY
0
R
01–07
POR STATE
0
0
0
0
0
0
0
0
0
0
DAY
YEAR
1
0
0
W
10 YEAR
1
1 YEAR
0
R
00–99
POR STATE
1
0
0
1
1
0
0
W
R
INT/
EXT
TEST
BATT BATT
LO ON
BLINK BLINK
CONTROL
10
0
XTAL
EN
WD
EN
WD
TIME
WP
0
0
0
W
POR STATE
1
0
1
0
0
0
1000 YEAR
0
100 YEAR
0
R
00–99
CENTURY
1
0
0
10
1
0
0
0
0
0
POR STATE
0
0
1
0
1
0
1
W
R
0
1
0
ONE
SEC
ALARM
CONFIGURATION
YEAR DAY
W
DATE
0
HR
0
MIN SEC
POR STATE
0
0
0
0
0
R
32kHz 1kHz 32kHz 1kHz
FOUT
CONFIGURATION
0
0
0
0
0
1
1
1
0
0
1
1
V
EN
V
EN
V
V
0
0
0
0
0
0
0
0
W
CC
CC
BATT
EN
BAT
EN
0
POR STATE
POR STATE
1
1
0
R
STATUS
0
0
XTAL
FAIL
BATT ALM
0
0
0
0
0
0
0
0
W
LO
OUT
0
0
0
0
POR STATE DEFINES THE POWER-ON RESET STATE OF THE REGISTER.
18 ______________________________________________________________________________________
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Table 1. Register Map (continued)
REGISTER ADDRESS
REGISTER FUNCTION
FUNCTION
A7
A6
A5
A4
A3
A2
A1
A0
VALUE
D7
D6
D5
D4
D3
D2
D1
D0
BATT TEST
0
0
0
1
1
0
1
0
ALARM
THRESHOLDS:
0–59
0
0
R
10 SEC
1
1 SEC
SEC
MIN
HR
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
1
1
0
0
1
0
POR STATE
1
1
1
1
1
1
1
1
1
1
1
W
0–59
0
0
10 MIN
1
1 MIN
1 HR
R
POR STATE
1
W
R
10 HR
00–23
01–12
0
0
10 HR
1
W
12/24
AM/
PM
POR STATE
1
1
1
1
1
1
1
01–28/29
01–30/31
POR STATE
R
0
0
0
0
10 DATE
1 DATE
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
DATE
1
1
1
1
1
1
1
W
01–12
R
0
0
0
0
0
0
1 MONTH
1
10 M
1
MONTH
POR STATE
1
W
WEEK DAY
1
R
01–07
POR STATE
0
0
0
0
0
0
0
0
0
0
DAY
1
W
10 YEAR
1
1 YEAR
1
R
00–99
POR STATE
YEAR
1
0
1
0
1
0
1
0
1
0
1
0
W
TEST
CONFIGURATION
(FACTORY
R
POR STATE
0
0
W
RESERVED)
RAM REGISTERS:
R
RAM 0
RAM DATA 0
00h-FFh
0
0
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
W
R
1
1
1
1
1
1
1
1
1
1
0
1
RAM DATA 95
00h-FFh
RAM 95
1
1
W
R
RAM BURST
W
POR STATE DEFINES THE POWER-ON RESET STATE OF THE REGISTER.
______________________________________________________________________________________ 19
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Power Control
provides power as a battery backup. V pro-
vides the primary power in dual-supply systems where
is connected as a backup source to maintain
Alarm-Generation Function
V
The alarm function is configured using the alarm-con-
figuration register and the alarm-threshold registers
(Table 1). Writing a one to D7 (ONE SEC) in the alarm-
configuration register sets the alarm function to occur
once every second, regardless of any other setting in
the alarm-configuration register or in any of the alarm-
threshold registers. When the alarm is triggered, D4
(ALM OUT) in the status register is set to one and the
open-drain alarm output ALM goes low. The alarm is
cleared by reading or writing to the alarm-configuration
register or by reading or writing to any of the alarm-
threshold registers. This resets the ALM output to a
high and the ALM OUT bit to zero.
BATT
CC
V
BATT
timekeeping in the absence of primary power. When
rises above the reset threshold, V , V powers
V
CC
RST CC
the MAX6917. When V
falls below the reset thresh-
CC
old, V
, and is less than V
, V
powers the
BATT
RST
TRD
MAX6917. If V
falls below the reset threshold, V
,
CC
RST
and is more than V
, V
TRU CC
still powers the MAX6917.
V
CC
slew rate in power-down is limited to 10V/ms (max)
for proper data retention.
V
Function
OUT
V
OUT
is an output supply voltage for battery-backed-up
devices such as SRAM. When V
reset threshold or is greater than V
When D7 (ONE SEC) is set to zero in the alarm-configu-
ration register, then the alarm function is set by the
remaining bits in the alarm-configuration register and
the contents of the respective alarm-threshold register.
For example, writing 01h (0000 0001) to the alarm-con-
figuration register causes the alarm to trigger every
time the seconds-timekeeping register matches the
seconds alarm-threshold register (i.e., once every
minute on a specific second). Writing 02h (0000 0010)
to the alarm configuration register causes the alarm to
trigger on a minutes match (i.e., once every hour).
Writing a 4Fh (0100 1111) to the alarm configuration
register causes the alarm to be triggered on a specific
second, of a specific minute, of a specific hour, of a
specific date, of a specific year.
rises above the
CC
BATT OUT
falls below V
. There is a typical
, V
connects
and
RST
to V
V
(Figure 19). When V
OUT
CC
, V
CC
connects to V
BATT
BATT
100mV hysteresis associated with the switching
between V and V on the V output. Connect
CC
BATT
OUT
to GND.
a 0.1µF capacitor from V
OUT
Power-On Reset (POR)
The MAX6917 contains an integral POR circuit that
ensures all registers are reset to a known state on power-
up. Once either V
or V
rises above 1.6V (typ), the
CC
BATT
POR circuit releases the registers for normal operation.
When V
or V
drops to less than 0.9V (typ), the
CC
BATT
MAX6917 resets all register contents to the POR defaults.
Oscillator Start Time
The MAX6917 oscillator typically takes 1s to 2s to begin
oscillating. To ensure the oscillator is operating correct-
ly, the system software should validate proper time-
keeping. This is accomplished by reading the seconds
register. Any reading with more than 0s, from the POR
value of 0s, is a validation of proper startup.
When setting the alarm-threshold registers, ensure that
both the hour-timekeeping register and the hour-alarm-
threshold register are using the same-hour format
(either 12hr or 24hr format).
The alarm function, as well as the ALM output, is opera-
tional in both V
and battery-backup mode.
CC
20 ______________________________________________________________________________________
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Table 2. Hex Register Address and Description
WRITE ADDRESS/COMMAND READ ADDRESS/COMMAND
POR SETTING
(HEX)
DESCRIPTION
(HEX)
(HEX)
00
02
04
06
08
0A
0C
0E
10
12
14
16
18
1A
1C
1E
20
22
24
26
28
2A
3E
40
42
44
46
•
01
03
05
07
09
0B
0D
0F
11
13
15
17
19
N/A
1D
1F
21
23
25
27
29
2B
3F
41
43
45
47
•
Clock burst
N/A
Seconds
00
Minutes
00
Hour
00
Date
Month
01
01
Day
01
Year
70
Control
48
Century
00
Alarm configuration
FOUT configuration
Status
19
C0
00
Battery test
Seconds alarm threshold
Minutes alarm threshold
Hours alarm threshold
Date alarm threshold
Month alarm threshold
Day alarm threshold
Year alarm threshold
Test configuration
RAM 0
N/A
7F
7F
BF
3F
1F
07
FF
00
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
•
RAM 1
RAM 2
RAM 3
RAM 4
•
•
•
•
•
•
•
•
•
F4
F6
F8
FA
FC
FE
F5
F7
F9
FB
FD
FF
RAM 91
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
RAM 92
RAM 93
RAM 94
RAM 95
RAM BURST
______________________________________________________________________________________ 21
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Crystal-Fail Detect
The crystal-fail detect circuit looks for a loss of oscillation
MR
from the 32.768kHz oscillator for 30 cycles (typ) or more.
Both the control register and the status register are used
in the crystal-failure detection scheme (Table 1).
CE OUT
t
t
RP
t
RCE
The crystal-fail detect circuit sets the XTAL FAIL bit in
the status register to one for a crystal failure and to zero
for normal operation. Once the status register is read,
the XTAL FAIL bit is reset to zero, if it was previously
one. If the crystal-fail-detect circuit continues to sense
a failed crystal, then the XTAL FAIL bit is set again.
RP
RESET
CE IN
On initial power-up, the crystal-fail detect circuit is
enabled. Since it takes a while for the low-power,
32.768kHz oscillator to start, the XTAL FAIL bit in the
status register can be set to one indicating a crystal
failure. The XTAL FAIL bit should be polled a number of
times to see if it is set to zero for successive polls. If the
polling is far enough apart, a few polled results could
guarantee that a maximum of 10s had elapsed since
power-on, at which time the oscillator would be consid-
ered truly failed if the XTAL FAIL bit remains one.
Figure 10. Manual-Reset Timing Diagram
The RESET output is also activated when the watchdog
interrupt function is enabled but no transition is detect-
ed on the WDI input. In this case, RESET is active for
the period t
before becoming inactive again. When
RP
RESET is active, all inputs—WDI, MR, CE_IN, SDA, and
SCL—are disabled.
The MAX6917EO30 is optimized to monitor 3.0V 10%
On subsequent power-ups, when XTAL EN is set to
one, if XTAL FAIL is set to one, time data should be
considered suspect.
power supplies. Except when MR is asserted, RESET is
not active until V
falls below 2.7V (3.0V - 10%), but is
CC
guaranteed to occur before the power supply falls
below 2.5V (3.0V - 15%).
The crystal-fail-detection circuit functions in both V
BATT
control register.
CC
and V
modes when the XTAL EN bit is set in the
The MAX6917EO33 is optimized to monitor 3.3V 10%
power supplies. Except when MR is asserted, RESET is
Manual Reset Input
not active until V
falls below 3.0V (3.0V is just above
CC
A logic low on MR asserts RESET. RESET remains
3.3V - 10%), but is guaranteed to occur before the
power supply falls below 2.8V (3.3V - 15%).
asserted while MR is low, and for t
after it returns
RP
high (Figure 10). MR has an internal pullup resistor, so
it can be left open if it is not used. Internal debounce
circuitry requires a minimum low time on the MR input
of 1µs with 35ns maximum glitch immunity.
The MAX6917EO50 is optimized to monitor 5.0V 10%
power supplies. Except when MR is asserted, RESET is
not active until V
falls below 4.5V (5.0V - 10%), but is
CC
guaranteed to occur before the power supply falls
below 4.1V (4.1V is just below 5.0V - 15%).
Reset Output
A µP’s reset input starts the µP in a known state. The
MAX6917’s µP supervisory circuit asserts a reset to
prevent code-execution errors during power-up, power-
down, and brownout conditions. The RESET output is
Negative-Going V
Transients
CC
The MAX6917 is relatively immune to short-duration nega-
tive transients (glitches) while issuing resets to the µP dur-
ing power-up, power-down, and brownout conditions.
guaranteed to be active for 0V < V
< V
, provided
CC
(min). If V
RST
Therefore, resetting the µP when V
experiences only
CC
V
is greater than V
drops below
CC
BATT
BATT
small glitches is usually not recommended. Typically, a
transient that goes 150mV below the reset threshold
and then exceeds the reset threshold, an internal timer
keeps RESET active for the reset timeout period t
V
CC
;
RP
and lasts for 90µs or less does not cause a reset pulse to
after this interval, RESET becomes inactive high. This
be issued. A 0.1µF capacitor mounted close to the V
pin provides additional transient immunity.
CC
condition occurs at either power-up or after a V
brownout.
CC
22 ______________________________________________________________________________________
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
BUFFER
V
V
CC
V
RST
V
CC
CC
V
CC
t
t
RP
RP
µP
MAX6917
RESET
WDI
4.7kΩ
t
t
WD
WD
WD EN AND WD TIME ARE SET
TO ZERO AND THE WATCHDOG
FUNCTION IS DISABLED.
RESET
RESET
GND
GND
Figure 11. Interfacing to µP with Bidirectional Reset I/O
Figure 12. Watchdog Timing Diagram
WDI can detect pulses as short as t
. Data bit D2 in
Interfacing to µPs with Bidirectional
Reset Pins
WDI
the control register controls the selection of the watch-
dog-timeout period. The power-up default is 1.6s (D2 =
0). A reset condition returns the timeout to 1.6s (D2 =
0). If D2 is set to one, then the watchdog-timeout period
is changed to 200ms. Data bit D3 in the control register
is the watchdog-enable function. A logic zero disables
the watchdog function, while a logic one enables it. The
POR state of WD EN is logic one, or the watchdog func-
tion is enabled. Disable the watchdog function by writ-
ing a zero to the WD EN bit in the control register,
within the 1.6s POR default timeout after power-up.
Microprocessors with bidirectional reset pins, such as
the Motorola 68HC11 series, can contend with the
MAX6917 RESET output. If, for example, the RESET
output is driven high and the µP wants to pull it low,
indeterminate logic levels can result. To correct this,
connect a 4.7kΩ resistor between the RESET output
and the µP reset I/O as shown in Figure 11. Buffer the
RESET output to other system components.
Battery-On Output
The battery-on output, BATT_ON, is an open-drain out-
put that indicates when the MAX6917 is powered from
WDI does not include a pulldown or pullup feature. For
this reason, WDI should not be left floating. When the
WD EN bit in the control register is set to zero, WDI
the backup-battery input, V
. When V
falls below
BATT
, and below V
CC
the reset threshold, V
, V
BATT OUT
RST
should be connected to V
or GND. WDI is disabled
CC
switches from V
to V
and BATT_ON becomes
CC
BATT
and does not draw cross-conduction current when V
CC
low. When V
rises above the reset threshold, V
,
CC
RST
falls below V
.
RST
V
OUT
reconnects to V
and BATT_ON becomes high
CC
(open-drain output with pullup resistor). If desired, the
BATT_ON output can be register selected, through the
BATT ON BLINK bit in the control register, to toggle on
and off 0.5s on, 0.5s off when active. The POR default
is logic zero for no blink.
Watchdog Software Considerations
There is a way to help the watchdog-timer monitor soft-
ware execution more closely, which involves setting and
resetting the watchdog input at different points in the
program rather than “pulsing” the watchdog input. This
technique avoids a “stuck” loop, in which the watchdog
timer would continue to be reset within the loop, keeping
the watchdog from timing out. Figure 13 shows an
example of a flow diagram where the I/O driving the
watchdog input is set high at the beginning of the pro-
gram, set low at the beginning of every subroutine or
loop, then set high again when the program returns to
the beginning. If the program should “hang” in any sub-
routine, the problem would quickly be corrected since
the I/O is continually set low and the watchdog timer is
allowed to time out, causing a reset to be issued.
Watchdog Input
The watchdog circuit monitors the µP’s activity. If the
µP does not toggle the watchdog input (WDI) within the
register-selectable watchdog-timeout period, RESET is
asserted for t . At the same time, the WD EN and WD
RP
TIME bits in the control register (Table 1) are reset to
zero and can only be set again by writing the appropri-
ate command to the control register. Thus, once a
RESET is asserted due to a watchdog timeout, the
watchdog function is disabled (Figure 12).
______________________________________________________________________________________ 23
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
START
MAX6917
V
OUT
SET WDI
HIGH
CHIP-ENABLE
OUTPUT
CONTROL
PROGRAM
CODE
RESET
GENERATOR
SUBROUTINE OF
PROGRAM LOOP
SET WDI HIGH
CE_IN
CE_OUT
RETURN
Figure 13. Watchdog Flow Diagram
Figure 14. Chip-Enable Gating
The propagation delay through the CE transmission
Chip-Enable Gating
gate depends on V , the source impedance of the
CC
Internal gating of chip-enable (CE) signals prevents
erroneous data from corrupting external SRAM in the
event of an undervoltage condition. The MAX6917 uses
a transmission gate from CE_IN to CE_OUT (Figure 14).
During normal operation (RESET inactive), the transmis-
sion gate is enabled and passes all CE transitions.
When reset is asserted, this path becomes disabled,
preventing erroneous data from corrupting the external
SRAM. The short CE propagation delay from CE_IN to
CE_OUT enables the MAX6917 to be used with most
µPs. If CE_IN is low when reset asserts, CE_OUT
driver connected to CE_IN, and the loading on
CE_OUT (see the Chip-Enable Propagation Delay vs.
CE_OUT Load Capacitance graph in the Typical
Operating Characteristics). For minimum propagation
delay, the capacitive load at CE_OUT should be mini-
mized, and a low-output-impedance driver should be
used on CE_IN (Figure 15).
VCC
remains low for t
write cycle.
to permit completion of the current
RCE
V
CC
BATT
3.6V
Chip-Enable Input
The CE transmission gate is disabled and CE_IN is high
impedance (disabled mode) while RESET is active. During
25Ω EQUIVALENT
MAX6917
a power-down sequence when V
passes the reset
CC
SOURCE IMPEDANCE
threshold, the CE transmission gate disables and CE_IN
immediately becomes high impedance if the voltage at
CE_IN is high. If CE_IN is low when RESET becomes
active, the CE transmission gate disables at the moment
50Ω
50Ω CABLE
CE_IN
CE_OUT
C
L
CE_IN goes high or t
after RESET is active, whichever
RCE
10pF
50Ω
occurs first (see the Chip-Enable Timing diagram). This
permits the current write cycle to complete during power-
down. The CE transmission gate remains disabled and
CE_IN remains high impedance (regardless of CE_IN
GND
activity) for most of the reset-timeout period (t ) any time
RST
a RESET is generated. When the CE transmission gate is
enabled, the impedance of CE_IN appears as a 46Ω (typ)
load in series with the load at CE_OUT.
C INCLUDES LOAD CAPACITANCE AND SCOPE PROBE CAPACITANCE.
L
Figure 15. Propagation Delay Test Circuit
24 ______________________________________________________________________________________
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
V
RST
V
RST
2.0V
V
CC
t
t
RP
t
RPD
RESET
V
RP
CC
CE_OUT
V
BATT
t
RCE
t
CED
CE_IN
Figure 16. Chip-Enable Timing Diagram
from a reset condition caused by V
< V
, the DATA
Chip-Enable Output
When the CE transmission gate is enabled, the imped-
ance seen at CE_OUT is equivalent to a 46Ω (typ)
resistor in series with the source driving CE_IN. In the
disabled mode, the transmission gate is off and an
CC
RST
VALID bit can be read to see if the data stored during
operation from the backup power supply is still valid (i.e.,
the backup power supply did not drop out). A one indi-
cates valid data and a zero indicates corrupted data.
Any time the internal supply to the MAX6917 (either
active pullup connects CE_OUT to V
(see Figures
OUT
V
BATT
or V
depending upon the operating conditions)
14, 16). This pullup turns off when the transmission
gate is enabled.
CC
drops below 1.5V to 1.6V (typ), the DATA VALID bit is set
to zero even if it has recently been set by a read of the
status register.
Test Configuration Register
This is a read-only register.
Data Valid Bit
DATA VALID has a POR setting of zero, indicating that
the data in the MAX6917 RTC is not guaranteed to be
valid (Table 1). A read of the status register sets the
DATA VALID bit to one, indicating valid data in the
MAX6917 RTC. In a system that uses a backup power
supply, the DATA VALID bit should be set to one by the
system software on first system power-up by reading the
status register. After that, any time the system recovers
______________________________________________________________________________________ 25
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
VBATT
V
CC
BATT_LO
BATT_LO
CONTROL
LOGIC
1.24V
R
SET+_EXT
R
SET+_INT
480kΩ
R
LOAD_EXT
(OPTIONAL)
INT/EXT
TEST
TRIP
TEST
INT/EXT
TEST = 0
R
SET-_INT
430kΩ
BATT
TEST
R
SET-_EXT
V
OUT
( 5mA)
MAX6917
Q
EXT
Figure 17. MAX6917 Battery Load and Test Circuit
0x0D (Figure 18). Writing to this register performs a
battery test and provided that the fresh battery is not
low, deactivates the BATT LO output and resets BATT
LO in the status register. Normal 24hr testing resumes.
If a different load or BATT LO thresholds are desired for
testing the backup battery, then external program resis-
tors can be used in conjunction with the TRIP and TEST
inputs (see the Battery Test-Control Register and Other
Test Options section).
Battery Test
Battery-Test Normal Operation
In normal operation, the battery-test circuitry uses the
control register POR settings of INT/EXT TEST, which is
set to logic low as default (Table 1). In this mode, all bat-
tery-test load resistors and threshold settings are internal.
When V
rises above V
, the MAX6917 automatically
CC
RST
performs one power-on battery monitor test. Additionally,
a battery check is performed every time that a reset is
issued, either from a manual reset or a watchdog timeout.
After that, periodic battery voltage monitoring at the facto-
Battery replacement following BATT_LO activation
should be done with V
nominal and not in battery-
CC
ry-programmed time interval of 24hr begins while V
applied.
is
backup mode so that SRAM data is not lost.
Alternatively, if SRAM data need not be saved, the bat-
CC
tery can be replaced with the V
supply removed. If a
CC
After each 24hr period (t
) has elapsed, the
BTCN
battery is replaced in battery-backup mode, sufficient
time must be allowed for the voltage on the V out-
MAX6917 connects V
test resistor (R
to an internal 0.91MΩ (typ)
BATT
SET+_Int
OUT
+ R
) for 1s (t
)
BTPW
SET-_Int
BATT
put to decay to zero. This ensures that the freshness-
seal mode of operation has been reset and is active
(Figure 17). During this 1s, if V
falls below the fac-
tory-programmed battery trip point V
, the open-
BTP
when V
is powered up again. If insufficient time is
CC
drain, battery-low output, BATT_LO, is asserted active
low and the BATT LO bit in the status register is set to
one. The BATT LO output can be register selected to
toggle at a 1Hz rate (0.5s on, 0.5s off) when active.
Once BATT LO is active, the 24hr tests stop until a
fresh battery is inserted and BATT LO is cleared by
writing any data to the battery test register at address
allowed, then V
must exceed V
during the sub-
CC
BATT
sequent power-up to ensure that the MAX6917 has left
battery-backup mode (Figure 19).
The MAX6917 does not constantly monitor an attached
battery because such monitoring would drastically
reduce the life of the battery. As a result, the MAX6917
26 ______________________________________________________________________________________
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
V
RST
V
CC
V
BATT
V
(BATTERY TEST POINT)
BTP
t
BTCN
t
BTPW
BATTERY-
t
BL
TEST ACTIVE
ONCE THE BATTERY IS DETECTED AS LOW,
THE PERIODIC BATTERY TESTING CEASES.
A BATTERY CHECK CAN BE INITIATED BY
WRITING TO THE REGISTER 0x1A.
BATT_LO
Figure 18. Battery-Test Timing Diagram
V
BATT
V
RST
V
V
V
RST
RST
RST
V
CC
BATTERY
ATTACH
BATTERY
DETACH
BATTERY
DETACH
BATTERY
ATTACH
V
BATT
0V
V
V
BATT
FLOATING
BATT
FLOATING
EXIT FRESHNESS
SEAL MODE
V
OUT
0V
V
CONNECTED TO V
V
CONNECTED
V
CONNECTED
V
CONNECTED
V
CONNECTED
BATT
BATT
OUT
CC
BATT
CC
FRESHNESS
SEAL RESET
TO V
TO V
TO V
TO V
OUT
OUT
OUT
OUT
Figure 19. Battery Switchover Diagram
only tests the battery for 1s every 24hr. If a good bat-
tery (one that has not been previously flagged with
BATT_LO) is removed between battery tests, the
MAX6917 does not immediately sense the removal and
does not activate BATT_LO until the next-scheduled
battery test. For this reason, a software-commanded
battery test should be performed after a battery
replacement by writing any data to the battery-test reg-
ister at address 1Ah.
ered down for excessively long periods can completely
drain their lithium cells without receiving any advanced
warning. To prevent such an occurrence, systems
using the MAX6917 battery-monitoring feature should
be powered up periodically (at least every few months)
to perform battery testing. Furthermore, anytime
BATT_LO is activated on the first battery test after a
power-up, data integrity should be checked through a
checksum or other technique. Timekeeping data would
also be suspect and should be checked for accuracy
against an accurate known reference.
Battery monitoring is only a useful technique when test-
ing can be done regularly over the entire life of a lithium
battery. Because the MAX6917 only performs battery
monitoring when V
is nominal, systems that are pow-
CC
______________________________________________________________________________________ 27
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
and/or D1 (BATT LO BLINK) in the control register to one,
the respective warning output toggles on every 0.5s and
off every 0.5s when set to active low by the internal
MAX6917 logic. This allows a more noticeable warning
indicator in systems where an LED is connected as a sta-
tus or warning light for the end user. The POR default set-
tings of zero leave these outputs set to logic low when
they are active.
Rf
MAX6917
Rd
Cg
12pF
Cd
12pF
D5 (INT/EXT TEST) selects whether the battery-test cir-
cuit is configured as internal or external (Table 1). If D5
is set to zero (default value), then the internal resistor-
divider is used between V
and GND to select the
BATT
battery-low trip point (Figure 17). The internal resistors,
X1
X2
EXTERNAL
CRYSTAL
R
and R
, are used to divide V
in
SET+_INT
SET-_IINT
BATT
half, as well as to provide the battery-test-load resis-
Figure 20. Oscillator Functional Schematic
tance of 0.91MΩ (typ).
If D5 (INT/EXT TEST) is set to one, then the two external
GROUND PLANE
VIA CONNECTION
resistors, R
and R
, are used to divide
SET+_EXT
SET-_EXT
V
down to the ratio for a trip point set at TRIP of
BATT
1.24V (V
*
*
GUARD RING
*
) (typ). R
plus R
in series
TRIP
SET+_EXT
SET-_EXT
*
provide the load resistance used during the 1s every-
24hr-battery test. If additional load resistance is
*
*
GROUND
PLANE VIA
CONNECTION
*
X1
*
**
desired, then an external load resistor, R
, can
LOAD_EXT
X2
be placed between V
and the collector or drain of
BATT
*
the transistor driven by TEST. The equivalent load resis-
tance used to test the battery is then R in par-
LOAD_EXT
SM WATCH CRYSTAL
*
allel with the series combination of R
plus
SET+_EXT
R
. In this mode, the internal resistors are
SET-_EXT
removed from TRIP and are not used as a load during
the battery-test pulse. TEST pulses high to perform the
battery test and remains low between tests.
**
*
**
GROUND PLANE
VIA CONNECTION
One final battery-test feature of the MAX6917 is the
software write address/command of 1Ah that forces a
1s battery test to be performed every time it is sent.
*LAYER 1 TRACE
**LAYER 2 LOCAL GROUND PLANE
CONNECT ONLY TO PIN 8
GROUND PLANE VIA CONNECTION
Frequency Outputs
The 1Hz and 32kHz (32.768kHz) frequency outputs
provide buffered, push-pull outputs for timing or clock-
ing of external devices. Each push-pull output is refer-
enced to GND for logic-low output levels and
Figure 21. Crystal Layout
Freshness-Seal Mode
When the battery is first attached to the MAX6917 without
power applied, the device does not immediately pro-
V
CC
referenced to V
for logic-high output levels.
OUT
vide battery-backup power to V
(Figure 19). Only
OUT
Disabled frequency outputs are held at a logic-low
level. The FOUT configuration register (Table 1) con-
tains individual enable bits that control the state of the
after V
and V
exceeds V
BATT
and later falls below both V
CC
RST RST
does the MAX6917 leave freshness-seal mode
and provide battery-backup power. This mode allows a
battery to be attached during manufacturing but not used
until after the system has been activated for the first time.
As a result, no battery energy is drained during storage
and shipping.
respective frequency output for V
operating mode
CC
and for V
operating mode.
BATT
Bits D5 (32kHz VBATT EN) and D4 (1Hz VBATT EN) in
the FOUT configuration register enable the respective
frequency output when operating from V
, if set to
BATT
Battery-Test Control Register and Other Test Options
There are two warning formats for the BATT_LO and
BATT_ON outputs. By setting D0 (BATT ON BLINK)
one, or disable the respective frequency output if set to
zero. POR settings disable all frequency outputs when
operating from V
.
BATT
28 ______________________________________________________________________________________
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Bits D7 (32kHz VCC EN) and D6 (1Hz VCC EN) in the
Place a guard ring around the crystal and tie the ring to
ground to help isolate the crystal from unwanted noise
pickup. Keep all signals out from beneath the crystal
and the X1 and X2 pins to prevent noise coupling.
Finally, an additional local ground plane on an adjacent
PC board layer can be added under the crystal to
shield it from unwanted pickup from traces on other lay-
ers of the board. This plane should be isolated from the
regular PC board ground, tied to the GND pin of the
MAX6917, and needs to be no larger than the perime-
ter of the guard ring. Ensure that this ground plane
does not contribute to significant capacitance between
the signal line and ground on the connections that run
from X1 and X2 to the crystal. See Figure 21.
FOUT configuration register enable the respective fre-
quency output when operating from V , if set to one,
CC
or disable the respective frequency output if set to
zero. POR settings enable both output frequencies
when operating from V
.
CC
Applications Information
Crystal Selection
Connect a 32.768kHz watch crystal directly to the
MAX6917 through pins 9 and 10 (X1, X2) (Figure 20).
Use a crystal with a specified load capacitance (C ) of
L
6pF. Refer to Applications Note 616: Considerations for
Maxim Real-Time Clock Crystal Selection from the
Maxim website (www.maxim-ic.com) for more informa-
tion regarding crystal parameters and crystal selection,
as well as a list of crystal manufacturers.
For frequency stability overtemperature, refer to the
Applications Note: Real-Time-Clock Selection and Opti-
mization from the Maxim website (www.maxim-ic.com.)
When designing the PC board, keep the crystal as
close to the X1 and X2 pins of the MAX6917 as possi-
ble. Keep the trace lengths short and small to reduce
capacitive loading and prevent unwanted noise pickup.
Chip Information
PROCESS: CMOS
______________________________________________________________________________________ 29
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Pin Configuration
Selector Guide
PART
SUPPLY VOLTAGE (V)
TOP VIEW
3.0
MAX6917EO30
MAX6917EO33
MAX6917EO50
V
1
2
3
4
5
6
7
8
9
20
19
V
V
OUT
BATT
3.3
5.0
TEST
TRIP
CC
18 RESET
17 BATT_LO
16 CE_OUT
15 ALM
BATT_ON
CE_IN
MR
MAX6917
WDI
14
SCL
GND
13 SDA
12 1HZ
X1
X2 10
11 32KHZ
QSOP
Typical Application Circuit
3.3V
3.3V 3.3V 3.3V
3.3V
3.3V
N.C.
LED
ALM
SDA
INTO
SDA
SCL
BATT_LO
BATT_ON
SCL
µC
1HZ
INT1
CS
X1
X2
CE_IN
RESET
WDI
CRYSTAL
RST
P1.0
GND
3.3V
N.C.
V
CC
TEST
TRIP
0.1µF
N.C.
MAX6917
N
32KHZ
N.C.
V
BATT
0.1µF
3.0V
I/O
CMOS SRAM
GND
V
OUT
0.1µF
USER RESET
MR
CE_OUT
CE
GND
30 ______________________________________________________________________________________
2
I C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
1
21-0055
E
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
MAX691ACUE-T
Power Supply Management Circuit, Adjustable, 1 Channel, PDSO16, 4.40 MM, MO-153AB, TSSOP-16
MAXIM
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