MAX7033_V01 [MAXIM]
315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock;
| 型号： | MAX7033_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock |
| 文件： | 总16页 (文件大小：908K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
General Description
Features
The MAX7033 fully integrated low-power CMOS super-
heterodyne receiver is ideal for receiving amplitude shift-
keyed (ASK) data in the 300MHz to 450MHz frequency
range. The receiver has an RF input signal range of
-114dBm to 0dBm. With few external components and a
low-current power-down mode, it is ideal for cost-sensitive
and power-sensitive applications typical in consumer
markets. The MAX7033 consists of a low-noise ampli-
fier (LNA), a fully differential image-rejection mixer, an
on-chip phase-locked loop (PLL) with integrated voltage-
controlled oscillator (VCO), a 10.7MHz IF limiting amplifier
stage with received-signal-strength indicator (RSSI), and
analog baseband data-recovery circuitry. The MAX7033
also has a discrete one-step automatic gain control
(AGC) that reduces the LNA gain by 35dB when the RF
input signal exceeds -62dBm. The AGC circuitry offers an
externally controlled hold feature.
● Optimized for 315MHz or 433MHz Band
● Operates from Single +3.3V or +5.0V Supplies
● High Dynamic Range with On-Chip AGC
● AGC Hold Circuit
● 1ms AGC Release Time
● Selectable Image-Rejection Center Frequency
● Selectable x64 or x32 f /f
Ratio
XTAL
LO
● Low 5.2mA Operating Supply Current
● < 3.5μA Low-Current Power-Down Mode for Efficient
Power Cycling
● 250μs Startup Time
● Built-In 44dB RF Image Rejection
● Better than -114dBm Receive Sensitivity
● -40°C to +105°C Operation
Ordering Information
The MAX7033 is available in 28-pin TSSOP and 32-pin
TQFN packages and is specified over the extended
(-40°C to +105°C) temperature range.
PART
TEMP RANGE
-40°C to +105°C
-40°C to +105°C
PIN-PACKAGE
28 TSSOP
MAX7033EUI+
MAX7033ETJ+
32 TQFN-EP*
Applications
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
● Security Systems
● Garage Door Openers
● Home Automation
● Remote Controls
● Local Telemetry
● Wireless Sensors
Typical Application Circuit appears at end of data sheet.
Pin Configurations
TOP VIEW
XTAL1
+
1
2
3
4
5
6
7
8
9
28 XTAL2
AVDD
LNAIN
27 SHDN
26 PDOUT
25 DATAOUT
LNASRC
AGND
+
N.C.
AGND
1
2
3
4
5
6
7
8
24 DATAOUT
23
24
V
DD5
V
DD5
MAX7033
LNAOUT
AVDD
23 DSP
22 DFFB
21 OPP
20 DSN
19 DFO
18 IFIN2
17 IFIN1
16 XTALSEL
15 AC
LNAOUT
AVDD
22 DSP
21 N.C.
20 DFFB
19 OPP
18 DSN
17 DFO
MAX7033
MIXIN1
MIXIN2
MIXIN1
MIXIN2
AGND
AGND 10
IRSEL 11
MIXOUT 12
DGND 13
DVDD 14
IRSEL
TSSOP
TQFN
19-3273; Rev 4; 4/14
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
Absolute Maximum Ratings
V
to AGND .....................................................-0.3V to +6.0V
Continuous Power Dissipation (T = +70°C)
A
DD5
AVDD to AGND ....................................................-0.3V to +4.0V
DVDD to DGND....................................................-0.3V to +4.0V
AGND to DGND ...................................................-0.1V to +0.1V
IRSEL, DATAOUT, XTALSEL,
28-Pin TSSOP (derate 12.8mW/°C above +70°C).1025.6mW
32-Thin QFN (derate 21.3mW/°C above +70°C) ...1702.1mW
Operating Temperature Range......................... -40°C to +105°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -60°C to +150°C
Lead Temperature (soldering 10s) ..................................+300°C
Soldering Temperature (reflow).......................................+260°C
AC, SHDN to AGND........................... -0.3V to (V
+ 0.3V)
+ 0.3V)
DD5
All Other Pins to AGND........................-0.3V to (V
DVDD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
DC Electrical Characteristics (+3.3V Operation)
(Typical Application Circuit, V
= V
= V
= +3.0V to +3.6V, no RF signal applied, T = -40°C to +105°C, unless otherwise
AVDD
DVDD
DD5 A
noted. Typical values are at V
= V
= V = +3.3V and T = +25°C.) (Note 1)
DD5 A
AVDD
DVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
,
AVDD
Supply Voltage
+3.3V nominal supply voltage
3.0
3.3
3.6
V
DVDD
f
f
f
f
= 315MHz
= 433MHz
= 315MHz
= 433MHz
5.2
5.7
2.6
3.5
6.23
6.88
RF
RF
RF
RF
Supply Current
I
V
= V
DVDD
mA
µA
DD
SHDN
V
V
= 0V,
= 0V
SHDN
XTALSEL
Shutdown Supply Current
I
SHDN
8.0
0.4
Input-Voltage Low
V
V
V
IL
IH
IH
Input-Voltage High
Input Logic Current High
V
V
- 0.4
DVDD
I
10
µA
f
f
f
I
I
= 433MHz, V
= 375MHz, V
= 315MHz, V
= V
= V
V
- 0.4
RF
IRSEL
IRSEL
IRSEL
DD5
DD5
1.1
Image-Reject Select Voltage
(Note 2)
/2
V
DD5
- 1.0
0.4
V
RF
DD5
= 0V
RF
DATAOUT Output-Voltage Low
DATAOUT Output-Voltage High
V
= 10µA
0.125
- 0.125
V
V
OL
SINK
V
= 10µA
V
DVDD
OH
SOURCE
DC Electrical Characteristics (+5.0V Operation)
(Typical Application Circuit, V
= +4.5V to +5.5V, no RF signal applied, T = -40°C to +105°C, unless otherwise noted. Typical
DD5
A
values are at V
= +5.0V and T = +25°C.) (Note 1)
A
DD5
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
TYP
5.0
5.2
5.7
3.7
4.2
MAX
5.5
UNITS
V
+5.0V nominal supply voltage
4.5
V
DD5
f
f
f
f
= 315MHz
= 433MHz
= 315MHz
= 433MHz
6.4
RF
RF
RF
RF
Supply Current
I
mA
V
= V
DD5
DD
SHDN
6.76
V
V
= 0V,
= 0V
SHDN
XTALSEL
Shutdown Supply Current
Input-Voltage Low
µA
V
I
SHDN
9.8
0.4
V
IL
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MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
Electrical Characteristics (continued)
(Typical Application Circuit, V
= +4.5V to +5.5V, no RF signal applied, T = -40°C to +105°C, unless otherwise noted. Typical
DD5
A
values are at V
= +5.0V and T = +25°C.) (Note 1)
A
DD5
PARAMETER
Input-Voltage High
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
V
- 0.4
- 0.4
IH
DD5
Input Logic Current High
I
15
µA
IH
f
f
f
I
I
= 433MHz, V
= 375MHz, V
= 315MHz, V
= V
= V
RF
IRSEL
IRSEL
IRSEL
DD5
DD5
1.1
Image-Reject Select Voltage
(Note 2)
/2
V
- 1.5
DD5
V
RF
DD5
= 0V
0.4
RF
DATAOUT Output-Voltage Low
DATAOUT Output-Voltage High
V
OL
= 10µA
0.125
V
V
SINK
V
= 10µA
V
- 0.125
DD5
OH
SOURCE
AC Electrical Characteristics
(Typical Application Circuit, V
= V
= V
= +3.0V to +3.6V, all RF inputs are referenced to 50Ω, f = 315MHz,
RF
AVDD
DVDD
DD5
T
= -40°C to +105°C, unless otherwise noted. Typical values are at V
= V
= V
= +3.3V and T = +25°C.) (Note 1)
A
AVDD
DVDD
DD5 A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL CHARACTERISTICS
Time for valid signal detection after V
SHDN
Startup Time
t
250
µs
ON
= V
DVDD
Receiver Input Frequency
f
300
450
MHz
dBm
RF
Maximum Receiver Input Level
Modulation depth > 18dB
Average carrier power level
Peak power level
0
-120
-114
8
Sensitivity (Note 3)
AGC Hysteresis
dBm
LNA gain from low to high
Switching time from low to high gain
Manchester coded
dB
ms
1
33
66
Maximum Data Rate
kbps
NRZ coded
LNA IN HIGH-GAIN MODE
f
f
f
= 433MHz
= 375MHz
= 315MHz
1 - j3.4
1 - j3.9
1 - j4.7
-22
RF
RF
RF
Input Impedance
Z
Normalized to 50Ω
IN_LNA
1dB Compression Point
P1dB
dBm
dBm
LNA
Input-Referred 3rd-Order Intercept
IIP3
-12
LNA
LO Signal Feedthrough to
Antenna
-80
3
dBm
dB
Noise Figure
NF
LNA
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MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
Electrical Characteristics (continued)
(Typical Application Circuit, V
= V
= V
= +3.0V to +3.6V, all RF inputs are referenced to 50Ω, f
= 315MHz,
RF
AVDD
DVDD
DD5
T
= -40°C to +105°C, unless otherwise noted. Typical values are at V
= V
= V
= +3.3V and T = +25°C.) (Note 1)
A
AVDD
DVDD
DD5 A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LNA IN LOW-GAIN MODE
f
f
f
= 433MHz
= 375MHz
= 315MHz
1 - j3.4
1 - j3.9
1 - j4.7
-10
RF
RF
RF
Normalized to 50Ω
(Note 4)
Input Impedance
Z
IN_LNA
1dB Compression Point
P1dB
dBm
dBm
LNA
Input-Referred 3rd-Order Intercept
IIP3
-7
LNA
LO Signal Feedthrough to
Antenna
-80
dBm
Noise Figure
NF
3
dB
dB
LNA
Voltage-Gain Reduction
MIXER
AGC enabled (depends on tank Q)
35
Input-Referred 3rd-Order Intercept
IIP3
-18
dBm
MIX
Output Impedance
Noise Figure
Z
330
16
42
44
44
48
13
Ω
OUT_MIX
NF
dB
MIX
f
f
f
= 433MHz, V
= 375MHz, V
= 315MHz, V
= V
= V
RF
RF
RF
IRSEL
IRSEL
IRSEL
DVDD
Image Rejection
(Not Including LNA Tank)
/2
dB
dB
DVDD
= 0V
LNA in high-gain mode
LNA in low-gain mode
LNA/Mixer Voltage Gain
330Ω IF filter load
INTERMEDIATE FREQUENCY (IF)
Input Impedance
Z
330
10.7
10
Ω
IN_IF
Operating Frequency
3dB Bandwidth
f
Bandpass response
MHz
MHz
dB
IF
RSSI Linearity
±0.5
80
RSSI Dynamic Range
dB
P
P
< -120dBm
1.15
2.2
RFIN
RSSI Level
V
V
> 0dBm, AGC enabled
RFIN
LNA gain from low to high
LNA gain from high to low
1.39
1.98
AGC Threshold
DATA FILTER
Maximum Bandwidth
DATA SLICER
50
kHz
kHz
Comparator Bandwidth
100
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MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
Electrical Characteristics (continued)
(Typical Application Circuit, V
= V
= V
= +3.0V to +3.6V, all RF inputs are referenced to 50Ω, f
= 315MHz,
RF
AVDD
DVDD
DD5
T
= -40°C to +105°C, unless otherwise noted. Typical values are at V
= V
= V
= +3.3V and T = +25°C.) (Note 1)
A
AVDD
DVDD
DD5 A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Maximum Load Capacitance
Output High Voltage
C
10
pF
V
LOAD
V
DD5
0
Output Low Voltage
V
CRYSTAL OSCILLATOR
V
V
V
V
= 0V
6.6128
13.2256
4.7547
9.5094
50
XTALSEL
XTALSEL
XTALSEL
XTALSEL
f
f
= 433MHz
RF
RF
= VDD5
= 0V
Crystal Frequency (Note 5)
f
MHz
XTAL
= 315MHz
= VDD5
Crystal Tolerance
Input Capacitance
ppm
pF
From each pin to ground
6.2
Note 1: 100% tested at T = +25°C. Guaranteed by design and characterization over temperature.
A
Note 2: IRSEL is internally set to 375MHz IR mode. It can be left open when the 375MHz image-rejection setting is desired. Bypass
to AGND with a 1nF capacitor in a noisy environment.
-3
Note 3: BER = 2 x 10 , Manchester encoded, data rate = 4kbps, IF bandwidth = 280kHz.
Note 4: Input impedance is measured at the LNAIN pin. Note that the impedance includes the 15nH inductive degeneration con-
nected from the LNA source to ground. The equivalent input circuit is 50Ω in series with 2.2pF.
Note 5: Crystal oscillator frequency for other RF carrier frequency within the 300MHz to 450MHz range is (f - 10.7MHz)/64 for
RF
V
= 0V, and (f - 10.7MHz)/32 for XTALSEL = V
.
XTALSEL
RF
DD5
Typical Operating Characteristics
(Typical Application Circuit, V
= V
= V
= +3.3V, f = 315MHz, T = +25°C, unless otherwise noted.)
AVDD
DVDD
DD5 RF A
SUPPLY CURRENT
vs. RF FREQUENCY
BIT-ERROR RATE
vs. AVERAGE CARRIER POWER
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
100
10
f
= 433MHz
+105°C
RF
+105°C
+85°C
1
f
= 315MHz
RF
+85°C
+25°C
-40°C
+25°C
0.1
0.01
-40°C
3.3
3.0
3.1
3.2
3.4
3.5
3.6
250
300
350
400
450
500
-130 -128 -126 -124 -122 -120 -118 -116 -114
AVERAGE CARRIER POWER (dBm)
SUPPLY VOLTAGE (V)
RF FREQUENCY (MHz)
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MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
Typical Operating Characteristics (continued)
(Typical Application Circuit, V
= V
= V
= +3.3V, f = 315MHz, T = +25°C, unless otherwise noted.)
AVDD
DVDD
DD5 RF A
RSSI AND DELTA
vs. IF INPUT POWER
RSSI vs. RF INPUT POWER
SENSITIVITY vs. TEMPERATURE
MAX7033 toc06
-108
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
3.5
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
AVERAGE CARRIER POWER
0.2% BER
IF BANDWIDTH = 280kHz
IF BANDWIDTH = 280kHz
V
= V
DVDD
AC
-110
-112
-114
-116
-118
2.5
1.5
f
= 433MHz
RF
0.5
V
= 0V
AC
-0.5
-1.5
-2.5
-3.5
DELTA
-120
-122
f
= 315MHz
RF
RSSI
-50
-124
-40
-15
10
35
60
85
110
-140 -120 -100 -80 -60 -40 -20
RF INPUT POWER (dBm)
0
-90
-70
-30
-10
10
TEMPERATURE (°C)
IF INPUT POWER (dBm)
LNA/MIXER VOLTAGE GAIN
vs. IF FREQUENCY
IMAGE REJECTION
vs. RF FREQUENCY
IMAGE REJECTION
vs. TEMPERATURE
65
55
45
35
25
15
5
55
50
45
40
35
30
45.0
44.5
44.0
43.5
43.0
42.5
42.0
41.5
41.0
40.5
f
= 315MHz
RF
UPPER
SIDEBAND
49dB IMAGE
REJECTION
LOWER
f
= 375MHz
RF
SIDEBAND
f
= 375MHz
f
RF
f
= 433MHz
RF
FROM RFIN
TO MIXOUT
= 315MHz
RF
f
= 315MHz
f
= 433MHz
RF
RF
-5
0
5
10
15
20
25
30
280 300 320 340 360 380 400 420 440 460 480
RF FREQUENCY (MHz)
-40
-15
10
35
60
85
IF FREQUENCY (MHz)
TEMPERATURE (°C)
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MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
Typical Operating Characteristics (continued)
(Typical Application Circuit, V
= V
= V
= +3.3V, f = 315MHz, T = +25°C, unless otherwise noted.)
AVDD
DVDD
DD5 RF A
NORMALIZED IF GAIN
vs. IF FREQUENCY
S
11
SMITH CHART PLOT OF RFIN
MAX7033 toc12
S
11
LOG MAGNITUDE PLOT OF RFIN
5
0
50
40
30
-5
WITH INPUT
MATCHING
20
500MHz
200MHz
10
-10
-15
-20
-25
-30
315MHz
0
-10
-20
-30
-40
-50
315MHz
-36dB
1
10
100
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
IF FREQUENCY (MHz)
REGULATOR VOLTAGE
vs. REGULATOR CURRENT
PHASE NOISE
vs. OFFSET FREQUENCY
PHASE NOISE
vs. OFFSET FREQUENCY
3.5
3.3
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
0
-20
0
-20
f
RF
= 315MHz
f
= 433MHz
RF
-40
-40
-40°C
-60
-60
+25°C
+85°C
+105°C
-80
-80
-100
-120
-140
-100
-120
-140
0
10
20
30
40
50
60
10
100
1k
10k 100k
1M
10M
10
100
1k
10k 100k
1M
10M
REGULATOR CURRENT (mA)
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
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MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
Pin Description
PIN
NAME
FUNCTION
TSSOP
TQFN
1
29
XTAL1
Crystal Input 1 (see the Phase-Locked Loop section)
Positive Analog Supply Voltage. For +5V operation, pin 2 is the output of an on-chip +3.2V
low-dropout regulator, and should be bypassed to AGND with a 0.1µF capacitor as close
as possible to the pin. Pin 7 must be externally connected to the supply from pin 2, and
bypassed to AGND with a 0.01µF capacitor as close as possible to the pin (see the Voltage
Regulator section and the Typical Application Circuit).
2, 7
4, 30
AVDD
3
4
31
32
2, 7
3
LNAIN
LNASRC
AGND
Low-Noise Amplifier Input (see the Low-Noise Amplifier section)
Low-Noise Amplifier Source for External Inductive Degeneration. Connect inductor to ground
to set the LNA input impedance (see the Low-Noise Amplifier section).
5, 10
6
Analog Ground
Low-Noise Amplifier Output. Connect to mixer input through an LC tank filter (see the Low-
Noise Amplifier section).
LNAOUT
8
9
5
6
MIXIN1
MIXIN2
1st Differential Mixer Input. Connect to LC tank filter from LNAOUT.
2nd Differential Mixer Input. Connect through a 100pF capacitor to V
side of the LC tank.
DD3
Image-Rejection Select. Set V
= 0V to center image rejection at 315MHz. Leave IRSEL
IRSEL
11
8
IRSEL
unconnected to center image rejection at 375MHz. Set V
= V
to center image
IRSEL
DD5
rejection at 433MHz.
12
13
9
MIXOUT
330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter.
10
DGND
Digital Ground
Positive Digital Supply Voltage. Connect to both of the AVDD pins. Bypass to DGND with a
0.01µF capacitor as close as possible to the pin (see the Typical Application Circuit).
14
15
16
11
12
14
DVDD
AC
Automatic Gain Control. See Figure 1. Internally pulled down to AGND with a 100kΩ resistor.
Crystal Divider Ratio Select. Drive XTALSEL low to select f /f
ratio of 64, or drive
LO XTAL
XTALSEL
XTALSEL high to select f /f
ratio of 32.
LO XTAL
1st Differential Intermediate-Frequency Limiter Amplifier Input. Bypass to AGND with a
1500pF capacitor as close to the pin as possible.
17
18
15
16
IFIN1
IFIN2
2nd Differential Intermediate-Frequency Limiter Amplifier Input. Connect to the output of a
10.7MHz bandpass filter.
19
20
21
22
23
17
18
19
20
22
DFO
DSN
OPP
DFFB
DSP
Data Filter Output
Negative Data Slicer Input
Noninverting Op-Amp Input for the Sallen-Key Data Filter
Data-Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
Positive Data Slicer Input
+5V Supply Voltage. Bypass to AGND with a 0.01µF capacitor as close as possible to the
pin. For +5V operation, V
appears at the pin 2 AVDD pin (see the Voltage Regulator section and the Typical Application
is the input to an on-chip voltage regulator whose +3.2V output
DD5
24
23
V
DD5
Circuit).
25
26
24
26
DATAOUT Digital Baseband Data Output
PDOUT
Peak-Detector Output
Power-Down Select Input. Drive high to power up the IC. Internally pulled down to AGND with
a 100kΩ resistor.
27
27
SHDN
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MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
Pin Description (continued)
PIN
NAME
FUNCTION
TSSOP
TQFN
Crystal Input 2. Can also be driven with an external reference oscillator (see the Crystal
Oscillator section).
28
28
XTAL2
1, 13,
21, 25
—
—
N.C.
No Connection
—
EP
Exposed Pad (TQFN Only). Connect EP to GND.
Functional Diagram
28-PIN TSSOP
PACKAGE
LNASRC
4
AC LNAOUT MIXIN1 MIXIN2
IRSEL
11
MIXOUT
12
IFIN1 IFIN2
17 18
15
6
8
9
0˚
IF LIMITING
AMPS
AUTOMATIC
GAIN
CONTROL
3
Q
I
LNA
LNAIN
AVDD
IMAGE
REJECTION
∑
2
24
7
90˚
MAX7033
3.2V REG
RSSI
V
DD5
AVDD
DVDD
DATA
FILTER
DIVIDE
BY 64
14
VCO
R
DF2
R
DF1
100kΩ
100kΩ
PHASE
LOOP
13
DGND
AGND
DETECTOR
FILTER
DATA
SLICER
5, 10
÷1
÷2
CRYSTAL
DRIVER
POWER-
DOWN
16
1
28
27
25
20 23 19
26
21
22
XTALSEL
XTAL1 XTAL2
SHDN DATAOUT
DSN DSP DFO
PDOUT OPP
DFFB
connect V
to the supply voltage. An on-chip voltage
DD5
Detailed Description
regulator drives one of the AVDD pins to approximately
+3.2V. For proper operation, DVDD and both the AVDD
pins must be connected together. Bypass V
and the pin 7 AVDD pin to AGND with 0.01μF capacitors,
and the pin 2 AVDD pin to AGND with a 0.1μF capacitor,
all placed as close as possible to the pins.
The MAX7033 CMOS superheterodyne receiver and a few
external components provide the complete receive chain
from the antenna to the digital output data. Depending on
signal power and component selection, data rates as high
as 33kbps Manchester (66kbps NRZ) can be achieved.
, DVDD,
DD5
The MAX7033 is designed to receive binary ASK data
modulated in the 300MHz to 450MHz frequency range.
ASK modulation uses a difference in amplitude of the car-
rier to represent logic 0 and logic 1 data.
Low-Noise Amplifier
The LNA is an nMOS cascode amplifier with off-chip
inductive degeneration, with a 3.0dB noise figure and an
IIP3 of -12dBm. The gain and noise figures are dependent
on both the antenna matching network at the LNA input
and the LC tank network between the LNA output and the
mixer inputs.
Voltage Regulator
For operation with a single +3.0V to +3.6V supply voltage,
connect AVDD, DVDD, and V
For operation with a single +4.5V to +5.5V supply voltage,
to the supply voltage.
DD5
Maxim Integrated
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MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
The off-chip inductive degeneration is achieved by con-
necting an inductor from LNASRC to AGND. This inductor
sets the real part of the input impedance at LNAIN, allow-
ing for a more flexible input impedance match, such as a
typical PCB trace antenna. A nominal value for this induc-
tor with a 50Ω input impedance is 15nH, but is affected
by PCB trace.
resistor. The resistor reduces the LNA gain by 35dB,
thereby reducing the RSSI output by about 500mV. The
LNA resumes high-gain mode when the RSSI level drops
back below 1.39V (approximately -70dBm at RF input)
for 1ms. The AGC has a hysteresis of 8dB. With the AGC
function, the MAX7033 can reliably produce an ASK out-
put for RF input levels up to 0dBm with modulation depth
of 18dB.
The LC tank filter connected to LNAOUT comprises L3
and C2 (see the Typical Application Circuit). Select L3
and C2 to resonate at the desired RF input frequency. The
resonant frequency is given by:
When the AC pin is high and SHDN goes high, the AGC
circuit is disabled and the LNA is always in high gain
mode. The AGC function can be resumed by bringing the
AC pin low when SHDN is high.
1
f
=
The MAX7033 features an AGC lock function that is
asserted when the level at the AC pin transitions from
low to high while SHDN is high. Locking the AGC locks
the LNA in the current gain state. As shown in Figure 1,
the AGC lock function can be enabled or disabled as long
as the SHDN pin is high. Changing the state of AC when
SHDN is low has no effect.
RF
2π L
× C
TOTAL
TOTAL
where:
L
= L3 + L
.
TOTAL
PARASITICS
C
= C2 + C
.
TOTAL
PARASITICS
L
and C
include inductance and
PARASITICS
PARASITICS
Mixer
capacitance of the PCB traces, package pins, mixer input
impedance, LNA output impedance, etc. These parasitics
at high frequencies cannot be ignored, and can have a
dramatic effect on the tank filter center frequency. Lab
experimentation should be done to optimize the center
frequency of the tank.
A unique feature of the MAX7033 is the integrated image
rejection of the mixer. This device eliminates the need
for a costly front-end SAW filter for most applications.
Advantages of not using a SAW filter are increased sen-
sitivity, simplified antenna matching, less board space,
and lower cost.
Automatic Gain Control
The mixer cell is a pair of double balanced mixers that
perform an IQ downconversion of the RF input to the
When the AC pin is low, the automatic gain-control (AGC)
circuit monitors the RSSI output. As the RSSI output
reaches 1.98V, which corresponds to RF input level of
-62dBm, the AGC switches on the LNA gain reduction
10.7MHz IF from a low-side injected LO (i.e., f
= f
LO
RF
- f ). The image-rejection circuit then combines these sig-
IF
nals to achieve 44dB of image rejection. Low-side injection
V
IH
V
IL
SHDN
PIN
V
IH
V
IL
AC PIN
AGC
AGC
AGC
AGC
NO
NO
NO
LOCK
UNLOCK
LOCK
UNLOCK
EFFECT
EFFECT
EFFECT
AGC
DISABLED
AGC
ENABLED
AGC
DISABLED
AGC ENABLED
Figure 1. AGC Lock Activation Cycles
Maxim Integrated
│ 10
www.maximintegrated.com
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
is required due to the on-chip image-rejection architec-
ture. The IF output is driven by a source follower biased to
create a driving-point impedance of 330Ω; this provides a
good match to the off-chip 330Ω ceramic IF filter.
Phase-Locked Loop
The PLL block contains a phase detector, charge pump,
integrated loop filter, VCO, asynchronous 64x clock
divider, and crystal oscillator driver. Besides the crystal,
this PLL does not require any external components. The
VCO generates a low-side LO. The relationship between
the RF, IF, and crystal frequencies is given by:
The IRSEL pin is a logic input that selects one of the
three possible image-rejection frequencies. When V
IRSEL
= 0V, the image rejection is tuned to 315MHz. V
=
IRSEL
V
= V
/2 tunes the image rejection to 375MHz, and V
DD5
IRSEL
f
- f
RF IF
f
=
tunes the image rejection to 433MHz. The IRSEL
XTAL
DD5
32 ×M
pin is internally set to V
when it is left unconnected, thereby eliminating the need
for an external V /2 voltage.
/2 (image rejection at 375MHz)
DD5
where:
M = 1 (V
= V
) or 2 (V = 0V)
XTALSEL
XTALSEL
DD5
DD5
To allow the smallest possible IF bandwidth (for best sen-
sitivity), minimize the tolerance of the reference crystal.
Table 1. Component Values for Typical Application Circuit
COMPONENT
VALUE FOR f = 433MHz
RF
VALUE FOR f = 315MHz
RF
DESCRIPTION
C1
C2
100pF
2pF
100pF
4pF
5%
± 0.1pF
C3
100pF
100pF
5%
C4
100pF
100pF
5%
C5
1500pF
220pF
1500pF
220pF
10%
C6
5%
C7
470pF
470pF
5%
C8
0.47µF
220pF
0.47µF
220pF
20%
C9
10%
C10
C11
C12
C13
C14
C15
L1
0.01µF
0.1µF
0.01µF
0.1µF
20%
20%
15pF
15pF
Depends on XTAL
15pF
15pF
Depends on XTAL
0.01µF
0.01µF
56nH
0.01µF
0.01µF
120nH
20%
20%
5% or better*
L2
15nH
15nH
5% or better*
L3
15nH
27nH
5% or better*
R1
5.1kΩ
5.1kΩ
5%
R2
Open
Open
—
R3
Short
Short
—
X1 (÷64)
X1 (÷32)
Y1
6.6128MHz**
13.2256MHz**
10.7MHz ceramic filter
4.7547MHz**
9.5094MHz**
10.7MHz ceramic filter
Crystek or Hong Kong Crystal
Crystek or Hong Kong Crystal
Murata
*Wire wound recommended.
**Crystal frequencies shown are for ÷64 (V
= 0V) and ÷32 (V
= V
)
XTALSEL
XTALSEL
DD
Maxim Integrated
│ 11
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MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
It is possible to use an external reference oscillator in
place of a crystal to drive the VCO. AC-couple the exter-
nal oscillator to XTAL2 with a 1000pF capacitor. Drive
XTAL2 with a signal level of approximately -10dBm.
AC-couple XTAL1 to ground with a 1000pF capacitor.
Intermediate Frequency and RSSI
The IF section presents a differential 330Ω load to provide
matching for the off-chip ceramic filter. The six internal
AC-coupled limiting amplifiers produce an overall gain of
approximately 65dB, with a bandpass-filter-type response
centered near the 10.7MHz IF frequency 1 with a 3dB
bandwidth of approximately 10MHz. The RSSI circuit
demodulates the IF by producing a DC output propor-
tional to the log of the IF signal level, with a slope of
approximately 14.2mV/dB (see the Typical Operating
Characteristics).
Data Filter
The data filter is implemented as a 2nd-order lowpass
Sallen-Key filter. The pole locations are set by the
combination of two on-chip resistors and two external
capacitors. Adjusting the value of the external capacitors
changes the corner frequency to optimize for different
data rates. The corner frequency should be set to approxi-
mately 1.5 times the fastest expected data rate from the
transmitter. Keeping the corner frequency near the data
rate rejects any noise at higher frequencies, resulting in
an increase in receiver sensitivity.
Applications Information
Crystal Oscillator
The crystal oscillator in the MAX7033 is designed to
present a capacitance of approximately 3pF between the
XTAL1 and XTAL2. If a crystal designed to oscillate with
a different load capacitance is used, the crystal is pulled
away from its stated operating frequency, introducing an
error in the reference frequency. Crystals designed to
operate with higher differential load capacitance always
pull the reference frequency higher. For example, a
4.7547MHz crystal designed to operate with a 10pF load
capacitance oscillates at 4.7563MHz with the MAX7033,
causing the receiver to be tuned to 315.1MHz rather than
315.0MHz, an error of about 100kHz, or 320ppm.
The configuration shown in Figure 2 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very flat amplitude response in the passband and
a rolloff rate of 40dB/decade for the two-pole filter. The
Bessel filter has a linear phase response, which works
well for filtering digital data. To calculate the value of C5
and C6, use the following equations, along with the coef-
ficients in Table 2:
b
C5 =
a 100k π f
(
)( )
(
)
)
C
C
In actuality, the oscillator pulls every crystal. The crystal’s
natural frequency is really below its specified frequency,
but when loaded with the specified load capacitance, the
crystal is pulled and oscillates at its specified frequency.
This pulling is already accounted for in the specification of
the load capacitance. Additional pulling can be calculated
if the electrical parameters of the crystal are known. The
frequency pulling is given by:
a
C6 =
4 100k π f
)( )
(
(
where f is the desired 3dB corner frequency.
C
Table 2. Coefficents to Calculate C5 and C6
FILTER TYPE
Butterworth (Q = 0.707)
Bessel (Q = 0.577)
a
b
1.414
1.3617
1.000
0.618
C
1
1
6
M
f
=
-
×10
P
2
C
+ C
C
+ C
SPEC
CASE
LOAD CASE
where:
f is the amount the crystal frequency pulled in ppm.
MAX7033
P
RSSI
R
C
C
C
C
is the motional capacitance of the crystal.
M
R
DF1
DF2
is the case capacitance.
CASE
SPEC
LOAD
100kΩ
100kΩ
is the specified load capacitance.
is the actual load capacitance.
22
DFFB
19
DFO
21
OPP
C6
C5
When the crystal is loaded as specified, i.e., C
=
LOAD
C
, the frequency pulling equals zero.
SPEC
Figure 2. Sallen-Key Lowpass Data Filter
Maxim Integrated
│ 12
www.maximintegrated.com
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
For example, to choose a Butterworth filter response with
a corner frequency of 5kHz:
MAX7033
1.000
C5 =
C6 =
≈ 450pF
1.414 100kΩ 3.14 5kHz
)( )( )(
(
)
DATA
SLICER
1.414
≈ 225pF
4 100kΩ 3.14 5kHz
( )( )( )(
)
25
20
DSN
23
DSP
19
DFO
Choosing standard capacitor values changes C5 to 470pF
and C6 to 220pF, as shown in the Typical Application
Circuit.
DATAOUT
R1
C4
Data Slicer
The data slicer takes the analog output of the data filter
and converts it to a digital signal. This is achieved by using
a comparator and comparing the analog input to a thresh-
old voltage. One input is supplied by the data filter output.
Both comparator inputs are accessible offchip to allow
for different methods of generating the slicing threshold,
which is applied to the second comparator input.
Figure 3. Generating Data Slicer Threshold
MAX7033
The suggested data slicer configuration uses a resistor
(R1) connected between DSN and DSP with a capacitor
(C4) from DSN to DGND (Figure 3). This configuration
averages the analog output of the filter and sets the
threshold to approximately 50% of that amplitude. With
this configuration, the threshold automatically adjusts as
the analog signal varies, minimizing the possibility for
errors in the digital data. The values of R1 and C4 affect
how fast the threshold tracks to the analog amplitude. Be
sure to keep the corner frequency of the RC circuit much
lower than the lowest expected data rate.
DATA
SLICER
25
23
DSP
20
DSN
19
DFO
DATAOUT
R4
R1
R2
R3
C4
*OPTIONAL
Figure 4. Generating Data Slicer Hysteresis
Note that a long string of zeros or ones can cause the
threshold to drift. This configuration works best if a coding
scheme, such as Manchester coding, which has an equal
number of zeros and ones, is used.
MAX7033
To prevent continuous toggling of DATAOUT in the
absence of an RF signal due to noise, add hysteresis to
the data slicer as shown in Figure 4.
DATA
SLICER
Peak Detector
The peak-detector output (PDOUT), in conjunction with
an external RC filter, creates a DC output voltage equal
to the peak value of the data signal. The resistor provides
a path for the capacitor to discharge, allowing the peak
detector to dynamically follow peak changes of the data-
filter output voltage. For faster data slicer response, use
the circuit shown in Figure 5.
25
23
DSP
19
DFO
26
PDOUT
20
DSN
DATAOUT
25kΩ
47nF
Figure 5. Using PDOUT for Faster Startup
Maxim Integrated
│ 13
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MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
To reduce the parasitic inductance, use wider traces and
a solid ground or power plane below the signal traces.
Also, use low-inductance connections to ground on all
GND pins, and place decoupling capacitors close to all
power-supply pins.
Layout Considerations
A properly designed PCB is an essential part of any RF/
microwave circuit. On high-frequency inputs and outputs,
use controlled-impedance lines and keep them as short
as possible to minimize losses and radiation. At high
frequencies, trace lengths that are on the order of λ/10 or
longer act as antennas.
Control Interface Considerations
When operating the MAX7033 with a +4.5V to +5.5V sup-
ply voltage, the SHDN and AC pins can be driven by a
microcontroller with either 3V or 5V interface logic levels.
When operating the MAX7033 with a +3.0V to +3.6V sup-
ply, only 3V logic from the microcontroller is allowed.
Keeping the traces short also reduces parasitic induc-
tance. Generally, 1in of a PCB trace adds about 20nH of
parasitic inductance. The parasitic inductance can have
a dramatic effect on the effective inductance of a pas-
sive component. For example, a 0.5in trace connecting a
100nH inductor adds an extra 10nH of inductance or 10%.
Typical Application Circuit
V
DD3
V
DD
(SEE TABLE)
X1
IF V IS
THEN V
IS
DD
DD3
3.0V TO 3.6V CONNECTED TO V
DD
CREATED BY LDO,
AVAILABLE AT AVDD
(PIN 2)
4.5V TO 5.5V
C11
C12
C13
1
2
3
4
28
XTAL1
AVDD
XTAL2
RF INPUT
TO/FROM µP
POWER-DOWN
DATA OUT
27
SHDN
PDOUT
C1
L1
26
25
LNAIN
LNASRC
MAX7033
R2
DATAOUT
C15
L2
5
6
24
23
AGND
V
DD5
R3
LNAOUT
DSP
C14
C3
V
DD3
7
8
9
22
21
20
19
18
17
16
15
L3
AVDD
DFFB
OPP
C2
MIXIN1
MIXIN2
AGND
IRSEL
MIXOUT
DGND
DVDD
C7
DSN
C4
10
DFO
C9
11
12
13
14
IFIN2
IFIN1
XTALSEL
AC
R1
**
FROM P
C5
C6
C8
*
Y1
C10
IF FILTER
IN
OUT
COMPONENT VALUES
IN TABLE 1
GND
**SEE THE MIXER SECTION.
*SEE PHASE-LOCKED LOOP SECTION.
Maxim Integrated
│ 14
www.maximintegrated.com
MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
Chip Information
PROCESS: CMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE OUTLINE
LAND
PATTERN NO.
CODE
NO.
28 TSSOP
U28+1
21-0066
21-0140
90-0171
90-0001
32 TQFN-EP
T3255+3
Maxim Integrated
│ 15
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MAX7033
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
7/04
Initial release
—
Updated Ordering Information, Pin Configurations, Absolute Maximum Ratings,
DC Electrical Characteristics, AC Electrical Characteristics, Typical Operating
Characteristics, Pin Description, Functional Diagram, Voltage Regulator and
Layout Considerations sections, Typical Application Circuit, Chip Information, and
Package Information
1
1/11
1–9, 13, 14, 15
Updated input impedance values in AC Electrical Characteristics table; updated
TOC3 and TOC4 labels in Typical Operating Characteristics; clarified equations
in Pin Description and Phase-Locked Loop and Crystal Oscillator sections;
updated components in Table 1; and added new Control Interface Considerations
section
2
3
9/11
4/14
3–6, 11–14
1
Updated Applications and General Description
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2014 Maxim Integrated Products, Inc.
│ 16
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