MAX7302_0712 [MAXIM]
SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA; 的SMBus /I²C接口， 9端口电平转换GPIO和LED驱动器，具有CLA
| 型号： | MAX7302_0712 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA |
| 文件： | 总30页 (文件大小：313K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0749; Rev 1; 12/07
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
General Description
Features
The MAX7302 I2C-/SMBus™-compatible, serial-interfaced
peripheral features 9 level-translating I/Os, and operates
from a 1.62V to 3.6V power supply. The MAX7302 fea-
LA
♦ 1.62V to 5.5V I/O Level-Translation Port Supply (V
♦ 1.62V to 3.6V Power Supply
)
♦ 9 Individually Configurable GPIO Ports
P1 Open-Drain I/O
tures a port supply V that allows level-translation on I/O
LA
ports to operate from a separate power supply from 1.62V
to 5.5V. An address select input, AD0, allows up to four
unique slave addresses for the device.
P2–P9 Push-Pull or Open-Drain I/Os
♦ Individual 33-Step PWM Intensity Control
♦ Blink Controls with 15 Steps on Outputs
The MAX7302 ports P2–P9 can be configured as inputs,
push-pull outputs, and open-drain outputs. Port P1 can
be configured as a general-purpose input, open-drain
output, or an open-drain INT output. Ports P2–P9 can be
configured as OSCIN and OSCOUT, respectively. Ports
P2–P9 can also be used as configurable logic arrays
(CLAs) to form user-defined logic gates, replacing exter-
nal discrete gates. Outputs are capable of sinking up to
25mA, and sourcing up to 10mA when configured as
push-pull outputs.
♦ 1kHz PWM Period Provides Flicker-Free LED
Intensity Control
♦ 25mA (max) Port Output Sink Current (100mA
max Ground Current)
♦ Inputs Overvoltage Protected Up to 5.5V (V
)
LA
♦ Transition Detection with Optional Interrupt Output
♦ Optional Input Debouncing
♦ I/O Ports Configurable as Logic Gates (CLA)
♦ External RST Input
The MAX7302 includes an internal oscillator for PWM,
blink, and key debounce, or to cascade multiple
MAX7302s. The external clock can be used to set a spe-
cific PWM and blink timing. The RST input asynchronous-
ly clears the 2-wire interface and terminates a bus lockup
involving the MAX7302.
♦ Oscillator Input and Output Enable Cascading
Multiple Devices
♦ Low 0.75µA (typ) Standby Current
Ordering Information
PIN-
PACKAGE
PKG
CODE
All ports configured as an output feature a 33-step PWM,
allowing any output to be set from fully off, 1/32 to 31/32
duty cycle, to fully on. All output ports also feature LED
blink control, allowing blink periods of 1/8s, 1/4s, 1/2s, 1s,
2s, 4s, or 8s. Any port can blink during this period with a
1/16 to 15/16 duty cycle.
PART
TEMP RANGE
MAX7302AEE+ -40°C to +125°C 16 QSOP
E16-4
16 TQFN-EP*
(3mm x 3mm)
MAX7302ATE+ -40°C to +125°C
T1633-4
+Denotes lead-free package.
*EP = Exposed paddle.
The MAX7302 is specified over the -40°C to +125°C
temperature range and is available in 16-pin QSOP and
16-pin TQFN (3mm x 3mm) packages.
Typical Operating Circuit
Applications
Cell Phones
+1.8V
+4.5V
Servers
V
DD
V
LA
System I/O Ports
μC
LCD/Keypad Backlights
LED Status Indicators
SDA
SCL
RST
INT
SDA
MAX7302
SCL
RST
P2
P1/INT
P3
P4
P5
P6
P7
P8
1.8V OPEN-DRAIN OUTPUT
4.5V PUSH-PULL OUTPUT
4.5V LOGIC INPUT
3.3V LOGIC INPUT
2.5V LOGIC INPUT
ADO
P9
GND
Pin Configurations appear at end of data sheet.
SMBus is a trademark of Intel Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.)
GND Current ....................................................................100mA
V
V
..........................................................................-0.3V to +4V
, SCL, SDA, AD0, RST, P1..................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
DD
LA
A
16-Pin QSOP (derate 8.3mW/°C over +70°C)..............666mW
16-Pin TQFN (derate 14.7mW/°C over +70°C) ..........1176mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
P2–P9 ............................................................-0.3V to V + 0.3V
LA
P1–P9 Sink Current ............................................................25mA
P2–P9 Source Current ........................................................10mA
SDA Sink Current ...............................................................10mA
V
V
Current .......................................................................10mA
Current ........................................................................35mA
DD
LA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = 1.62V to 3.6V, T = T
to T
, unless otherwise noted. Typical values are at V
= 3.3V, V = 3.3V, T = +25°C.) (Note 1)
DD LA A
DD
A
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
3.60
5.50
1.6
UNITS
Operating Supply Voltage
Port Logic Supply Voltage
Power-On-Reset Voltage
Power-On-Reset Hysteresis
V
1.62
1.62
1.0
V
V
DD
V
LA
V
V
rising
DD
1.3
V
POR
PORHYST
V
10
158
300
mV
Internal oscillator disabled;
SCL, SDA, digital inputs at V
GND; P1–P9 (as inputs) at V or
LA
or
DD
I
0.75
17
2
STB
GND
Standby Current (Interface Idle)
µA
µA
Internal oscillator enabled;
SCL, SDA, digital inputs at V
GND; P1–P9 (as inputs) at V or
LA
or
DD
I
25
OSC
GND
f
= 400kHz;
SCL
Supply Current (Interface Running)
Port Supply Current (V
I
31
40
5
SUP
other digital inputs at V
or GND
DD
)
I
Port inputs at V or GND
0.06
µA
V
LA
VLA
LA
Input High Voltage SDA, SCL, AD0, RST
Input Low Voltage SDA, SCL, AD0, RST
Input High Voltage P1–P9
V
0.7 x V
0.7 x V
0.7 x V
IH
DD
DD
LA
V
0.3 x V
V
IL
DD
DD
V
Input is V
Input is V
referred
referred
V
IHP
DD
DD
Input Low Voltage P1–P9
V
0.3 x V
V
ILP
Input High Voltage P1–P9
V
Input is V referred
V
IHPA
LA
Input Low Voltage P1–P9
V
Input is V referred
0.3 x V
+1
V
ILPA
LA
LA
Input Leakage Current SDA, SCL, AD0, RST
Input Leakage Current P1–P9
I
, I
V
V
or GND
or GND
-1
-2
µA
µA
IH IL
DD
LA
I
, I
+2
IHP ILP
Input Capacitance SDA, SCL, AD0,
P1–P9, RST
8
pF
V
V
V
V
V
V
= 1.62V, I
= 3mA
0.05
0.19
0.19
1.58
0.11
0.31
0.31
DD
DD
DD
LA
SINK
Output Low Voltage P1–P9
V
= 2.5V, I
= 3.3V, I
= 16mA
= 20mA
V
OL
SINK
SINK
= 1.62V, I
= 0.5mA
1.55
SOURCE
Output High Voltage P2–P9
Output Low Voltage SDA
V
≥ 2.5V, I
≥ 3.3V, I
= 5mA
V
V
- 0.4 2.32
V
V
OH
LA
SOURCE
SOURCE
LA
LA
= 10mA
- 0.6
3.1
LA
V
I
= 6mA
0.3
OLSDA
SINK
2
_______________________________________________________________________________________
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
PORT, INTERRUPT (INT), AND RESET (RST) TIMING CHARACTERISTICS
(V
DD
= 1.62V to 3.6V, T = T
to T
, unless otherwise noted. Typical values are at V
= 3.3V, V = 3.3V, T = +25°C.) (Note 1)
LA A
DD
A
MAX
MIN
(Figures 10, 15, 16 and 17)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
f
C
C
= internal oscillator
= OSCIN external input
≤ 100pF
32
kHz
MHz
µs
CLK
Oscillator Frequency
Port Output Data Valid High Time
f
CLK
1
4
CLK
t
PPVH
L
L
Port Output Data Valid Low Time (Note 6)
Port Input Setup Time
t
≤ 100pF (Note 2)
1/f
s
PPVL
CLK
t
C = 100pF
0
4
µs
PSU
L
Port Input Hold Time
t
C = 100pF
µs
PH
L
CLA Rise Time P5, P9 as Push-Pull Outputs
17
14
t
C = 100pF, V ≥ 2.7V
ns
ns
RFCLA
L
LA
CLA Fall Time P5, P9 as Push-Pull Outputs
CLA Propagation Delay P2, P3, or P4 to P5; P6, P7,
or P8 to P9
t
C = 100pF, V ≥ 2.7V
28
50
PDCLA
L
LA
INT Input Data Valid Time
t
C = 100pF
C = 100pF
L
4
4
µs
µs
ns
ns
IV
L
INT Reset Delay Time from Acknowledge
RST Rising to START Condition Setup Time
RST Pulse Width
t
IR
t
900
500
RST
t
W
SERIAL INTERFACE TIMING CHARACTERISTICS
(V
= 1.62V to 3.6V, T = T
to T
, unless otherwise noted. Typical values are at V
= 3.3V, V = 3.3V, T = +25°C.) (Note 1)
LA A
DD
A
MAX
DD
MIN
(Figure 10)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
kHz
ms
µs
Serial-Clock Frequency
Bus Timeout
f
400
SCL
TIMEOUT
t
31
Bus Free Time Between a STOP and a START Condition
Hold Time, (Repeated) START Condition
Repeated START Condition Setup Time
STOP Condition Setup Time
t
1.3
0.6
0.6
0.6
BUF
t
µs
HD,STA
t
µs
SU,STA
SU,STO
HD,DAT
t
µs
Data Hold Time
t
(Note 3)
0.9
µs
Data Setup Time
t
100
1.3
0.7
ns
SU,DAT
SCL Clock Low Period
t
µs
LOW
SCL Clock High Period
t
µs
HIGH
Rise Time of Both SDA and SCL Signals, Receiving
Fall Time of Both SDA and SCL Signals, Receiving
Fall Time of SDA Transmitting
t
(Notes 2, 4)
(Notes 2, 4)
(Note 4)
20 + 0.1C
300
300
250
ns
R
b
t
20 + 0.1C
ns
F
b
t
20 + 0.1C
ns
F.TX
b
Pulse Width of Spike Suppressed
Capacitive Load for Each Bus Line
t
(Note 5)
50
ns
SP
C
(Note 2)
400
pF
b
Note 1: All parameters are tested at T = +25°C. Specifications over temperature are guaranteed by design.
A
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V of the SCL signal) to bridge the
IL
undefined region of SCL’s falling edge.
Note 4: C = total capacitance of one bus line in pF. t and t are measured between 0.3 x V
and 0.7 x V
.
DD
b
R
F
DD
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Note 6: A startup time is required for the internal oscilator to start if it is not running already.
_______________________________________________________________________________________
3
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Typical Operating Characteristics
(V
= 3.3V, V = 3.3V and T = +25°C, unless otherwise noted.)
LA A
DD
STANDBY CURRENT
vs. TEMPERATURE
STANDBY CURRENT
vs. TEMPERATURE
STANDBY CURRENT
vs. TEMPERATURE
2.0
20
16
12
8
100
90
80
70
60
50
40
30
20
10
0
INTERFACE IDLE
INTERNAL OSCILLATOR
DISABLED
INTERFACE RUNNING
V
= 3.6V
DD
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= 3.6V
DD
V
= 3.3V
DD
V
= 1.62V
DD
V
= 3.6V
DD
V
= 3.3V
DD
V
= 1.62V
50
DD
V
= 1.62V
50
DD
4
V
= 3.3V
DD
INTERFACE IDLE
INTERNAL OSCILLATOR
RUNNING
0
-50 -25
0
25
75 100 125
-50 -25
0
25
50
75 100 125
-50 -25
0
25
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT LOW VOLTAGE
vs. SINK CURRENT
OUTPUT HIGH VOLTAGE
vs. TEMPERATURE
OUTPUT LOW VOLTAGE
vs. TEMPERATURE
0.4
0.3
0.2
0.1
0
3.6
3.0
2.4
1.8
1.2
0.6
0
0.30
0.24
0.18
0.12
0.06
0
LOAD CURRENT = 20mA
V
= 1.62V
DD
V
= 3.3V
DD
V
= 3.6V
DD
V
= 3.3V
DD
V
= 3.3V
DD
LOAD CURRENT = 10mA
-50 -25 25
TEMPERATURE (°C)
0
5
10
15
20
(mA)
25
30
35
0
50
75 100 125
-50 -25
0
25
50
75 100 125
I
SINK
TEMPERATURE (°C)
OUTPUT HIGH VOLTAGE
vs. SOURCE CURRENT
INTERNAL OSCILLATOR FREQUENCY
vs. TEMPERATURE
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
45
40
35
30
V
= 3.6V
LA
V
= 3.3V
LA
V
= 3.6V
DD
V
= 3.3V
DD
V
= 1.62V
LA
V
= 1.62V
DD
0
2
4
I
6
8
10
12
-50 -25
0
25
50
75 100 125
(mA)
TEMPERATURE (°C)
SOURCE
4
_______________________________________________________________________________________
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Typical Operating Characteristics (continued)
(V
= 3.3V, V = 3.3V and T = +25°C, unless otherwise noted.)
LA A
DD
CLA PROPAGATION DELAY
OUTPUT RISING
STAGGERED PWM OUTPUTS
MAX7302 toc09
MAX7302 toc10
C = 100pF
L
PORT2
5V/div
PORT2
2V/div
PORT3
5V/div
PORT3
2V/div
PORT4
5V/div
PORT5
2V/div
PORT5
5V/div
400μs/div
40ns/div
CLA PROPAGATION DELAY
OUTPUT FALLING
MAX7302 toc11
C = 100pF
L
PORT2
2V/div
PORT3
2V/div
PORT5
2V/div
40ns/div
_______________________________________________________________________________________
5
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Pin Description
PIN
NAME
FUNCTION
Port Supply for P1–P9. Connect V to a power supply between 1.62V and 5.5V.
QSOP
TQFN
LA
1
15
V
LA
Bypass V to GND with a 0.047µF ceramic capacitor.
LA
Address Input. Sets the device slave address. Connect to GND, V , SCL, or SDA to
DD
provide four address combinations.
2
3
16
1
AD0
Reset Input. RST is an active-low input, referenced to V , that clears the 2-wire interface
DD
RST
and can be configured to put the device in the power-up reset and/or to reset the PWM
and blink timing.
Input/Output Port. P1/INT is a general-purpose I/O that can be configured as a
transition detection interrupt output.
4
5
6
2
3
4
P1/INT
P2/OSCIN
P3/OSCOUT
P4–P9
Input/Output Port. P2/OSCIN is a general-purpose I/O that can be configured as the
oscillator input for PWM and blink features.
Input/Output Port. P3/OSCOUT is a general-purpose I/O that can be configured as the
PWM/blink/timing oscillator output for PWM and blink features.
7, 8, 9,
11, 12, 13
5, 6, 7,
9, 10, 11
Input/Output Ports. P4–P9 are general-purpose I/Os.
10
14
15
16
—
8
GND
SCL
SDA
Ground
12
13
14
EP
Serial-Clock Input
Serial-Data I/O
V
Positive Supply Voltage. Bypass V
to GND with a 0.047µF ceramic capacitor.
DD
DD
EP
Exposed Paddle on Package Underside. Connect to GND.
6
_______________________________________________________________________________________
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Block Diagram
V
LA
V
DD
MAX7302
AD0
SCL
SDA
RST
P1–P9
OUTPUT
LOGIC
I/O
2
I C
I/O
CONTROL
INPUT
LOGIC
REGISTER
BANK
CLA
GND
its output ports. Output ports have PWM and blink
capabilities, as well as logic drive.
Detailed Description
The MAX7302 9-port, general-purpose port expander
operates from a 1.62V to 3.6V power supply. Port P1
can be configured as an input and an open-drain out-
put. Port P1 can also be configured to function as an
INT output. Ports P2–P9 can be configured as inputs,
push-pull outputs, and open-drain outputs. Ports P2–P9
can be used as simple configurable logic arrays
(CLAs) to form user-defined logic gates.
Initial Power-Up
On power-up, the MAX7302 default configuration has all
9 ports, P1–P9, configured as input ports with logic lev-
els referenced to V . The transition detection interrupt
LA
status flag resets and stays high (see Tables 1 and 2).
Device Configuration Registers
The device configuration registers set up the interrupt
function, serial-interface bus timeout, and PWM/blink
oscillator options, global blink period, and reset options
(see Tables 3 and 4).
Each port configured as an open-drain or push-pull
output can sink up to 25mA. Push-pull outputs also
have a 5mA source drive capability. The MAX7302 is
rated to sink a total of 100mA into any combination of
_______________________________________________________________________________________
7
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Table 1. Register Address Map
REGISTER
ADDRESS
0x01
AUTOINCREMENT ADDRESS
POR STATE
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0xCC
0x8F
0x00
0x00
0x80
0x80
0x00
0x00
0x00
0x00
0xF0
0x80
Port P1 or INT Output
0x02
0x03
Port P2 or OSCIN Input
0x02
Port P3 or OSCOUT Output
Port P4
0x03
0x04
0x04
0x05
Port P5
0x05
0x06
Port P6
0x06
0x07
Port P7
0x07
0x08
Port P8
0x08
0x09
Port P9
0x09
0x0A or 0x4A
0x27
Configuration 26
0x26
Configuration 27
0x27
0x28
Ports P2–P5 Configurable Logic CLA0
Ports P6–P9 Configurable Logic CLA1
Write Ports P2–P5 Same Data; Read P2
Write Ports P6–P9 Same Data; Read P6
FACTORY RESERVED (Do not write to these registers)
CLA0 and CLA1 Configurable Logic Enable
CLA0 and CLA1 Configurable Logic Lock
Configuration 67 Lock, Ports P1–P5 Lock
Ports P6–P9 Lock
0x28
0x29
0x29
0x2A
0x3C
0x3D
0x3C–0x3F
0x70
0x3D
0x3E
0x3F–0x40
0x71
0x71
0x72
0x72
0x73
0x73
0x74
FACTORY RESERVED (Do not write to these registers)
0x00
0x01
Table 2. Power-Up Register Status
REGISTER DATA
ADDRESS
CODE (HEX)
REGISTER
POWER-UP CONDITION
D7 D6 D5 D4 D3 D2 D1 D0
Ports P_ are V -referred input ports with interrupt
LA
and debounce disabled
Ports P1–P9
0x01–0x09
0x26
1
1
1
0
1
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
0
1
RST does not reset registers or counters; blink period
is 1Hz; transition flag clear; interrupt status flag clear
Configuration 26
Configuration 27
Ports P1–P9 are GPIO ports; bus timeout is
disabled
0x27
Ports CLA0 to CLA1
CLA0 to CLA1
Default gate structure
CLA not enable
0x28–0x29
0x70
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Configuration 27 Lock,
Ports P1–P5 Lock
Configuration 27 is not locked;
ports P1–P5 are not locked
0x72
0x73
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
Ports P6–P9 Lock
Ports P6–P9 are not locked
8
_______________________________________________________________________________________
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Table 3. Configuration Register (0x26)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
An interrupt has occurred on at least one interrupt enabled input port.
No interrupt has occurred on an interrupt enabled input port.
A transition has occurred on an input port.
No transition has occurred on an input port.
Reserved
0
1*
0
Interrupt status flag
(read only)
D7
Transition flag
(read only)
D6
1*
—
0/1
0*
1
D5
Reserved
Blink prescalor bits
D4, D3, D2
Blink timer bits, see Table 10.
RST does not reset counters PWM/blink
RST resets PWM/blink counters
D1
RST timer
RST POR
0*
1
RST does not reset registers to power-on-reset state.
RST resets registers to power-on-reset state.
D0
*Default state.
Table 4. Configuration Register (0x27)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
Enables the bus timeout feature.
Disables the bus timeout feature.
Reserved
0
1
D7
Bus timeout
0
D6, D5, D4
Reserved
P3/OSCOUT
P2/OSCIN
1
Reserved
0
Sets P3 to output the oscillator.
D3
D2
D1
1*
0
Sets P3 as a GPIO controlled by register 0x03.
Sets P2 as the oscillator input.
1*
0
Sets P2 as a GPIO controlled by register 0x02.
Sets P1 as the interrupt output.
P1/INT output
Input transition
1
Sets P1 as a GPIO controlled by register 0x01.
Set to 0 on power-up to detect transition on inputs.
D0
0
*Default state.
_______________________________________________________________________________________
9
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
level of the port input, read the port I/O register bit, D0.
This readback value is the instantaneous logic level at
the time of the read request if debounce is disabled for
the port (port I/O register bit D2 = 0), or the debounced
result if debounce is enabled for the port (port I/O reg-
ister bit D2 = 1).
Slave Address
The MAX7302 is set to one of four I2C slave addresses,
using the address input AD0 (see Table 5) and is
accessed over an I2C or SMBus serial interface up to
400kHz. The MAX7302 slave address is determined on
each I2C transmission, regardless of whether or not the
transmission is actually addressing the device. The
MAX7302 distinguishes whether address input AD0 is
I/O Output Port
Configure a port as an output by writing a logic-low to the
MSB (bit D7) of the port I/O register. See Figures 2 and 3
for output port structure. The device reads back the logic
level, PWM, or the blink setting of the port (see Table 7).
The MAX7302 monitors the logic level of ports configured
as CLA outputs (see the Configurable Logic Array (CLA)
section).
connected to SDA, SCL, V , or GND during the trans-
DD
mission. Therefore, the MAX7302 slave address can be
configured dynamically in an application without tog-
gling the device supply.
I/O Port Registers
The port I/O registers set the I/O ports, one register per
port (see Tables 6 and 7). Ports can be independently
configured as inputs or outputs (D7), push-pull or open
drain (D6). Port P1 can only be configured as an input or
an open-drain output. The push-pull bit (D6) setting for
the port I/O register P1 is ignored.
Port Supplies and Level Translation
The port supply, V , provides the logic supplies to all
LA
push-pull I/O ports. Ports P2–P9 can be configured as
push-pull I/O ports (see Figure 3). V powers the logic-
LA
high port output voltage sourcing the logic-high port load
current. V provides level translation capability for the
LA
I/O Input Port
Configure a port as an input by writing a logic-high to
the MSB (bit D7) of the port I/O register (see Table 6).
See Figure 1 for input port structure. To obtain the logic
outputs and operates over a 1.62V to 5.5V voltage inde-
pendent of the MAX7302 power-supply voltage, V
.
DD
Each port set as an input can be configured to switch
midrail of either the V or the V port supplies.
DD
LA
Table 5. Slave Address Selection
Whenever the port supply reference is changed from V
DD
DEVICE ADDRESS
AD0
to V , or vice versa, read the port register to clear any
LA
R
transition flag on the port.
CONNECTION
A6 A5 A4 A3 A2 A1 A0
W
1
1
1
1
0
GND
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
V
DD
SCL
SDA
Table 6. Port I/O Registers (I/O Port Set as an Input, Registers 0x01/0x41 to 0x09/049)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
D7
Port I/O set bit
1
0
1
0
1
0
0
1
0
1
0
1
Sets the I/O port as an input.
Refers the input to the V supply voltage.
LA
Port supply
reference
D6
Refers the input to the V
supply voltage.
DD
Disables the transition interrupt.
Transition interrupt
enable
D5
D4, D3
D2
Enables the transition interrupt.
Reserved bits
Do not write to these registers.
Disables debouncing of the input port.
Enables debouncing of the input port.
No transition has occurred since the last port read.
A transition has occurred since the last port read.
Port input is logic-low.
Debounce
Port transition state
(read only)
D1
D0
Port status
(read only)
Port input is logic-high.
10 ______________________________________________________________________________________
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
V
DD
V
LA
PORT_ [2]
(DEBOUNCE)
PORT_ [6]
(THRESHOLD
SELECT)
PORT_ [0]
(PORTIN)
0
1
I/O
DEBOUNCE LOGIC
PORT_ [4:3]
TRANSITION
DETECTION
TRANSITION
DETECTION
PORT_ [5]
INTERRUPT
ENABLE
INTERRUPT
LOGIC
INT
INT2
INT9
INT
Figure 1. Input Port Structure
Table 7. Port I/O Registers (I/O Port Set as an Output, Registers 0x01 to 0x09)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
D7
Port I/O set bit
0
Sets the I/O port as an output.
Output port set to
push-pull
or open drain
0
1
Sets the output type to open drain.
Sets the output type to push-pull.
D6
0
Sets the output to PWM mode.
D5
PWM/blink enable
1
Sets the output to blink mode.
D4
D3
D2
D1
D0
Duty-cycle bit 4
Duty-cycle bit 3
Duty-cycle bit 2
Duty-cycle bit 1
Duty-cycle bit 0
0/1
0/1
0/1
0/1
0/1
MSB of the 5-bit duty-cycle setting. See Tables 9 and 11.
Bit 3 of the 5-bit duty-cycle setting. See Tables 9 and 11.
Bit 2 of the 5-bit duty-cycle setting. See Tables 9 and 11.
Bit 1 of the 5-bit duty-cycle setting. See Tables 9 and 11.
LSB of the 5-bit duty-cycle setting. See Tables 9 and 11.
______________________________________________________________________________________ 11
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
PORT_ [5]
5-BIT PWM
PORT_ [4:0]
0
1
I/O
3-BIT PRESCALER
CONFIG26 [4:2]
4-BIT BLINK
PORT_ [3:0]
CLOCK
Figure 2. Output Port Structure
V+
V
V+
V
LA
LA
SELECT
INPUT
SELECT
INPUT
PORT
P2–P9
PORT P1
OUTPUT
OUTPUT
P1
P2–P9
Figure 3. Port I/O Structure
Ports P2–P9 are overvoltage protected to V . This is true
When a bit position in the port lock register is set, the
corresponding port I/O registers cannot change. When a
port I/O register is locked as an output, none of its output
register settings can change. When a port I/O register is
locked as an input, only bits D0 and D1 can change, and
the locked input behaviour options, such as debounce
and transition detection, operate as normal.
LA
even for a port used as an input with a V
port logic-
DD
input threshold. Port P1 is overvoltage protected to 5.5V,
independent of V and V (see Figure 3). To mix logic
DD
LA
outputs with more than one voltage swing on a group of
ports using the same port supply, set the port supply volt-
age (V ) to be the highest output voltage. Use push-pull
LA
outputs and port P1 for the highest voltage ports, and use
open-drain outputs with external pullup resistors for the
lower voltage ports. When P2–P9 are acting as inputs ref-
Input Debounce
The MAX7302 samples the input ports every 31ms if
input debouncing is enabled for an input port (D2 = 1
of the port I/O register). The MAX7302 compares each
new sample with the previous sample. If the new sam-
ple and the previous sample have the same value, the
corresponding internal register updates.
erenced to V , make sure the V voltage is greater
DD
LA
than V - 0.3V.
DD
Port Lock Registers
Use the port lock registers to lock any combination of
port I/O register functionality (see Table 8). The port
lock registers are unlocked on power-up or by configur-
ing the RSTPOR bit to reset to POR value. The bits in
the port lock register can only be written to once. After
setting a bit to logic-high, the bit can only be cleared
by powering off the device.
When the port input is read through the serial interface,
the MAX7302 does not return the instantaneous value
of the logic level from the port because debounce is
active. Instead, the MAX7302 returns the stored
debounced input signal.
12 ______________________________________________________________________________________
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Table 8. Port Lock Registers
REGISTER DATA
ADDRESS
CODE
D7
D6
D5
D4
D3
D2
D1
D0
Port
P5
Port
P4
Port
P3
Port
P2
Port
P1
Configuration
register 0x27
0x72
0x73
—
0
Port
P9
Port
P8
Port
P7
Port
P6
—
—
—
—
When debouncing is enabled for a port input, transition
detection applies to the stored debounced input signal
value, rather than to the instantaneous value at the
input. This process allows for useful transition detection
of noisy signals, such as keyswitch inputs, without
causing spurious interrupts.
The INT output never reasserts during a read sequence
because this process could cause a recursive reentry
into the interrupt service routine. Instead, if a data
change occurs during the read that would normally set
the INT output, the interrupt assertion is delayed until
the STOP condition. If the changed input data is read
before the STOP condition, a new interrupt is not
required and not asserted. The INT bit and INT output
(if selected) have the same value at all times.
Port Input Transition Detection and Interrupt
Any transition on ports configured as inputs automatically
set the D1 bit of that port’s I/O registers high. Any input can
be selected to assert an interrupt output indicating a transi-
tion has occurred at the input port(s). The MAX7302 sam-
ples the port input (internally latched into a snapshot
register) during a read access to its port P_ I/O register.
The MAX7302 continuously compares the snapshot with
the port’s input condition. If the device detects a change
for any port input, an internal transition flag sets for that
port. Read register 0x26 to clear the interrupt, then read all
the port I/O registers (0x01 to 0x09) by initiating a burst
read to clear the MAX7302’s internal transition flag. Note
that when debouncing is enabled for a port input, transition
detection applies to the stored debounced input signal
value, rather than to the instantaneous value at the input.
Transition bits D4 and D3 must be set to 0 to detect the
next rising or falling edge on the input port P_.
Transition Flag
The Transition bit in device configuration register 0x26 is
a NOR of all the port I/O registers’ individual Transition
bits. A port I/O register’s Transition bit sets when that
port is set as an input, and the input changes from the
port’s I/O registers last read through the serial interface.
A port’s individual Transition bit clears by reading that
port’s I/O register. The Transition flag of configuration
register 0x26 is only cleared after reading all port I/O
registers on which a transition has occurred.
RST Input
The active-low RST input operates as a hardware reset
2
which voids any on-going I C transaction involving the
MAX7302. This feature allows the MAX7302 supply cur-
rent to be minimized in power critical applications by
effectively disconnecting the MAX7302 from the bus.
RST also operates as a chip enable, allowing multiple
The MAX7302 allows the user to select the input port(s)
that cause an interrupt on the INT output. Set INT for
each port by using the INTenable bit (bit D5) in each
port P_ register. The appropriate port’s transition flag
always sets when an input changes, regardless of the
port’s INTenable bit settings. The INTenable bits allow
processor interrupt only on critical events, while the
inputs and the transition flags can be polled periodical-
ly to detect less critical events.
2
devices to use the same I C slave address if only one
MAX7302 has its RST input high at any time. RST can
be configured to restore all port registers to the power-
up settings by setting bit D0 of device configuration reg-
ister 0x26 (Table 1). RST can also be configured to reset
the internal timing counters used for PWM and blink by
setting bit D1 of device configuration register 0x26.
When debounce is disabled, signal transtions between
the 9th and 11th falling edges of clock will not be regis-
tered since the transition is detected and cleared at the
same read cycle.
2
When RST is low, the MAX7302 is forced into the I C
STOP condition. The reset action does not clear the
interrupt output INT. The RST input is referenced to VDD
and is overvoltage tolerant up to the supply voltage, VLA
.
Ports configured as outputs do not feature transition
detection, and therefore, cannot cause an interrupt.
The exception to this rule is the CLA outputs.
______________________________________________________________________________________ 13
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
connects to the P2/OSCIN port. The P3/OSCOUT port
provides a buffered and level-shifted output of the inter-
nal oscillator or external clock to drive other devices.
Select the P2/OSCIN and P3/OSCOUT port options
using the device configuration register 0x67 bits D2
and D3 (see Table 4).
INT Output
Port P1 can be configured as a latching interrupt out-
put, INT, that flags any transients on any combination of
selected ports configured as inputs. Configurable logic
gate outputs can also be monitored as readback inputs
with the same options as normal I/O port inputs. Any
transitions occurring at the selected inputs assert INT
low to alert the host processor of data changes at the
selected inputs. Reset INT by reading any ports I/O
registers (0x01 to 0x09).
The P2/OSCIN port is overvoltage protected to supply
voltage V , so the external clock can exceed V
if
LA
DD
V
is greater than V . The port P2 register (see
LA
DD
Tables 2 and 6) sets the P2/OSCIN logic threshold
(30%/70%) to either the V supply or the V
.
LA
DD
Standby Mode
Upon power-up, the MAX7302 enters standby mode
when the serial interface is idle. If any of the PWM
intensity control, blink, or debounce features are used,
the operating current rises because the internal PWM
oscillator is running and toggling counters. When using
OSCIN to override the internal oscillator, the operating
current varies according to the frequency at OSCIN.
When the serial interface is active, the operating cur-
rent also increases because the MAX7302, like all I2C
slaves, has to monitor every transmission. The bus
timeout and debounce circuits use the internal oscilla-
tor even if OSCIN is selected.
Use OSCOUT or an external clock source to cascade
up to four MAX7302s per master for applications requir-
ing additional ports. To synchronize the blink action
across multiple MAX7302s (see Figures 4 and 5), use
OSCOUT from one MAX7302 to drive OSCIN of the
other MAX7302s. This process ensures the same blink
frequency of all the devices, but also make sure to syn-
chronize the blink phase. The blink timing of multiple
MAX7302s is synchronous at the instant of power-up
because the blink and PWM counters clear by each
MAX7302’s internal reset circuit, and by default the
MAX7302s’ internal oscillators are off upon power-up.
Ensure that the blink phase of all the devices remains
synchronized by programming the OSCIN and
OSCOUT functionality before programming any feature
that causes a MAX7302’s internal oscillator to operate
(blink, PWM, bus timeout, or key debounce). Configure
the RST input to reset the internal timing counters used
for PWM and blink by setting bit D1 of device configu-
ration register 0x26 (see Table 3).
Internal Oscillator and OSCIN/OSCOUT
External Clock Options
The MAX7302 contains an internal 32kHz oscillator. The
MAX7302 always uses the internal oscillator for bus
timeout and for debounce timing (when enabled). It is
used by default to generate PWM and blink timing. The
internal oscillator only runs when the clock output
OSCOUT is needed to keep the operating current as
low as possible.
PWM and Blink Timing
The MAX7302 divides the 32kHz nominal internal oscilla-
tor OSC or external clock source OSCIN frequency by 32
to provide a nominal 1kHz PWM frequency. Use the reset
The MAX7302 can use an external clock source instead
of the internal oscillator for the PWM and blink timing.
The external clock can range from DC to 1MHz, and it
MAX7302
MAX7302
MAX7302
MAX7302
P3/OSCOUT
P2/OSCIN
P2/OSCIN
MAX7302
MAX7302
P3/OSCOUT
P2/OSCIN
P2/OSCIN
P3/OSCOUT
Figure 4. Synchronizing Multiple MAX7302s (Internal Oscillator)
14 ______________________________________________________________________________________
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
MAX7302
0 TO 1MHz
MAX7302
MAX7302
EXTERNAL
OSCILLATOR
P2/OSCIN
P2/OSCIN
P2/OSCIN
P2/OSCIN
MAX7302
MAX7302
MAX7302
0 TO 1MHz
EXTERNAL
OSCILLATOR
P2/OSCIN
P3/OSCOUT
P2/OSCIN
P3/OSCOUT
Figure 5. Synchronizing Multiple MAX7302s (External Clock)
Table 9. PWM Settings on Output Port
REGISTER DATA
PWM SETTINGS
D7
0
D6
X
D5
0
D4
0
D3
0
D2
D1
0
D0
0
Port P_ is a static logic-level low output port
Port P_ is a PWM output port; PWM duty cycle is 1/32
Port P_ is a PWM output port; PWM duty cycle is 2/32
Port P_ is a PWM output port; PWM duty cycle is 3/32
Port P_ is a PWM output port; PWM duty cycle is 4/32
…
0
0
0
0
1
0
X
0
0
0
0
1
0
X
0
0
0
1
0
0
X
0
0
0
1
1
0
X
0
0
0
0
0
…
Port P_ is a PWM output port; PWM duty cycle is 30/32
Port P_ is a PWM output port; PWM duty cycle is 31/32
Port P_ is a static logic-level high output port
0
0
0
X
X
1
0
0
1
1
1
1
1
1
X
1
1
X
1
1
X
0
1
X
function to synchronize multiple MAX7302s that are oper-
ating from the same OSCIN, or to synchronize a single
MAX7302’s blink timing to an external event. Configure
the RST input to reset the internal timing counters used by
PWM and blink by setting bit D1 of the device configura-
tion register 0x26 (see Table 3).
OSCOUT from its internal clock, and use this signal to
drive the remaining MAX7302s’ OSCIN.
A PWM period contains 32 cycles of the nominal 1kHz
PWM clock (see Figure 6). Set ports individually to a
PWM duty cycle between 0/32 and 31/32. For static
logic-level low output, set the ports to 0/32 PWM, and
for static logic-level high output, set the port register to
0111XXXX (see Table 9). The MAX7302 staggers the
PWM timing of the 9-port outputs, in single or dual
ports, by 1/8 of the PWM period. These phase shifts
distribute the port-output switching points across the
PWM period (see Figure 7). This staggering reduces
the di/dt output-switching transient on the supply and
also reduces the peak/mean current requirement.
The MAX7302 uses the internal oscillator by default.
Configure port P2 using device configuration register
0x27 bit D2 (see Table 4) as an external clock source
input, OSCIN, if the application requires a particular or
more accurate timing for the PWM or blink functions.
OSCIN only applies to PWM and blink; the MAX7302
always uses the internal oscillator for debouncing and
bus timeout. OSCIN can range up to 1MHz. Use device
configuration register 0x27 bit D3 (see Table 4) to con-
figure port P3 as OSCOUT to output a MAX7302’s
clock. The MAX7302 buffers the clock output of either
the internal oscillator OSC or the external clock source
OSCIN, according to port D2’s setup. Synchronize mul-
tiple MAX7302s without using an external clock source
input by configuring one MAX7302 to generate
All ports feature LED blink control. A global blink period
of 1/8s, 1/4s, 1/2s, 1s, 2s, 4s, or 8s applies to all ports
(see Table 10). Any port can blink during this period
with a 1/16 to 15/16 duty cycle, adjustable in 1/16
increments (see Table 11). For PWM fan control, the
MAX7302 can set the blink frequency to 32Hz.
______________________________________________________________________________________ 15
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
PORT
REGISTER
VALUE
977μs NOMINAL PWM PERIOD (1024Hz PERIOD)
OUTPUT STATIC LOW (STATIC LOGIC-LOW OUTPUT OR LED DRIVE ON)
HIGH-Z
LOW
0b0X000000
0b0X000001
0b0X000010
0b0X000011
HIGH-Z
LOW
OUTPUT LOW 1/32 DUTY PWM
OUTPUT LOW 2/32 DUTY PWM
OUTPUT LOW 3/32 DUTY PWM
HIGH-Z
LOW
HIGH-Z
LOW
HIGH-Z
LOW
0b0X011101
OUTPUT LOW 29/32 DUTY PWM
HIGH-Z
LOW
OUTPUT LOW 30/32 DUTY PWM
0b0X011110
0b0X011111
0b0111XXXX
HIGH-Z
LOW
OUTPUT LOW 31/32 DUTY PWM
HIGH-Z
LOW
OUTPUT STATIC HIGH (STATIC LOGIC-HIGH OUTPUT OR LED DRIVE OFF)
Figure 6. Static and PWM Port Output Waveforms
977μs NOMINAL PWM PERIOD
NEXT PWM PERIOD
NEXT PWM PERIOD
0
1
2
3
4
5
6
7
8
OUTPUT P8
OUTPUTS P1, P9
OUTPUT P2
OUTPUT P3
OUTPUT P4
OUTPUT P5
OUTPUT P6
OUTPUT P7
OUTPUT P8
OUTPUTS P1, P9
OUTPUT P8
OUTPUTS P1, P9
OUTPUT P2
OUTPUTP3
OUTPUT P4
OUTPUT P5
OUTPUT P6
OUTPUT P7
OUTPUT P2
OUTPUT P3
Figure 7. Staggered PWM Phasing Between Port Outputs
16 ______________________________________________________________________________________
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Table 10. Blink and PWM Frequencies
DEVICE CONFIGURATION
REGISTER 0x26
BLINK OR PWM
FREQUENCY (32kHz
INTERNAL OSCILLATOR)
(Hz)
BLINK OR PWM
FREQUENCY (0 TO 1MHz
EXTERNAL OSCILLATOR)
BLINK OR PWM SETTING
BIT D4
BIT D3
BIT D2
BLINK2 BLINK1 BLINK0
Blink period is 8s (0.125Hz)
Blink period is 4s (0.25Hz)
Blink period is 2s (0.5Hz)
Blink period is 1s (1Hz)
Blink period is a 1/2s (2Hz)
Blink period is a 1/4s (4Hz)
Blink period is an 1/8s (8Hz)
Blink period is a 1/32s (32Hz)
PWM
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
0.125
0.25
0.5
1
OSCIN / 262,144
OSCIN / 131,072
OSCIN / 65,536
OSCIN / 32,768
OSCIN / 16,384
OSCIN / 8192
OSCIN / 4096
OSCIN / 1024
OSCIN / 32
2
4
8
32
1024
Table 11. Blink Settings on Output Ports
REGISTER DATA
PWM SETTINGS
D7
D6
X
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
Port P_ is a static logic-level low output port
Port P_ is a PWM output port; PWM duty cycle is 1/16
Port P_ is a PWM output port; PWM duty cycle is 2/16
Port P_ is a PWM output port; PWM duty cycle is 3/16
…
0
0
0
0
X
1
0
0
0
0
1
X
1
0
0
0
1
0
X
1
0
0
1
0
0
…
Port P_ is a PWM output port; PWM duty cycle is 14/16
Port P_ is a PWM output port; PWM duty cycle is 15/16
Port P_ is a static logic-level high output port (32/32)
0
0
0
X
X
1
1
1
1
0
0
1
1
1
X
1
1
X
1
1
X
0
1
X
Table 12. CLA0 (P2–P5) Configuration Register Setting (0x28)
REGISTER BIT
FUNCTION
D5
D4
D3
D2
0
1
0
1
0
0
1
1
0
0
1
1
D1
D0
XOR noninverted
XOR P3 inverted
0
0
1
1
0
1
0
1
0
1
0
1
0
1
X
X
XOR P2 inverted
XOR both ports inverted
3 input AND/OR all noninverted
3 input AND/OR P2 inverted
0
0
0
0
1
1
1
1
3 input AND/OR P3 inverted
3 input AND/OR P4 inverted
1
1
1
3 input AND/OR P2 and P3 inverted
3 input AND/OR P2 and P4 inverted
3 input AND/OR P3 and P4 inverted
3 input AND/OR all inverted
______________________________________________________________________________________ 17
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Table 12. CLA0 (P2–P5) Configuration Register Setting (0x28) (continued)
REGISTER BIT
FUNCTION
D5
D4
D3
D2
0
D1
D0
0
2 input AND/OR P2 and P3 noninverted
2 input AND/OR P2 and P3 inverted
2 input AND/OR P2 inverted and P3
2 input AND/OR P2 and P3 both inverted
2 input AND/OR P2 and P4 noninverted
2 input AND/OR P2 and P4 inverted
2 input AND/OR P2 inverted and P4
2 input AND/OR P2 and P4 both inverted
2 input AND/OR P3 and P4 noninverted
2 input AND/OR P3 and P4 inverted
2 input AND/OR P3 inverted and P4
2 input AND/OR P3 and P4 both inverted
1
0
0
X
1
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
X
1
0
1
1
0
1
0
1
X
Table 13. Output P5 Configuration
BIT
LOGIC LEVEL
FUNCTION
Output not cascaded to CLA1
Output cascaded to CLA1
Output noninverted
0
1
0
1
D7
D6
Output inverted
Table 14. CLA1 (P6–P9) Configuration Register Setting (0x29)
REGISTER BIT
FUNCTION
D5
D4
D3
D2
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
D1
D0
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
XOR noninverted
XOR P7 inverted
0
1
X
X
XOR P6 inverted
XOR both ports inverted
3 input AND/OR all noninverted
3 input AND/OR P6 inverted
0
0
0
0
1
1
1
1
3 input AND/OR P7 inverted
3 input AND/OR P8 inverted
1
0
1
1
1
1
3 input AND/OR P6 and P7 inverted
3 input AND/OR P6 and P8 inverted
3 input AND/OR P7 and P8 inverted
3 input AND/OR all inverted
2 input AND/OR P6 and P7 noninverted
2 input AND/OR P6 and P7 inverted
2 input AND/OR P6 inverted and P7
2 input AND/OR P6 and P7 both inverted
X
18 ______________________________________________________________________________________
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Table 14. CLA1 (P6–P9) Configuration Register Setting (0x29) (continued)
REGISTER BIT
FUNCTION
D5
D4
0
D3
D2
D1
D0
0
2 input AND/OR P6 and P8 noninverted
2 input AND/OR P6 and P8 inverted
2 input AND/OR P6 inverted and P8
2 input AND/OR P6 and P8 both inverted
2 input AND/OR P7 and P8 noninverted
2 input AND/OR P7 and P8 inverted
2 input AND/OR P7 inverted and P8
2 input AND/OR P7 and P8 both inverted
1
0
1
0
X
1
0
1
1
1
0
0
1
0
1
0
1
1
0
X
1
1
Table 15. Output P9 and Cascade P5
Input Configuration
Table 17. Configurable Logic-Array Lock
Register (0x71)
BIT
LOGIC LEVEL
FUNCTION
Cascade input noninverted
Cascade input inverted
Output noninverted
REGISTER DATA
REGISTER
D7–D2
D1
D0
0
1
0
1
D7
CLA0 and CLA1 configurable
logic lock
CLA1 CLA0
D6
CLA0 is not locked
CLA0 is locked
CLA1 is not locked
CLA1 is locked
—
—
—
—
X
X
0
1
0
1
X
X
Output inverted
Table 16. Configurable Logic-Array
Enable Register (0x70)
REGISTER DATA
REGISTER
D7–D2
D1
D0
CLA0 and CLA1 configurable
logic enable
CLA1 CLA0
Ports P2–P5 are GPIO ports
—
—
—
—
X
X
0
1
0
1
X
X
Ports P2–P5 are configurable logic
CLA0
Ports P6–P9 are GPIO ports
Ports P6–P9 are configurable logic
CLA1
______________________________________________________________________________________ 19
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Table 18. Port I/O Registers (I/O Port 5 and 9 Configured as CLA Outputs, Registers
0x05 and 0x09)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
D7
Don’t care
x
0
1
0
1
Don’t care.
Refers inputs to the VL supply voltage; sets outputs to open drain.
Refers inputs to the V supply voltage; sets outputs to push-pull.
Port supply
reference
D6
D5
D4
D3
D2
D1
D0
DD
Disables the transition interrupt.
Enables the transition interrupt.
Transition interrupt
enable
Transition detection
bit 1
0
0
Detects the next transition on the port input.
Detects the next transition on the port input.
Transition detection
bit 0
0
1
0
1
0
1
Disables debouncing of the input port.
Enables debouncing of the input port.
No transition has occurred since the last port read.
A transition has occurred since the last port read.
Port input is logic-low.
Debounce
Port transition state
Port status
Port input is logic-high.
RSTPOR bit in the configure register. Each lock bit can
only be written to once per power cycle.
Configurable Logic Array (CLA)
The CLA configures groups of four ports as either a
combinational logic gate up to three inputs, or a two
input exclusive OR/NOR gate (see Tables 12-15).
Eight-port dual groups can be cascaded to form a
two-level gate with the intermediate term brought out
as an output or not, as desired. If fewer than three
gate inputs are needed, the unused CLA input(s)
(which can be any combination of the three CLA
inputs) remain available as independent GPIO ports
(see Figure 8). Use the configurable logic-array enable
register (see Table 16) to enable ports as CLAs. Use the
configurable logic-array lock register (see Table 17) to
permanently lock in any logic-array combination of CLAs
until the next power cycle. Setting D0 and D1 to logic-
high in the configurable logic-array lock register locks the
corresponding bit position in the configurable logic-array
enable register. Additionally, the appropriate CLA_ regis-
ter (addresses 0x28 and 0x29) cannot be changed.
A CLA’s input(s) and output can be read through the
serial interface like a normal input port. The MAX7302
creates a gate that provides an independent real-time
logic function, and every node of it can be examined
through the I2C interface with optional debounce and
transition detection.
Setting bits D0 and D1 to logic-high enables the CLA
functionality and sets ports P5 and P9 as CLA outputs
(see Table 16). When in CLA mode, the port I/O regis-
ter data is interpreted differently for CLA output ports
(see Table 18). Bit D7 that normally selects the port
direction is ignored because either port P5 or P9 is
always an output. Bit D6 sets both the CLA output type
(push-pull or open drain) and the logic threshold for
reading the CLA output status back through the I2C
interface. The other bits set the readback options, such
as debounce and transition detection interrupt.
The configurable logic-array lock register is unlocked
on power-up, or by RST when configured by the
20 ______________________________________________________________________________________
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
ENABLE P2
DEBOUNCE
DEBOUNCE
TRANSITION DETECTION
TRANSITION DETECTION
PIN P2
INVERT P2
PIN P3
INVERT P3
P2–P5
[CLA0]
ENABLE P3
ENABLE P4
DEBOUNCE
TRANSITION DETECTION
PIN P4
INVERT P4
INVERT P5
P5 OUTPUT REGISTER
PIN P5
P5 IS CLA/GPIO
ENABLE EXOR23
ENABLE EXOR23 = /D5 * D4 IN CLA REGISTER 0x28
INVERT P5 CASCADE
ENABLE P5 CASCADE
ENABLE P6
DEBOUNCE
DEBOUNCE
TRANSITION DETECTION
TRANSITION DETECTION
PIN P6
INVERT P6
P6–P9
[CLA1]
PIN P7
INVERT P7
ENABLE P7
ENABLE P8
PIN P8
DEBOUNCE
TRANSITION DETECTION
INVERT P8
INVERT P9
P9 OUTPUT REGISTER
PIN P9
P9 IS CLA/GPIO
ENABLE EXOR67
ENABLE EXOR67 = /D5 * D4 IN CLA REGISTER 0x29
Figure 8. Configurable Logic-Array Structure
P2
P3
P4
P2
P3
P2
P3
P4
P2
P2
P3
P5
P6
P5
P6
P7
P4
P5
P6
P7
P7
P8
P9
P7
P9
P7
P9
P9
P9
EXAMPLE 1:
EXAMPLE 2:
EXAMPLE 3:
EXAMPLE 4:
EXAMPLE 5:
REGISTER 0x28: DATA VALUE 8’b1011_1110 REGISTER 0x28: DATA VALUE 8’b0010_0011 REGISTER 0x28: DATA VALUE 8’b1001_1011 REGISTER 0x28: DATA VALUE 8’b0101_1010 REGISTER 0x28: DATA VALUE 8’b1110_1111
REGISTER 0x29: DATA VALUE 8’b0000_1100 REGISTER 0x29: DATA VALUE 8’b0011_1101 REGISTER 0x29: DATA VALUE 8’b1101_1010 REGISTER 0x29: DATA VALUE 8’b0001_1010 REGISTER 0x29: DATA VALUE 8’b0101_1010
Figure 9. Configurable Logic Examples
______________________________________________________________________________________ 21
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Each transmission consists of a START condition (see
Figure 11) sent by a master, followed by the MAX7302
Serial Interface
Serial Addressing
The MAX7302 operates as a slave that sends and
receives data through an I2C-compatible, 2-wire inter-
face. The interface uses a serial-data line (SDA) and a
serial-clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX7302 and generates the SCL clock that
synchronizes the data transfer (see Figure 10).
7-bit slave address plus R/W bit, a register address byte,
one or more data bytes, and finally a STOP condition
(see Figure 11).
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (see Figure 11).
The MAX7302 SDA line operates as both an input and
an open-drain output. A 4.7kΩ (typ) pullup resistor is
required on SDA. The MAX7302 SCL line operates only
as an input. A 4.7kΩ (typ) pullup resistor is required on
SCL if there are multiple masters on the 2-wire inter-
face, or if the master in a single-master system has an
open-drain SCL output.
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(see Figure 12).
SDA
t
BUF
t
SU,STA
t
SU,DAT
t
HD,STA
t
LOW
t
SU,STO
t
HD,DAT
t
SCL
t
HIGH
HD,STA
t
t
F
R
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
RESET
t
WL(RST)
Figure 10. 2-Wire Serial Interface Timing Details
SDA
SCL
SDA
SCL
S
P
START
CONDITION
STOP
CONDITION
DATA LINE STABLE; CHANGE OF DATA
DATA VALID ALLOWED
Figure 11. START and STOP Conditions
Figure 12. Bit Transfer
22 ______________________________________________________________________________________
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data (see
Figure 13). Thus, each effectively transferred byte
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
the master is transmitting to the MAX7302, the MAX7302
generates the acknowledge bit because the MAX7302
is the recipient. When the MAX7302 is transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
Message Format for Writing to the MAX7302
A write to the MAX7302 comprises the transmission of the
MAX7302’s slave address with the R/W bit set to zero, fol-
lowed by at least 1 byte of information (see Figure 16).
The first byte of information is the command byte. The
command byte determines which register of the
MAX7302 is to be written to by the next byte, if received.
If a STOP condition is detected after the command byte is
received, the MAX7302 takes no further action beyond
storing the command byte (see Figure 15).
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register of
the MAX7302 selected by the command byte (see Figure
16). If multiple data bytes are transmitted before a STOP
condition is detected, these bytes are generally stored in
subsequent MAX7302 internal registers because the
command byte address autoincrements (see Table 3).
The Slave Address
The MAX7302 has a 7-bit long slave address (Figure
14). The 8th bit following the 7-bit slave address is the
R/W bit. Set R/W bit low for a write command and high
for a read command.
Message Format for Reading
The MAX7302 is read using the MAX7302’s internally
stored command byte as an address pointer the same
way the stored command byte is used as an address
pointer for a write. The pointer autoincrements after
each data byte is read using the same rules as for a
write. Thus, a read is initiated by first configuring the
MAX7302’s command byte by performing a write
(Figure 15). The master can now read n consecutive
bytes from the MAX7302 with the first data byte being
read from the register addressed by the initialized com-
mand byte (see Figure 17). When performing read-
after-write verification, remember to reset the command
byte’s address because the stored command byte
address has been autoincremented after the write.
The first 5 bits of the MAX7302 slave address (A6–A2)
are always 1, 0, 0, 1, and 1. Slave address bit A1, A0 is
selected by the address input AD0. AD0 can be con-
nected to GND, V , SDA, or SCL. The MAX7302 has
DD
four possible slave addresses (see Table 5), and there-
fore, a maximum of four MAX7302 devices can be con-
trolled independently from the same interface.
CLOCK PULSE
START
FOR ACKNOWLEDGE
CONDITION
SCL
1
2
8
9
SDA BY
TRANSMITTER
SDA BY
RECEIVER
S
Figure 13. Acknowledge
1
0
0
1
1
A1
A0
R/W
ACK
SDA
MSB
SCL
LSB
Figure 14. Slave Address
D15 D14 D13 D12 D11 D10
D9
D8
ACKNOWLEDGE FROM MAX7302
SLAVE ADDRESS
S
0
A
REGISTER ADDRESS
A
P
R/W
ACKNOWLEDGE FROM MAX7302
Figure 15. Register Address Received
______________________________________________________________________________________ 23
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
WRITE TO OUTPUT PORTS REGISTERS
(P4)
1
2
3
4
5
6
7
8
9
SCL
SDA
SLAVE ADDRESS
COMMAND BYTE
S
1
0
0
1
1
A1
A0
0
A
0
0
0
0
0
1
0
0
A
MSB
DATA
LSB
A
P
STOP
START CONDITION
R/W
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE
DATA VALID
P9 TO P1
t
PPV
Figure 16. Write to Output Port Registers
READ FROM INPUT PORTS REGISTERS
1
2
3
4
5
6
7
8
9
SCL
SDA
S
1
0
0
1
1
A1
A0
1
A
MSB
DATA1
LSB
A
MSB
DATA4
DATA4
LSB NA
P
STOP
START CONDITION
R/W
ACKNOWLEDGE FROM SLAVE
DATA2
ACKNOWLEDGE FROM MASTER
NO ACKNOWLEDGE
DATA1
DATA3
P9 TO P1
t
PH
t
PSU
Figure 17. Read from Input Port Registers
INTERRUPT VALID/RESET
1
2
3
4
5
6
7
8
9
SCL
SDA
S
1
0
0
1
1
A1
A0
1
A
MSB
DATA2
LSB
A
MSB
DATA3
LSB
NA
P
START CONDITION
R/W
STOP
NO ACKNOWLEDGE
ACKNOWLEDGE FROM SLAVE
DATA2
ACKNOWLEDGE FROM MASTER
DATA3
DATA1
P9 TO P1
INT
t
IR
t
IR
t
t
IV
IV
Figure 18. Interrupt and Reset Timing
Operation with Multiple Masters
If the MAX7302 is operated on a 2-wire interface with
multiple masters, a master reading the MAX7302
should use a repeated start between the write that sets
the MAX7302’s address pointer, and the read(s) that
takes the data from the location(s). This is because it is
possible for master 2 to take over the bus after master
1 has set up the MAX7302’s address pointer, but
before master 1 has read the data. If master 2 subse-
quently changes the MAX7302’s address pointer, then
master 1’s delayed read can be from an unexpected
location.
Bus Timeout
Clear device configuration register 0x27 bit D7 to
enable the bus timeout function (see Table 4), or set it
to disable the bus timeout function. Enabling the time-
out feature resets the MAX7302 serial-bus interface
when SCL stops either high or low during a read or
write. If either SCL or SDA is low for more than nominal-
ly 31ms after the start of a valid serial transfer, the inter-
face resets itself and sets up SDA as an input. The
MAX7302 then waits for another START condition.
24 ______________________________________________________________________________________
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
V
is the supply voltage used to drive the
SUPPLY
LED (V)
Applications Information
Hot Insertion
Serial interfaces SDA, SCL, and AD0 remain high
impedance with up to 6V asserted on them when the
V
is the forward voltage of the LED (V)
LED
V
is the output low voltage of the MAX7302
OL
when sinking I
(V)
LED
MAX7302 is powered down (V
= 0V) independent of
DD
the voltages on the port supply V . When V
= 0V, or
DD
I
is the desired operating current of the LED (A).
LA
LED
if V
falls below the MAX7302’s reset threshold, all I/O
DD
For example, to operate a 2.2V red LED at 20mA from a
5V supply, R = (5 - 2.2 - 0.8) / 0.020 = 100Ω.
ports become high impedance. The ports remain high
LED
impedance to signals between 0V and the port supply
Driving Load Currents Higher than 25mA
The MAX7302 can sink current from loads drawing
more than 25mA by sharing the load across multiple
ports configured as open-drain outputs. Use at least
one output per 25mA of load current; for example, drive
a 90mA white LED with four ports.
V
. If a signal outside this range is applied to a port,
LA
the port’s protection diodes clamp the input signal to
or 0V, as appropriate. If supply V is lower than
V
LA
LA
the input signal, the port pulls up V and the protec-
LA
tion diode effectively powers any load on V from the
LA
input signal. This behavior is safe if the current through
each protection diode is limited to 10mA.
The register structure of the MAX7302 allows only one
port to be manipulated at a time. Do not connect ports
directly in parallel because multiple ports cannot be
switched high or low at the same time, which is neces-
sary to share a load safely. Multiple ports can drive
high-current LEDs because each port can use its own
external current-limiting resistor to set that port’s cur-
rent through the LED.
If it is important that I/O ports remain high impedance
when all the supplies are powered down, including the
port supply V , then ensure that there is no direct or
LA
parasitic path for MAX7302 input signals to drive current
into either the regulator providing V or other circuits
LA
powered from V . One simple way to achieve this is
LA
with a series small-signal Schottky diode, such as the
BAT54, between the port supply and the V input.
LA
The exceptions to this paralleling rule are the four ports,
P2–P5, and the four ports, P6–P9. These groups of four
ports can be programmed simultaneously through the
pseudoregisters 0x3C and 0x3D, respectively. A write
access to 0x3C writes the same data to registers 0x02
through 0x05. A write access to 0x3D writes the same
data to registers 0x06 through 0x09. Either of these
groups of four ports can be paralleled to drive a load
up to 100mA.
Output Level Translation
The open-drain output configuration of the ports allows
them to level translate the outputs to lower (but not
higher) voltages than the V
supply. An external
LA
pullup resistor converts the high-impedance, logic-high
condition to a positive voltage level. Connect the resis-
tor to any voltage up to V . For interfacing CMOS
LA
inputs, a pullup resistor value of 220kΩ is a good start-
ing point. Use a lower resistance to improve noise
immunity, in applications where power consumption is
less critical, or where a faster rise time is needed for a
given capacitive load.
Power-Supply Considerations
The MAX7302 operates with a V
of 1.62V to 3.6V. Bypass V
power-supply voltage
DD
to GND with a 0.047µF
DD
capacitor as close as possible to the device. The port
supply V is connected to a supply voltage between
LA
Driving LED Loads
When driving LEDs, use a resistor in series with the
LED to limit the LED current to no more than 25mA.
Choose the resistor value according to the following
formula:
1.62V to 5.5V and bypassed with a 0.1µF capacitor as
close as possible to the device. The V
supply and port
DD
supply are independent and can be connected to differ-
ent voltages or the same supply as required.
Power supplies V
either order or together.
and V
can be sequenced in
LA
DD
R
LED
= (V
- V
- VOL) / I
LED LED
SUPPLY
where:
R
is the resistance of the resistor in series with
LED
the LED (Ω)
______________________________________________________________________________________ 25
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Pin Configurations
TOP VIEW
+
V
12
11
10
9
LA
1
2
3
4
5
6
7
8
16 V
DD
ADO
RST
15 SDA
14 SCL
13 P9
GND
P6
13
14
15
16
SDA
8
7
6
5
V
DD
P1/INT
P2/OSCIN
P3/OSCOUT
P4
MAX7302
MAX7302
12 P8
P5
V
LA
11 P7
*EP
P4
AD0
+
10 GND
1
2
3
4
P5
9
P6
QSOP
TQFN
*EP = Exposed pad.
Chip Information
PROCESS: BiCMOS
26 ______________________________________________________________________________________
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
______________________________________________________________________________________ 27
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
(NE - 1)
X e
MARKING
E
E/2
D2/2
(ND - 1)
e
X e
D/2
AAAA
C
D2
D
L
k
b
0.10 M
C A B
C
L
E2/2
L
E2
C
L
C
L
0.10
C
0.08
A
C
A2
A1
L
L
e
e
PACKAGE OUTLINE
8, 12, 16L THIN QFN, 3x3x0.8mm
1
21-0136
I
2
28 ______________________________________________________________________________________
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PKG
8L 3x3
12L 3x3
16L 3x3
EXPOSED PAD VARIATIONS
REF. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
D2
E2
PKG.
PIN ID
JEDEC
CODES
A
b
0.70 0.75 0.80 0.70 0.75 0.80
0.25 0.30 0.35 0.20 0.25 0.30
0.70 0.75 0.80
0.20 0.25 0.30
MIN.
0.25
0.95
0.95
0.95
0.95
0.65
0.65
0.95
0.95
NOM. MAX.
MIN.
0.25
0.95
0.95
0.95
NOM. MAX.
TQ833-1
T1233-1
T1233-3
0.70
1.10
1.10
1.10
1.25
1.25
1.25
0.70
1.10
1.10
1.10
1.10
0.80
0.80
1.10
1.10
1.25
1.25
1.25
1.25
1.25
0.95
0.95
0.35 x 45°
0.35 x 45°
0.35 x 45°
0.35 x 45°
0.35 x 45°
0.225 x 45°
0.225 x 45°
0.35 x 45°
0.35 x 45°
WEEC
D
2.90 3.00 3.10 2.90 3.00 3.10 2.90 3.00 3.10
2.90 3.00 3.10 2.90 3.00 3.10 2.90 3.00 3.10
WEED-1
WEED-1
WEED-1
WEED-2
WEED-2
WEED-2
WEED-2
WEED-2
E
e
0.65 BSC.
0.50 BSC.
0.50 BSC.
T1233-4
T1633-2
1.25
1.25
0.95
0.95
1.25
1.25
L
0.35 0.55 0.75 0.45 0.55 0.65 0.30 0.40 0.50
1.10
0.80
0.80
1.10
0.95
0.65
0.65
0.95
N
ND
NE
A1
A2
k
8
12
16
T1633F-3
T1633FH-3
T1633-4
2
3
4
2
3
4
1.25
1.25
0
0.02 0.05
0
0.02 0.05
0
0.02 0.05
T1633-5
1.10
0.95
0.20 REF
0.20 REF
0.20 REF
-
-
-
-
-
-
0.25
0.25
0.25
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
.
10. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
11. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
12. WARPAGE NOT TO EXCEED 0.10mm.
PACKAGE OUTLINE
8, 12, 16L THIN QFN, 3x3x0.8mm
2
21-0136
I
2
______________________________________________________________________________________ 29
2
SMBus/I C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
7/07
Initial release
—
Corrected configuration 26 errors in Tables 1 and 2 and updated package outline
for 16-pin QSOP.
1
12/07
8, 27
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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