MAX7310AUE [MAXIM]
2-Wire-Interfaced 8-Bit I/O Port Expander with Reset; 2线接口， 8位I / O端口扩展器，带有复位
| 型号： | MAX7310AUE |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 2-Wire-Interfaced 8-Bit I/O Port Expander with Reset |
| 文件： | 总15页 (文件大小：313K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2698; Rev 3; 2/05
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
General Description
Features
The MAX7310 provides 8-bit parallel input/output port
expansion for SMBus™-compatible and I2C™-compati-
ble applications. The MAX7310 consists of an input port
register, an output port register, a polarity inversion reg-
ister, a configuration register, a bus timeout register,
and an SMBus/I2C-compatible serial interface. The sys-
tem master can invert the MAX7310 input data by writ-
ing to the active-high polarity inversion register. The
system master can enable or disable bus timeout by
writing to the bus timeout register.
♦ 400kHz 2-Wire Interface
♦ 2.3V to 5.5V Operation
♦ Low Standby Current (1.7µA typ)
♦ Bus Timeout for Lock-Up-Free Operation
♦ 56 Slave ID Addresses
♦ Polarity Inversion
♦ Eight I/O Pins that Default to Inputs on Power-Up
♦ 5V Tolerant Open-Drain Output on I/O0
♦ 4mm x 4mm, 0.8mm Thin QFN Package
♦ -40°C to +125°C Operation
Any of the eight I/O ports may be configured as input or
output. An active-low reset input sets the eight I/Os as
inputs. Three address select pins configure one of 56
slave ID addresses.
The MAX7310 is available in 16-pin thin QFN, TSSOP,
and QSOP packages and is specified over the -40°C to
+125°C automotive temperature range.
Applications
Ordering Information
Servers
RAID Systems
PIN-
PACKAGE
PKG
CODE
PART
TEMP RANGE
Industrial Control
Medical Equipment
Instrumentation, Test Measurement
MAX7310AUE -40°C to +125°C 16 TSSOP
MAX7310AEE -40°C to +125°C 16 QSOP
—
—
MAX7310ATE -40°C to +125°C 16 Thin QFN T1644-4
SMBus is a trademark of Intel Corp.
2
Purchase of I C components of Maxim Integrated Products, Inc.,
or one of its sublicensed Associated Companies, conveys a
2
license under the Philips I C Patent Rights to use these compo-
2
nents in an I C system, provided that the system conforms to the
2
I C Standard Specification as defined by Philips.
Pin Configurations
TOP VIEW
12
11
10
9
SCL
1
2
3
4
5
6
7
8
16 V+
RESET
15
SDA
AD0
AD1
AD2
RESET
V+
I/O3
I/O2
GND
I/O1
13
14
15
16
8
7
6
5
14 I/O7
13 I/O6
12 I/O5
MAX7310
MAX7310ATE
SCL
SDA
11
10
9
I/O0
I/O1
GND
I/O4
I/O3
I/O2
1
2
3
4
TSSOP/QSOP
THIN QFN
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
ABSOLUTE MAXIMUM RATINGS
V+ to GND................................................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
I/O1–I/O7 as an Input.......................(V - 0.3V) to (V
+ 0.3V)
16-Pin TSSOP (derate 5.7mW/°C above +70°C) .........457mW
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
16-Pin Thin QFN (derate 16.9mW/°C above +70°C) ...1349mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
SS
DD
I/O0 as an Input..............................................(V - 0.3V) to +6V
SS
SCL, SDA, AD0, AD1, AD2, RESET ...............(V - 0.3V) to +6V
SS
DC Current on I/O0 ........................................................ +400µA
DC Current on I/O1 to I/O7 ............................................. 50mA
Maximum GND and V+ Current........................................180mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V+ = 2.3V to 5.5V, GND = 0, RESET = V+, T = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = 3.3V, T = +25°C.)
A
A
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
5.5
30
UNITS
Supply Voltage
V+
2.3
V
V+ = 2.3V
19
29
All outputs floating,
Supply Current
I+
all inputs at V+ or GND,
V+ = 3.3V
V+ = 5.5V
V+ = 2.3V
V+ = 3.3V
V+ = 5.5V
40
µA
f
= 400kHz
SCL
65
80
1.5
1.7
2.1
1.6
3.4
3.9
5
All outputs floating,
all inputs at V+ or GND,
Standby Current
µA
V
f
= 0
SCL
Power-On Reset Voltage
SCL, SDA
2.1
Input Voltage Low
Input Voltage High
V
0.8
V
V
IL
V
2
IH
Low-Level Output Voltage
Leakage Current
Input Capacitance
I/Os
V
I
= 6mA
0.4
+1
V
OIL
SINK
I
-1
µA
pF
L
C
10
I
Input Voltage Low
Input Voltage High
Input Leakage Current
V
0.8
+1
V
V
IL
V
2
-1
IH
I
All inputs at V+ or GND
µA
L
V+ = 2.3V, V = 0.5V
OL
8
14
22
30
11
18
Low-Level Output Current
I
mA
mA
V+ = 3.3V, V = 0.5V
OL
12.5
19
OL
V+ = 5.5V, V = 0.5V
OL
V+ = 3.3V, V
V+ = 5.5V, V
= 2.4V
= 4.5V
6.5
12.5
OH
OH
High Output Current for I/O1–I/O7
I
OH
AD0, AD1, AD2, AND RESET
Input Voltage Low
0.8
V
V
Input Voltage High
2
2
_______________________________________________________________________________________
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
DC ELECTRICAL CHARACTERISTICS (continued)
(V+ = 2.3V to 5.5V, GND = 0, RESET = V+, T = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = 3.3V, T = +25°C.)
A
A
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
µA
Leakage Current
-1
+1
Input Capacitance
10
pF
AC ELECTRICAL CHARACTERISTICS
(V+ = 2.3V to 5.5V, GND = 0, RESET = V+, T = -40°C to +125°C, unless otherwise noted.) (Note 1)
A
PARAMETER
SCL Clock Frequency
BUS Timeout
SYMBOL
CONDITIONS
MIN
TYP
MAX
400
60
UNITS
kHz
f
(Note 2)
SCL
TIMEOUT
t
30
ms
Bus Free Time Between STOP
and START Condition
t
Figure 2
Figure 2
1.3
µs
µs
µs
BUF
Hold Time (Repeated) START
Condition
t
0.6
HD, STA
Repeated START Condition Setup
Time
t
Figure 2
Figure 2
0.6
0.6
SU, STA
STOP Condition Setup Time
Data Hold Time
t
µs
µs
µs
µs
µs
ns
ns
SU, STO
t
Figure 2 (Note 3)
Figure 2
0.9
HD, DAT
Data Setup Time
t
0.1
1.3
0.7
SU, DAT
SCL Low Period
t
Figure 2
LOW
SCL High Period
t
Figure 2
HIGH
SCL/SDA Fall Time (Transmitting)
Pulse Width of Spike Supressed
PORT TIMING
t
F
Figure 2 (Note 4)
(Note 5)
250
1
t
50
SP
Output Data Valid
t
t
Figure 9
µs
µs
µs
PV
PS
PH
Input Data Setup Time
Input Data Hold Time
RESET
Figure 10
Figure 10
29
0
t
Reset Pulse Width
100
ns
Note 1: All parameters are 100% production tested at T = +25°C. Specifications over temperature are guaranteed by design.
A
Note 2: Minimum SCL clock frequency is limited by the MAX7310 bus timeout feature, which resets the serial bus interface if either
SDA or SCL is held low for a 30ms minimum.
Note 3: A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V of the SCL signal) in
IL
order to bridge the undefined region of SCL’s falling edge.
Note 4: t measured between 90% to 10% of V+.
F
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
_______________________________________________________________________________________
3
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT
vs. TEMPERATURE
STANDBY SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
32
2.50
2.25
2.00
1.75
1.50
1.25
1.00
70
60
50
40
30
20
V+ = 3.3V, f = 440kHz,
SCL
NO LOAD ON I/O0–I/O7
V+ = 3.3V, f = 0,
SCL
NO LOAD ON I/O0–I/O7
f
= 440kHz,
SCL
NO LOAD ON I/O0–I/O7
31
30
29
28
27
26
10
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
2.0
2.5 3.0
3.5 4.0
4.5 5.0 5.5
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
I/O0–I/O7 OUTPUT SINK CURRENT
vs. TEMPERATURE
I/O0–I/O7 OUTPUT SINK CURRENT
vs. SUPPLY VOLTAGE
I/O1–I/O7 OUTPUT SOURCE CURRENT
vs. TEMPERATURE
30
25
20
15
10
5
35
30
25
20
15
10
5
9
V+ = 2.3V,
V
OH
= 1.4V
8
7
V
V
= 3.3V
= 2.3V
CC
CC
6
5
V
OL
= 0.5V
V
OL
= 0.5V
0
0
4
-40 -25 -10
5
20 35 50 65 80 95 110 125
2.0
2.5 3.0
3.5 4.0
4.5 5.0 5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
Pin Description
PIN
TSSOP/
QSOP
THIN
NAME
FUNCTION
QFN
15
16
1
1
SCL
SDA
Serial Clock Line
Serial Data Line
2
3
AD0
Address Input 0
4
5
2
AD1
Address Input 1
3
AD2
Address Input 2
6
4
I/O0
Input/Output Port 0 (Open Drain)
Input/Output Port 1
Supply Ground
7
5
I/O1
8
6
GND
I/O2–I/O7
9–14
7–12
Input/Output Port 2—Input/Output Port 7
External Reset (Active Low). Pull RESET low to configure I/O pins as inputs. Set RESET
high for normal operation.
15
16
—
13
14
RESET
V+
Supply Voltage. Bypass with a 0.047µF capacitor to GND.
Exposed Pad on Package Underside. Connect to GND.
Exposed
pad
PAD
AD0
AD1
AD2
MAX7310
I/O0
I/O1
SCL
SDA
INPUT/
OUTPUT
PORTS
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
SMBus
CONTROL
8 BIT
INPUT
FILTER
WRITE PULSE
READ PULSE
N
V+
POWER-ON
RESET
RESET
GND
Figure 1. MAX7310 Block Diagram
port register, a polarity inversion register, a configura-
tion register, and a bus timeout register. An active-low
reset input sets the eight I/O lines as inputs. Three
slave ID address select pins (AD0, AD1, and AD2)
choose one of 56 slave ID addresses (Figure 1).
Detailed Description
The MAX7310 general-purpose input/output (GPIO)
peripheral provides up to eight I/O ports, controlled
through an I2C-compatible serial interface. The
MAX7310 consists of an input port register, an output
________________________________________________________________________________________
5
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
Table 1 is the register address table. Tables 2–6 list
register 0 through register 4 information.
SCL is high. The bus is then free for another transmis-
sion (Figure 3).
Bit Transfer
Serial Interface
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
Serial Addressing
The MAX7310 operates as a slave that sends and
receives data through a 2-wire interface. The interface
uses a serial data line (SDA) and a serial clock line
(SCL) to achieve bidirectional communication between
master(s) and slave(s). A master, typically a microcon-
troller, initiates all data transfers to and from the
MAX7310, and generates the SCL clock that synchro-
nizes the data transfer (Figure 2).
Acknowledge
The acknowledge bit is a clocked 9th bit, which the
recipient uses as a handshake receipt of each byte of
data (Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
the master is transmitting to the MAX7310, the
MAX7310 generates the acknowledge bit since the
MAX7310 is the recipient. When the MAX7310 is trans-
mitting to the master, the master generates the
acknowledge bit.
Each transmission consists of a start condition sent by
a master, followed by the MAX7310 7-bit slave address
plus an R/W bit, a register address byte, one or more
data bytes, and finally a stop condition (Figure 3).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a start (S) condition by transitioning SDA from
high to low while SCL is high. When the master has fin-
ished communicating with the slave, it issues a stop (P)
condition by transitioning SDA from low to high while
Slave Address
The MAX7310 has a 7-bit-long slave address (Figure
6). The 8th bit following the 7-bit slave address is the
R/W bit. Set this bit low for a write command and high
for a read command.
SDA
t
BUF
t
t
SU, STA
SU, DAT
t
HD, STA
t
LOW
t
t
SU, STO
HD, DAT
SCL
t
HIGH
t
HD, STA
t
t
F
R
REPEATED START CONDITION
START CONDITION
STOP CONDITION START CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagrams
SDA
S
P
SCL
START
CONDITION
STOP
CONDITION
Figure 3. Start and Stop Conditions
_______________________________________________________________________________________
6
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
SDA
SCL
DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED
Figure 4. Bit Transfer
START CONDITION
CLOCK PULSE FOR ACKNOWLEDGMENT
SCL
1
2
8
9
SDA
BY TRANSMITTER
S
SDA
BY RECEIVER
Figure 5. Acknowledge
FIXED
PROGRAMMABLE
R/W
0
A5
A4
A3
A2
A1
A0
ACK
SDA
MSB
LSB
SCL
Figure 6. Slave Address
The first bits (MSBs) of the MAX7310 slave address are
always zero. Slave address bits AD2, AD1, and AD0
choose 1 of 56 slave ID addresses (Table 7).
ister address byte acts as a pointer to determine which
register is written or read.
The input port register is a read-only port. It reflects the
incoming logic levels of the I/O ports, regardless of
whether the pin is defined as an input or an output by
the configuration register. Writes to the input port regis-
ter are ignored.
Registers
The register address byte is the first byte to follow the
address byte during a read/write transmission. The reg-
_______________________________________________________________________________________
7
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
The polarity inversion register enables polarity inversion
Table 1. Register Address
of ports defined as inputs by the configuration register.
Set the bit in the polarity inversion register (write with a
1) to invert the corresponding port pin’s polarity. Clear
the bit in the polarity inversion register (write with a
zero) to retain the corresponding port pin’s original
polarity.
REGISTER
ADDRESS
(hex)
FUNCTION
PROTOCOL
Read byte.
0x00
0x01
Input port register
Output port register Read/write byte.
The configuration register configures the directions of
the ports. Set the bit in the configuration register to
enable the corresponding port pin as an input with a
high-impedance output driver. Clear the bit in the con-
figuration register to enable the corresponding port pin
as an output.
Polarity inversion
Read/write byte.
register
0x02
Configuration
Read/write byte.
register
0x03
0x04
Timeout register
Read/write byte.
Set bit T0 to enable the bus timeout function and low to
disable the bus timeout function. Enabling the timeout
feature resets the serial bus interface when SCL stops
either high or low during a read or write access to the
MAX7310. If either SCL or SDA is low for more than
30ms min and 60ms max after the start of a valid serial
transfer, the interface resets itself. Resetting the serial
bus interface sets up SDA as an input. The MAX7310
then waits for another start condition.
Factory reserved.
Do not write to this
register.
0xFF
Reserved register
Table 2. Register 0—Input Port Register
BIT
I7
I6
I5
I4
I3
I2
I1
I0
Standby
The MAX7310 goes into standby when all pins are set
to V+ or GND. Standby supply current is typically
1.7µA.
The output port register sets the outgoing logic levels of
the I/O ports, defined as outputs by the configuration
register. Reads from the output port register reflect the
value that is in the flip-flop controlling the output selec-
tion, not the actual I/O value, which may differ if the out-
put is overloaded.
Table 3. Register 1—Output Port Register
BIT
O7
O6
O5
O4
O3
O2
O1
O0
Default
0
0
0
0
0
0
0
0
Table 4. Register 2—Polarity Inversion Register
BIT
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Default
1
1
1
1
0
0
0
0
Table 5. Register 3—Configuration Register
BIT
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Default
1
1
1
1
1
1
1
1
Table 6. Register 4—Timeout Register
BIT
T7
T6
T5
T4
T3
T2
T1
T0
Default
x
x
x
x
x
x
x
1
8
_______________________________________________________________________________________
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
Table 7. MAX7310 Address Map
AD2
GND
GND
GND
GND
V+
AD1
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
GND
GND
V+
AD0
GND
V+
A6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
GND
V+
GND
V+
V+
V+
GND
V+
V+
GND
GND
GND
GND
V+
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
GND
V+
V+
GND
GND
V+
V+
V+
V+
V+
GND
GND
GND
GND
V+
GND
GND
V+
GND
V+
V+
GND
GND
V+
GND
V+
V+
V+
GND
V+
V+
V+
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
GND
V+
GND
V+
GND
V+
GND
V+
_______________________________________________________________________________________
9
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
Table 7. MAX7310 Address Map (continued)
AD2
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
AD1
GND
GND
V+
AD0
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
GND
V+
A6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V+
GND
GND
V+
V+
GND
GND
V+
GND
V+
V+
GND
GND
V+
GND
V+
GND
V+
V+
Applications Information
Chip Information
TRANSISTOR COUNT: 10,256
Power-Supply Consideration
PROCESS: BiCMOS
The MAX7310 operates from a supply voltage of 2.3V to
5.5V. Bypass the power supply to GND with a 0.047µF
capacitor as close to the device as possible. For the
QFN version, connect the underside exposed pad to
GND.
10 ______________________________________________________________________________________
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
DATA FROM
SHIFT REGISTER
CONFIGURATION
REGISTER
DATA FROM
SHIFT REGISTER
D
Q
OUTPUT PORT
REGISTER DATA
FF
D
C
Q
Q
C
Q
WRITE
CONFIGURATION
PULSE
K
I/O0
FF
WRITE PULSE
K
ESD-PROTECTION DIODE
OUTPUT
PORT
GND
REGISTER
INPUT
PORT
REGISTER
D
Q
INPUT PORT
REGISTER DATA
FF
C
D
Q
Q
K
READ PULSE
POLARITY
REGISTER DATA
DATA FROM
SHIFT REGISTER
FF
WRITE POLARITY
PULSE
C
Q
K
POLARITY
INVERSION
REGISTER
Figure 7. Simplified Schematic of I/O0
______________________________________________________________________________________ 11
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
DATA FROM
SHIFT REGISTER
OUTPUT PORT
REGISTER DATA
CONFIGURATION
REGISTER
V+
DATA FROM
SHIFT REGISTER
D
Q
FF
ESD-PROTECTION DIODE
ESD-PROTECTION DIODE
D
C
Q
Q
C
K
Q
WRITE
CONFIGURATION
PULSE
I/O1 TO I/O7
FF
WRITE PULSE
K
OUTPUT
PORT
REGISTER
INPUT
PORT
GND
REGISTER
D
Q
INPUT PORT
REGISTER DATA
FF
C
D
Q
Q
K
READ PULSE
POLARITY
REGISTER DATA
DATA FROM
SHIFT REGISTER
FF
WRITE POLARITY
PULSE
C
Q
K
POLARITY
INVERSION
REGISTER
Figure 8. Simplified Schematic of I/O1–I/O7
12 ______________________________________________________________________________________
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
SCL
SDA
1
2
3
4
5
6
7
8
9
SLAVE ADDRESS
COMMAND BYTE
DATA TO PORT
DATA 1
0
0
0
A
P
S
0
A5 A4 A3 A2 A1 A0
0
A
0
0
0
0
1
A
START CONDITION
R/W ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
WRITE TO
PORT
DATA OUT
FROM PORT
DATA 1 VALID
t
PV
Figure 9. Write to Output Port Register Through Write-Byte Protocol
SLAVE ADDRESS
DATA FROM PORT
DATA 1
DATA FROM PORT
SDA
NA
P
S1
0
A5 A4 A3 A2 A1 A0
A
A
DATA 4
1
START CONDITION
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM MASTER
NO ACKNOWLEDGE STOP
FROM MASTER CONDITION
R/W
WRITE FROM
PORT
DATA INTO
PORT
DATA 2
DATA 3
DATA 4
t
PH
t
PS
NOTE 1: THIS FIGURE ASSUMES THE COMMAND HAS PREVIOUSLY BEEN PROGRAMMED WITH 0x00.
NOTE 2: TRANSFER OF DATA CAN BE STOPPED AT ANY MOMENT BY A STOP CONDITION. WHEN THIS OCCURS,
DATA PRESENT AT THE LAST ACKNOWLEDGED PHASE IS VALID (OUTPUT MODE). INPUT DATA IS LOST.
Figure 10. Read Input Port Register Through Receive-Byte Protocol
______________________________________________________________________________________ 13
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
12, 16, 20, 24L THIN QFN, 4x4x0.8mm
1
C
21-0139
2
PACKAGE OUTLINE
12, 16, 20, 24L THIN QFN, 4x4x0.8mm
2
C
21-0139
2
14 ______________________________________________________________________________________
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
1
21-0055
E
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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