MAX7360_V01 [MAXIM]
I 2C-Interfaced Key-Switch Controller and LED Driver/GPIOs with Integrated ESD Protection;
| 型号： | MAX7360_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | I 2C-Interfaced Key-Switch Controller and LED Driver/GPIOs with Integrated ESD Protection |
| 文件： | 总32页 (文件大小：894K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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2
MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
General Description
Features
● Integrated ESD Protection
2
The MAX7360 I C-interfaced peripheral provides
microprocessors with management of up to 64 key
switches, with an additional eight LED drivers/GPIOs
that feature constant-current, PWM intensity control, and
rotary switch control options.
• ±8kV IEC 61000-4-2 Contact Discharge
• ±15kV IEC 61000-4-2 Air-Gap Discharge
● +14V Tolerant, Open-Drain I/O Ports Capable of
Constant-Current LED Drive
The key-switch drivers interface with metallic or resistive
switches with on-resistances up to 5kΩ. Key inputs are
monitored statically, not dynamically, to ensure low-
EMI operation. The MAX7360 features autosleep and
autowake modes to further minimize the power consumption
of the device. The autosleep feature puts the device in a
low-power state (1µA, typ) after a sleep timeout period.
The autowake feature configures the MAX7360 to return
to normal operating mode from sleep upon a keypress.
● Rotary Switch-Capable Input Pair (PORT6, PORT7)
● 256-Step PWM Individual LED Intensity Control
● Individual LED Blink Rates and Common LED
Fade In/Out Rates from 256ms to 4096ms
● FIFO Queues Up to 16 Debounced Key Events
● User-Configurable Key Debounce (9ms to 40ms)
● Keyscan Uses Static Matrix Monitoring for Low
EMI Operation
● +1.62V to +3.6V Operation
● Monitors Up to 64 Keys
The key controller debounces and maintains a FIFO of
keypress and release events (including autorepeat, if
enabled). An interrupt (INTK) output can be configured to
alert keypresses, as they occur, or at maximum rate.
● Key-Switch Interrupt (INTK) on Each Debounced
Event/FIFO Level, or End of Definable Time Period
● Port Interrupt (INTI) for Input Ports for Special-Key
There are eight open-drain I/O ports, which can be used
to drive LEDs. The maximum constant-current level for
each open-drain port is 20mA. The intensity of the LED
on each open-drain port can be individually adjusted
through a 256-step PWM control. An input port pair
(PORT6, PORT7) can be configured to accept 2-bit gray
code inputs from a rotary switch. In addition, if not used
for key-switch control, up to six column pins can be used
as general-purpose open-drain outputs (GPOs) for LED
drive or logic control.
Functions
● 400kbps, +5.5V Tolerant 2-Wire Serial Interface
with Selectable Bus Timeout
2
● Four I C Address Choices
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
40 TQFN-EP*
36 WLP
MAX7360ETL+
MAX7360EWX+
The MAX7360 is offered in a 40-pin (5mm x 5mm) thin
QFN package with an exposed pad, and a small 36-bump
wafer level package (WLP) for cell phones, pocket PCs,
and other portable consumer electronic applications. The
MAX7360 operates over the -40°C to +85°C extended
temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Simplified Block Diagram
+1.8V
+14V
ROTARY
SWITCH
TO
µC
Applications
● Cell Phones
● PDAs
● Handheld Games
● Portable Consumer Electronics
● Printers
SCL
SDA
INTI
INTK
PORT7
PORT6
MAX7360
PORT0
AD0
ROW_(8x)
COL_(8x)
● Instrumentation
8 x 8
19-4566; Rev 3; 7/19
2
MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Absolute Maximum Ratings
V
to GND ............................................................-0.3V to +4V
Storage Temperature Range............................ -65°C to +150°C
ESD Protection
CC
COL0–COL7, ROW0–ROW7 to GND.....................-0.3V to +4V
SDA, SCL, AD0, INTI, INTK to GND.......................-0.3V to +6V
PORT0–PORT7 to GND .......................................-0.3V to +16V
Human Body Model (R = 1.5kΩ, C = 100pF)
D
S
All Pins.............................................................................±2kV
All Other Pins to GND.............................. -0.3V to (V
+ 0.3V)
IEC 61000-4-2 (R = 330Ω, C = 150pF)
CC
D
S
DC Current on PORT0–PORT7, COL2–COL7 ..................25mA
GND Current ......................................................................80mA
Contact Discharge
ROW0–ROW7, COL0–COL7, PORT0–PORT7 to GND....±8kV
Air-Gap Discharge
Continuous Power Dissipation (T = +70°C)
A
TQFN (derate 22.2mW/NC above +70°C) ................1777mW
WLP (derate 21.7mW/NC above +70°C) ..................1739mW
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature......................................................+150°C
ROW0–ROW7, COL0–COL7, PORT0–PORT7 to GND...±15kV
Lead Temperature (TQFN only; soldering, 10s)..............+300°C
Soldering Temperature (reflow).......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Note 1)
Package Thermal Characteristics
TQFN
WLP
Junction-to-Ambient Thermal Resistance (θ )WLP.... 46°C/W
Junction-to-Ambient Thermal Resistance (θ ) ..........45°C/W
JA
JA
Junction-to-Case Thermal Resistance (θ ).................2°C/W
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
= +1.62V to +3.6V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +3.3V, T = +25°C.) (Notes 2, 3)
CC
A
CC A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Supply Voltage
V
1.62
3.3
3.6
V
CC
External Supply Voltage
PORT0–PORT7
V
14
V
PORT_
All key switches open, oscillator running,
COL2–COL7 configured as key switches,
34
50
V
= V
CC
Operating Supply Current
I
PORT_
µA
CC
34 +
20 x N
N keys pressed
Sleep-Mode Supply Current
Key-Switch Source Current
Key-Switch Source Voltage
Key-Switch Resistance
I
1.3
20
3
µA
µA
V
SL
I
35
0.5
5
KEY
V
0.43
KEY
R
(Note 4)
kΩ
ms
KEY
Startup Time from Shutdown
t
2
2.4
START
Output Low Voltage
COL2–COL7
V
I
= 10mA
SINK
0.5
V
OL
T
T
T
= +25°C, V
= +2.61V
125
102
-7
128
131
164
+14
Oscillator Frequency
(PWM Clock)
A
A
A
CC
f
kHz
OSC
= T
to T
, V
≤ 3.6V
MIN
MAX CC
Oscillator Frequency Variation
Key-Scan Frequency
Δf
= +25°C
%
OSC
f
Derived from oscillator clock
64
kHz
KEY
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Electrical Characteristics (continued)
(V
= +1.62V to +3.6V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +3.3V, T = +25°C.) (Notes 2, 3)
CC
A
CC A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GPIO SPECIFICATIONS
Input High Voltage
PORT0–PORT7
0.7 x
V
V
V
IH
V
CC
Input Low Voltage
PORT0–PORT7
0.3 x
V
IL
V
CC
V
V
≤ V
-0.25
-1
+0.25
+5
Input Leakage Current
PORT0–PORT7
IN
CC
I
IN
µA
< V
CC
IN
Output Low Voltage
PORT0–PORT7
V
I
< 20mA
0.6
V
OL
SINK
Input Capacitance
PORT0–PORT7
20
pF
V
V
V
V
V
= +1.62V to +3.6V, T = +25°C
8.55
8.67
11.52
10.51
21.33
20.69
10mA Port Sinking Current
PORT0–PORT7
CC
CC
CC
CC
CC
A
mA
= +3.3V, V = +1V
OL
9.76
= +1.62V to +3.6V, T = +25°C
A
19.40
19.55
20mA Port Sinking Current
PORT0–PORT7
mA
%
= +3.3V, V = +1V
20
OL
= +3.3V, V = +1V, T = +25°C, 20mA
OL
A
Port Sink Current Variation
±1.5
±2.4
0.6
output mode
Output Logic-Low Voltage
INTI, INTK
I
= 10mA
V
SINK
PWM Frequency
f
Derived from oscillator clock
500
Hz
PWM
SERIAL-INTERFACE SPECIFICATIONS
Input High Voltage
SDA, SCL, AD0
0.7 x
V
CC
V
V
V
IH
Input Low Voltage
SDA, SCL, AD0
0.3 x
V
IL
V
CC
V
V
≤ V
-0.25
-0.5
+0.25
+0.5
Input Leakage Current
SDA, SCL, AD0
IN
CC
I
IN
µA
> V
IN
CC
Output Low Voltage
SDA
V
I
= 6mA
0.6
V
OL
SINK
Input Capacitance
SDA, SCL, AD0
C
10
pF
IN
I2C TIMING SPECIFICATIONS
SCL Serial-Clock Frequency
f
Bus timeout disabled
0
400
kHz
µs
SCL
Bus Free Time Between a STOP
and START Condition
t
1.3
BUF
Hold Time (Repeated) START
Condition
t
0.6
µs
HD, STA
Repeated START Condition
Setup Time
t
0.6
0.6
µs
µs
SU, STA
STOP Condition Setup Time
t
SU, STO
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Electrical Characteristics (continued)
(V
= +1.62V to +3.6V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +3.3V, T = +25°C.) (Notes 2, 3)
CC
A
CC A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
µs
Data Hold Time
t
(Note 5)
0.9
HD, DAT
Data Setup Time
t
100
1.3
0.7
ns
SU, DAT
SCL Clock Low Period
SCL Clock High Period
t
µs
LOW
t
µs
HIGH
Rise Time of Both SDA and SCL
Signals, Receiving
20 +
t
(Notes 4, 6)
(Notes 4, 6)
300
300
250
ns
ns
R
0.1C
b
Fall Time of Both SDA and SCL
Signals, Receiving
20 +
0.1C
t
F
b
Fall Time of SDA Signal,
Transmitting
20 +
t
(Notes 4, 7)
(Notes 4, 8)
(Note 4)
ns
ns
pF
F, TX
0.1C
b
Pulse Width of Spike Suppressed
t
SP
50
Capacitive Load for Each Bus Line
C
400
b
Note 2: All parameters are tested at T = +25°C. Specifications over temperature are guaranteed by design.
A
Note 3: All digital inputs at V
or GND.
CC
Note 4: Guaranteed by design.
Note 5: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V of the SCL signal) to bridge
IL
the undefined region of SCL’s falling edge.
Note 6: C = total capacitance of one bus line in pF. t and t measured between +0.3V
and +0.7V
.
b
R
F
CC
CC
Note 7: I
≤ 6mA.
SINK
Note 8: Input filters on the SDA, SCL, and AD0 inputs suppress noise spikes less than 50ns.
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Typical Operating Characteristics
(V
= +2.5V, T = +25°C, unless otherwise noted.)
A
CC
GPO OUTPUT LOW VOLTAGE
GPO OUTPUT LOW VOLTAGE
GPO OUTPUT LOW VOLTAGE
vs. SINK CURRENT (COL2–COL7)
vs. SINK CURRENT (COL2–COL7)
vs. SINK CURRENT (COL2–COL7)
250
250
200
150
100
50
250
200
150
100
50
V
CC
= 2.4V
V
CC
= 3.0V
V
CC
= 3.6V
T
= +85°C
A
T
= +85°C
200
A
T
A
= +85°C
T
A
= +25°C
150
100
50
T
= +25°C
A
T
= +25°C
A
T
A
= -40°C
T
A
= -40°C
T
A
= -40°C
0
0
0
0
5
10
15
20
0
5
10
15
20
0
5
10
15
20
SINK CURRENT (mA)
SINK CURRENT (mA)
SINK CURRENT (mA)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
KEY-SWITCH SOURCE CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
45
40
35
30
25
20
15
18.4
18.3
18.2
18.1
18.0
17.9
17.8
17.7
17.6
17.5
17.4
3.0
2.5
2.0
1.5
1.0
0.5
AUTOSLEEP = OFF
V
= O
COL0
T
= -40NC, +85°C
A
T
= +85°C
A
T
= -40°C
A
T
= +25°C
A
T
A
= +85°C
T
A
= +25°C
T = +25°C
A
T
A
= -40°C
T
A
= -40°C
T
A
= +85°C
3.2
T
= -40°C, +25°C
A
0
2.0
2.4
SUPPLY VOLTAGE (V)
3.2
2.8
SUPPLY VOLTAGE (V)
1.6
2.8
3.6
1.6
2.0
2.4
SUPPLY VOLTAGE (V)
3.2
3.6
1.6
2.0
2.4
3.6
2.8
CONSTANT-CURRENT GPIO OUTPUT
SINK CURRENT vs. OUTPUT VOLTAGE
CONSTANT-CURRENT GPIO OUTPUT
SINK CURRENT vs. OUTPUT VOLTAGE
CONSTANT-CURRENT GPIO OUTPUT
SINK CURRENT vs. OUTPUT VOLTAGE
25
20
15
10
5
25
20
15
10
5
25
20
15
10
5
V
CC
= 2.4V
V
CC
= 3.0V
V
CC
= 3.6V
T
= -40°C
T
= -40°C
T = -40°C
A
A
A
T
= +25°C
T = +25°C
A
T
A
= +25°C
A
T
A
= +85°C
T = +85°C
A
T
A
= +85°C
0
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Pin Configurations
TOP VIEW
30 29 28 27 26 25 24 23 22 21
20
31
32
33
N.C.
PORT0
PORT1
PORT2
19 COL7
18 COL6
17 COL5
PORT3 34
16
COL4
15 GND
14
35
36
37
38
39
40
GND
PORT4
PORT5
PORT6
PORT7
N.C.
MAX7360
COL3
13 COL2
12
EP*
COL1
+
11 COL0
1
2
3
4
5
6
7
8
9
10
TQFN
*EP = EXPOSED PAD, CONNECT EP TO GROUND.
TOP VIEW
BUMP IN BOTTOM
MAX7360
ROW0
A1
PORT6
A2
PORT4
A3
PORT3
A4
PORT1
A5
PORT0
A6
ROW1
B1
PORT7
B2
PORT5
B3
GND
B4
PORT2
B5
AD0
B6
ROW3
C1
GND
C2
ROW2
C3
I.C.
C4
N.C.
C5
V
CC
C6
ROW4
D1
ROW5
D2
COL2
D3
INTK
D4
GND
D5
INTI
D6
ROW6
E1
COL0
E2
GND
E3
COL5
E4
COL7
E5
SCL
E6
ROW7
F1
COL1
F2
COL3
F3
COL4
F4
COL6
F5
SDA
F6
WLP
(2.6mm x 2.6mm)
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Pin Description
PIN
NAME
FUNCTION
TQFN
WLP
A6
1
2
3
4
ROW0 Row Input from Key Matrix. Leave ROW0 unconnected or connect to GND if unused.
ROW1 Row Input from Key Matrix. Leave ROW1 unconnected or connect to GND if unused.
ROW2 Row Input from Key Matrix. Leave ROW2 unconnected or connect to GND if unused.
ROW3 Row Input from Key Matrix. Leave ROW3 unconnected or connect to GND if unused.
B6
C4
C6
5, 15,
25, 35
B4, C5,
D2, E4
GND
Ground
6
7
8
9
D6
D5
E6
D4
ROW4 Row Input from Key Matrix. Leave ROW4 unconnected or connect to GND if unused.
ROW5 Row Input from Key Matrix. Leave ROW5 unconnected or connect to GND if unused.
ROW6 Row Input from Key Matrix. Leave ROW6 unconnected or connect to GND if unused.
ROW7 Row Input from Key Matrix. Leave ROW7 unconnected or connect to GND if unused.
10, 20, 27,
30, 40
C2
N.C.
No Connection. Not internally connected. Leave unconnected.
11
12
F6
E5
COL0
COL1
Column Output to Key Matrix. Leave COL0 unconnected if unused.
Column Output to Key Matrix. Leave COL1 unconnected if unused.
Column Output to Key Matrix. Leave COL2 unconnected if unused. COL2 can be
configured as a GPO (see Table 9 in the Register Tables section).
13
14
16
17
18
19
F5
F4
F3
E3
F2
F1
COL2
COL3
COL4
COL5
COL6
COL7
Column Output to Key Matrix. Leave COL3 unconnected if unused. COL3 can be
configured as a GPO (see Table 9 in the Register Tables section).
Column Output to Key Matrix. Leave COL4 unconnected if unused. COL4 can be
configured as a GPO (see Table 9 in the Register Tables section).
Column Output to Key Matrix. Leave COL5 unconnected if unused. COL5 can be
configured as a GPO (see Table 9 in the Register Tables section).
Column Output to Key Matrix. Leave COL6 unconnected if unused. COL6 can be
configured as a GPO (see Table 9 in the Register Tables section).
Column Output to Key Matrix. Leave COL7 unconnected if unused. COL7 can be
configured as a GPO (see Table 9 in the Register Tables section).
21
22
23
24
26
28
29
E2
E1
D3
D1
C1
B1
A1
SDA
SCL
INTK
INTI
I2C-Compatible, Serial-Data I/O
I2C-Compatible, Serial-Clock Input
Active-Low Key-Switch Interrupt Output. INTK is open drain and requires a pullup resistor.
Active-Low GPI Interrupt Output. INTI is open drain and requires a pullup resistor.
V
CC
Positive Supply Voltage. Bypass V
to GND with a 0.1µF or higher ceramic capacitor.
CC
AD0
I.C.
Address Input. AD0 selects up to four device slave addresses (Table 3).
Internally Connected. Connect to GND for normal operation.
GPIO Port. Open-drain I/O rated at +14V. PORT0 can be configured as a constant-current
output.
31
32
33
34
B2
A2
B3
A3
PORT0
PORT1
PORT2
PORT3
GPIO Port. Open-drain I/O rated at +14V. PORT1 can be configured as a constant-current
output.
GPIO Port. Open-drain I/O rated at +14V. PORT2 can be configured as a constant-current
output.
GPIO Port. Open-drain I/O rated at +14V. PORT3 can be configured as a constant-current
output.
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Pin Description (continued)
PIN
NAME
FUNCTION
TQFN
WLP
GPIO Port. Open-drain I/O rated at +14V. PORT4 can be configured as a constant-current
output.
36
A4
PORT4
PORT5
PORT6
PORT7
EP
GPIO Port. Open-drain I/O rated at +14V. PORT5 can be configured as a constant-current
output.
37
38
39
—
C3
A5
B5
—
GPIO Port. Open-drain I/O rated at +14V. PORT6 can be configured as a constant-current
output, or a rotary switch input.
GPIO Port. Open-drain I/O rated at +14V. PORT7 can be configured as a constant-current
output, or a rotary switch input.
Exposed Pad (TQFN only). EP is internally connected to GND. Connect EP to a ground
plane to increase thermal performance.
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Functional Block Diagram
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
LED ENABLE
GPIO ENABLE
GPIO INPUT
PORT GPIO
AND
CONSTANT-
CURRENT
LED DRIVE
PWM
GPIO
LOGIC
MAX7360
ROTARY
COL0
COL1
COL2*
COL3*
COL4*
COL5*
COL6*
COL7*
COLUMN ENABLE
GPO ENABLE
CURRENT
SOURCE
COLUMN
DRIVES
128kHz
OSCILLATOR
CURRENT DETECT
INTI
INTK
KEY
SCAN
CONTROL
REGISTERS
FIFO
SDA
SCL
AD0
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
2
I C
INTERFACE
OPEN-
DRAIN
ROW
ROW ENABLE
DRIVES
BUS
TIMEOUT
POR
*GPO
To prevent overloading the microprocessor with too many
interrupts, interrupt requests are issued on a programmable
number of FIFO entries, and/or after a set period of time
(Table 10). The key-switch status is checked by reading
the key-switch FIFO. A 1-byte read access returns both
the next key event in the FIFO (if there is one) and the
FIFO status. INTK functions as an open-drain general-
purpose output (GPO) capable of driving an LED if key-
switch interrupts are not required.
Detailed Description
The MAX7360 is a microprocessor peripheral low-noise
key-switch controller that monitors up to 64 key switches
with optional autorepeat, and key events that are presented
in a 16-byte FIFO. The MAX7360 also features eight
open-drain GPIOs configured for digital I/O or constant-
current output for LED applications up to +14V.
The MAX7360 features an automatic sleep mode and
automatic wakeup that further reduce supply current
consumption. The MAX7360 can be configured to enter
sleep mode after a programmable time following a key
event. The FIFO content is maintained and can be read
in sleep mode. The MAX7360 does not enter autosleep
when a key is held down. The autowake feature takes the
MAX7360 out of sleep mode following a keypress event.
Enable/disable autosleep and autowake through the
configuration register (Table 8).
Up to six of the key-switch outputs function as open-
drain GPOs capable of driving additional LEDs when the
application requires fewer keys to be scanned. For
each key-switch output used as a GPO, the number of
monitored key switches reduces by eight.
Initial Power-Up
On power-up, all control registers are set to power-up
values and the MAX7360 is in sleep mode (Table 1).
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Table 1. Register Address Map and Power-Up Condition
ADDRESS
CODE
(hex)
READ/
WRITE
POWER-UP
VALUE (hex)
REGISTER
FUNCTION
DESCRIPTION
0x00
0x01
Read only
0x3F
0x0A
Keys FIFO
Read FIFO key-scan data out
Power-down, key-release enable, autowakeup, and I2C
timeout enable
R/W
Configuration
0x02
0x03
0x04
0x05
0x06
R/W
R/W
R/W
R/W
R/W
0xFF
0x00
0xFE
0x00
0x07
Debounce
Interrupt
GPO
Key debounce time settling and GPO enable
Key-switch interrupt INTK frequency setting
COL2–COL7 and INTK GPO control
Delay and frequency for key repeat
Idle time to autosleep
Key repeat
Sleep
GPIO global
configuration
0x40
R/W
0x00
Rotary switch, GPIO standby, GPIO reset, fade
0x41
0x42
R/W
R/W
0x00
0x00
GPIO control
PORT0–PORT7 input/output control
PORT0–PORT7 debounce time setting
GPIO debounce
GPIO constant-
current setting
0x43
R/W
0xC0
PORT0–PORT7 constant-current output setting
0x44
0x45
R/W
R/W
0x00
0x00
GPIO output mode
Common PWM
PORT0–PORT7 output mode control
Common PWM duty-cycle setting
Rotary switch
configuration
0x46
R/W
0x00
Rotary switch interrupt frequency and debounce time setting
I2C timeout flag
GPIO input register
Rotary switch count
PORT0 PWM
I2C timeout since last POR
0x48
0x49
0x4A
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
Read only
Read only
Read only
R/W
0x00
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
PORT0–PORT7 input values
Switch cycles since last read
PORT0 individual duty-cycle setting
PORT1 individual duty-cycle setting
PORT2 individual duty-cycle setting
PORT3 individual duty-cycle setting
PORT4 individual duty-cycle setting
PORT5 individual duty-cycle setting
PORT6 individual duty-cycle setting
PORT7 individual duty-cycle setting
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PORT1 PWM
PORT2 PWM
PORT3 PWM
PORT4 PWM
PORT5 PWM
PORT6 PWM
PORT7 PWM
PORT0 configuration PORT0 interrupt, PWM mode control and blink period setting
PORT1 configuration PORT1 interrupt, PWM mode control and blink period setting
PORT2 configuration PORT2 interrupt, PWM mode control and blink period setting
PORT3 configuration PORT3 interrupt, PWM mode control and blink period setting
PORT4 configuration PORT4 interrupt, PWM mode control and blink period setting
PORT5 configuration PORT5 interrupt, PWM mode control and blink period setting
PORT6 configuration PORT6 interrupt, PWM mode control and blink period setting
PORT7 configuration PORT7 interrupt, PWM mode control and blink period setting
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Table 2. Key-Switch Mapping
PIN
COL0
KEY 0
KEY 1
KEY 2
KEY 3
KEY 4
KEY 5
KEY 6
KEY 7
COL1
KEY 8
COL2*
KEY 16
KEY 17
KEY 18
KEY 19
KEY 20
KEY 21
KEY 22
KEY 23
COL3*
KEY 24
KEY 25
KEY 26
KEY 27
KEY 28
KEY 29
KEY 30
KEY 31
COL4*
KEY 32
KEY 33
KEY 34
KEY 35
KEY 36
KEY 37
KEY 38
KEY 39
COL5*
KEY 40
KEY 41
KEY 42
KEY 43
KEY 44
KEY 45
KEY 46
KEY 47
COL6*
KEY 48
KEY 49
KEY 50
KEY 51
KEY 52
KEY 53
KEY 54
KEY 55
COL7*
KEY 56
KEY 57
KEY 58
KEY 59
KEY 60
KEY 61
KEY 62
KEY 63
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
KEY 9
KEY 10
KEY 11
KEY 12
KEY 13
KEY 14
KEY 15
*These columns can be configured as GPOs.
determines how INTK is deasserted. Write to bit D7 to
put the MAX7360 into sleep mode or operating mode.
Autosleep and autowake, when enabled, also change the
status of D7 (see Table 8 in the Register Tables section).
Key-Scan Controller
Key inputs are scanned statically, not dynamically, to
ensure low-EMI operation. As inputs only toggle in
response to switch changes, the key matrix can be routed
closer to sensitive circuit nodes.
Debounce Register (0x02)
The key-scan controller debounces and maintains a FIFO
of keypress and release events (including autorepeated
keypresses, if autorepeat is enabled). Table 2 shows the
key-switch order. The user-programmable key-switch
debounce time, and autosleep timer, is derived from the
64kHz clock, which in turn is derived from the 128kHz
oscillator. Time delay for autorepeat and key-switch
interrupt is based on the key-switch debounce time.
The debounce register sets the time for each debounce
cycle, as well as setting whether the GPO ports are
enabled or disabled. Bits D0–D4 set the debounce time
in increments of 1ms starting at 9ms and ending at 40ms
(see Table 9 in the Register Tables section). Bits D5, D6,
and D7 set which of the GPO ports is enabled. Note the
GPO ports are enabled only in the combinations shown in
Table 9, from all disabled to all enabled.
Keys FIFO Register (0x00)
Key-Switch Interrupt Register (0x03)
The keys FIFO register contains the information pertaining
to the status of the keys FIFO, as well as the key events
that have been debounced (see Table 7 in the Register
Tables section). Bits D0–D5 denote which of the 64 keys
have been debounced and the keys are numbered as in
Table 2.
The interrupt register contains information related to the
settings of the interrupt request function, as well as the
status of the INTK output, which can also be configured
as a GPO. If bits D0–D7 are set to 0x00, the INTK output
is configured as a GPO that is controlled by bit D1 in the
port register. There are two types of interrupts, the FIFO-
based interrupt and time-based interrupt. Set bits D0–D4
to assert interrupts at the end of the selected number of
debounce cycles following a key event (see Table 10 in
the Register Tables section). This number ranges from
1–31 debounce cycles. Setting bits D7, D6, and D5 set
the FIFO-based interrupt when there are 2–14 key events
stored in the FIFO. Both interrupts can be configured
simultaneously and INTK asserts depending on which
condition is met first. INTK deasserts depending on the
status of bit D5 in the configuration register.
D7 indicates if there is more data in the FIFO, except
when D5:D0 indicate key 63 or key 62. When D5:D0
indicate key 63 or key 62, the host should read one more
time to determine whether there is more data in the FIFO.
Use key 62 and key 63 for rarely used keys. D6 indicates
if it is a keypress or release event, except when D5:D0
indicate key 63 or key 62.
Reading the key-scan FIFO clears the interrupt INTK
depending on the setting of bit D5 in the configuration
register (0x01).
Ports Register (0x04)
Configuration Register (0x01)
The ports register sets the values of PORT2–PORT7 and
the INTK port, when configured, as open-drain GPOs.
2
The configuration register controls the I C bus timeout feature,
enables key-release detection, enables autowake, and
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
The settings in this register are ignored for ports not configured
as GPOs, and a read from this register returns the values
stored in the register (see Table 11 in the Register Tables
section).
Autowake
Keypresses initiate autowake and the MAX7360 goes into
operating mode. Keypresses that autowake the MAX7360
are not lost. When a key is pressed while the MAX7360 is
in sleep mode, all analog circuitry, including switch-matrix
current sources, turn on in 2ms. The initial key needs to
be pressed for 2ms plus the debounce time to be stored
in the FIFO. Write a 0 to D1 in the configuration register
(0x01) to disable autowakeup.
Autorepeat Register (0x05)
The MAX7360 autorepeat feature notifies the host that at
least one key has been pressed for a continuous period.
The autorepeat register enables or disables this feature,
sets the time delay after the last key event before the key
repeat code (0x7E) is entered into the FIFO, and sets
the frequency at which the key-repeat code is entered
into the FIFO thereafter. Bit D7 specifies whether the
autorepeat function is enabled with 0 denoting autorepeat
disabled, and 1 denoting autorepeat enabled. Bits D0–
D3 specify the autorepeat delay in terms of debounce
cycles ranging from 8–128 debounce cycles (see Table
12 in the Register Tables section). Bits D4, D5, and D6
specify the autorepeat rate or frequency ranging from
4–32 debounce cycles.
GPIOs
The MAX7360 has eight GPIO ports with LED control
functions. The ports can be used as logic inputs, logic outputs,
or constant-current PWM LED drivers. In addition, PORT7
and PORT6 can function as a rotary switch input pair.
When in PWM mode, the ports are set up to start their
PWM cycle in 45N phase increments. This prevents large
current spikes on the LED supply voltage when driving
multiple LEDs.
GPIO Global Configuration Register (0x40)
When autorepeat is enabled, holding the key pressed
results in a key-repeat event that is denoted by 0x7E. The
key being pressed does not show up again in the FIFO.
The GPIO global configuration register controls the main
settings for the eight GPIOs (see Table 14 in the Register
Tables section).
Only one autorepeat code is entered into the FIFO,
regardless of the number of keys pressed. The autorepeat
code continues to be entered in the FIFO at the frequency
set by bits D[4:6] until another key event is recorded.
Following the key-release event, if any keys are still
pressed, the MAX7360 restarts the autorepeat sequence.
Bit D7 enables PORT[7:6] as inputs for a rotary switch. Bit
D5 enables interrupt generation for I C timeouts. D4 is the
main enable/shutdown bit for the GPIOs. D3 functions as a
software reset for the GPIO registers (0x40 to 0x5F). Bits
D[2:0] set the fade in/out time for the GPIOs configured
as constant-current sinks.
2
Autosleep Register (0x06)
GPIO Control Register (0x41)
Autosleep puts the MAX7360 in sleep mode to draw minimal
current. When enabled, the MAX7360 enters sleep mode
if no keys are pressed for the autosleep time (see Table
13 in the Register Tables section).
The GPIO control register configures each port as either
an input or an output (see Table 15 in the Register
Tables section). All GPIOs allow individual configurations,
and power up as inputs. Enabling rotary switch mode
automatically sets D7 and D6 as inputs. The ports
consume additional current if their inputs are left undriven.
Key-Switch Sleep Mode
In sleep mode, the MAX7360 draws minimal current.
Switch-matrix current sources are turned off and pulled up
GPIO Debounce Configuration Register (0x42)
to V . When autosleep is enabled, key-switch inactivity
CC
The GPIO debounce configuration register sets the
amount of time a GPIO must be held for the MAX7360
to register a logic transition (see Table 16 in the Register
Tables section). The GPIO debounce setting is independent
of the key-switch debounce setting. Five bits (D[4:0]) set
32 possible debounce times from 9ms up to 40ms.
for a period longer than the autosleep time puts the part
into sleep mode (FIFO data is maintained). Writing a 1 to
D7 in the configuration register, or a keypress, can take the
MAX7360 out of sleep mode. Bit D7 in the configuration
register gives the sleep-mode status and can be read any
time. The FIFO data is maintained while in sleep mode.
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
GPIO Constant-Current Setting Register (0x43)
Rotary Switch Count Register (0x4A) (Read Only)
The MAX7360 keeps a count of the rotary switch rotations
in two’s compliment format (see Table 23 in the Register
Tables section). The register values wrap around as the
count value switches from a positive to a negative value
and back again. The count resets to zero after an I C read
to this register.
The GPIO constant-current setting register sets the global
constant-current amount (see Table 17 in the Register
Tables section). Bits D1 and D0 set the global current
values from 5mA up to 20mA.
2
GPIO Output Mode Register (0x44)
The GPIO output mode register sets an output as either
a constant-current or non-constant-current output for
PORT[7:0] (see Table 18 in the Register Tables section).
Outputs are configured as constant-current outputs by
default to prevent accidental loading of an LED across
an unregulated output. The constant-current circuits
automatically turn off when not in use to reduce current
consumption.
PORT0–PORT7 Individual PWM Ratio Registers
(0x50 to 0x57)
Each port has an individual PWM ratio register (0x50
to 0x57, see Table 24 in the Register Tables section).
Use values 0x00 to 0xFE in these registers to configure
the number of cycles out of 256 the output sinks current
(LED is on), from 0 cycles to 254 cycles. Use 0xFF to
have an output continuously sink current (always on). For
applications requiring multiple ports to have the same
intensity, program a particular port’s configuration
register (0x58 to 0x5F) to use the common PWM register
(0x45). New PWM settings take place at the beginning of
a PWM cycle, to allow changes from common intensity to
individual intensity with no interruption in the PWM cycle.
Common PWM Register (0x45)
The common PWM register stores the common constant-
current output PWM duty cycle (see Table 19 in the
Register Tables section). The values stored in this register
translate over to a PWM duty cycle in the same manner
as the individual PWM registers (0x50 to 0x57). Ports can
use their own individual PWM value, or the common PWM
value. Write to this register to change the duty cycle of
several ports at once.
PORT0–PORT7 Configuration Registers
(0x58 to 0x5F)
Registers 0x58 to 0x5F set individual configurations for
each port (see Table 25 in the Register Tables section).
Bits D7 and D6 determine the interrupt settings for the
inputs. Interrupts can assert upon detection of a logic
transition, a rising edge, or not at all. D5 sets the port’s
PWM setting to either the common or individual PWM
setting. Bits D[4:2] enable and set the ports’ individual blink
period from 0 to 4096ms. Bits D1 and D0 set a port’s blink
duty cycle.
Rotary Switch Configuration Register (0x46)
The rotary switch configuration register stores rotary
switch settings for PORT7 and PORT6 (see Table 20
in the Register Tables section). D7 determines whether
switch counts or a time delay will trigger an interrupt
if enabled. D[6:4] set the count or time amount to wait
before sending an interrupt. Bits D[3:0] set the debounce
cycle time for the rotary switch inputs. Debounce time
ranges from 0 to 15ms.
Fading
Set the fade cycle time in the GPIO global configuration
register (0x40) to a non-zero value to enable fade in/out
(see Table 14 in the Register Tables section). Fade in
increases an LED’s PWM intensity in 16 even steps from
zero to its stored value. Fade out decreases an LED’s
PWM intensity in 16 even steps from its current value to
zero. Fading occurs automatically in any of the following
scenarios:
2
I C Timeout Flag Register (0x48) (Read Only)
2
The I C timeout flag register contains a single bit (D0),
which indicates if an I C timeout has occurred (see Table
21 in the Register Tables section). Read this register to
clear an I C timeout initiated interrupt.
2
2
GPIO Input Register (0x49) (Read Only)
The GPIO input register contains the input data for all of
the GPIOs (see Table 22 in the Register Tables section).
Ports configured as outputs are read as high. There is
one debounce period delay prior to detecting a transi-
tion on the input port. This prevents a false interrupt
from occurring when changing a port from an output to
an input. The GPIO input register reports the state of
all input ports regardless of any interrupt mask settings.
Ports configured as an input have a 2µA internal pullup to
1) Change the common PWM register value from any
value to zero to cause all ports using the common
PWM register settings to fade out. No ports using
individual PWM settings are affected.
2) Change the common PWM register value to any
value from zero to cause all ports using the common
PWM register settings to fade in. No ports using
individual PWM settings are affected.
V
CC
for PORT[5:0] and a 10µA internal pullup to V
for
CC
PORT[7:6].
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
3) Put the part out of shutdown to cause all ports to
GPIO Port Interrupts (INTI)
fade in. Changing an individual PWM intensity during
fade in automatically cancels that port’s fade and
immediately output at its newly programmed intensity.
2
Three possible sources generate INTI: I C timeout,
GPIOs configured as inputs, and the rotary switch
(registers 0x48, 0x49, and 0x4A). Read the respective
data/status registers for each type of interrupt to clear INTI.
4) Put the part into shutdown to cause all ports to fade
out. Changing an individual PWM intensity during
fade out automatically cancels that port’s fade and
immediately turns off.
Set register 0x46 for rotary switch-based interrupts. Set
registers 0x58 to 0x5F for individual GPI-based interrupts.
If multiple sources generate the interrupt, all the related
status registers must be read to clear INTI.
Blink
Each port has its own blink control settings through registers
0x58 to 0x5F (see Table 25 in the Register Tables
section). The blink period ranges from 0 (blink disabled)
to 4.096s. Settable blink duty cycles range from 6.25%
to 50%. All blink periods start at the same PWM cycle for
synchronized blinking between multiple ports.
Rotary Switch
The MAX7360 can accept a 2-bit rotary switch inputs on
PORT6 and PORT7. Rotation of the switch in a clockwise
direction increments the count. Enable rotary switch
mode from the GPIO global configuration register (0x40).
Several settings for PORT6 and PORT7 occur during
rotary switch mode:
When the blink setting is changed, the internal controller
waits until the current blink period finishes before applying
the change. As a result, the change in blink period may
not always be instantaneous.
1) Each port has a 10µA pullup to V
.
CC
2) Register 0x46 sets the debounce time.
3) A debounced rising edge on PORT6 while PORT7 is
high decreases the count.
4) A debounced rising edge on PORT6 while PORT7 is
low increases the count.
PORT7
For more details, see Figure 1.
INCREMENT
PORT6
Serial Interface
Figure 2 shows the 2-wire serial interface timing details.
PORT7
Serial Addressing
The MAX7360 operates as a slave that sends and
receives data through an I C-compatible 2-wire interface.
DECREMENT
2
PORT6
The interface uses a serial-data line (SDA) and a serial-
clock line (SCL) to achieve bidirectional communication
ROTARY SWITCH
DEBOUNCE
Figure 1. Rotary Switch Input Signal Timing
t
R
t
t
F
SDA
F, TX
t
BUF
t
SU, DAT
t
SU, STA
t
HD, STA
t
LOW
t
SU, STO
t
HD, DAT
t
HIGH
SCL
t
HD, STA
t
R
t
F
START
CONDITION
REPEATED
START CONDITION
STOP
START
CONDITION CONDITION
Figure 2. 2-Wire Serial Interface Timing Details
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
between master(s) and slave(s). A master (typically a
microcontroller) initiates all data transfers to and from the
MAX7360 and generates the SCL clock that synchronizes
the data transfer.
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 4). The data on SDA must remain stable while
SCL is high.
The MAX7360’s SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kΩ,
is required on SDA. The MAX7360’s SCL line operates
only as an input. A pullup resistor is required on SCL if
there are multiple masters on the 2-wire interface, or if
the master in a single-master system has an open-drain
SCL output.
Acknowledge
The acknowledge bit is a clocked 9th bit (Figure 5), which
the recipient uses to handshake receipt of each byte of
data. Thus, each byte transferred effectively requires 9
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge clock
pulse; therefore, the SDA line is stable low during the high
period of the clock pulse. When the master is transmitting
to the MAX7360, the MAX7360 generates the acknowledge
bit because the MAX7360 is the recipient. When the
MAX7360 is transmitting to the master, the master
generates the acknowledge bit because the master is the
recipient.
Each transmission consists of a START (S) condition
(Figure 3) sent by a master, followed by the MAX7360
7-bit slave address plus R/W bit, a register address byte,
one or more data bytes, and finally, a STOP (P) condition.
START and STOP Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START condition by transitioning SDA from high
to low while SCL is high. When the master has finished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
Table 3. 2-Wire Interface Address Map
DEVICE ADDRESS
PIN AD0
A7
0
A6
1
A5
1
A4
1
A3
0
A2
0
A1
0
A0
GND
R/W
R/W
R/W
R/W
V
0
1
1
1
0
1
0
CC
SDA
SCL
0
1
1
1
1
0
0
0
1
1
1
1
1
0
SDA
SCL
P
S
STOP
CONDITION
START
CONDITION
Figure 3. START and STOP Conditions
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 4. Bit Transfer
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
START
CONDITION
CLOCK PULSE FOR
ACKNOWLEDGE
1
2
8
9
SCL
SDA
BY
TRANSMITTER
SDA
BY
RECEIVER
S
Figure 5. Acknowledge
0
1
1
1
A3
A2
A1
R/W
ACK
SDA
SCL
MSB
LSB
Figure 6. Slave Address
COMMAND BYTE IS STORED ON RECEIPT OF
ACKNOWLEDGE CONDITION
D7 D6 D5 D4 D3 D2 D1 D0
ACKNOWLEDGE FROM MAX7360
S
SLAVE ADDRESS
R/W
0
A
COMMAND BYTE
A
P
ACKNOWLEDGE FROM MAX7360
Figure 7. Command Byte Received
ACKNOWLEDGE FROM MAX7360
ACKNOWLEDGE FROM MAX7360
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
ACKNOWLEDGE FROM MAX7360
SLAVE ADDRESS
S
0
A
COMMAND BYTE
A
DATA BYTE
1 BYTE
A
P
R/W
AUTOINCREMENT
COMMAND BYTE ADDRESS
Figure 8. Command and Single Data Byte Received
signals, care must be taken to ensure that AD0 transitions
no sooner than the signals on SDA and SCL.
Slave Addresses
The MAX7360 has a 7-bit long slave address (Figure 6).
The bit following a 7-bit slave address is the R/W bit,
which is low for a write command and high for a read
command.
The MAX7360 monitors the bus continuously, waiting for
a START condition, followed by its slave address. When
the MAX7360 recognizes its slave address, it acknowl-
edges and is then ready for continued communication.
The first 4 bits (MSBs) of the MAX7360 slave address are
always 0111. Slave address bits A3, A2, and A1 corre-
spond, by the matrix in Table 3, to the states of the device
address input AD0, and A0 corresponds to the R/W bit.
The AD0 input can be connected to any of four signals
Bus Timeout
The MAX7360 features a 20ms minimum bus timeout
on the 2-wire serial interface, largely to prevent the
MAX7360 from holding the SDA I/O low during a read
transaction should the SCL lock up for any reason before
a serial transaction is completed. Bus timeout operates
by causing the MAX7360 to internally terminate a serial
(GND, V , SDA, or SCL), giving four possible slave
CC
address pairs and allowing up to four MAX7360 devices
to share the bus. Because SDA and SCL are dynamic
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
ACKNOWLEDGE FROM MAX7360
ACKNOWLEDGE FROM MAX7360
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
ACKNOWLEDGE FROM MAX7360
SLAVE ADDRESS
S
0
A
COMMAND BYTE
A
DATA BYTE
N BYTES
A
P
R/W
AUTOINCREMENT
COMMAND BYTE ADDRESS
Figure 9. N Data Bytes Received
is read using the same rules as for a write (Table 4). Thus,
a read is initiated by first configuring the MAX7360’s com-
mand byte by performing a write (Figure 7). The master can
now read n consecutive bytes from the MAX7360, with the
first data byte being read from the register addressed by
the initialized command byte. When performing read-after-
write verification, remember to reset the command byte’s
address, because the stored command byte address is gen-
erally autoincremented after the write (Figure 9, Table 4).
Table 4. Autoincrement Rules
REGISTER
FUNCTION
ADDRESS
CODE (hex)
AUTOINCREMENT
ADDRESS (hex)
Keys FIFO
0x00
0x00
Autoshutdown
0x06
0x00
All other key switch
All other GPIO
0x01 to 0x05
0x40 to 0x5F
Addr + 0x01
Addr + 0x01
transaction, either read or write, if SCL low exceeds 20ms.
After a bus timeout, the MAX7360 waits for a valid START
condition before responding to a consecutive transmis-
sion. This feature can be enabled or disabled under user
control by writing to the configuration register (Table 8 in
the Register Tables section).
Operation with Multiple Masters
When the MAX7360 is operated on a 2-wire interface
with multiple masters, a master reading the MAX7360
uses a repeated start between the write that sets the
MAX7360’s address pointer, and the read(s) that takes
the data from the location(s). This is because it is
possible for master 2 to take over the bus after master
1 has set up the MAX7360’s address pointer, but before
master 1 has read the data. If master 2 subsequently
resets the MAX7360’s address pointer, master 1’s read
can be from an unexpected location.
Message Format for Writing
the Key-Scan Controller
A write to the MAX7360 comprises the transmission of
the slave address with the R/W bit set to zero, followed
by at least 1 byte of information. The first byte of informa-
tion is the command byte. The command byte determines
which register of the MAX7360 is to be written by the next
byte, if received. If a STOP condition is detected after the
command byte is received, the MAX7360 takes no further
action (Figure 7) beyond storing the command byte.
Command Address Autoincrementing
Address autoincrementing allows the MAX7360 to be
configured with fewer transmissions by minimizing the
number of times the command address needs to be sent.
The command address stored in the MAX7360 generally
increments after each data byte is written or read (Table 4).
Autoincrement only works when doing a multiburst read
or write.
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register of
the MAX7360 selected by the command byte (Figure 8).
If multiple data bytes are transmitted before a STOP condition
is detected, these bytes are generally stored in subsequent
MAX7360 internal registers, because the command byte
address generally autoincrements (Table 4).
Applications Information
2
Reset from I C
After a catastrophic event such as ESD discharge or
microcontroller reset, use bit D7 of the configuration register
(0x01) as a software reset for the key-switch state (the
key-switch register values and FIFO remain unaffected).
Use bit D4 of the GPIO global configuration register
(0x40) as a software reset for the GPIOs.
Message Format for Reading
the Key-Scan Controller
The MAX7360 is read using the internally stored com-
mand byte as an address pointer, the same way the stored
command byte is used as an address pointer for a write.
The pointer generally autoincrements after each data byte
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
REGULAR KEYPRESS
EVENT
EXAMPLES OF VALID THREE-KEY COMBINATIONS
GHOST-KEY
EVENT
KEY-SWITCH MATRIX
KEY-SWITCH MATRIX
KEY-SWITCH MATRIX
Figure 10. Ghost-Key Phenomenon
Figure 11. Valid Three-Key Combinations
Ghost-Key Elimination
Switch On-Resistance
The MAX7360 is designed to be insensitive to resistance,
either in the key switches, or the switch routing to and
from the appropriate COL_ and ROW_ up to 4kΩ (max).
These controllers are therefore compatible with low-cost
membrane and conductive carbon switches.
Ghost keys are a phenomenon inherent with key-switch
matrices. When three switches located at the corners of
a matrix rectangle are pressed simultaneously, the switch
that is located at the last corner of the rectangle (the ghost
key) also appears to be pressed. This occurs because
the potentials at the two sides of the ghost-key switch are
identical due to the other three connections—the switch is
electrically shorted by the combination of the other three
switches (Figure 10). Because the key appears to be
pressed electrically, it is impossible to detect which of the
four keys is the ghost key.
Hot Insertion
The INTI, INTK, SCL, and AD0 inputs and SDA remain
high impedance with up to +3.6V asserted on them when
the MAX7360 powers down (V
= 0). I/O ports (PORT0–
CC
PORT7) remain high impedance with up to +14V asserted
on them when not powered. Use the MAX7360 in hot-
swap applications.
The MAX7360 employs a proprietary scheme that detects
any three-key combination that generates a fourth ghost
key, and does not report the third key that causes a
ghost-key event. This means that although ghost keys
are never reported, many combinations of three keys
are effectively ignored when pressed at the same time.
Applications requiring three-key combinations (such as
<Ctrl><Alt><Del>) must ensure that the three keys are
not wired in positions that define the vertices of a rect-
angle (Figure 11). There is no limit on the number of keys
that can be pressed simultaneously as long as the keys
do not generate ghost-key events and FIFO is not full.
Staggered PWM
The LED’s on-time in each PWM cycle are phase
delayed 45N into eight evenly spaced start positions.
Optimize phasing when using fewer than eight ports as
constant-current outputs by allocating the ports with the
most appropriate start positions. For example, if using
four constant-current outputs, choose PORT0, PORT2,
PORT4, and PORT6 because their PWM start positions
are evenly spaced. In general, choose the ports that
spread the PWM start positions as evenly as possible.
This optimally spreads out the current demand from the
ports’ load supply.
Low-EMI Operation
The MAX7360 uses two techniques to minimize EMI radi-
ating from the key-switch wiring. First, the voltage across
the switch matrix never exceeds +0.55V if not in sleep
INTK/INTI
There are two interrupt outputs, INTK and INTI. Each
interrupt operates independently from the other. See
the Key-Switch Interrupt Register (0x03) and the GPIO
Port Interrupts (INTI) sections for additional information
regarding these two interrupts.
mode, independent of supply voltage V . This reduces
CC
the voltage swing at any node when a switch is pressed
to +0.55V maximum. Second, the keys are not dynamically
scanned, which would cause the key-switch wiring to
continuously radiate interference. Instead, the keys are
monitored for current draw (only occurs when pressed),
and debounce circuitry only operates when one or more
keys are actually pressed.
Power-Supply Considerations
The MAX7360 operates with a +1.62V to +3.6V power-
supply voltage. Bypass the power supply to GND with a
0.1µF or higher ceramic capacitor as close as possible to
the device.
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
ESD Protection
Table 5. ESD Test Levels
All of the MAX7360 pins meet the 2kV Human Body Model
ESD tolerances. Key-switch inputs and GPIOs meet IEC
61000-4-2 ESD protection. The IEC test stresses consist
of 10 consecutive ESD discharges per polarity, at the
maximum specified level and below (per IEC 61000-4-2).
Test criteria include:
1A—CONTACT
DISCHARGE
1B—AIR-GAP DISCHARGE
TEST
VOLTAGE (kV)
TEST VOLTAGE
LEVEL
LEVEL
(kV)
1
2
3
4
X
2
1
2
3
4
X
2
4
4
8
1) The powered device does not latch up during the
ESD discharge event.
6
8
10
2) The device subsequently passes the final test used
Special
Special
for prescreening.
X = Open level. The level has to be specified in the dedicated
equipment specification. If higher voltages than those shown
are specified, special test equipment could be needed.
Table 5 and Table 6 are from the IEC 61000-4-2: Edition
1.1 1999-05: Electromagnetic compatibility (EMC) Testing
and measurement techniques—Electrostatic discharge
immunity test.
Table 6. ESD Waveform Parameters
FIRST PEAK OF
INDICATED
VOLTGE
(kV)
RISE TIME (t ) WITH
DISCHARGE SWITCH
CURRENT (±30%)
AT 30ns
CURRENT
(±30%) AT 60ns
(A)
r
CURRENT
DISCHARGE ±10%
(A)
LEVEL
(ns)
(A)
1
2
3
4
2
4
6
8
7.5
15
0.7 to 1
0.7 to 1
0.7 to 1
0.7 to 1
4
8
2
4
6
8
22.5
30
12
16
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Register Tables
Table 7. Keys FIFO Register Format (0x00)
KEYS FIFO REGISTER DATA
SPECIAL FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
The key number indicated by D5:D0 is a key
event. D7 is always for a key press of key 62 and
key 63. When D7 is 0, the key read is the last
data in the FIFO. When D7 is 1, there is more
data in the FIFO. When D6 is 1, key data read
from FIFO is a key release. When D6 is 0, key
data read from FIFO is a key press.
FIFO
Key
empty release
X
X
X
X
X
X
flag
flag
FIFO is empty.
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
FIFO is overflow. Continue to read data in FIFO
Key 63 is pressed. Read one more time to
determine whether there is more data in FIFO.
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
Key 63 is released. Read one more time to
determine whether there is more data in FIFO.
Key repeat. Indicates the last data in FIFO.
Key repeat. Indicates more data in FIFO.
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
Key 62 is pressed. Read one more time to
determine whether there is more data in FIFO.
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
Key 62 is released. Read one more time to
determine whether there is more data in FIFO.
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Table 8. Configuration Register Format (0x01)
REGISTER
DEFAULT
VALUE
DESCRIPTION
VALUE
FUNCTION
BIT
Key-switch operating mode. Key switches always remain active
when constant-current PWM is enabled (bit 4 of register 0x40 is high)
regardless of autosleep, autowakeup, or an I2C write to this bit.
X
(when 0x40
D4 = 1)
0
Key-switch sleep
When constant-current PWM is disabled
(bit 4 of register 0x40 is low), I2C write,
autosleep, and autowakeup all can change
this bit. This bit can be read back by I2C any
time for current status.
D7
Sleep
(when 0x40 mode. The entire chip
D4 = 0)
0
is shut down.
1
Key-switch operating
mode
(when 0x40
D4 = 0)
D6
D5
Reserved
Interrupt
Reserved
0
0
—
0
0
INTK cleared when FIFO is empty
INTK cleared after host read. In this mode, I2C should read the FIFO
until interrupt condition is removed or further INT may be lost.
1
D4
D3
D2
D1
0
0
1
0
0
1
0
1
—
0
1
0
1
Disable key releases
Enable key releases
—
Key-release
enable
Reserved
Disable keypress wakeup
Enable keypress wakeup
I2C timeout enabled
I2C timeout disabled
Autowakeup
enable
Timeout
disable
D0
0
Table 9. Debounce Register Format (0x02)
REGISTER DATA
REGISTER DESCRIPTION
D7
D6
D5
D4
D3
D2
D1
D0
PORTS ENABLE
DEBOUNCE TIME
Debounce time is 9ms
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
Debounce time is 10ms
Debounce time is 11ms
Debounce time is 12ms
.
.
.
Debounce time is 37ms
Debounce time is 38ms
Debounce time is 39ms
Debounce time is 40ms
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
GPO ports disabled (full key-scan functionality)
GPO port 7 enabled
0
0
0
0
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
GPO ports 7 and 6 enabled
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Table 9. Debounce Register Format (0x02) (continued)
REGISTER DATA
REGISTER DESCRIPTION
D7
D6
D5
D4
D3
D2
D1
D0
PORTS ENABLE
DEBOUNCE TIME
GPO ports 7, 6, and 5 enabled
0
1
1
1
1
1
0
0
1
1
1
0
1
X
1
X
X
X
X
1
X
X
X
X
1
X
X
X
X
1
X
X
X
X
1
X
X
X
X
1
GPO ports 7, 6, 5, and 4 enabled
GPO ports 7, 6, 5, 4, and 3 enabled
GPO ports 7, 6, 5, 4, 3, and 2 enabled
Power-up default setting
Table 10. Key-Switch Interrupt Register Format (0x03)
REGISTER DATA
REGISTER DESCRIPTION
D7
D6
D5
D4
D3
D2
D1
D0
FIFO-BASED INTK
TIME-BASED INTK
INTK used as GPO
FIFO-based INTK disabled
INTK asserts every debounce cycle
INTK asserts every 2 debounce cycles
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Not all zero
0
0
0
0
0
0
0
1
1
0
.
.
.
INTK asserts every 29 debounce cycles
INTK asserts every 30 debounce cycles
INTK asserts every 31 debounce cycles
Time-based INTK disabled
INTK asserts when FIFO has 4 key events
INTK asserts when FIFO has 6 key events
INTK asserts when FIFO has 8 key events
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
0
0
Not all zero
0
0
0
0
1
1
1
0
1
.
.
.
INTK asserts when FIFO has 14 key events
1
1
1
0
0
0
0
0
Both time-based and FIFO-based interrupts
active
Not all zero
Not all zero
Power-up default setting
0
0
0
0
0
0
0
0
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Table 11. Ports Register Format (0x04)
REGISTER
DEFAULT
DESCRIPTION
PORT 7 Control
PORT 6 Control
PORT 5 Control
PORT 4 Control
PORT 3 Control
PORT 2 Control
VALUE
FUNCTION
VALUE
BIT
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Clear port 7 low
D7
1
1
1
1
1
1
Set port 7 high (high impedance)
Clear port 6 low
D6
D5
D4
D3
D2
Set port 6 high (high impedance)
Clear port 5 low
Set port 5 high (high impedance)
Clear port 4 low
Set port 4 high (high impedance)
Clear port 3 low
Set port 3 high (high impedance)
Clear port 2 low
Set port 2 high (high impedance)
Clear port INTK low
Set port INTK high (high impedance)
—
D1
D0
INTK Port Control
1
0
Reserved
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I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Table 12. Autorepeat Register Format (0x05)
REGISTER DATA
REGISTER DESCRIPTION
D7
D6
D5
D4
D3
D2
D1
D0
ENABLE
AUTOREPEAT RATE
AUTOREPEAT DELAY
Autorepeat is disabled
0
1
X
X
X
X
X
X
X
Autorepeat is enabled
AUTOREPEAT RATE
AUTOREPEAT DELAY
Key-switch autorepeat delay is 8 debounce
cycles
1
1
1
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
0
1
0
Key-switch autorepeat delay is 16 debounce
cycles
Key-switch autorepeat delay is 24 debounce
cycles
.
.
.
Key-switch autorepeat delay is 112 debounce
cycles
1
1
1
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
0
1
1
1
0
1
Key-switch autorepeat delay is 120 debounce
cycles
Key-switch autorepeat delay is 128 debounce
cycles
Key-switch autorepeat frequency is 4 debounce
cycles
1
1
1
0
0
0
0
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
Key-switch autorepeat frequency is 8 debounce
cycles
Key-switch autorepeat frequency is 12
debounce cycles
.
.
.
Key-switch autorepeat frequency is 32
debounce cycles
1
1
1
1
X
X
X
X
Power-up default setting
0
0
0
0
0
0
0
0
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Table 13. Autosleep Register Format (0x06)
REGISTER
REGISTER DATA
AUTOSHUTDOWN TIME
RESERVED
AUTOSLEEP REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
No Autosleep
0
0
0
0
0
0
0
0
Autosleep for (ms)
8192
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
1
4096
2048
1024
512
256
256
Power-up default settings
Table 14. GPIO Global Configuration Register (0x40)
REGISTER
DEFAULT
VALUE
DESCRIPTION
VALUE
FUNCTION
BIT
0
1
0
0
PORT6/PORT7 operate as GPIOs
PORT6/PORT7
rotary switch
D7
D6
0
0
PORT6/PORT7 operate as a rotary switch input
Reserved
—
Disabled
I2C timeout
interrupt enable
INTI is asserted when I2C bus times out. INTI is deasserted when a
D5
0
1
read is performed on the I2C timeout flag register (0x48).
PWM, constant-current circuits, and GPIs are shut down. GPO
values depend on their setting. Register 0x41 to 0x5F values are
stored and cannot be changed. The entire part is shut down if the
key switches are in sleep mode (D7 of register 0x01).
0
D4
GPIO enable
GPIO reset
0
Normal GPIO operation. PWM, constant-current circuits, and GPIOs
are enabled regardless of key-switch sleep mode state (see Table 8).
1
0
Normal operation
Return all GPIO registers (registers 0x40 to 0x5F) to their POR
value. This bit is momentary and resets itself to 0 after the write
cycle.
D3
0
1
000
No fading
PWM intensity ramps up (down) between the common PWM value
and 0% duty cycle in 16 steps over the following time period:
D[2:0] = 001 = 256ms
Fade in/out
time
D[2:0]
000
D[2:0] = 010 = 512ms
D[2:0] = 011 = 1024ms
XXX
D[2:0] = 100 = 2048ms
D[2:0] = 101 = 4096ms
D[2:0] = 110/111 = Undefined
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Table 15. GPIO Control Register (0x41)
REGISTER
DEFAULT
DESCRIPTION
PORT7
VALUE
FUNCTION
VALUE
BIT
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Port is an input
D7
0
0
0
0
0
0
0
0
Port is an output
Port is an input
Port is an output
Port is an input
Port is an output
Port is an input
Port is an output
Port is an input
Port is an output
Port is an input
Port is an output
Port is an input
Port is an output
Port is an input
Port is an output
D6
D5
D4
D3
D2
D1
D0
PORT6
PORT5
PORT4
PORT3
PORT2
PORT1
PORT0
Table 16. GPIO Debounce Configuration Register (0x42)
REGISTER DATA
REGISTER DESCRIPTION
D7
D6
D5
D4
D3
D2
D1
D0
RESERVED
DEBOUNCE TIME
Power-up default setting
debounce time is 9ms
0
0
0
0
0
0
0
0
Debounce time is 10ms
Debounce time is 11ms
Debounce time is 12ms
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
.
.
.
Debounce time is 37ms
Debounce time is 38ms
Debounce time is 39ms
Debounce time is 40ms
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Table 17. GPIO Constant-Current Setting Register (0x43)
REGISTER
DEFAULT
VALUE
DESCRIPTION
VALUE
FUNCTION
BIT
D[7:6]
D[5:2]
Reserved
Reserved
11
0000
00
Set always as 11
11
—
0000
Constant current is 5mA
Constant current is 6.67mA
Constant current is 10mA
Constant current is 20mA
01
Constant-
current setting
D[1:0]
00
10
11
Table 18. GPIO Output Mode Register (0x44)
REGISTER
DEFAULT
VALUE
DESCRIPTION
PORT7
VALUE
FUNCTION
BIT
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Port is a constant-current open-drain output
Port is a non-constant-current open-drain output
Port is a constant-current open-drain output
Port is a non-constant-current open-drain output
Port is a constant-current open-drain output
Port is a non-constant-current open-drain output
Port is a constant-current open-drain output
Port is a non-constant-current open-drain output
Port is a constant-current open-drain output
Port is a non-constant-current open-drain output
Port is a constant-current open-drain output
Port is a non-constant-current open-drain output
Port is a constant-current open-drain output
Port is a non-constant-current open-drain output
Port is a constant-current open-drain output
Port is a non-constant-current open-drain output
D7
0
0
0
0
0
0
0
0
D6
D5
D4
D3
D2
D1
D0
PORT6
PORT5
PORT4
PORT3
PORT2
PORT1
PORT0
Table 19. Common PWM Register (0x45)
REGISTER DATA
D4 D3
COMMON PWM
REGISTER DESCRIPTION
D7
D6
D5
D2
D1
D0
0
Power-up default setting (common PWM
ratio is 0/256)
0
0
0
0
0
0
0
Common PWM ratio is 1/256
Common PWM ratio is 2/256
Common PWM ratio is 3/256
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
.
.
.
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Table 19. Common PWM Register (0x45) (continued)
REGISTER DATA
D4 D3
COMMON PWM
REGISTER DESCRIPTION
D7
D6
D5
D2
D1
D0
Common PWM ratio is 252/256
Common PWM ratio is 253/256
Common PWM ratio is 254/256
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
Common PWM ratio is 256/256
(100% duty cycle)
1
1
1
1
1
1
1
1
Table 20. Rotary Switch Configuration Register (0x46)
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
REGISTER DESCRIPTION
INT
TYPE
COUNTS/CYCLES
DEBOUNCE CYCLE TIME
No debounce time
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
Debounce time is 1ms
Debounce time is 2ms
Debounce time is 3ms
X
X
X
X
X
X
.
.
.
Debounce time is 15ms
X
X
X
X
1
1
1
1
No interrupt generated by rotary switch
X
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INTI asserted when rotary switch count = ±1
INTI asserted when rotary switch count = ±2
INTI asserted when rotary switch count = ±3
.
.
.
INTI asserted when rotary switch count = ±7
0
1
1
1
X
X
X
X
INTI asserted 25ms after first debounced event
INTI asserted 50ms after first debounced event
INTI asserted 75ms after first debounced event
1
1
1
0
0
0
0
1
1
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
.
.
.
INTI asserted 175ms after first debounced event
1
1
1
1
X
X
X
X
Power-up default setting
0
0
0
0
0
0
0
0
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
2
Table 21. I C Timeout Flag Register (0x48) (Read Only)
REGISTER
DEFAULT
VALUE
DESCRIPTION
VALUE
FUNCTION
BIT
D[7:1]
Reserved
0000000
0
—
0000000
No I2C timeout has occurred since last read or POR
I2C timeout has occurred since last read or POR. This bit is reset to
zero when a read is performed on this register. I2C timeouts must be
enabled for this function to work (see Table 8).
I2C timeout flag
D0
0
1
Table 22. GPIO Input Register (0x49) (Read Only)
REGISTER
DEFAULT
VALUE
DESCRIPTION
PORT7
VALUE
FUNCTION
BIT
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Port is input low
Port is input high
Port is input low
Port is input high
Port is input low
Port is input high
Port is input low
Port is input high
Port is input low
Port is input high
Port is input low
Port is input high
Port is input low
Port is input high
Port is input low
Port is input high
D7
1
1
1
1
1
1
1
1
D6
D5
D4
D3
D2
D1
D0
PORT6
PORT5
PORT4
PORT3
PORT2
PORT1
PORT0
Table 23. Rotary Switch Count Register (0x4A) (Read Only)
REGISTER DATA
D4 D3
CYCLE COUNT
REGISTER DESCRIPTION
D7
D6
D5
D2
D1
D0
Cycle count in two’s complement (see the
Rotary Switch Configuration Register (0x46)
section)
X
X
X
X
X
X
X
X
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Table 24. PORT0–PORT7 Individual PWM Ratio Registers (0x50 to 0x57)
REGISTER DATA
REGISTER DESCRIPTION
D7
D6
D5
D4
D3
D2
D1
D0
0
PORT PWM
Power-up default setting (port PWM ratio is
0/256)
0
0
0
0
0
0
0
PORT PWM ratio is 1/256
PORT PWM ratio is 2/256
PORT PWM ratio is 3/256
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
.
.
.
PORT PWM ratio is 252/256
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
PORT PWM ratio is 253/256
PORT PWM ratio is 254/256
PORT PWM ratio is 256/256 (100% duty cycle)
Table 25. PORT0–PORT7 Configuration Registers (0x58 to 0x5F)
REGISTER
DEFAULT
VALUE
DESCRIPTION
VALUE
FUNCTION
BIT
0
1
Interrupt is not masked
D7
Interrupt mask
0
Interrupt is masked. PORT7 interrupt mask is ignored when the
device is configured for rotary switch input.
Rising edge-triggered
interrupts
0
1
Edge/level
detect
Interrupts only occur when the GPIO port
is configured as an input
D6
D5
0
0
Rising or falling edge-
triggered interrupts
0
1
Port uses individual PWM intensity register to set the PWM ratio
Port uses common PWM intensity register to set the PWM ratio
Port does not blink
Common PWM
000
001
010
011
100
101
110/111
00
Port blink period is 256ms
Port blink period is 512ms
D[4:2]
D[1:0]
Blink period
Port blink period is 1024ms
000
Port blink period is 2048ms
Port blink period is 4096ms
Undefined
LED is on for 50% of the blink period
LED is on for 25% of the blink period
LED is on for 12.5% of the blink period
LED is on for 6.25% of the blink period
01
Blink-on time
00
10
11
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Typical Application Circuit
+3.3V
+14V
+14V
+1.8V
COL7
COL6
V
CC
PORT0
PORT1
PORT2
COL5
KEY 0
KEY 8
KEY 16
KEY 24
KEY 32
KEY 40
COL4
MAX7360
COL3
COL2
KEY 1
KEY 2
KEY 9
KEY 17
KEY 18
KEY 25
KEY 26
KEY 33
KEY 34
KEY 41
KEY 42
PORT3
PORT4
+3.3V
COL1
COL0
KEY 10
PORT5
PORT6
PORT7
ROW7
ROW6
ROW5
ROW4
ROW3
ROW2
ROW1
ROW0
KEY 3
KEY 4
KEY 5
KEY 6
KEY 7
KEY 11
KEY 12
KEY 13
KEY 14
KEY 15
KEY 19
KEY 20
KEY 21
KEY 22
KEY 23
KEY 27
KEY 28
KEY 29
KEY 30
KEY 31
KEY 35
KEY 36
KEY 37
KEY 38
KEY 39
KEY 43
KEY 44
KEY 45
KEY 46
KEY 47
V
CC
SDA
SCL
INTI
SDA
SCL
INTI
INTK
AD0
µC
INTK
GND
GND
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
40 TQFN-EP
36 WLP
PACKAGE CODE DOCUMENT NO.
T4055+1
21-0140
21-0301
W362A2+1
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MAX7360
I C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
4/09
Initial release
—
Updated Absolute Maximum Ratings and Notes 7 and 8 (now Notes 6 and 7) in
Electrical Characteristics
1
8/10
2, 3, 4
Added the Package Thermal Characteristics section; updated the Df
max values in the Electrical Characteristics
min and
OSC
2
3
1/13
7/19
2
Updated Blink section
13
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2019 Maxim Integrated Products, Inc.
│ 32
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