MAX7401ESA+T [MAXIM]
Switched Capacitor Filter, 1 Func, Bessel, Lowpass, CMOS, PDSO8, 0.150 INCH, SOIC-8;
| 型号： | MAX7401ESA+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Switched Capacitor Filter, 1 Func, Bessel, Lowpass, CMOS, PDSO8, 0.150 INCH, SOIC-8 开关 |
| 文件： | 总12页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4788; Rev 1; 6/99
8 t h -Ord e r, Lo w p a s s , Be s s e l,
S w it c h e d -Ca p a c it o r Filt e rs
1/MAX7405
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX7401/MAX7405 8th-order, lowpass, Bessel,
switched-capacitor filters (SCFs) operate from a single
+5V (MAX7401) or +3V (MAX7405) s up p ly. The s e
devices draw only 2mA of supply current and allow cor-
ner frequencies from 1Hz to 5kHz, making them ideal
for low-power post-DAC filtering and anti-aliasing appli-
cations. They feature a shutdown mode that reduces
supply current to 0.2µA.
♦ 8th-Order, Lowpass Bessel Filters
♦ Low Noise and Distortion: -82dB THD + Noise
♦ Clock-Tunable Corner Frequency (1Hz to 5kHz)
♦ 100:1 Clock-to-Corner Ratio
♦ Single-Supply Operation
+5V (MAX7401)
Two clocking options are available on these devices:
self-clocking (through the use of an external capacitor)
or external clocking for tighter corner-frequency control.
An offset adjust pin allows for adjustment of the DC out-
put level.
+3V (MAX7405)
♦ Low Power
2mA (Operating Mode)
0.2µA (Shutdown Mode)
The MAX7401/MAX7405 Bessel filters provide low over-
shoot and fast settling. Their fixed response simplifies
the design task to selecting a clock frequency.
♦ Available in 8-Pin SO/DIP Packages
♦ Low Output Offset: ±5mV
Ord e rin g In fo rm a t io n
Ap p lic a t io n s
PART
TEMP. RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
8 SO
ADC Anti-Aliasing
Post-DAC Filtering
Air-Bag Electronics
CT2 Base Stations
Speech Processing
MAX7401CSA
MAX7401CPA
MAX7401ESA
MAX7401EPA
MAX7405CSA
MAX7405CPA
MAX7405ESA
MAX7405EPA
8 Plastic DIP
8 SO
8 Plastic DIP
8 SO
P in Co n fig u ra t io n
8 Plastic DIP
8 SO
TOP VIEW
8 Plastic DIP
COM
IN
1
2
3
4
8
7
6
5
CLK
SHDN
OS
Typ ic a l Op e ra t in g Circ u it
MAX7401
MAX7405
GND
V
DD
OUT
V
SUPPLY
0.1µF
SO/DIP
V
DD
SHDN
OUT
INPUT
IN
OUTPUT
MAX7401
MAX7405
CLOCK
CLK
COM
OS
0.1µF
GND
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
8 t h -Ord e r, Lo w p a s s , Be s s e l,
S w it c h e d -Ca p a c it o r Filt e rs
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND
Continuous Power Dissipation (T = +70°C)
A
MAX7401 ..............................................................-0.3V to +6V
MAX7405 ..............................................................-0.3V to +4V
8-Pin SO (derate 5.88mW/°C above +70°C)................471mW
8-Pin DIP (derate 9.09mW/°C above +70°C)...............727mW
Operating Temperature Ranges
IN, OUT, COM, OS, CLK ...........................-0.3V to (V + 0.3V)
DD
SHDN........................................................................-0.3V to +6V
OUT Short-Circuit Duration...................................................1sec
MAX740 _C_A ....................................................0°C to +70°C
MAX740 _E_A .................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX7401
(V
DD
= + 5V, filte r outp ut me a s ure d a t OUT, 10kΩ || 50p F loa d to GND a t OUT, OS = COM, 0.1µF from COM to GND,
SHDN = V , f
= 100kHz, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
DD CLK
A
MIN
PARAMETER
FILTER CHARACTERISTICS
Corner Frequency
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1/MAX7405
f
C
(Note 1)
0.001 to 5
100:1
10
kHz
Clock-to-Corner Ratio
Clock-to-Corner Tempco
Output Voltage Range
Output Offset Voltage
f / f
C
CLK
ppm/°C
V
0.25
-0.1
V
DD
- 0.25
±25
V
V
IN
= V
= V / 2
±5
mV
OFFSET
COM
DD
DC Insertion Gain with
Output Offset Removed
V
COM
= V / 2 (Note 2)
0.15
0.3
dB
dB
DD
Total Harmonic Distortion
plus Noise
f
= 200Hz, V = 4Vp-p,
IN IN
THD+N
-82
1
measurement bandwidth = 22kHz
OS Voltage Gain to OUT
Input Voltage Range at OS
A
OS
V/V
V
V
OS
V
±0.1
COM
V
/ 2
- 0.5
V
+ 0.5
/ 2
DD
DD
Input, COM externally driven
Output, COM internally biased
V
/ 2
/ 2
DD
COM Voltage Range
V
COM
V
V
DD
/ 2
- 0.2
V
/ 2
DD
V
DD
+ 0.2
Input Resistance at COM
Clock Feedthrough
R
75
125
10
1
kΩ
mVp-p
kΩ
COM
Resistive Output Load Drive
R
C
10
50
L
L
Maximum Capacitive Load at
OUT
500
pF
Input Leakage Current at COM
Input Leakage Current at OS
CLOCK
±0.1
±0.1
±10
±10
µA
µA
SHDN = GND, V
= 0 to V
DD
COM
V
= 0 to (V - 1V) (Note 3)
DD
OS
Internal Oscillator Frequency
Clock Input Current
Clock Input High
f
C
= 1000pF (Note 4)
= 0 or 5V
CLK
29
38
48
kHz
µA
V
OSC
OSC
I
V
±15
±30
CLK
V
V
- 0.5
IH
DD
Clock Input Low
V
IL
0.5
V
2
_______________________________________________________________________________________
8 t h -Ord e r, Lo w p a s s , Be s s e l,
S w it c h e d -Ca p a c it o r Filt e rs
1/MAX7405
ELECTRICAL CHARACTERISTICS—MAX7401 (continued)
(V
DD
= + 5V, filte r outp ut me a s ure d a t OUT, 10kΩ || 50p F loa d to GND a t OUT, OS = COM, 0.1µF from COM to GND,
SHDN = V , f
= 100kHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
DD CLK
A
MIN
MAX
A
PARAMETER
POWER REQUIREMENTS
Supply Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
4.5
5.5
3.5
1
V
Supply Current
I
DD
Operating mode, no load, IN = OS = COM
2
mA
µA
dB
Shutdown Current
I
0.2
60
SHDN = GND, CLK driven from 0 to V
DD
SHDN
Power-Supply Rejection Ratio
SHUTDOWN
PSRR
Measured at DC
V
V
DD
- 0.5
V
V
SHDN Input High
SDH
V
SDL
0.5
SHDN Input Low
±0.1
±10
µA
SHDN Input Leakage Current
V
= 0 to V
DD
SHDN
ELECTRICAL CHARACTERISTICS—MAX7405
(V
DD
= + 3V, filte r outp ut me a s ure d a t OUT, 10kΩ || 50p F loa d to GND a t OUT, OS = COM, 0.1µF from COM to GND,
SHDN = V , f
= 100kHz, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
DD CLK
A
MIN
PARAMETER
FILTER CHARACTERISTICS
Corner Frequency
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
C
(Note 1)
0.001 to 5
100:1
10
kHz
Clock-to-Corner Ratio
Clock-to-Corner Tempco
Output Voltage Range
Output Offset Voltage
f
/f
CLK C
ppm/°C
V
0.25
-0.1
V
- 0.25
±25
DD
V
V
IN
= V
= V / 2
±5
mV
OFFSET
COM
DD
DC Insertion Gain with
Output Offset Removed
V
COM
= V / 2 (Note 2)
0.03
0.3
dB
dB
DD
Total Harmonic Distortion
plus Noise
f
= 200Hz, V = 2.5Vp-p,
IN IN
THD+N
-84
1
measurement bandwidth = 22kHz
OS Voltage Gain to OUT
Input Voltage Range at OS
A
OS
V/V
V
V
OS
V
±0.1
COM
V
- 0.1
/ 2
V
+ 0.1
/ 2
DD
DD
COM Voltage Range
V
COM internally biased or externally driven
V
V
/ 2
COM
COM
DD
Input Resistance at COM
Clock Feedthrough
R
75
125
10
1
kΩ
mVp-p
kΩ
Resistance Output Load Drive
R
C
10
50
L
L
Maximum Capacitive
Load at OUT
500
pF
Input Leakage Current at COM
Input Leakage Current at OS
±0.1
±0.1
±10
±10
µA
µA
SHDN = GND, V
= 0 to V
DD
COM
V
= 0 to (V - 1V) (Note 3)
DD
OS
_______________________________________________________________________________________
3
8 t h -Ord e r, Lo w p a s s , Be s s e l,
S w it c h e d -Ca p a c it o r Filt e rs
ELECTRICAL CHARACTERISTICS—MAX7405 (continued)
(V
DD
= + 3V, filte r outp ut me a s ure d a t OUT, 10kΩ || 50p F loa d to GND a t OUT, OS = COM, 0.1µF from COM to GND,
SHDN = V , f
= 100kHz, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
DD CLK
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK
Internal Oscillator Frequency
Clock Input Current
Clock Input High
f
C
= 1000pF (Note 4)
OSC
26
34
43
kHz
µA
V
OSC
I
V
CLK
= 0 or 3V
±15
±30
CLK
V
V
- 0.5
IH
DD
Clock Input Low
V
IL
0.5
V
POWER REQUIREMENTS
Supply Voltage
V
2.7
3.6
3.5
1
V
DD
Supply Current
I
DD
Operating mode, no load, IN = OS = COM
2
mA
µA
dB
Shutdown Current
I
0.2
60
SHDN = GND, CLK driven from 0 to V
SHDN
DD
Power-Supply Rejection Ratio
SHUTDOWN
PSRR
Measured at DC
1/MAX7405
V
V
DD
- 0.5
V
V
SHDN Input High
SDH
V
SDL
0.5
SHDN Input Low
V
= 0 to V
±0.1
±10
µA
SHDN Input Leakage Current
SHDN
DD
FILTER CHARACTERISTICS—MAX7401/MAX7405
(V = +5V for MAX7401, V = +3V for MAX7405; filter output measured at OUT; 10kΩ || 50pF load to GND at OUT; SHDN = V ;
DD
DD
DD
V
V
V
/2; f
= 100kHz; T = T
to T ; unless otherwise noted. Typical values are at T = +25°C.)
MAX A
COM = OS = DD
CLK
A
MIN
PARAMETER
CONDITIONS
MIN
-1.0
-3.3
TYP
-0.8
-3.0
-33
MAX
-0.6
-2.7
-29
UNITS
f
= 0.5f
C
IN
f
IN
= f
C
Insertion Gain Relative to
DC Gain
dB
f
IN
= 3f
C
f
IN
= 6f
-79
-74
C
Note 1: The maximum f is defined as the clock frequency, f
= 100 · f at which the peak SINAD drops to 68dB with a sinu-
C,
C
CLK
soidal input at 0.2f .
C
Note 2: DC insertion gain is defined as ∆V
/ ∆V .
IN
OUT
Note 3: OS voltages above V - 1V saturate the input and result in a 75µA typical input leakage current.
DD
3
3
Note 4: For MAX7401, f
(kHz) 38 · 10 / C
(pF). For MAX7405, f
(kHz) 34 · 10 / C
(pF).
OSC
OSC
OSC
OSC
4
_______________________________________________________________________________________
8 t h -Ord e r, Lo w p a s s , Be s s e l,
S w it c h e d -Ca p a c it o r Filt e rs
1/MAX7405
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +5V for MAX7401, V = +3V for MAX7405; f
= 100kHz; SHDN = V ; V
= V = V / 2; T = +25°C; unless otherwise
CLK
DD
DD
DD COM OS DD A
noted.)
FREQUENCY RESPONSE
PASSBAND FREQUENCY RESPONSE
PHASE RESPONSE
10
0
0.5
0
0
-50
f = 1kHz
C
f = 1kHz
C
f = 1kHz
C
-10
-20
-30
-40
-50
-60
-70
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-100
-150
-200
-250
-300
-350
-400
0
1
2
3
4
5
0
202
404
606
808
1010
0
400
800
1200
1600
2000
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
OFFSET VOLTAGE
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
20
15
10
5
2.03
2.02
2.01
2.00
1.99
1.98
1.97
NO LOAD
V
= V
= V / 2
IN COM DD
NO LOAD
MAX7401
MAX7401
MAX7405
MAX7401
MAX7405
0
-5
-10
-15
-20
MAX7405
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40 -20
0
20
40
60
80 100
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
INTERNAL OSCILLATOR FREQUENCY
vs. C CAPACITANCE
NORMALIZED OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
OFFSET VOLTAGE vs. TEMPERATURE
OSC
1.0
0.5
0
10,000
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
C
OSC
= 390pF
V
= V
= V / 2
IN COM DD
1000
100
10
MAX7405
-0.5
-1.0
-1.5
MAX7401
1
0.1
-40 -20
0
20
40
60
80 100
0.01
0.1
1
10
100
1000
2.5
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (°C)
C
OSC
CAPACITANCE (nF)
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
5
8 t h -Ord e r, Lo w p a s s , Be s s e l,
S w it c h e d -Ca p a c it o r Filt e rs
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +5V for MAX7401, V = +3V for MAX7405; f
= 100kHz; SHDN = V ; V
= V = V / 2; T = +25°C; unless otherwise
CLK
DD
DD
DD COM OS DD A
noted.)
MAX7401
MAX7401
NORMALIZED OSCILLATOR FREQUENCY
vs. TEMPERATURE
THD PLUS NOISE vs.
INPUT SIGNAL AMPLITUDE
THD PLUS NOISE vs. INPUT SIGNAL
AMPLITUDE AND RESISTIVE LOAD
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
f
= 200Hz
IN
C
OSC
= 390pF
NO LOAD
(SEE TABLE A)
-10
f = 1kHz
C
MEASUREMENT BW = 22kHz
-20
-30
-40
-50
-60
-70
-80
-90
MAX7401
R = 500Ω
L
MAX7405
R = 1kΩ
L
A
B
R = 10kΩ
L
1/MAX7405
0
1
2
3
4
5
-40 -20
0
20
40
60
80 100
0
1
2
3
4
5
AMPLITUDE (Vp-p)
TEMPERATURE (°C)
AMPLITUDE (Vp-p)
MAX7405
THD PLUS NOISE vs. INPUT SIGNAL
AMPLITUDE AND RESISTIVE LOAD
MAX7405
THD PLUS NOISE vs.
INPUT SIGNAL AMPLITUDE
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
f
= 200Hz
NO LOAD
(SEE TABLE A)
IN
f = 1kHz
C
MEASUREMENT BW = 22kHz
R = 500Ω
L
R = 1kΩ
L
A
B
R = 10kΩ
L
-90
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0.5
1.0
1.5
2.0
2.5
3.0
AMPLITUDE (Vp-p)
AMPLITUDE (Vp-p)
Table A. THD Plus Noise vs. Input
Signal Amplitude Test Conditions
f
f
f
CLK
(kHz)
MEASUREMENT
BANDWIDTH (kHz)
IN
C
TRACE
(Hz)
(kHz)
A
B
1000
200
5
1
500
100
80
22
6
_______________________________________________________________________________________
8 t h -Ord e r, Lo w p a s s , Be s s e l,
S w it c h e d -Ca p a c it o r Filt e rs
1/MAX7405
P in De s c rip t io n
PIN
NAME
FUNCTION
Common Input. Biased internally at mid-supply. Bypass externally to GND with a 0.1µF capacitor. To over-
ride internal biasing, drive with an external supply.
1
COM
2
3
4
5
IN
Filter Input
GND
Ground
V
DD
Positive Supply Input: +5V for MAX7401, +3V for MAX7405
Filter Output
OUT
OS
Offset Adjust Input. To adjust output offset, bias OS externally. Connect OS to COM if no offset adjustment is
needed. Refer to Offset and Common-Mode Input Adjustment section.
6
7
8
Shutdown Input. Drive low to enable shutdown mode; drive high or connect to V for normal operation.
DD
SHDN
CLK
Clock Input. To override the internal oscillator, connect to an external clock; otherwise, connect an external
capacitor (C
) from CLK to GND to set the internal oscillator frequency.
OSC
_______________De t a ile d De s c rip t io n
The MAX7401/MAX7405 Bessel filters provide low over-
shoot and fast settling responses. Both parts operate
with a 100:1 clock-to-corner frequency ratio and a 5kHz
maximum corner frequency.
A
2V/div
Lowpass Bessel filters such as the MAX7401/MAX7405
delay all frequency components equally, preserving the
shape of step inputs (subject to the attenuation of the
higher frequencies). Bessel filters settle quickly—an
important characteristic in applications that use a multi-
plexer (mux) to select an input signal for an analog-to-
digital converter (ADC). An anti-aliasing filter placed
between the mux and the ADC must settle quickly after
a new channel is selected.
B
C
2V/div
2V/div
200µs/div
Figure 1 shows the difference between Bessel and
Butterworth filters when a 1kHz square wave is applied
to the filter input. With the filter cutoff frequencies set at
5kHz, trace B shows the Bessel filter response and
trace C shows the Butterworth filter response.
A: 1kHz INPUT SIGNAL
B: BESSEL FILTER RESPONSE; f = 5kHz
C
C: BUTTERWORTH FILTER RESPONSE; f = 5kHz
C
Figure 1. Bessel vs. Butterworth Filter Response
Ba c k g ro u n d In fo rm a t io n
Most switched-capacitor filters (SCFs) are designed with
biquadratic sections. Each section implements two filter-
ing poles, and the sections are cascaded to produce
higher order filters. The advantage to this approach is
ease of design. However, this type of design is highly
sensitive to component variations if any section’s Q is
high. An alternative approach is to emulate a passive net-
work using switched-capacitor integrators with summing
and scaling. Figure 2 shows a basic 8th-order ladder filter
structure.
R1
L5
L7
L1
L3
+
-
V
0
V
IN
C6
R2
C2
C4
C8
Figure 2. 8th-Order Ladder Filter Network
_______________________________________________________________________________________
7
8 t h -Ord e r, Lo w p a s s , Be s s e l,
S w it c h e d -Ca p a c it o r Filt e rs
A s witc he d -c a p a c itor filte r s uc h a s the MAX7401/
Lo w -P o w e r S h u t d o w n Mo d e
These devices feature a shutdown mode that is activat-
ed by driving SHDN low. In shutdown mode, the filter’s
supply current reduces to 0.2µA (typ) and its output
becomes high impedance. For normal operation, drive
MAX7405 emulates a passive ladder filter. The filter’s
component sensitivity is low when compared to a cas-
caded biquad design because each component affects
the entire filter shape, not just one pole-zero pair. In other
words, a mismatched component in a biquad design will
have a concentrated error on its respective poles, while
the same mismatch in a ladder filter design results in an
error distributed over all poles.
SHDN high or connect to V
.
DD
___________Ap p lic a t io n s In fo rm a t io n
Offs e t a n d Co m m o n -Mo d e
In p u t Ad ju s t m e n t
Clo c k S ig n a l
The voltage at COM sets the common-mode input volt-
age and is biased at mid-supply with an internal resistor-
d ivid e r. Byp a s s COM with a 0.1µF c a p a c itor a nd
connect OS to COM. For applications requiring offset
adjustment or DC level shifting, apply an external bias
voltage through a resistor-divider network to OS, as
shown in Figure 3. (Note: Do not leave OS unconnect-
ed.) The output voltage is represented by this equation:
External Clock
The MAX7401/MAX7405 family of SCFs is designed for
use with external clocks that have a 40% to 60% duty
cycle. When using an external clock with these devices,
drive CLK with a CMOS gate powered from 0 to V
.
DD
Varying the rate of the external clock adjusts the corner
frequency of the filter as follows:
1/MAX7405
f = f
/ 100
C
CLK
V
= (V - V
) + V
OUT
IN
COM OS
Internal Clock
When using the internal oscillator, connect a capacitor
(C ) between CLK and ground. The value of the
with V
= V / 2 (typical), and where (V - V
) is
COM
DD
IN
COM
OSC
lowpass filtered by the SCF, and V
is added at the
OS
capacitor determines the oscillator frequency as follows:
output stage. See the Electrical Characteristics for the
voltage range of COM and OS. Changing the voltage on
COM or OS significantly from mid-supply reduces the fil-
ter’s dynamic range.
3
K 10
f
(kHz) =
; C
in pF
OSC
OSC
C
OSC
P o w e r S u p p lie s
The MAX7401 operates from a single +5V supply, and
the MAX7405 op e ra te s from a s ing le + 3V s up p ly.
where K = 38 for MAX7401 and K = 34 for MAX7405.
Minimize the stray capacitance at CLK so that it does
not affect the internal oscillator frequency. Vary the rate
of the internal oscillator to adjust the filter’s corner fre-
quency by a 100:1 clock-to-corner frequency ratio. For
example, an internal oscillator frequency of 100kHz
produces a nominal corner frequency of 1kHz.
Bypass V to GND with a 0.1µF capacitor. If dual sup-
DD
p lie s a re re q uire d (± 2.5V for MAX7401, ± 1.5V for
MAX7405), connect COM to system ground and connect
V
SUPPLY
In p u t Im p e d a n c e vs . Clo c k Fre q u e n c ie s
The MAX7401/MAX7405’s input impedance is effectively
that of a switched-capacitor resistor and is inversely pro-
portional to frequency. The input impedance values
determined below represent the average input imped-
ance since the input current is not continuous. As a rule,
use a driver with an output impedance less than 10% of
the filter’s input impedance. Estimate the input imped-
ance of the filter using the following formula:
0.1µF
V
DD
SHDN
OUT
OUTPUT
INPUT
IN
COM
0.1µF
0.1µF
50k
MAX7401
MAX7405
50k
50k
CLOCK
CLK
OS
1
Z
=
IN
f
C
IN
(
)
CLK
GND
where f
= clock frequency and C = 3.37pF.
IN
CLK
Figure 3. Offset Adjustment Circuit
8
_______________________________________________________________________________________
8 t h -Ord e r, Lo w p a s s , Be s s e l,
S w it c h e d -Ca p a c it o r Filt e rs
1/MAX7405
Table 1. Typical Harmonic Distortion
TYPICAL HARMONIC DISTORTION (dB)
f
f
f
V
IN
(Vp-p)
CLK
C
IN
FILTER
MAX7401
MAX7405
(kHz)
(kHz)
(Hz)
2nd
-91
-89
-87
-83
3rd
-83
-79
-83
-82
4th
-90
-92
-87
-88
5th
-93
-92
-88
-88
100
500
100
500
1
5
1
5
200
1000
200
4
2
1000
An t i-Alia s in g a n d P o s t -DAC Filt e rin g
V+
When using the MAX7401/MAX7405 for anti-aliasing or
post-DAC filtering, synchronize the DAC and the filter
clocks. If the clocks are not synchronized, beat frequen-
cies may alias into the passband.
*
V
DD
SHDN
The high clock-to-corner frequency ratio (100:1) also
eases the requirements of pre- and post-SCF filtering. At
the input, a lowpass filter prevents the aliasing of fre-
quencies around the clock frequency into the passband.
At the output, a lowpass filter attenuates the clock
feedthrough.
OUT
OUTPUT
INPUT
IN
COM
MAX7401
MAX7405
V+
V-
CLOCK
CLK
OS
0.1µF
0.1µF
A high clock-to-corner frequency ratio allows a simple
RC lowpass filter, with the cutoff frequency set above
the SCF corner frequency, to provide input anti-aliasing
and reasonable output clock attenuation.
GND
V-
Ha rm o n ic Dis t o rt io n
Harmonic distortion arises from nonlinearities within the
filter. These nonlinearities generate harmonics when a
pure sine wave is applied to the filter input. Table 1 lists
the MAX7401/MAX7405’s typical harmonic-distortion
values with a 10kΩ load at TA = +25°C.
*DRIVE SHDN TO V- FOR LOW-POWER SHUTDOWN MODE.
Figure 4. Dual-Supply Operation
GND to the negative supply. Figure 4 shows an example
of dual-supply operation. Single- and dual-supply perfor-
mance are equivalent. For either single- or dual-supply
operation, drive CLK and SHDN from GND (V- in dual-
supply operation) to V . For ±5V dual-supply applica-
tions, use the MAX291–MAX297.
DD
Ch ip In fo rm a t io n
In p u t S ig n a l Am p lit u d e Ra n g e
The optimal input signal range is determined by observ-
ing the voltage level at which the total harmonic distor-
tion plus noise (THD+N) is minimized for a given corner
frequency. The Typical Operating Characteristics show
graphs of the devices’ THD+N response as the input
signal’s peak-to-peak amplitude is varied. These mea-
surements are made with OS and COM biased at mid-
supply.
TRANSISTOR COUNT: 1116
_______________________________________________________________________________________
9
8 t h -Ord e r, Lo w p a s s , Be s s e l,
S w it c h e d -Ca p a c it o r Filt e rs
________________________________________________________P a c k a g e In fo rm a t io n
1/MAX7405
10 ______________________________________________________________________________________
8 t h -Ord e r, Lo w p a s s , Be s s e l,
S w it c h e d -Ca p a c it o r Filt e rs
1/MAX7405
P a c k a g e In fo rm a t io n (c o n t in u e d )
______________________________________________________________________________________ 11
8 t h -Ord e r, Lo w p a s s , Be s s e l,
S w it c h e d -Ca p a c it o r Filt e rs
NOTES
1/MAX7405
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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Switched Capacitor Filter, 1 Func, Bessel, Lowpass, CMOS, PDSO8, 0.150 INCH, MS-012AA, SOIC-8
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