MAX77641AEWV+T [MAXIM]
Power Supply Support Circuit,;型号: | MAX77641AEWV+T |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | Power Supply Support Circuit, |
文件: | 总53页 (文件大小:2352K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
Click here for production status of specific part numbers.
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
General Description
Benefits and Features
The MAX77640/MAX77641 are a low-I power solution
Q
● Compact, High-Efficiency Power Solution
• 3-Output Single-Inductor Multiple-Output (SIMO)
Buck-Boost Regulator
for applications where size and efficiency are critical. The
device integrates a 3-output single-inductor multiple-out-
put (SIMO) buck-boost regulator, a 150mA LDO, and a
3-channel current-sink driver.
• 150mA LDO
• 3-Channel Current-Sink Driver
• Flexible Power Sequencing
• GPIO and Reset Output
The SIMO operates on an input between 2.7V and 5.5V.
The outputs are independently programmable between
0.8V and 5.25V depending on ordering option. Each out-
put is a buck-boost with glitchless transition between buck
and boost operation. The SIMO can support >300mA
● 3-Output SIMO Extends Battery Life
• 2.7V to 5.5V Input Voltage Range from Single Cell
Li-Ion
loads (1.8V
, 3.7V ).
• 0.8V to 5.25V Output Voltage Range (Table 1)
OUT
IN
• Supports >300mA loads (1.8V
• Improves Overall System Efficiency while Reducing
Size
• Maintains Regulation without Dropout unlike
Traditional Bucks
• Glitchless Buck-Boost Operation
, 3.7V )
OUT
IN
The 150mA LDO provides ripple rejection for noise-sen-
sitive applications. The current sinks can be programmed
to blink LEDs in custom patterns. The device integrates
a power sequencer to control power-up/down order of
each output. Default output voltages and sequence order
2
are factory-programmable. An I C serial interface further
configures the device.
● Low Quiescent Current
• 300nA Shutdown Current
• 5.6μA Operating Current (3 SIMO Channels and
LDO On)
The MAX77640/MAX77641 are available in a 30-bump
wafer-level package (WLP). Total solution size is 16mm .
For a similar product with a battery charger, refer to the
MAX77650.
2
● Small Size
• 2.75mm x 2.15mm (0.7mm max heigh) WLP
• 30-Bump, 0.4mm Pitch, 6 x 5 Array
• 16mm Total Solution Size
Applications
2
● Hearables: Bluetooth Headphones and Earbuds
● Wearables: Fitness, Health, and Activity Monitors
● Action Cameras, Wearable/Body Cameras
● Internet of Things (IoT) Gadgets
Ordering Information appears at end of data sheet.
Simplified Application Circuit
2.7V TO 5.5V
DC INPUT
MAX77640
IN_SBB
2
16mm SOLUTION SIZE
SYS
V
SYS
4.15mm
IN_LDO
SBB0
2.05V
1.2V
3.3V
GND
C
LDO
SBB1
SBB2
V
SYS
C
SBB0
C
SBB1
C
SBB2
SYSTEM
RESOURCES
ONKEY
nEN
PGND
GPIO
GPIO
1.5µH
LXA
LXB
V
IO
C
SYS
LDO
1.85V
BST
SYS
V
/POWER
IO
L
SDA
SCL
nRST
SDA
SCL
nRST
nIRQ
LED0
LED1
LED2
nIRQ
● 0.2mm COMPONENT PITCH
● PULLUP RESISTORS NOT DRAWN
PROCESSOR
PWR_HLD
PWR_HLD
19-100307; Rev 2; 8/18
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
TABLE OF CONTENTS
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
30 WLP 0.4mm Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Characteristics—Top Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics—SIMO Buck-Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical Characteristics—LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical Characteristics—Current Sinks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2
Electrical Characteristics—I C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Bump Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MAX77640/MAX77641 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Bump Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Detailed Description—Top Level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Support Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Top-Level Interconnect Simplified Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Voltage Monitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SYS POR Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SYS Undervoltage-Lockout Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SYS Overvoltage-Lockout Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
nEN Enable Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
nEN Manual Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
nEN Dual-Functionality: Push-Button vs. Slide-Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Interrupts (nIRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Reset Output (nRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Power Hold Input (PWR_HLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
General-Purpose Input Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
On/Off Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Flexible Power Sequencer (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Debounced Inputs (nEN and GPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Thermal Alarms and Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Detailed Description—SIMO Buck-Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SIMO Features and Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
www.maximintegrated.com
Maxim Integrated | 2
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
TABLE OF CONTENTS (CONTINUED)
SIMO Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
SIMO Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
SIMO Output Voltage Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SIMO Active Discharge Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SIMO Available Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Boost Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SIMO Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Unused SIMO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Detailed Description—LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Features and Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
LDO Active-Discharge Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
LDO Dropout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
LDO Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Current Limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Using the LDO as a Load Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Input and Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Detailed Description—Current Sinks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
LED Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Unused Current Sink Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2
Detailed Description—I C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
www.maximintegrated.com
Maxim Integrated | 3
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
LIST OF FIGURES
Figure 1. Top-Level Interconnect Simplified Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 2. nEN Usage Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 3. GPIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 4. Top-Level On/Off Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 5. Power-Up/Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 6. Flexible Power Sequencer Basic Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 7. Startup Timing Diagram Due to nEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 8. Debounced Inputs Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 9. SIMO Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 10. SIMO Switching Frequency Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 11. PCB Top-Metal and Component Layout Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 12. LDO Simplified Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 13. LDO Capacitance for Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 14. Current Sink Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2
Figure 15. I C Simplified Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 16. Slave Address Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
www.maximintegrated.com
Maxim Integrated | 4
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
LIST OF TABLES
Table 1. Regulator Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 2. On/Off Controller Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 3. SIMO Available Output Current for Common Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 4. Example Inductors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2
Table 5. I C Slave Address Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
www.maximintegrated.com
Maxim Integrated | 5
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Absolute Maximum Ratings
nEN, PWR_HLD, nIRQ, nRST to GND .......-0.3V to V
SCL, SDA, GPIO to GND ...............................-0.3V to V + 0.3V
SYS to GND .......................................................... -0.3V to +6.0V
SYS to IN_SBB ..................................................... -0.3V to +0.3V
nIRQ, nRST, SDA, GPIO Continous Current .................... ±20mA
+ 0.3V
BST to LXB ............................................................-0.3V to +6.0V
SBB0, SBB1, SBB2 Short-Circuit Duration.................Continuous
PGND to GND........................................................-0.3V to +0.3V
LGND to GND........................................................-0.3V to +0.3V
Operating Temperature Range.............................-40°C to +85°C
Junction Temperature.......................................................+150°C
Storage Temperature Range ..............................-65°C to +150°C
Soldering Temperature (reflow) ........................................+260°C
Continuous Power Dissipation (Multilayer Board)
SYS
IO
LDO to GND (Note 1) ............................ -0.3V to V
+ 0.3V
+ 0.3V
SYS
IN_LDO
IN_LDO, V to GND...................................-0.3V to V
IO
LED0, LED1, LED2 to LGND ................................ -0.3V to +6.0V
IN_SBB to PGND .................................................. -0.3V to +6.0V
LXA Continuous Current (Note 1) ..................................1.2A
LXB Continuous Current (Note 2) ..................................1.2A
(T = +70°C, derate 20.4mW/°C above +70°C)..........1632mW
A
RMS
RMS
SBB0, SBB1, SBB2 to PGND (Note 3) ................. -0.3V to +6.0V
BST to IN_SBB...................................................... -0.3V to +6.0V
Note 1: LXA has internal clamping diodes to PGND and IN_SBB. It is normal for these diodes to briefly conduct during switching
events. Avoid steady-state conduction of these diodes.
Note 2: Do not externally bias LXB. LXB has an internal low-side clamping diode to PGND, and an internal high-side clamping diode
that dynamically shifts to the selected SIMO output. It is normal for these internal clamping diodes to briefly conduct during
switching events. When the SIMO regulator is disabled, the LXB to PGND absolute maximum voltage is -0.3V to V
+0.3V.
SBB0
Note 3: When the active discharge resistor is engaged, limit its power dissipation to an average of 10mW.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Package Information
30 WLP 0.4mm Pitch
Package Code
W302H2+1
Outline Number
21-100047
Land Pattern Number
Thermal Resistance, Four-Layer Board:
Refer to Application Note 1891
Junction to Ambient (θ
)
49°C/W (2s2p board)
JA
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
www.maximintegrated.com
Maxim Integrated | 6
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Electrical Characteristics—Top Level
(V
= V
= V
= 3.7V, V = 1.8V, limits are 100% production tested at T = +25°C, Min/Max limits over the operating
IN_LDO IO A
SYS
IN_SBB
temperature range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Voltage
Range
V
SYS
2.7
5.5
V
Main bias is off
(SBIA_EN = 0).
This is the standby
state
0.3
1.0
1
Current measured
into SYS, IN_SBB,
and IN_LDO, all
resources are off
(LDO, SBB0,
Main bias is on in
low-power mode
(SBIA_EN = 1,
SBIA_LPM = 1)
Shutdown Supply
Current
I
μA
SHDN
SBB1, SBB2,
LED0, LED1,
Main bias is on in
normal mode
(SBIA_EN = 1,
SBIA_LPM = 0)
LED2), T
+25°C
=
A
28.0
5.6
Current measured
Main bias is in low-
into SYS, IN_SBB, power mode
and IN_LDO. LDO, (SBIA_LPM = 1)
SBB0, SBB1, and
13
60
Quiescent Supply
Current
I
μA
Q
Main bias is
normal-power
SBB2 are enabled
with no load. LED0,
40
mode (SBIA_LPM
LED1, and LED2
= 0)
are disabled
POWER-ON RESET (POR)
POR Threshold
V
V
SYS
falling
1.6
1.9
2.1
V
POR
POR Threshold
Hysteresis
100
mV
UNDERVOLTAGE LOCKOUT (UVLO)
V
V
falling, UVLO_F[3:0] = 0xA
falling, UVLO_F[3:0] = 0xF
2.5
2.6
2.7
SYS
UVLO Threshold
V
V
SYSUVLO
2.75
2.85
2.95
SYS
UVLO Threshold
Hysteresis
V
SYSUVLO_HY
S
UVLO_H[3:0] = 0x5
300
mV
OVERVOLTAGE LOCKOUT (OVLO)
OVLO Threshold
V
V
SYS
rising
5.70
5.85
6.00
V
SYSOVLO
THERMAL MONITORS
Overtemperature-
Lockout Threshold
T
T rising
165
80
°C
°C
°C
°C
OTLO
J
Thermal Alarm
Temperature 1
T
T rising
J
JAL1
JAL2
Thermal Alarm
Temperature 2
T
T rising
J
100
15
Thermal Alarm
Temperature Hysteresis
www.maximintegrated.com
Maxim Integrated | 7
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Electrical Characteristics—Top Level (continued)
(V
= V
= V
= 3.7V, V = 1.8V, limits are 100% production tested at T = +25°C, Min/Max limits over the operating
IN_LDO IO A
SYS
IN_SBB
temperature range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ENABLE INPUT (nEN)
V
V
5.5V
= 5.5V,
= 0V, and
SYS
T
T
= +25°C
= +85°C
-1
±0.001
±0.01
+1
nEN
A
nEN Input Leakage
Current
I
μA
nEN_LKG
V
V
= 5.5V,
= 0V and
SYS
nEN
A
5.5V
nEN Input Falling
Threshold
V
-
V
V
-
-
SYS
1.4
SYS
1.0
V
V
nEN falling
nEN falling
V
V
TH_nEN_F
nEN Input Rising
Threshold
V
SYS
0.6
-
SYS
0.9
TH_nEN_F
DBEN_nEN = 0
DBEN_nEN = 1
MRT_OTP = 0
MRT_OTP = 1
100
30
16
8
μs
nEN Debounce Time
t
DBNC_nEN
ms
14
7
20
nEN Manual Reset Time
t
s
MRST
10.5
POWER HOLD INPUT (PWR_HLD)
V
V
= V = 5.5V,
T
T
= +25°C
= +85°C
-1
±0.001
±0.01
+1
SYS
IO
A
PWR_HLD Input
Leakage Current
I
PWR_HLD_LK
G
= 0V,
μA
PWR_HLD
A
and 5.5V
PWR_HLD Input
Voltage Low
V
V
V
V
= 1.8V
= 1.8V
= 1.8V
0.3 x V
V
V
IL
IO
IO
IO
IO
PWR_HLD Input
Voltage High
V
IH
0.7 x V
IO
PWR_HLD Input
Hysteresis
V
HYS
50
mV
μs
PWR_HLD Glitch Filter
t
Both rising and falling edges are filtered
100
PWR_HLD_GF
Maximum time for PWR_HLD input to
assert after nRST deasserts during the
power-up sequence
t
PWR_HLD_WA
IT
PWR_HLD Wait Time
3.5
4.0
5.0
0.4
+1
s
OPEN-DRAIN INTERRUPT OUTPUT (nIRQ)
nIRQ Output Voltage
Low
V
OL
I
= 2mA
= 25pF
V
SINK
nIRQ Output Falling
Edge Time
t
C
2
ns
f_nIRQ
IRQ
V
= V = 5.5V,
T
T
= +25°C
= +85°C
-1
±0.001
SYS
IO
A
nIRQ set to be high
impedance (i.e., no
interrupts), V
0V and 5.5V
nIRQ Output High
Leakage Current
I
μA
V
nIRQ_LKG
±0.01
A
=
nIRQ
OPEN-DRAIN RESET OUTPUT (nRST)
nRST Output Voltage
Low
V
OL
I
= 2mA
0.4
SINK
www.maximintegrated.com
Maxim Integrated | 8
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Electrical Characteristics—Top Level (continued)
(V
= V
= V
= 3.7V, V = 1.8V, limits are 100% production tested at T = +25°C, Min/Max limits over the operating
IN_LDO IO A
SYS
IN_SBB
temperature range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
nRST Output Falling
Edge Time
t
C
RST
= 25pF
2
ns
f_nRST
nRST Deassert Delay
Time
t
See Figure 5 for more information
See Figure 5 for more information
5.12
ms
ms
RSTODD
nRST Assert Delay
Time
t
10.24
RSTOAD
V
SYS
= V
=
T
A
= +25°C
-1
±0.001
+1
IO
5.5V, nRST set to
be high impedance
(i.e., not reset),
nRST Output High
Leakage Current
I
μA
nRST_LKG
T
A
= +85°C
±0.01
V
nRST
= 0V and
5.5V
GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
Input Voltage Low
Input Voltage High
V
V
V
= 1.8V
0.3 x V
+1
V
V
IL
IO
IO
V
IH
= 1.8V
0.7 x V
-1
IO
IO
IO
DIR = 1, V
5.5V, V
and 5.5V
=
= 0V
T
T
= +25°C
= +85°C
±0.001
±0.01
IO
A
Input Leakage Current
I
μA
GPI_LKG
GPIO
A
Output Voltage Low
Output Voltage High
Input Debounce Time
V
OL
I
I
= 2mA
0.4
V
V
SINK
V
OH
= 1mA
0.8 x V
SOURCE
t
DBEN_GPI = 1
30
3
ms
DBNC_GPI
Output Falling Edge
Time
t
C
= 25pF
= 25pF
ns
ns
f_GPIO
GPIO
GPIO
Output Rising Edge
Time
t
C
3
r_GPIO
FLEXIBLE POWER SEQUENCER
Power-Up Event Periods
t
See Figure 6 for more information
See Figure 6 for more information
1.28
2.56
ms
ms
EN
Power-Down Event
Periods
t
DIS
Electrical Characteristics—SIMO Buck-Boost
(V
= 3.7V, V
= 3.7V, C
= 10μF, L = 1.5μH, limits are 100% production tested at T = +25°C, Min/Max limits over the
SBBx A
SYS
IN_SBB
operating temperature range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUT VOLTAGE RANGE (SBB0)
Minimum Output
Voltage
0.8
V
Maximum Output
Voltage
2.375
6
V
Output DAC Bits
bits
www.maximintegrated.com
Maxim Integrated | 9
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Electrical Characteristics—SIMO Buck-Boost (continued)
(V
= 3.7V, V
= 3.7V, C
= 10μF, L = 1.5μH, limits are 100% production tested at T = +25°C, Min/Max limits over the
SBBx A
SYS
IN_SBB
operating temperature range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output DAC LSB Size
25
mV
OUTPUT VOLTAGE RANGE (SBB1)
MAX77640
MAX77641
MAX77640
MAX77641
0.8
2.4
Minimum Output
Voltage
V
1.5875
5.25
6
Maximum Output
Voltage
V
Output DAC Bits
bits
mV
MAX77640
MAX77641
12.5
50
Output DAC LSB Size
OUTPUT VOLTAGE RANGE (SBB2)
MAX77640
MAX77641
MAX77640
MAX77641
0.8
2.4
3.95
5.25
6
Minimum Output
Voltage
V
V
Maximum Output
Voltage
Output DAC Bits
bits
mV
Output DAC LSB Size
50
STATIC OUTPUT VOLTAGE ACCURACY
V
falling,
T
T
= +25°C
= -40°C
-2.5
-4.0
+2.5
+4.0
SBBx
A
threshold where
LXA switches high.
Specified as a
percentage of
target output
Output Voltage
Accuracy
%
A
to +85°C
voltage.
TIMING CHARACTERISTICS
Delay time from the SIMO receiving its
first enable signal to when it begins to
switch in order to service that output.
Enable Delay
60
μs
Soft-Start Slew Rate
dV/dt
3.3
5.0
6.6
mV/μs
SS
POWER STAGE CHARACTERISTICS
SBB0, SBB1,
SBB2 are disabled,
T
T
T
= +25°C
= +85°C
= +25°C
-1.0
±0.1
±1.0
±0.1
+1.0
A
A
A
LXA Leakage Current
μA
V
V
= 5.5V,
= 0V, or 5.5V
IN_SBB
LXA
SBB0, SBB1,
SBB2 are disabled,
-1.0
+1.0
+1.0
LXB Leakage Current
BST Leakage Current
V
V
= 5.5V,
= 0V or 5.5V,
μA
μA
IN_SBB
T
A
= +85°C
±1.0
LXA
all V
= 5.5V
SBBx
V
V
V
= 5.5V,
= 5.5V,
= 11V
T
T
= +25°C
= +85°C
+0.01
+0.1
IN_SBB
A
LXB
BST
A
www.maximintegrated.com
Maxim Integrated | 10
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Electrical Characteristics—SIMO Buck-Boost (continued)
(V
= 3.7V, V
= 3.7V, C
= 10μF, L = 1.5μH, limits are 100% production tested at T = +25°C, Min/Max limits over the
SBBx A
SYS
IN_SBB
operating temperature range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SBB0, SBB1,
T
T
= +25°C
= +85°C
+0.1
+1.0
A
SBB2 are disabled,
active-discharge
disabled
Disabled Output
Leakage Current
(ADE_SBBx = 0),
μA
+0.2
140
A
V
V
V
= 5.5V,
SBBx
= 0V, V
=
LXB
SYS
= V
=
BST
IN_SBB
5.5V
Active Discharge
Impedance
SBB0, SBB1, SBB2 are disabled, active
discharge enabled (ADE_SBBx = 1)
R
80
260
Ω
A
AD_SBBx
CONTROL SCHEME
IP_SBBx = 0b11
IP_SBBx = 0b10
IP_SBBx = 0b01
IP_SBBx = 0b00
0.414
0.589
0.713
0.892
0.500
0.707
0.866
1.000
0.586
0.806
0.947
1.108
Peak Current Limit
(Note 5)
I
P_SBB
Note 4: Guaranteed by design and characterization but not directly production tested. Production test coverage is provided by the
Shutdown Supply Current and Quiescent Supply Current specification in the Electrical Characteristics—Top Level table.
Note 5: Typical values align with bench observations using the stated conditions. Minimum and maximum values are tested in
production with DC currents. See the Typical Operating Characteristics SIMO switching waveforms to gain more insight on
this specification.
Electrical Characteristics—LDO
(V
= 3.7V, V
= 2.05V, V
= 1.85V, C
= 10μF, limits are 100% production tested at T = +25°C, Min/Max limits over
LDO A
SYS
IN_LDO
LDO
the operating temperature range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL CHARACTERISTICS
IN_LDO cannot exceed SYS voltage
(Note 6)
Input Voltage
V
1.8
5.5
1
V
IN_LDO
Current measured into IN_LDO, LDO
output disabled (Note 4)
LDO Shutdown Current
I
I
0.1
1.7
μA
IN_LDO
LDO output
enabled and in
regulation,
5.15
V
=
IN_LDO
2.05V, V
1.85V
=
Current measured
LDO
LDO Quiescent Supply
Current (Note 4)
into IN_LDO, I
0mA
=
LDO
μA
IN_LDO
LDO output
enabled and in
dropout, V
=
2.3
IN_LDO
1.8V, V
target
LDO
is 1.85V
Maximum Output
Current
I
150
mA
OUT
www.maximintegrated.com
Maxim Integrated | 11
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Electrical Characteristics—LDO (continued)
(V
= 3.7V, V
= 2.05V, V
= 1.85V, C
= 10μF, limits are 100% production tested at T = +25°C, Min/Max limits over
LDO A
SYS
IN_LDO
LDO
the operating temperature range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
Current Limit
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
V
LDO
externally forced to 1.3V
165
255
375
mA
LIM_LDO
GENERAL CHARACTERISTICS / OUTPUT VOLTAGE RANGE
Programmable with TV_LDO[6:0] in
12.5mV steps
Output Voltage Range
1.3500
2.9375
V
Output DAC Bits
7
bits
mV
Output DAC LSB Size
STATIC CHARACTERISTICS
12.5
Initial Output Voltage
Accuracy
I
= 75mA, T = +25°C
-2.5
-3
+2.5
+3
%
%
LDO
A
V
programmed from 1.35V to
LDO
Output Voltage
Accuracy
2.9375V, V
not in dropout, I
= 1.8V to 5.5V, LDO
IN_LDO
= 0mA to 150mA,
LDO
T
A
= -5°C to +85°C
Main bias circuits
are in normal-
power mode
f = 10Hz to
100kHz, I
550
800
=
=
=
OUT
(SBIA_LPM = 0)
15mA, V
SYS
Output Noise
μV
RMS
3.7V, V
IN_LDO
Main bias circuits
are in low-power
mode (SBIA_LPM
= 1)
2.05V, V
1.85V
=
LDO
TIMING CHARACTERISTICS
Enable Delay
T
= +25°C
0.6
1.25
2.50
ms
A
V
from 10% to 90% of final
LDO
Soft-Start Slew Rate
dV/dt
0.5
1.25
mV/μs
SS
value, T = +25°C
A
POWER STAGE CHARACTERISTICS
V
SYS
= 3.7V, 1.85V programmed output
Dropout Voltage
V
voltage (TV_LDO[6:0] = 0x20),
90
180
0.9
mV
LDO_DO
V
= 1.7V, I
= 150mA (Note 1)
LDO
IN_LDO
V
SYS
= 3.7V, 1.85V
programmed output
voltage
(TV_LDO[6:0] =
T
A
= +25°C
0.6
0x20), V
=
IN_LDO
1.7V, I
=
LDO
I
(Note 1)
MAX
Dropout On-Resistance
R
DSON
Ω
V
=3.7V, 1.85V
SYS
programmed output
voltage
(TV_LDO[6:0] =
T
A
= +85°C
1.2
0x20), V
=
IN_LDO
1.7V, I
=
LDO
I
(Note 1)
MAX
www.maximintegrated.com
Maxim Integrated | 12
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Electrical Characteristics—LDO (continued)
(V
= 3.7V, V
= 2.05V, V
= 1.85V, C
= 10μF, limits are 100% production tested at T = +25°C, Min/Max limits over
LDO A
SYS
IN_LDO
LDO
the operating temperature range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Active-Discharge
Impedance
Regulator disabled, active discharge
enabled (ADE_LDO = 1)
R
50
100
200
Ω
AD_LDO
Regulator disabled,
active discharge
disabled
T
7)
= +25°C (Note
T = +85°C
A
A
+0.1
+1.0
+1.0
Disabled Output
Leakage Current
(ADE_LDO = 0),
μA
V
SYS
= V
=
IN_LDO
5.5V, V
= 5.5V
LDO
and 0V
Note 6: Dropout is the condition where the input voltage is in its valid input range but the output cannot be properly regulated because
the input voltage is not sufficiently higher than the output voltage. See the LDO Dropout section for more information.
Note 7: Guaranteed by design and characterization but not directly production tested. The ability to disconnect the active discharge
resistance is functionally checked in a production test.
Electrical Characteristics—Current Sinks
(V
= V
= 3.7V, V = 1.8V, limits are 100% production tested at T = +25°C, Min/Max limits over the operating temperature
IN_SBB IO A
SYS
range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
µA
GENERAL CHARACTERISTICS
Change in supply current at SYS when
one channel is enabled and delivering
Current-Sink Quiescent
Current
I
6
12
Q
12.8mA, V
= 0.2V
LEDx
All current-sink
drivers combined,
outputs disabled,
T
= +25ºC
= +85ºC
+0.1
+1.0
+1.0
A
A
Current-Sink Leakage
µA
T
V
LEDx
= 5.5V
3.2mA CURRENT-SINK RANGE (LED_FSx[1:0] = 0b01, VLEDx = 0.2V)
Minimum Sink Current
Maximum Sink Current
Current-Sink DAC Bits
Current-Sink DAC LSB
BRT_LEDx[4:0] = 0b00000
BRT_LEDx[4:0] = 0b11111
0.1
3.2
5
mA
mA
bits
mA
0.1
3.20
T
T
= +25ºC
3.10
3.03
3.25
3.36
A
BRT_LEDx[4:0] =
0b11111
Current-Sink Accuracy
mA
mV
= -40ºC to
A
3.20
35
+85ºC
BRT_LEDx[4:0] = 0b11111, I
2.9mA
=
LEDx
Dropout Voltage
V
DO
70
6.4mA CURRENT-SINK RANGE (LED_FSx[1:0] = 0b10, VLEDx = 0.2V)
Minimum Sink Current
Maximum Sink Current
Current-Sink DAC Bits
Current-Sink DAC LSB
BRT_LEDx[4:0] = 0b00000
BRT_LEDx[4:0] = 0b11111
0.2
6.4
5
mA
mA
bits
mA
0.2
www.maximintegrated.com
Maxim Integrated | 13
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Electrical Characteristics—Current Sinks (continued)
(V
= V
= 3.7V, V = 1.8V, limits are 100% production tested at T = +25°C, Min/Max limits over the operating temperature
IN_SBB IO A
SYS
range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
T
= +25ºC
6.30
6.40
6.50
A
A
BRT_LEDx[4:0] =
0b11111
Current-Sink Accuracy
mA
T
= -40ºC to
6.06
6.40
35
6.72
70
+85ºC
LED_FSx[1:0] = 0b11, BRT_LEDx[4:0] =
0b11111, I = 5.75mA
Dropout Voltage
V
DO
mV
LEDx
12.8mA CURRENT-SINK RANGE (LED_FSx[1:0] = 0b11, VLEDx = 0.2V)
Minimum Sink Current
Maximum Sink Current
Current-Sink DAC Bits
Current-Sink DAC LSB
BRT_LEDx[4:0] = 0b00000
BRT_LEDx[4:0] = 0b11111
0.4
12.8
5
mA
mA
bits
mA
0.4
12.8
T
T
= +25ºC
12.6
13.0
A
BRT_LEDx[4:0] =
0b11111
Current-Sink Accuracy
mA
mV
= -40ºC to
A
12.16
12.80
35
13.44
+85ºC
BRT_LEDx[4:0] = 0b11111, I
11.5mA
=
LEDx
Dropout Voltage
V
DO
70
TIMING CHARACTERISTICS
Root Clock Frequency
25.6
32.0
38.4
Hz
TIMING CHARACTERISTICS / BLINK PERIOD SETTINGS
0.5
16
s
Minimum Blink Period
Maximum Blink Period
Blink Period LSB
P_LEDx[3:0] = 0b0000
clocks
s
8
P_LEDx[3:0] = 0b1111
256
0.5
16
clocks
s
clocks
TIMING CHARACTERISTICS / BLINK DUTY CYCLE
Minimum Blink Duty
Cycle
D_LEDx[3:0] = 0b0000
D_LEDx[3:0] = 0b1111
6.25
%
Maximum Blink Duty
Cycle
100
%
%
Blink Duty Cycle LSB
6.25
2
Electrical Characteristics—I C Serial Interface
(V
= V
= 3.7V, V = 1.8V, limits are 100% production tested at T = +25°C, Min/Max limits over the operating temperature
IN_SBB IO A
SYS
range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
V
IO
Voltage Range
V
1.7
1.8
3.6
V
IO
www.maximintegrated.com
Maxim Integrated | 14
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
2
Electrical Characteristics—I C Serial Interface (continued)
(V
= V
= 3.7V, V = 1.8V, limits are 100% production tested at T = +25°C, Min/Max limits over the operating temperature
IN_SBB IO A
SYS
range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
-1
TYP
0
MAX
+1
UNITS
V
V
= 3.6V, V
= 1.7V, V
= V
= V
= 0V or 3.6V
= 0V or 1.7V
IO
SDA
SDA
SCL
SCL
V
IO
Bias Current
μA
-1
0
+1
IO
SDA AND SCL I/O STAGE
SCL, SDA Input High
Voltage
V
V
V
= 1.7V to 3.6V
= 1.7V to 3.6V
0.7 x V
IO
V
V
IH
IO
SCL, SDA Input Low
Voltage
V
0.3 x V
IL
IO
IO
SCL, SDA Input
Hysteresis
0.05 x
V
HYS
V
V
IO
SCL, SDA Input
Leakage Current
I
V
= 3.6V, V
= V
= 0V and 3.6V
-10
+10
0.4
μA
V
I
IO
SCL
SDA
SDA Output Low
Voltage
V
OL
Sinking 20mA
SCL, SDA Pin
Capacitance
C
10
pF
ns
I
Output Fall Time from
t
120
OF
V
IH
to V (Note 1)
IL
2
I C-COMPATIBLE INTERFACE TIMING (STANDARD, FAST, AND FAST-MODE PLUS) (Note 8)
Clock Frequency
f
0
1000
kHz
μs
SCL
Hold Time (REPEATED)
START Condition
t
0.26
HD_STA
SCL Low Period
SCL High Period
t
0.5
μs
μs
LOW
t
0.26
HIGH
Setup Time REPEATED
START Condition
t
0.26
μs
SU_STA
HD_DAT
Data Hold Time
Data Setup Time
t
0
μs
ns
t
50
SU_DAT
Setup Time for STOP
Condition
t
0.26
0.5
μs
μs
ns
SU_STO
Bus Free Time between
STOP and START
Condition
t
BUF
Pulse Width of
Suppressed Spikes
Maximum pulse width of spikes that must
be suppressed by the input filter
t
50
SP
2
I C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, CB = 100pF) (Note 8)
Clock Frequency
f
3.4
MHz
ns
SCL
Setup Time REPEATED
START Condition
t
160
SU_STA
Hold Time (REPEATED)
START Condition
t
160
160
ns
ns
HD_STA
SCL Low Period
t
LOW
www.maximintegrated.com
Maxim Integrated | 15
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
2
Electrical Characteristics—I C Serial Interface (continued)
(V
= V
= 3.7V, V = 1.8V, limits are 100% production tested at T = +25°C, Min/Max limits over the operating temperature
IN_SBB IO A
SYS
range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SCL High Period
Data Setup Time
Data Hold Time
SCL Rise Time
SYMBOL
CONDITIONS
MIN
60
10
0
TYP
MAX
UNITS
ns
t
HIGH
t
ns
SU_DAT
HD_DAT
t
70
40
ns
t
T
T
= +25°C
= +25°C
10
ns
rCL
A
Rise Time of SCL Signal
after REPEATED
START Condition and
after Acknowledge Bit
t
10
80
ns
rCL1
A
SCL Fall Time
SDA Rise Time
SDA Fall Time
t
T
A
T
A
T
A
= +25°C
= +25°C
= +25°C
10
10
10
40
80
80
ns
ns
ns
fCL
t
rDA
t
fDA
Setup Time for STOP
Condition
t
160
ns
pF
ns
SU_STO
Bus Capacitance
C
100
1.7
B
Pulse Width of
Suppressed Spikes
Maximum pulse width of spikes that must
be suppressed by the input filter
t
10
SP
2
I C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, CB = 400pF) (Note 8)
Clock Frequency
f
MHz
ns
SCL
Setup Time REPEATED
START Condition
t
160
160
SU_STA
Hold Time (REPEATED)
START Condition
t
ns
HD_STA
SCL Low Period
SCL High Period
Data Setup Time
Data Hold Time
SCL Rise Time
t
320
120
10
0
ns
ns
ns
ns
ns
LOW
t
HIGH
t
SU_DAT
HD_DAT
t
150
80
t
T
T
= +25°C
= +25°C
20
RCL
A
Rise Time of SCL Signal
after REPEATED
START Condition and
after Acknowledge Bit
t
20
80
ns
RCL1
A
SCL Fall Time
SDA Rise Time
SDA Fall Time
t
T
A
T
A
T
A
= +25°C
= +25°C
= +25°C
20
20
20
80
ns
ns
ns
FCL
t
160
160
RDA
t
FDA
Setup Time for STOP
Condition
t
160
ns
pF
ns
SU_STO
Bus Capacitance
C
400
B
Pulse Width of
Suppressed Spikes
Maximum pulse width of spikes that must
be suppressed by the input filter
t
10
SP
Note 8: Design guidance only. Not production tested.
www.maximintegrated.com
Maxim Integrated | 16
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Typical Operating Characteristics
(Typical Applications Circuit, V
= V
= 3.7V, V = 1.8V, T = +25°C, unless otherwise noted.)
IN_SBB IO A
SYS
www.maximintegrated.com
Maxim Integrated | 17
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Typical Operating Characteristics (continued)
(Typical Applications Circuit, V
= V
= 3.7V, V = 1.8V, T = +25°C, unless otherwise noted.)
IN_SBB IO A
SYS
(Inductor = Toko DFE201210S-2R2M, 2.2μH, 127mΩ, ISAT = 1.5A, 2.0x1.2x1.0mm)
www.maximintegrated.com
Maxim Integrated | 18
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Typical Operating Characteristics (continued)
(Typical Applications Circuit, V
= V
= 3.7V, V = 1.8V, T = +25°C, unless otherwise noted.)
IN_SBB IO A
SYS
(Inductor = Toko DFE201210S-2R2M, 2.2μH, 127mΩ, ISAT = 1.5A, 2.0x1.2x1.0mm)
www.maximintegrated.com
Maxim Integrated | 19
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Typical Operating Characteristics (continued)
(Typical Applications Circuit, V
= V
= 3.7V, V = 1.8V, T = +25°C, unless otherwise noted.)
IN_SBB IO A
SYS
(Inductor = Toko DFE201210S-2R2M, 2.2μH, 127mΩ, ISAT = 1.5A, 2.0x1.2x1.0mm)
www.maximintegrated.com
Maxim Integrated | 20
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Typical Operating Characteristics (continued)
(Typical Applications Circuit, V
= V
= 3.7V, V = 1.8V, T = +25°C, unless otherwise noted.)
IN_SBB IO A
SYS
(Inductor = Toko DFE201210S-2R2M, 2.2μH, 127mΩ, ISAT = 1.5A, 2.0x1.2x1.0mm)
www.maximintegrated.com
Maxim Integrated | 21
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Typical Operating Characteristics (continued)
(Typical Applications Circuit, V
= V
= 3.7V, V = 1.8V, T = +25°C, unless otherwise noted.)
IN_SBB IO A
SYS
www.maximintegrated.com
Maxim Integrated | 22
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Typical Operating Characteristics (continued)
(Typical Applications Circuit, V
= V
= 3.7V, V = 1.8V, T = +25°C, unless otherwise noted.)
IN_SBB IO A
SYS
www.maximintegrated.com
Maxim Integrated | 23
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Typical Operating Characteristics (continued)
(Typical Applications Circuit, V
= V
= 3.7V, V = 1.8V, T = +25°C, unless otherwise noted.)
IN_SBB IO A
SYS
www.maximintegrated.com
Maxim Integrated | 24
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Bump Configuration
MAX77640/MAX77641
TOP VIEW
(BUMP SIDE DOWN)
1
2
3
4
5
6
+
PWR_HLD nEN
SDA
LED2
LED1
LED0
A
B
GPIO
NC
nRST
nIRQ
GND
SYS
LGND
GND
NC
SCL
LDO
BST
LXB
IN_LDO
SBB0
V
IO
C
GND
GND
LXA
SBB1
D
SYS
IN_SBB PGND
SBB2
E
WLP
(2.75mm x 2.15mm x 0.7mm)
Bump Descriptions
PIN
NAME
FUNCTION
TYPE
TOP LEVEL
Active-High Power Hold Input. Assert PWR_HLD to keep the on/off controller in its on state.
PWR_HLD If PWR_HLD is not needed, connect it to SYS and use the SFT_RST bits to power the
device down.
digital
input
A1
Active-Low Enable Input. nEN supports push-button or slide-switch configurations. An
external pullup resistor (10kΩ to 100kΩ) to SYS is required.
digital
input
A2
A3
B4
B1
B2
nEN
2
SDA
SCL
I C Data
digital i/o
digital
input
2
I C Clock
GPIO
nRST
General Purpose Input/Output. The GPIO I/O stage is internally biased with V
.
digital i/o
IO
Active-Low, Open-Drain Reset Output. Connect a 100kΩ pullup resistor between nRST and
a voltage equal to or less than V
digital
output
.
SYS
Active-Low, Open-Drain Interrupt Output. Connect a 100kΩ pullup resistor between
nIRQ and a voltage equal to or less than V
digital
output
C2
nIRQ
SYS
GND
.
SYS
System Power Output. SYS provides power to the system resources as well as the control
logic of the device. Connect to IN_SBB and bypass to GND with a 22μF ceramic capacitor.
power
input
E2, E3
C3, D1,
D2, E1
Quiet Ground. Connect GND to PGND, LGND, and the low-impedance ground plane of the
PCB.
ground
www.maximintegrated.com
Maxim Integrated | 25
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Bump Descriptions (continued)
PIN
C4
NAME
FUNCTION
TYPE
power
input
2
V
I C Interface and GPIO Driver Power
IO
C1, D3
N.C.
No Connection. Leave this pin unconnected.
LDO
power
output
B5
B6
LDO
Linear Regulator Output. Connect to GND if unused.
Linear Regulator Input. Connect to GND if unused.
power
input
IN_LDO
RGB LED DRIVER
Current Sink Port 0. LED0 is typically connected to the cathode of an LED and is capable
of sinking up to 12.5mA. Connect to ground if unused.
A6
A5
A4
B3
LED0
power
power
power
ground
Current Sink Port 1. LED1 is typically connected to the cathode of an LED and is capable
of sinking up to 12.5mA. Connect to ground if unused.
LED1
LED2
LGND
Current Sink Port 2. LED2 is typically connected to the cathode of an LED and is capable
of sinking up to 12.5mA. Connect to ground if unused.
Current Sink Ground. Connect LGND to GND, PGND, and the low-impedance ground
plane of the PCB.
SIMO BUCK-BOOST
SIMO Power Input. Connect IN_SBB to SYS and bypass to PGND with a 22μF ceramic
capacitor as close as possible to the IN_SBB pin.
power
input
E4
C6
D6
E6
C5
IN_SBB
SBB0
SBB1
SBB2
BST
SIMO Buck-Boost Output 0. SBB0 is the power output for channel 0 of the SIMO buck-
boost. Bypass SBB0 to PGND with a 10μF ceramic capacitor.
power
output
SIMO Buck-Boost Output 1. SBB1 is the power output for channel 1 of the SIMO buck-
boost. Bypass SBB1 to PGND with a 10μF ceramic capacitor.
power
output
SIMO Buck-Boost Output 2. SBB2 is the power output for channel 2 of the SIMO buck-
boost. Bypass SBB2 to PGND with a 10μF ceramic capacitor.
power
output
SIMO Power Input for the High-Side Output NMOS Drivers. Connect a 3300pF ceramic
capacitor between BST and LXB.
power
input
Switching Node A. LXA is driven between PGND and IN_SBB when any SIMO channel is
enabled. LXA is driven to PGND when all SIMO channels are disabled. Connect a 1.5μH
inductor between LXA and LXB.
D4
LXA
power i/o
Switching Node B. LXB is driven between PGND and SBBx when SBBx is enabled. LXB is
driven to PGND when all SIMO channels are disabled. Connect a 1.5μH inductor between
LXA and LXB.
D5
E5
LXB
power i/o
ground
Power ground for the SIMO low-side FETs. Connect PGND to GND, LGND, and the low-
impedance ground plane of the PCB.
PGND
www.maximintegrated.com
Maxim Integrated | 26
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Detailed Description—Top Level
The MAX77640/MAX77641 provide highly-integrated power solutions for low-power applications where small size, low-
quiescent current, and efficiency are critical. These devices integrate a single-inductor, multiple-output (SIMO) buck-
boost regulator with three output channels. See Table 1. The three outputs of the SIMO regulator share capacity and are
typically capable of providing 300mA total to the system.
A 150mA LDO is available to post-regulate SIMO outputs for audio, sensors, or other noise-sensitive applications. The
LDO can also operate directly from SYS.
These devices also integrate 3-channel LED current sink drivers with individual pattern control, and a general-purpose
2
input/output (GPIO). A bidirectional I C serial interface allows for configuring and checking the status of the device.
An internal on/off controller interfaces to either a momentary push-button on-key or an on-key slider switch. The on/off
controller provides regulator power-up/down sequencing as well as other functions such as manual reset.
Table 1. Regulator Summary
V
IN
REGULATOR
NAME
REGULATOR
TOPOLOGY
MAXIMUM
(mA)
MAX77640 V
RANGE/
MAX77641 V
RANGE/
OUT
OUT
RANGE
(V)
I
RESOLUTION
RESOLUTION
OUT
SBB0
SBB1
SBB2
LDO
SIMO
SIMO
up to 300*
up to 300*
up to 300*
150
2.5 to 5.5
2.5 to 5.5
2.5 to 5.5
1.8 to 5.5
0.8 to 2.375V in 25mV steps
0.8 to 2.375V in 25mV steps
2.4 to 5.25V in 50mV steps
2.4 to 5.25V in 50mV steps
0.8 to 1.5875V in 12.5mV
steps
SIMO
0.8 to 3.95V in 50mV steps
1.35 to 2.9375V in 12.5mV
steps
1.35 to 2.9375V in 12.5mV
steps
PMOS LDO
*Shared capacity with other SBBx channels. See the SIMO Available Output Current section for more information.
Support Materials
The following support materials are available for these devices:
● AN6516: MAX77640/MAX77641 Programmer's Guide provides a description of all device registers and software
advice.
2
2
● AN6515: MAX77640/MAX77641 I C Implementer's Guide provides a detailed look at the I C serial interface and
standard read/write patterns.
● MAX77640/MAX77641 SIMO Calculator details the SIMO design procedure. See the SIMO Available Output
Current section of the data sheet for more information.
Visit the product page at www.maximintegrated.com/MAX77640 and/or contact Maxim for more information.
www.maximintegrated.com
Maxim Integrated | 27
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Top-Level Interconnect Simplified Diagram
Figure 1 shows simplified internal signal routing.
VREF
VIREF
SYS_RST
FPS
SBB0
SBB1
SBB2
MAX77640
MAX77641
SYS_RST
SIMO
CLK
VREF
VIREF
COMM
SYSUVLO
VREF
VIREF
SYS_RST
FPS
IN_LDO
LDO
MAIN BIAS AND
SYSOVLO
CLOCK
OTLO
POR
BOK
LDO
FPS
COMM
BIAS_EN
SYS
nEN
SBIA_LPM
LED0
LED1
CLK
VREF
VIREF
SYS_RST
COMM
100µs/30ms
DEBOUNCE
TIMER
DBEN_nEN
DBNEN
CURRENT
SINK
TOP-LEVEL
DIGITAL
CONTROL
tDBNC_nEN
LED1
nRST
V
IO
V
IO
RST
100µs
PWR_HLD
GLITCH FILTER
tPWR_HLD_GF
PWR_HLD2
nIRQ
V
IO
IRQ_TOP
10ns/30ms
DEBOUNCE
TIMER
DBEN_GPI
DI
tDBNC_nEN
GPIO
SDA
SCL
COMM
I2C
DO
Figure 1. Top-Level Interconnect Simplified Diagram
Voltage Monitors
SYS POR Comparator
The SYS POR comparator monitors V
and generates a power-on reset signal (POR). When V
is below V
,
POR
SYS
SYS
the device is held in reset (SYSRST = 1). When V
rises above V
, internal signals and on-chip memory
SYS
POR
stabilize and the device is released from reset (SYSRST = 0).
www.maximintegrated.com
Maxim Integrated | 28
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
SYS Undervoltage-Lockout Comparator
The SYS undervoltage lockout (UVLO) comparator monitors V
and generates a SYSUVLO signal when the V
SYS
SYS
falls below UVLO threshold. The SYSUVLO signal is provided to the top-level digital controller. See Figure 4 and Table
2 for additional information regarding the UVLO comparator:
● When the device is in the STANDBY state, the UVLO comparator is disabled.
● When transitioning out of the STANDBY state, the UVLO comparator is enabled allowing the device to check for
sufficient input voltage. If the device has sufficient input voltage, it can transition to the on-state; if there is insufficient
input voltage, the device transitions back to the STANDBY state.
SYS Overvoltage-Lockout Comparator
These devices are rated for 5.5V maximum operating voltage (V
) with an absolute maximum input voltage of 6.0V.
SYS
An overvoltage-lockout monitor increases the robustness of the device by inhibiting operation when the supply voltage is
greater than V . See Figure 4 and Table 2 for additional information regarding the OVLO comparator:
SYSOVLO
● When the device is in the STANDBY state, the OVLO comparator is disabled.
nEN Enable Input
nEN is an active-low internally debounced digital input that typically comes from the system’s on-key. The debounce time
is programmable with DBEN_nEN. The primary purpose of this input is to generate a wake-up signal for the PMIC that
turns on the SIMO and/or LDO. Maskable rising/falling interrupts are available for nEN (nEN_R and nEN_F) for alternate
functionality. nEN requires and external pullup resistor (10kΩ to 100kΩ) to SYS.
The nEN input can be configured to work either with a momentary push-button (nEN_MODE = 0) or a persistent slide-
switch (nEN_MODE = 1). See Figure 2 for more information. In both push-button mode and slide-switch mode, the on/
off controller looks for a falling edge on the nEN input to initiate a power-up sequence.
nEN Manual Reset
nEN works as a manual reset input when the on/off controller is in the on via on/off controller state. The manual reset
function is useful for forcing a power-down in case the communication with the processor fails. When nEN is configured
for a push-button mode and the input is asserted (nEN = low) for an extended period (t
), the on/off controller initiates
MRST
a power-down sequence and goes to standby mode. When nEN is configured for a slide-switch mode and the input is
deasserted (nEN = high) for an extended period (t
to standby mode.
), the on/off controller initiates a power-down sequence and goes
MRST
A dedicated internal oscillator is used to create the 30ms (t
) and 8s/16s (t
) timers for nEN. Whenever
MRST
DBNC_nEN
the device is actively counting either of these times, the supply current increases by the oscillator's supply current (65μA
when the battery voltage is at 3.7V). As soon as the event driving the timer goes away or is fulfilled, the oscillator
automatically turns off and its supply current goes away.
nEN Dual-Functionality: Push-Button vs. Slide-Switch
The nEN digital input can be configured to work with a push-button switch or a slide-switch. Figure 2 shows nEN's dual
functionality for power-on sequencing and manual reset. The default configuration of the device is push-button mode
(nEN_MODE = 0) and no additional programming is necessary. Applications that use a slide-switch on-key configuration
must set nEN_MODE = 1 within t
.
MRST
www.maximintegrated.com
Maxim Integrated | 29
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
STANDBY
POWER-ON SEQUENCE
ON
POWER-DOWN SEQUENCE
STATE
BATTERY
INSERTION
VSYS
SYS
t
DBNC_nEN
nEN
t
t
t
DBNC_nEN
DBNC_nEN
t
t
MRST
MRST
PUSH-BUTTON MODE
SYS
t
DBNC_nEN
nEN
DBNC_nEN
nEN
SLIDE-SWITCH MODE
NOT DRAWN TO SCALE
Figure 2. nEN Usage Timing Diagram
Interrupts (nIRQ)
nIRQ is an active-low, open-drain output that is typically routed to the host processor's interrupt input to signal an
important change in the device's status. Refer to the Programmer's Guide for a comprehensive list of all interrupt bits and
status registers.
A pullup resistor to a voltage less than or equal to V
interrupt bits in the register map.
is required for this node. nIRQ is the logical NOR of all unmasked
SYS
All interrupts are masked by default. Masked interrupt bits do not cause the nIRQ pin to change. Unmask the interrupt
bits to allow nIRQ to assert.
Reset Output (nRST)
nRST is an open-drain, active-low output that is typically used to hold the processor in a reset state when the device
is powered down. During a power-up sequence, the nRST deasserts after the last regulator in the power-up chain is
enabled (t
). During a power-down sequence, the nRST output asserts before any regulator is powered down
RSTODD
(t
). See Figure 5 for nRST timing.
RSTOAD
A pullup resistor to a voltage less than or equal to V
is required for this node.
SYS
Power Hold Input (PWR_HLD)
PWR_HLD is an active-high digital input. PWR_HLD has a 100μs glitch filter (t
). As shown in Figure 1, the
PWR_HLD_GF
output of this glitch filter is PWR_HLD2 that drives the top-level digital control. Figure 4 and its associated transition Table
2 shows how PWR_HLD is processed by the top-level digital control.
● After the power-up sequence, the system processor must assert PWR_HLD within the PWR_HLD wait time
(t
) to hold the power supply in the on-state. If the PWR_HLD input is not asserted within
PWR_HLD_WAIT
the t
period, a power-down sequence is initiated.
PWR_HLD_WAIT
● While in the on-state, the system processor must assert PWR_HLD as long as power is required. If the system
processor wants to turn off, it can either pull PWR_HLD low or it can write the SFT_RST bits to execute the software
cold reset (SFT_CRST) or software off (SFT_OFF) functions to execute the power-down sequence.
If the power hold function is not used, connect PWR_HLD to SYS and use the SFT_RST bits to power the device down.
www.maximintegrated.com
Maxim Integrated | 30
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
General-Purpose Input Output (GPIO)
A general-purpose input/output (GPIO) is provided to increase system flexibility. See Figure 3 for the GPIO block
diagram.
Clear DIR to configure GPIO as a general-purpose output (GPO). The GPO can either be in push-pull mode (DRV = 1)
or open-drain mode (DRV = 0).
● The push-pull output mode is ideal for applications that need fast (~2ns) edges and low-power consumption.
● The open-drain mode requires an external pullup resistor (typically 10kΩ to 100kΩ). Connect the external pullup
resistor to a bias voltage that is less than or equal to V
.
IO
• The open-drain mode can be used to communicate to different logic domains. For example, to send a signal from
the GPO on a 1.8V logic domain (V = 1.8V) to a device on a 1.2V logic domain, connect the external pullup
IO
resistor to 1.2V.
• The open-drain mode can be used to connect several open-drain (or open-collector) devices together on the same
bus to create wired logic (wired AND logic is positive-true; wired OR logic is negative-true).
● The general-purpose input (GPI) functions are still available while the pin is configured as a GPO. In other words, the
DI (input status) bit still functions properly and does not collide with the state of the DIR bit.
Set DIR to disable the output drivers associated with the GPO and have the device function as a GPI. The GPI features
a 30ms debounce timer (t
) that can be enabled or disabled with DBEN_GPI.
DBNC_GPI
● Enable the debounce timer (DBEN_GPI = 1) if the GPI is connected to a device that can bounce or chatter (like a
mechanical switch).
● If the GPI is connected to a circuit with clean logic transitions and no risk of bounce, disable the debounce timer
(DBEN_GPI = 0) to eliminate unnecessary logic delays. With no debounce timer, the GPI input logic propagates
to nIRQ in 10ns.
A dedicated internal oscillator is used to create the 30ms (t
) debounce timer. Whenever the device is actively
DBNC_GPI
counting this time, the supply current increases by the oscillator's supply current (65μA when the battery voltage is at
3.7V). As soon as the event driving the timer goes away or is fulfilled, the oscillator automatically turns off and its supply
current goes away.
Maskable rising and falling interrupts (GPI_R and GPI_F) are available to signal a change in the GPI's status.
● To interrupt on a rising edge only: unmask the rising edge interrupt and mask the falling edge interrupt (GPI_RM = 0,
GPI_FM = 1).
● To interrupt on a falling edge only: unmask the falling edge interrupt and mask the rising edge interrupt (GPI_RM = 1,
GPI_FM = 0).
● To interrupt on either rising or falling edge: unmask both rising and falling edge interrupts (GPI_RM = 0, GPI_FM = 0).
Refer to the Programmer's Guide for more details.
www.maximintegrated.com
Maxim Integrated | 31
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
SYS
MAX77640
DRV
MAX77641
DIR
DO
GPI_RM
GPI_FM
DBNC_EN
DI
V
IO
COMM
CNFG_GPIO
GPI_R
GPI_F
GPI_R
GPI_RM
Q
Q
D
R
1
1
DRV
nIRQ
DBNC_EN
READ
(GPI_R)
IRQ
GPIO
GND
0
1
30ms DEBOUNCE
DI
(t
)
DBNC_GPI
GPI_FM
GPI_F
D
R
DIR
DO
LOGIC
OTHER nIRQ ASSERTION
SOURCES NOT SHOWN
READ
(GPI_F)
Figure 3. GPIO Block Diagram
On/Off Controller
The on/off controller monitors multiple power-up (wakeup) and power-down (shutdown) conditions to enable or disable
the SIMO channels and LDO.
The basic function of the on/off controller is to control the power sequencer (see Figure 4 and Table 2). A typical use
case is described as follows:
1. Start in the no-power state.
2. Apply a battery to the system and transition through path 1 and 2 to the standby state.
3. Press the system's on-key (nEN = low) and transition through path 3A and 4 to the "PWR_HLD?" state.
4. The processor boots up and drives PWR_HLD high, which drives the transition through path 4C to the
on through the on/off controller state.
5. These devices perform its desired functions in the on through on/off controller state. When it is ready to turn off,
the processor drives PWR_HLD low that drives the transition through path 5B and 8 to the standby state.
2
The SIMO can be enabled through the I C interface for systems that do not require a hardware (on-key) input. Connect
nEN to SYS and follow this procedure:
1. Start in the no-power state.
2. Apply a battery to the system and transition through path 1 and 2 to the standby state.
2
3. Go to the on via software state by writing SBIA_EN = 1 through I C.
4. In the on via software state, the host controller can now enable/disable SIMO outputs through I C writes.
2
5. To return to standby state (shutdown), first disable all SIMO outputs then write SBIA_EN = 0.
www.maximintegrated.com
Maxim Integrated | 32
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
NO POWER
SYS<VPOR
ANY
STATE
STATE
0
V
ACTION
1
DECISION
POWER-ON
RESET (POR)
2
X
TRANSITION NAME.
SEE TABLE 2
2A
STANDBY
3
11
DISABLE MAIN BIAS
ENABLE MAIN BIAS
12
ENABLE MAIN BIAS
3A
6
6
8
2B
9
POWER-UP
SEQUENCE
(FIGURE 5)
POWER-DOWN
SEQUENCE
(FIGURE 5)
IMMEDIATE
SHUTDOWN
(FIGURE 5)
3
4
7
4B
ANY
STATE
PWR_HLD?
4C
4A
10
3
5A
ON VIA
SOFTWARE
ON VIA ON/OFF
CONTROLLER
5B
10
2B
Figure 4. Top-Level On/Off Controller
Table 2. On/Off Controller Transitions
TRANSITION/
STATE
CONDITION
System voltage is below the POR threshold (V < V ).
SYS
0
1
POR
System voltage is above the POR threshold (V
> V
).
POR
SYS
www.maximintegrated.com
Maxim Integrated | 33
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Table 2. On/Off Controller Transitions (continued)
TRANSITION/
CONDITION
STATE
2
Internal signals and on-chip memory stabilize and the device is released from reset.
2
The device is waiting for a wake-up signal or an I C command to enable the main bias circuits.
● This is the lowest current state of the device (I = 0.3μA typ).
Q
● Main bias circuits are off, POR comparator is on.
STANDBY
2
● I C is on when V is valid.
IO
● Peripheral functions do not operate in this state because the main bias circuits are off. To utilize a function,
enter the on through software or on through on/off controller states.
2
2A
2B
Main bias circuits enabled through I C (SBIA_EN = 1).
2
Main bias circuits disabled through I C (SBIA_EN = 0).
ON VIA
SOFTWARE
The main bias circuits are enabled through software and all peripheral functions can be manually enabled or
disabled through I C.
2
A wake-up signal has been received.
● A debounced on-key (nEN) falling edge has been detected (DBNEN = 1)
or
3
● Internal wake-up flag has been set due to SFT_RST = 0b01 (WKUP = 1)
Main bias circuits are OK (BOK = 1)
3A
4
Power-up sequence complete.
4A
4B
4C
PWR_HLD wait time has expired and PWR_HLD2 is low (t > t
&& PWR_HLD2 = 0).
PWR_HLD_WAIT
PWR_HLD wait time has not expired and PWR_HLD2 is low (t < t
PWR_HLD2 = 1
&& PWR_HLD2 = 0).
PWR_HLD_WAIT
On state.
ON VIA ON/OFF
CONTROLLER
● All flexible power sequencers (FPS) are on.
● The main bias circuits are enabled.
● I = 5.6μA (typ) with all regulators enabled (no load) and the main bias circuits in low-power mode.
Q
5A
5B
PWR_HLD2 = 1
PWR_HLD2 = 0 OR
System overtemperature lockout (T >T
) or
OTLO
J
Software cold reset (SFT_RST[1:0] = 0b01) or
Software power off (SFT_RST[1:0] = 0b10) or
Manual reset occurred. See the nEN Manual Reset section for more information.
System overtemperature lockout (T >T
) or
OTLO
J
6
7
System undervoltage lockout (V
< V
+ V
) or
) or
SYSUVLO_HYS
SYS
SYSUVLO
System overvoltage lockout (V
> V
)
SYS
SYSOVLO
System undervoltage lockout (V
System overvoltage lockout (V
< V
SYSUVLO
SYS
> V
)
SYS
SYSOVLO
Note: The overvoltage-lockout transition does not apply to the ON VIA SOFTWARE state.
Finished with the power-down sequence.
8
9
Finished with immediate shutdown.
10
11
12
System overtemperature lockout (T > T
J
).
OTLO
Done disabling main bias.
Done enabling main bias.
www.maximintegrated.com
Maxim Integrated | 34
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
POWER-UP SEQUENCE
POWER-DOWN SEQUENCE
START
FROM TOP LEVEL #3A
START FROM TOP LEVEL
#4A, #5B OR #5C
CLEAR WAKEUP
FLAG (WKUP = 0)
CLEAR WAKEUP FLAGS
FPS ENABLE PULSE 0
TEMPERATURE IS
NOT OKAY
(T >T
J
)
OTLO
OTLO?
TEMPERATURE IS OKAY
(T <T
WAIT t
EN
)
OTLO
J
WAIT 60ms
FPS ENABLE PULSE 1
SFT_RST = 0b00
OR PWR_HLD2 = 1
WAIT t
EN
SFT_RST = 0b01
FPS ENABLE PULSE 2
SFT_RST = 0b10
OR PWR_HLD2 = 0
SET WAKEUP
FLAG (WKUP = 1)
WAIT t
EN
FPS ENABLE PULSE 3
SET THE APPROPRIATE BIT IN THE EVENT
RECORDER REGISTER (ERCFLAG) TO INDICATE
THE SOURCE OF THE POWER-DOWN EVENT.
WAIT t
RSTODD
ASSERT nRST
DE-ASSERT nRST
WAIT t
RSTOAD
END
TO TOP LEVEL #4
FPS DISABLE PULSE 3
WAIT t
DIS
IMMEDIATE SHUTDOWN
FPS DISABLE PULSE 2
START
FROM TOP LEVEL #7
WAIT t
DIS
SET THE APPROPRIATE BIT IN THE EVENT
RECORDER REGISTER (ERCFLAG) TO INDICATE
THE SOURCE OF THE POWER-DOWN EVENT.
FPS DISABLE PULSE 1
WAIT t
DIS
ASSERT nRST
DISABLE FPS3, FPS2, FPS1, FPS0
FPS DISABLE PULSE 0
WAIT 125ms
WAIT 125ms
RESET DEVICE
RESET DEVICE
(PULSE SYSRST FOR 5µs)
(PULSE SYSRST FOR 5µs)
END
END
RETURN BACK TO
THE ON STATE
TO TOP LEVEL #9
TO TOP LEVEL #8
Figure 5. Power-Up/Power-Down Sequence
www.maximintegrated.com
Maxim Integrated | 35
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Flexible Power Sequencer (FPS)
The FPS allows SIMO channels to power up under hardware or software control. Additionally, each channel can power
up independently or together with adjustable power-up and power-down delays (sequencing). Figure 6 shows four
resources powering up under FPS control.
The FPS consists of 1 master sequencing timer and 4 slave resources (SBB0, SBB1, SBB2, and LDO). When the FPS is
enabled, a master timer generates four sequencing events for device power-up and power-down.
NOT DRAWN TO SCALE
ENFPS
t
t
SAME FOR ALL FPS DISABLE PULSES
DIS
DIS
t
SAME FOR ALL FPS ENABLE PULSES
EN
= 2x t
EN
0
1
2
3
3
2
1
0
PLSFPS
FPS RESOURCES
SBB0
LDO
SBB1
SBB2
Figure 6. Flexible Power Sequencer Basic Timing Diagram
www.maximintegrated.com
Maxim Integrated | 36
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
NOT DRAWN TO SCALE
ENABLE MAIN BIAS
PWR_HLD?
DISABLE MAIN BIAS
STANDBY
NO
ON VIA ON/OFF
CONTROLLER
STATE
POR
STANDBY
POWER-UP SEQUENCE
POWER-DOWN SEQUENCE
POWER
V
SYS
V
~1.9V
POR
t
~100µs
POR
nRST_INT
(INTERNAL)
t
~5µs
RESET
t
DBNC_nEN
nEN
t
SBIA_EN~500µs
BIAS EN
(INTERNAL)
FPS0
FPS1
FPS2
FPS3
t
t
t
t
t
t
DIS
EN
EN
EN
DIS
DIS
REGULATORS
tRSTOAD
tWAIT~125ms
t
PWR_HLD_WAIT
t
RSTODD
nRST
t
BOOT
SYSTEM
SOFTWARE
t
WAIT~60ms
t
PWR_HLD_HIGH
PWR_HLD
Figure 7. Startup Timing Diagram Due to nEN
www.maximintegrated.com
Maxim Integrated | 37
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Debounced Inputs (nEN and GPI)
nEN is debounced on both rising and falling edges to reject undesired transitions. The input must be at a stable logic
level for the entire debounce period for the output to change its logic state. Figure 8 shows an example timing diagram
for the nEN debounce.
NOT DRAWN TO SCALE
BOUNCING IS
REJECTED
STABLE SIGNAL IS
ACCEPTED
BOUNCING IS
REJECTED
STABLE SIGNAL IS
ACCEPTED
nEN
t
= 10ns
t
= 10ns
DBUF
DBUF
EN
(INTERNAL)
DBEN
t
t
DBNCEN
DBNCEN
(INTERNAL)
Figure 8. Debounced Inputs Timing Diagram
Thermal Alarms and Protection
These devices have thermal alarms to monitor if the junction temperature rises above 80°C (T
) and 100ºC (T
).
JAL2
JAL1
Over-temperature lockout (OTLO) is entered if the junction temperature exceeds T
(approximately 165ºC typ).
OTLO
OTLO causes transition 10 in Figure 4 which causes the SIMO to immediately shutdown from the on via on/off controller
state. Resources do not enable until the temperature falls below T by approximately 15ºC.
OTLO
The TJAL1_S and TJAL2_S status bits continuously indicate the junction temperature alarm status. Maskable interrupts
are available to singal a change in either of these bits. Refer to the Programmer's Guide for details.
Register Map
The register map and register reset conditions are detailed in the Programmer's Guide.
www.maximintegrated.com
Maxim Integrated | 38
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Detailed Description—SIMO Buck-Boost
These devices have a micropower single-inductor, multiple-output (SIMO) buck-boost DC-to-DC converter designed for
applications that emphasize low supply current and small solution size (Figure 9). A single inductor is used to regulate
three separate outputs, saving board space while delivering better total system efficiency than equivalent power solutions
using one buck and linear regulators.
The SIMO configuration utilizes the entire battery voltage range due to its ability to create output voltages that are above,
below, or equal to the input voltage. Peak inductor current for each output is programmable to optimize the balance
between efficiency, output ripple, EMI, PCB design, and load capability.
SYS
3300pF
(0603/0201)
1.5µH
22µF
(1005/0402)
PGND
LXA
LXB
BST
IN_SBB
IN_SBB
SBB0
SYNCHRONOUS RECTIFIER
MAIN POWER STAGE
M1
REVERSE
BLOCKING
BST
10µF
(1005/0402)
DRV_SBB
M3_0
DIS_SBB1
IZX
ERROR COMPARATOR
ACTIVE-DISCHARGE
ILIM
DRV_SBB
M2
M4
REG0
CHG
DIS
R
AD_SSB0
AD_SBB0
(140Ω)
SBB1
SBB2
I
I
LIM
SYNCHRONOUS
RECTIFIER (M3_1)
AND
ERROR COMPARATOR
AND
CHG
DIS
DIS_SBB[2:0]
BST
DRV_SBB
DIS_SBB1
10µF
(1005/0402)
ZX
SIMO
CONTROLLER
REG[2:0]
REG1
AD_SBB1
ACTIVE-DISCHARGE
DIGITAL AND
REGISTERS
CNFG_SBB_TOP,
CNFG_SBBX_A,
CNFG_SBBX_B
SYNCHRONOUS
RECTIFIER (M3_2)
AND
ERROR COMPARATOR
AND
DRV_SBB
AD_SBB[2:0]
BST
DRV_SBB
DIS_SBB2
10µF
(1005/0402)
REG2
AD_SBB2
ACTIVE-DISCHARGE
COMPONENT SIZES ARE LISTED IN METRIC/IMPERIAL FOR CONVENIENCE. FOR EXAMPLE, 1005/0402 IS 1.0X0.5mm OR 0.04X0.02 INCHES.
Figure 9. SIMO Detailed Block Diagram
www.maximintegrated.com
Maxim Integrated | 39
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
SIMO Features and Benefits
● 3 Output Channels
● Ideal for Low-Power Designs
• Delivers > 300mA at 1.8V from a 3.7V Input
• ±3% Accurate Output Voltage
● Small Solution Size
• Multiple Outputs from a Single 1.5μH Inductor
• Small 10μF (0402) Output Capacitors
● Flexible and Easy to Use
• Single Mode of Operation
• Glitchless Transitions Between Buck, Buck-Boost, and Boost Scenarios
• Programmable Peak Inductor Current
• Programmable On-Chip Active Discharge
● Long Battery Life
• High-Efficiency, > 87% at 3.3V Output
• Better Total System Efficient than Buck + LDOs
• Low Quiescent Current, 1μA per Output
• Low Input Operating Voltage, 2.7V (min)
SIMO Control Scheme
The SIMO buck-boost is designed to service multiple outputs simultaneously. A proprietary controller ensures that all
outputs get serviced in a timely manner, even while multiple outputs are contending for the energy stored in the inductor.
When no regulator needs service, the state machine rests in a low-power rest state.
When the controller determines that a regulator requires service, it charges the inductor (M1 + M4) until the peak current
limit is reached (I
= IP_SBB). See Figure 9. The inductor energy then discharges (M2 + M3_x) into the output until
LIM
the current reaches zero (I ). In the event that multiple output channels need servicing at the same time, the controller
ZX
ensures that no output utilizes all of the switching cycles. Instead, cycles interleave between all the outputs that are
demanding service, while outputs that do not need service are skipped.
SIMO Soft-Start
The soft-start feature of the SIMO limits inrush current during startup. The soft-start feature is achieved by limiting the
slew rate of the output voltage during startup (dV/dt ).
SS
More output capacitance results in higher input current surges during startup. The following set of equations and example
describes the input current surge phenomenon during startup.
The current into the output capacitor (I
) during soft-start is:
CSBB
dV
I
= C
Equation 1
CSBB
SBB
dt
(
)
SS
where C
is the capacitance on the output of the regulator, and dV/dtSS is the voltage change rate of the output.
SBB
The input current (I ) during soft-start is:
IN
V
SBBx
I
+ I
(
)
CSBB LOAD
V
IN
I
=
Equation 2
IN
ξ
(
)
www.maximintegrated.com
Maxim Integrated | 40
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
where I
is from the calculation above, I
is current consumed from the external load, V
is the output
SBBx
CSBB
LOAD
voltage, V is the input voltage, and ξ is the efficiency of the regulator.
IN
For example, given the following conditions, the peak input current (I ) during soft-start is ~71mA:
IN
Given:
● V is 3.5V
IN
● V
● C
is 3.3V
= 10µF
SBB2
SBB2
● dV/dt = 5mV/µs
SS
● R
= 330Ω (I
= 3.3V/330Ω = 10mA)
LOAD2
LOAD2
● ξ is 85%
Calculation:
● I
● I
= 10µF x 5mV/µs (from Equation 1)
CSBB
CSBB
(
= 50mA
3.3V
3.5V
50mA + 10mA
)
● I
=
(from Equation 2)
IN
0.85
● I = 71mA
IN
SIMO Output Voltage Configuration
Each SIMO buck-boost channel has a dedicated register to program its target output voltage (TV_SBBx) and its
peak current limit (IP_SBBx). Additional controls are available for enabling/disabling the active discharge resistors
(ADE_SBBx), as well as enabling/disabling the SIMO buck-boost channels (EN_SBBx). For a full description of bits,
registers, default values, and reset conditions, refer to the Programmer's Guide.
SIMO Active Discharge Resistance
Each SIMO buck-boost channel has an active-discharge resistor (R
) that is automatically enabled/disabled
AD_SBBx
based on a ADE_SBBx and the status of the SIMO regulator. The active discharge feature may be enabled
(ADE_SBBx = 1) or disabled (ADE_SBBx = 0) independently for each SIMO channel. Enabling the active discharge
feature helps ensure a complete and timely power down of all system peripherals. If the active-discharge resistor is
enabled by default, then the active-discharge resistor is on whenever V
is below V
and above V
.
POR
SYS
SYSUVLO
These resistors discharge the output when ADE_SBBx = 1, and their respective SIMO channel is off. Note if the
regulator is forced on through EN_SBBx = 0b110 or 0b111, then the resistors do not discharge the output even if
the regulator is disabled by the main-bias.
Note that when V
is less than 1.0V, the NMOS transistors that control the active-discharge resistors lose their
SYS
gate drive and become open.
When the active-discharge resistor is engaged, limit its power dissipation to an average of 10mW. For example,
consider the case where the active-discharge resistance is discharging the output capacitor each time the regulator
turns off; the 10mW limit allows discharge of 80μF of capacitance charged to 5V every 100ms (P = 1/2xCxV^2/t =
1/2x80μFx5V^2/100ms = 10mW).
www.maximintegrated.com
Maxim Integrated | 41
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Applications Information
SIMO Available Output Current
The available output current on a given SIMO channel is a function of the input voltage, output voltage, the peak current
limit setting, and the output current of the other SIMO channels. Maxim offers a SIMO calculator that outlines the available
capacity for specific conditions. Table 3 is an extraction from the calculator.
Table 3. SIMO Available Output Current for Common Applications
PARAMETERS
EXAMPLE 1
2.7V
EXAMPLE 2
3.2V
EXAMPLE 3
3.4V
V.IN.MIN
R.L.DCR
SBB1
0.1Ω
0.1Ω
0.12Ω
1V at 100mA
1.2V at 75mA
1.8V at 50mA
1A
1.2V at 50mA
2.05V at 100mA
3.3V at 30mA
0.866A
1.2V at 20mA
2.05V at 80mA
3.3V at 10mA
0.5A
SBB0
SBB2
I.PEAK.0
I.PEAK.1
I.PEAK.2
1A
0.707A
0.5A
1A
1A
0.5A
Utilized Capacity
73%
79%
73%
*R.C.IN = R.C.OUT = 5mΩ, L = 1.5μH
Inductor Selection
Choose an inductance from 1.0μH to 2.2μH (1.5μH inductors is recommended for most designs). Larger inductances
transfer more energy to the output for each cycle and typically result in larger output voltage ripple and better
efficiency. See the Output Capacitor Selection section for more information on how to size the output capacitor in order
to control ripple.
Choose the inductor saturation current to be greater than or equal to the maximum peak current limit setting that is used
for all of the SIMO buck-boost channels (I
). For example, if SBB0 is set for 0.5A, SBB1 is set for 0.866A, and SBB2
P_SBB
is set for 1.0A, then choose the saturation current to be greater than or equal to 1.0A.
Choose the RMS current rating of the inductor (typically the current at which the temperature rises appreciably) based
on the expected load currents for the system.
Carefully consider the DC-resistance (DCR), AC-resistance (ACR) and physical size of the inductor. Smaller size
inductors tend to have higher DCR and ACR which reduces SIMO efficiency. Inductors with low ACR in the 1MHz to
2MHz range are recommended for best efficiency.
See Table 4 for examples of inductors that work well with this device. This table was created in 2016. Inductor technology
advances rapidly. Always consider the most current inductor technology for new designs to achieve the best possible
performance.
www.maximintegrated.com
Maxim Integrated | 42
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Table 4. Example Inductors
MANUFACTURER
Samsung
Murata
PART
L (μH)
2.2
I
(A)
I
(A)
DCR (Ω)
0.073
0.117
0.076
0.127
0.086
0.095
0.110
0.170
X (mm)
2.0
Y (mm)
1.6
Z (mm)
1.0
SAT
2.9
RMS
CIGT201610EH2R2MN
DFE201610E-2R2M
DFE201610E-1R5M
DFE201210S-2R2M
DFE201210S-1R5M
CIGT201208EH2R2MN
DFE201208S-1R5M
DFE201208S-2R2M
2.7
2.2
2.6
2.4
2.3
2.2
2.0
2.4
2.0
1.9
3.2
2.0
1.6
1.0
Murata
1.5
2.0
1.6
1.0
Murata
2.2
1.80
2.6
1.8
2.0
1.6
2.0
1.2
1.0
Murata
1.5
2.0
1.2
1.0
Samsung
Murata
2.2
2.0
1.25
1.2
0.8
1.5
2.0
0.8
Murata
2.2
2.0
1.2
0.8
Input Capacitor Selection
Bypass IN_SBB to GND with a minimum 10µF ceramic capacitor (CIN_SBB). Larger values of CIN_SBB improve the
decoupling for the SIMO regulator. CIN_SBB reduces the current peaks drawn from the battery and reduces switching
noise in the system. The ESR/ESL of the input capacitor should be very low (i.e., ≤ 5mΩ and ≤ 500pH) for frequencies
up to 2MHz. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR,
and small temperature coefficients. A 6.3V capacitor voltage rating is recommended for the input voltage range of up to
5.5V.
Boost Capacitor Selection
Choose the boost capacitance (C
) to be 3.3nF. Smaller values of C
(<1nF) result in insufficient gate drive for M3.
BST
BST
Larger values of C
(>10nF) have the potential to degrade the startup performance. Ceramic capacitors with 0201 or
BST
0402 case size are recommended.
Output Capacitor Selection
Choose each output bypass capacitor (C
) based on the desired output voltage ripple (typically 10μF). Larger
SBBx
values of C
improve output voltage ripple but increase input surge current during soft-start and output voltage
SBBx
change. The output voltage ripple is a function of the inductor, output voltage, and peak current limit setting.
Maxim offers a calculator to aid output capacitance selection. Do not exceed the maximum output capacitance as
calculated by the SIMO calculator.
The impedance of the output capacitor (ESR, ESL) should be very low (i.e., ≤ 5mΩ & ≤ 500pH) for frequencies up
to 2MHz. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR,
and small temperature coefficients. Generally, small case size capacitors derate heavily compared to larger case
sizes (0603 case size performs better than 0402). Consider the effective capacitance value carefully by consulting
the manufacturer's data sheet.
SIMO Switching Frequency
The SIMO buck-boost regulator utilizes a pulse frequency modulation (PFM) control scheme. The switching frequency for
each output is a function of the input voltage, output voltage, load current, and inductance. For example, switching
frequency increases when load is increased and decreases when inductor value is increased. Maxim offers a SIMO
Calculator to help calculate the switching frequency. See Figure 10 for examples of trends based on these parameters.
www.maximintegrated.com
Maxim Integrated | 43
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
SIMO SWITCHING WAVEFORM
TYPICAL CASE - 115kHz
toc34
IP_SBB0 = 500mA,VSBB0 = 1.2V,
L = 1.5µH, VSYS = 3.6V, IL = 20mA
VSBB0
20mV/div
10μs/div
INCREASE LOAD
INCREASE INDUCTOR VALUE
INCREASE V
SYS
SIMO SWITCHING WAVEFORMS
INCREASED INDUCTANCE - 78.7kHz
SIMO SWITCHING WAVEFORMS
INCREASED INPUT VOLTAGE - 102kHz
SIMO SWITCHING WAVEFORMS
INCREASED LOAD CURRENT - 230 kHz
toc34
toc34
toc34
IP_SBB0 = 500mA,VSBB0 = 1.2V,
L = 2.2µH, VSYS = 3.6V, IL = 20mA
IP_SBB0 = 500mA,VSBB0 = 1.2V,
L = 1.5µH, VSYS = 5.5V, IL = 20mA
IP_SBB0 = 500mA,VSBB0 = 1.2V,
L = 1.5µH, VSYS = 3.6V, IL = 40mA
VSBB0
20mV/div
VSBB0
VSBB0
20mV/div
20mV/div
10μs/div
10μs/div
10μs/div
Figure 10. SIMO Switching Frequency Measurements
Unused SIMO Outputs
Do not leave unused outputs unconnected. If an output is unconnected and enabled, inductor current discharges
into that unconnected pin (~50nF parasitic capacitance only), and the output voltage soars above the absolute
maximum rating, potentially causing damage to the device. If the unused output is always disabled (EN_SBBx =
0x4 or 0x5), connect that output to ground. If an unused output can be enabled at any point during operation (such
as startup or accidental software access), then implement one of the following:
1. Bypass the unused output with a 1μF ceramic capacitor to ground.
2. Connect the unused output to the power input (IN_SBB). This connection is beneficial because it does
not require an external component for the unused output. The power input and its capacitance receives
the energy packets when the regulator is enabled and V
is below the target output voltage of the
IN_SBB
unused output. Circulating the energy back to the power input ensures that the unused output voltage
does not fly high.
● Note that some OTP options of the device have the active-discharge resistors enabled by default
(ADE_SBBx) such that connecting an unused output SBBx to IN_SBB creates a 140Ω (R
) to
AD_SBBx
ground until software can be ran to disable the active-discharge resistor. Connecting an unused SBBx
to IN_SBB is not recommended if the regulator's active-discharge resistor is enabled by default.
www.maximintegrated.com
Maxim Integrated | 44
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
3. Connect the unused output to another power output that is above the target voltage of the unused
output. In the same way as the option listed above, this connection is beneficial because it does not
require an external component for the unused output. Unlike the option above, this connection is preferred
in cases where the unused output voltage bias level is always above the unused output voltage target
because no energy packages are provided to the unused output.
● Note that some OTP options of the device have the active-discharge resistors enabled by default
(ADE_SBBx). If the other power output used to bias the unused output is normally off, then the active-
discharge resistor of the unused output does not create a continuous current draw. Once the system
is enabled, it should turn off the unused output's active-discharge resistor (ADE_SBBx = 0).
PCB Layout
Use the MAX77640/MAX77641 evaluation kit as a PCB layout reference. Good printed circuit board (PCB) layout is
necessary to achieve optimal performance. The evaluation kit (EVKIT) provides an example layout that optimizes its
performance. PCB layouts must:
1. Minimize parasitic inductance in the SIMO input capacitor loop which is from the IN_SBB pin to the capacitor's
positive terminal and from the PGND pin to the capacitor's negative terminal.
2. Minimize the parasitic inductance in the SIMO output capacitor loop which is from SBBx to the capacitor's
positive terminal and from the PGND pin to the capacitor's negative terminal.
3. Use wide traces for the inductor connections in order to minimize the resistance. Do not make the traces
too large. Trace width that doesn't directly lower impedance of the LX connection only increases the fringe
capacitance of the LX connection to adjacent nodes and therefore increases noise coupling.
Figure 11 shows an example PCB top-metal layout.
V
IO
SCL
LED0
LED1
LED2
SDA
nEN
PWR_HLD
GPIO
nRST
nIRQ
C
LDO
SBB0
SBB1
SBB2
LDO
C
SBB0
C
SBB1
C
SBB2
LEGEND
0603
GND
SYS
C
SYS
0402
0201
VIAS
COMPONENT SIZES LISTED IN IMPERIAL.
L
1.5μH
(0805)
LXA
LXB
Figure 11. PCB Top-Metal and Component Layout Example
www.maximintegrated.com
Maxim Integrated | 45
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Detailed Description—LDO
2
These devices include a 150mA low-dropout linear regulator (LDO). Output voltage is programmable through I C
between 1.35V and 2.9375V in 12.5mV steps using the TV_LDO[6:0] bitfield. The LDO input (INLDO) can be connected
directly to SYS or supplied by an external stepdown regulator for increased power efficiency. A 100Ω (typ) active-
discharge resistor is available to quickly discharge the LDO's output after the regulator has been disabled. See Figure 12
for a simplified block diagram.
IN_LDO
SBB0
10µF*
(0402)
*THE FLOORPLAN IS SUCH
VREF
EN_LDO
THAT THE SBB0 OUTPUT
CAPACITOR IS ALSO THE
IN_LDO INPUT CAPACITOR.
150mA
LDO
ADE_LDO
LDO
LDO
10µF
(0402)
R
ADE_LDO
Figure 12. LDO Simplified Block Diagram
Features and Benefits
● 150mA LDO
● 1.8V to 5.5V Input Volage Range
● Adjustable Output Voltage
● 180mV Maximum Dropout Voltage
● Programmable On-Chip Active Discharge
LDO Active-Discharge Resistor
The LDO has a 100Ω active-discharge resistor (R
) that is enabled based on a configuration bit (ADE_LDO) and
AD_LDO
the status of the LDO regulator. Enabling the active discharge feature helps ensure a complete and timely power down
of all system peripherals. The active-discharge resistance is disabled when V
< V
or V
< 1.0V.
IN_LDO
SYS
POR
LDO Dropout
When the LDO input voltage is sufficiently higher than the LDO target regulation voltage, the LDO provides voltage
regulation, power-supply rejection (PSRR), and noise filtering as specified in the Electrical Characteristics. The LDO
is in dropout when the input voltage is not sufficiently higher than the output voltage. In dropout, the voltage regulation
is lost and only minimal PSRR and noise filtering is provided. The Electrical Characteristics table specifies both a
dropout voltage and a dropout on-resistance for the LDO. Applications should avoid dropout by having an input voltage
greater than the output voltage plus the dropout voltage. A dropout detection interrupt is available (DOD_R; refer to
the Programmer's Guide for more information).
www.maximintegrated.com
Maxim Integrated | 46
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
LDO Soft-Start
The soft-start feature of the LDO limits inrush current during startup. The soft-start feature is achieved by limiting the slew
rate of the output voltage during startup (dV/dt ).
SS
More output capacitance results in higher input current surges during startup. The following equation and example
describes the input current surge phenomenon during startup.
The input current (I ) during soft-start is:
IN
dV
I
= C
+ I
LDO
IN
LDO
dt
SS
where:
● C
is the capacitance on the output of the regulator
LDO
● dV/dt is the voltage change rate of the output
SS
For example, given the following conditions, the input current (I ) during soft-start is 22.5mA:
IN
Given:
● C
= 10µF
LDO
● dV/dt = 1.25mV/µs
SS
● R
= 185Ω (I
= 1.85V/185Ω = 10mA)
LDO
LDO
Calculation:
● I = 10µF x 1.25mV/µs + 10mA
IN
● I = 22.5mA
IN
Applications Information
Current Limit
The LDO is rated for 150mA of output current with a typical current limit of 255mA (I
). The LDO is a voltage
LIM_LDO
regulator when it is enabled and its output current is less than I
. The LDO becomes a current source when
LIM_LDO
overloaded beyond I
. When overloaded, the LDO continues to source current as long as the LDO is enabled
LIM_LDO
and the overload persists. If the overload is removed, the LDO reverts back to operating as a voltage regulator.
Current limit provides short-circuit protection for the LDO output. A shorted LDO output creates power dissipation (P
)
DISS
in the device according to the following equation: P
= (V
-V
) x I
DISS
IN_LDO LDO LIM_LDO
For example, if the LDO input voltage (V
) is 5V and a hard short is causing the output voltage (V
) to be 0V,
LDO
IN_LDO
then P
is typically 1.275W. If this power dissipation causes significant self-heating, then the thermal alarm 1 (TJAL1)
DISS
can be used to notify the system's processor of an issue.
Using the LDO as a Load Switch
If required, the LDO can be used as a load switch. For example, if a 1.8V load switch is desired, power the LDO input
(IN_LDO) with 1.8V and program the LDO output voltage to 1.9V (any value 100mV or higher than the input voltage
works). In this configuration, the LDO is in dropout and its quiescent current typically is 2.3μA (I
).
IN_LDO
Input and Output Capacitor Selection
Sufficient input bypass capacitance (C
) and output capacitance (C
) is required for stable operation of the
LDO
IN_LDO
LDO. Figure 13 provides guidance on capacitor selection, and refers to required effective capacitance which is the actual
value of capacitance seen by the LDO during operation. Effective capacitance is almost always lower than the nominal
capacitance and is a commonly overlooked design parameter. Determine the effective capacitance by assessing the
capacitor's initial tolerance, variation with temperature, and variation with DC bias. Consult the capacitor manufacturer
for the specific details of derating.
Choose the input capacitor C
such that the effective capacitance is equal to or greater than the value found
IN_LDO
www.maximintegrated.com
Maxim Integrated | 47
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
in Figure 13, based on expected load conditions for the application. A single 10μF, 1005/0402 (mm/inch) capacitor is
recommended for typical applications, but ensure that the load current and derated capacitance does not compromise
the stability curve in Figure 13. Larger values of C
improve stability and decoupling for the LDO regulator. The
IN_LDO
floorplan of the device is such that SBB0 is adjacent to IN_LDO, and if SBB0 powers the input of the LDO, then the two
nodes can share the SBB0 output capacitor (C
power source during LDO regulator operation.
. C
reduces the current peaks drawn from the battery or input
SBB0) IN_LDO
Choose the output capacitor C
such that the effective capacitance is equal to or greater than the value found
LDO
in Figure 13, based on expected load conditions for the application. A single 10μF, 1005/0402 (mm/inch) capacitor is
recommended for typical applications, but ensure that the load current and derated capacitance does not compromise
the stability curve in Figure 13. Larger values of C
improve stability and output PSRR, but increases the input surge
LDO
currents during soft-start and output voltage changes. The effective output capacitance should not exceed 100μF to
maintain LDO stability.
For example, consider the case of the MAX77640A where:
1. Size is very important.
2. The LDO input is powered by SBB0 which is 2.05V.
3. The LDO output is 1.85V.
4. The LDO output current is ≤ 80mA.
A small 1005/0402 (mm/inch) capacitor such as the GRM155R60J106ME15 (Murata, 10μF, 6.3V X5R) gives 5.7μF at
60°C and 5.4μF at -20°C and has a ± 20% tolerance, so the worst-case effective capacitance is 4.3μF (5.4μF derated by
20% tolerance). With just 4.3μF of capacitance at the output, Figure 13 shows the LDO is stable with load currents of ≤
35mA. To get stability at 80mA, 6μF is required. There are a few options to consider here:
● Add more capacitors to the design.
● Replace the 1005/0402 (mm/inch) capacitor with a 1608/0603 (mm/inch) capacitor.
● Consider point-of-load capacitance in the assessment of effective capacitance. For example, if there is a point-of-
load capacitor downstream from the LDO that is sufficiently close to the local LDO output capacitor, it can cover
the gap. The capacitor can be considered 'sufficiently close' if the PCB does not add more than 25nH and 25mΩ
of extra ESR and ESL (more or less within 1").
Note the impedance of either the input or output capacitor (ESR, ESL) should be very low (i.e., ≤ 50mΩ + ≤ 5nH) for
frequencies up to 0.5MHz. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small
size, low ESR, and small temperature coefficients.
EFFECTIVE LDO CAPACITANCE
REQUIRED FOR STABILITY
EFFECTIVE LDO CAPACITANCE
REQUIRED FOR STABILITY
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
STABLE REGION
STABLE REGION
INPUT CAPACITANCE
OUTPUT CAPACITANCE
UNSTABLE REGION
UNSTABLE REGION
0
25
50
75
100
125
150
0
25
50
75
100
125
150
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 13. LDO Capacitance for Stability
www.maximintegrated.com
Maxim Integrated | 48
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Detailed Description—Current Sinks
These devices have a 3-channel current sink driver designed to drive LED's in portable devices. This block can
also be used as a general-purpose current sink driver for other applications. The driver's on-time and frequency
are independently programmable for each output to achieve a desired blink pattern. Alternatively, the LEDs can be
continuously on (i.e., not blinking). The blink period is programmable from 0.5s to 8s, with an on-time duty cycle from
6.25% to 100%.
Figure 14 utilizes a common set of clock dividers to drive three identical current sink modules. Refer to the Programmer's
Guide for more information.
MAX77640
MAX77641
BIAS
CLK_64_S
CLK
CLOCK
DIVIDER
CLOCK DIVIDER
AND INVERTER
CLK_64
CLK_32
EN_LED_MSTR
CURRENT SINK
LED0
BRT_LED0[4:0]
DAC
INV_LED0
P_LED0[3:0]
D_LED0[3:0]
CLK_32
EN_LED0
PWM
LOGIC
2/4/8Ω
LED_FS0[1:0]
CURRENT SINK
LED1
BRT_LED1[4:0]
INV_LED0
P_LED1[3:0]
D_LED1[3:0]
CLK_32
LED_FS1[1:0]
CURRENT SINK
LED2
BRT_LED24:0]
INV_LED0
P_LED2[3:0]
D_LED2[3:0]
CLK_32
LGND
LED_FS2[1:0]
Figure 14. Current Sink Block Diagram
Applications Information
LED Assignment
The three current sinks (LED0, LED1, LED2) are identical. In the typical application where a red, green, blue LED cluster
is used (RGB), the assignment of the RGB elements to the LED0/1/2 pins should be done in whatever way makes the
PCB layout the easiest.
Unused Current Sink Ports
If a current sink port is not utilized in a given application, connect that port to ground. Additionally, software should ensure
that the unused current sink is not enabled (EN_LEDx = 0).
www.maximintegrated.com
Maxim Integrated | 49
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
2
Detailed Description—I C Serial Interface
2
The MAX77640/MAX77641 feature a revision 3.0 I C-compatible, 2-wire serial interface consisting of a bidirectional
2
serial data line (SDA) and a serial clock line (SCL). As shown in Figure 15, the I C SDA and SCL signals are internally
decoded by the devices used to communicate with the top-level control logic as well as the SIMO, LDO, GPIO, and
current sinks. The MAX77640/MAX77641 are slave-only devices which rely on an external bus master to generate SCL.
2
SCL clock rates from 0Hz to 3.4MHz are supported. I C is an open-drain bus and therefore, SDA and SCL require
pullups.
2
2
The MAX77640/MAX77641 I C communication controller implements 7-bit slave addressing. An I C bus master initiates
communication with the slave by issuing a START condition followed by the slave address (Figure 16). The OTP
address is factory programmable for one of two options (Table 5). All slave addresses not mentioned in Table 5 are not
acknowledged.
The devices use 8-bit registers with 8-bit register addressing. They support standard communication protocols: (1)
writing to a single register (2) writing to multiple sequential registers with an automatically incrementing data pointer
(3) reading from a single register (4) reading from multiple sequential registers with an automatically incrementing data
2
2
pointer. For additional information on the I C protocols, refer to the MAX77640/MA77641 I C Implementation Guide and/
2
or the I C specification that is freely available on the internet.
COMMUNICATIONS CONTROLLER
V
IO
SCL
SDA
INTERFACE
DECODERS
SHIFT REGISTERS
BUFFERS
GND
TOP
LEVEL
CURRENT
SINKS
SIMO
LDO
GPIO
2
Figure 15. I C Simplified Block Diagram
.
www.maximintegrated.com
Maxim Integrated | 50
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
2
Table 5. I C Slave Address Options
ADDRESS
7-BIT SLAVE ADDRESS
8-BIT WRITE ADDRESS
8-BIT READ ADDRESS
Main Address
(ADDR = 1)*
0x48, 0b 100 1000
0x90, 0b 1001 0000
0x91, 0b 1001 0001
Main Address
(ADDR = 0)*
0x40, 0b 100 0000
0x49, 0b 100 1001
0x80, 0b 1000 0000
0x92, 0b 1001 0010
0x81, 0b 1000 0001
0x93, 0b 1001 0011
Test Mode**
*Perform all reads and writes on the main address. ADDR is a factory one-time programmable (OTP) option, allowing for
address changes in the event of a bus conflict. Contact Maxim for more information.
**When test mode is unlocked, the additional address is acknowledged. Test mode details are confidential. If possible,
leave the test mode address unallocated to allow for the rare event that debugging needs to be performed in cooperation
with Maxim.
S
1
1
0
2
0
3
1
4
0
5
0
6
0
7
R/W
A
9
SDA
SCL
ACKNOWLEDGE
8
Figure 16. Slave Address Example
www.maximintegrated.com
Maxim Integrated | 51
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Typical Application Circuit
MAX77640
MAX77641
SYS
V
SYS
IN_SBB
PGND
2.7V to 5.5V
POWER INPUT
C
SYS
22µF/6.3V
(0603)
SBB0
V
SBB0
SIMO BUCK-BOOST
SBB1
SBB2
V
V
SBB1
SBB2
1.5µH
LXA
LXB
10µF
6.3V
C
BST
(0402)
BST
3300pF/6.3V
(0201)
SYSTEM
RESOURCES
GPIO
BIAS
SUCH AS:
SYS, SBB2
IN_LDO
LDO
LED0
LED1
LED2
LGND
CURRENT
SINKS
LDO
V
LDO
10µF
6.3V
(0402)
V
IO
V
/POWER
IO
SDA
SCL
*
*
SDA
SCL
GPIO
GPIO
GPIO
2
I C
PROCESSOR
nRST
nIRQ
*
*
nRST
nIRQ
10kΩ
V
SYS
nEN
TOP LEVEL
PWR_HLD
PWR_HLD
MOMENTARY
ONKEY
GND
*THE PROCESSOR HAS AN INTERNAL PULL
RESISTOR FOR THIS NODE.
Ordering Information
PIN-
PACKAGE
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
OPTIONS
SBB0/SBB1/SBB2 upper values 2.375V/1.5875V/3.95V,
samples with various OTP options
MAX77640EWV+*
MAX77640AEWV+T
MAX77641EWV+*
MAX77641AEWV+T
30 WLP
SBB0/SBB1/SBB2 upper values 2.375V/1.5875V/3.95V,
production device, DIDM = 0b00, CID = 0b0000**
30 WLP
30 WLP
30 WLP
SBB0/SBB1/SBB2 upper values 2.375V/5.25V/5.25V,
samples with various OTP options
SBB0/SBB1/SBB2 upper values 2.375V/5.25V/5.25V,
production device, DIDM = 0b01, CID = 0b0001**
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*Custom samples only. Not for production or stock. Contact factory for more information.
**See the Programmer's Guide for the options associated with a specified DIDM and CID.
www.maximintegrated.com
Maxim Integrated | 52
MAX77640/MAX77641
Ultra-Low Power PMIC with 3-Output SIMO,
150mA LDO, and Power Sequencer
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
4/18
6/18
8/18
0
1
2
Initial release
—
Updated Ordering Information table
52
1
Updated bump pitch in Benefits and Features section
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max
limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2018 Maxim Integrated Products, Inc.
相关型号:
©2020 ICPDF网 联系我们和版权申明