MAX77756EVKIT [MAXIM]
Emulates System Loading;
| 型号： | MAX77756EVKIT |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Emulates System Loading |
| 文件： | 总34页 (文件大小：1138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
General Description
Benefits and Features
The MAX77756 is a synchronous 500mA step-down
DC-DC converter with integrated dual-input power multi-
plexer (MUX). The converter operates on an input supply
as low as 3.0V and as high as 24V. Default output volt-
age is factory-programmed to either 1.8V, 3.3V, or 5.0V.
Output voltage is further adjustable through external
● Wide Input Power Supply
• 3V to 24V Supply Voltage
• 500mA (max) Output Current
• 1.8V, 3.3V, or 5.0V Factory-Set V
2
with
OUT
Optional I C Control: 1.5V to 7.5V in 50mV Steps
• External Feedback Resistor V
Option (1V to
OUT
2
resistors or an I C serial interface.
99% V
)
SUP
• Hardware or Software Enable
The dual-input power MUX selects the higher voltage
from two different input sources to power the step-down
converter. Control circuitry ensures that only one channel
of the MUX is on at a time to prevent cross-conduction
between input sources. For single-input applications, the
MUX can be bypassed and the step-down converter can
be powered directly from the SUP pin.
● Dual-Input Power MUX Replaces Common-Cathode
Diode Arrays
• Automatic Ideal-Diode ORing Voltage Selector
• 250mΩ MOSFETs Minimize Power Consumption,
BOM, and Solution Size
● Low I Enables Always-On Rails
Q
The MAX77756 is available in a small 2.33mm x 1.42mm
(0.7mm max height), 15-bump wafer-level package
(WLP). For a similar buck converter without a power
MUX, refer to the MAX77596.
• 1.5μA Quiescent Current (Only SUP Powered)
• 19μA Quiescent Current (IN1/IN2 Powered)
• 88% Peak Efficiency (12V
, 3.3V
)
SUP
OUT
● Safe and Easy to Use
• Short-Circuit Hiccup Mode and Thermal Protection
• 8ms Soft-Start
• Software-Enabled Spread Spectrum
• Pin-Programmable Inductor Peak Current Level
Applications
● USB Type-C Power Delivery Accessories and
Devices
● Notebook and Tablet Computers
● Home Automation, Low I Smart Hubs
● Battery-Powered Systems, Backup Battery,
Uninterruptible Rails
Ordering Information appears at end of data sheet.
● Small Size
Q
• 2.33mm x 1.42mm (0.7mm max height)
Wafer-Level Package (WLP)
• 15-Bump, 0.4mm Pitch, 3 x 5 Array
Simplified Block Diagram
POWER MUX
3V TO 24V DC SOURCE 1
IN1
- MAIN BATTERY
- USB PD PROVIDER
SUP
BST
IDEAL
IN2
3V TO 24V DC SOURCE 2
- BACKUP BATTERY
- SOLAR CELL ARRAY
10µH
LX
V
IO
V
OUT
BUCK
1.5V TO 7.5V
1.8V, 3.3V, 5.0V DEFAULTS
500mA MAX
SDA
SCL
EN
CONVERTER
HARDWARE OR
SOFTWARE
ENABLE
OUT/ FB
POK
DIGITAL
CONTROL
POWER OK
PGND
AGND, ILIM, BIAS
PINS NOT DRAWN
24V, 500mA DC-DC BUCK CONVERTER WITH IDEAL-DIODE “ORING” MUX
19-8710; Rev 1; 10/17
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Absolute Maximum Ratings
IN1, IN2, SUP to PGND ........................................-0.3V to +26V
BIAS to PGND.........................................................-0.3V to +6V
IN1, IN2 Repetitive Forward Current (T = +85°C)
A
10% Duty Square Wave ...................................................4.1A
EN to PGND..............................................-0.3V to V
+ 0.3V
IN1, IN2 SUP Continuous Current ................................1.6A
LX Continuous Current (Note 1)....................................1.6A
OUT/FB Short-Circuit Duration..................................Continuous
SUP
RMS
RMS
BST to LX..............................................................................+6V
BST to PGND........................................................-0.3V to +31V
OUT/FB to PGND..................................................-0.3V to +12V
Continuous Power Dissipation (T = +70°C)
A
POK, ILIM to PGND .................................-0.3V to V
+ 0.3V
(derate 16.22mW/°C above +70°C) ..........................1298mW
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature......................................................+150°C
Soldering Temperature (reflow).......................................+260°C
BIAS
POK, SDA Sink Current .....................................................20mA
to PGND ...........................................................-0.3V to +6V
V
IO
SDA, SCL to PGND......................................-0.3V to V + 0.3V
IO
AGND to PGND....................................................-0.3V to +0.3V
Note 1: LX has internal clamp diodes to PGND and SUP. Applications that forward bias these diodes should not exceed the IC’s package
power dissipation limits.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
15 WLP
Package Code
W151G2+1
Outline Number
21-100111
Land Pattern Number
Thermal Resistance, Four-Layer Board:
90-100052 (Refer to Application Note 1891)
Junction to Ambient (θ
)
61.65°C/W
JA
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Maxim Integrated
│ 2
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Electrical Characteristics
(V
= V
= 12V, V = 1.8V, V
= V
= 0V, configuration registers in reset. Limits are 100% production tested at T = +25°C,
IN2 A
SUP
EN
IO
IN1
limits over T = -40°C to +85°C are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STEP-DOWN CONVERTER
SUP Voltage Range
V
3
24
V
V
SUP
SUP Undervoltage Lockout
V
V
rising
SUP
2.75
2.9
300
0.75
3.0
UVLO
SUP Undervoltage Lockout
Hysteresis
mV
SUP Shutdown Current
I
V
= 0V (buck converter disabled)
3.0
μA
SUP-SHDN
EN
SUP QUIESCENT CURRENT
I
I
I
I
= 0mA, V
= 0mA, V
= 0mA, V
= 1.8V
= 3.3V
= 5.0V
6
18
3.0
5.0
70
LOAD
LOAD
LOAD
LOAD
OUT
OUT
OUT
1.5
2.65
32
SUP Quiescent Current
BIAS Regulator Voltage
I
μA
SUP-Q
= 0mA, external feedback version
V
= 5.5V to 24V, BIAS not internally
SUP
V
5
V
V
BIAS
connected to OUT (Note 1)
Internal feedback version target regulation
voltage, adjustable through I C from 1.5V
to 7.5V in 50mV/LSB with
2
Output Voltage Regulation
Range
V
1.5
7.5
OUT-REG
V_OUTREG[7:0]
OUTPUT VOLTAGE ACCURACY
V
= 12V,
SUP
I
T
= 250mA,
= +25°C
1.78
1.746
3.27
3.2
1.8
1.8
3.3
3.3
5
1.82
1.854
3.33
3.4
OUT
V
OUT-REG
A
= 1.8V, 1.8V
factory-default
version
V
I
T
= 4.5V to 24V,
SUP
= 0mA to 500mA,
= -40°C to +85°C
OUT
A
V
I
T
= 12V,
SUP
V
= 250mA,
= +25°C
OUT-REG
OUT
= 3.3V, 3.3V
factory-default
version
A
OUT Voltage Accuracy
V
V
OUT
V
I
T
= 4.5V to 24V,
SUP
= 0mA to 500mA,
= -40°C to +85°C
OUT
A
V
I
T
= 12V,
SUP
= 250mA,
= +25°C
4.95
4.85
5.05
5.15
OUT
V
OUT-REG
A
= 5.0V, 5.0V
factory-default
version
V
= 6V to 24V, I
OUT
SUP
= 0mA to 500mA, T
=
5
A
-40°C to +85°C
Maxim Integrated
│ 3
www.maximintegrated.com
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Electrical Characteristics (continued)
(V
= V
= 12V, V = 1.8V, V
= V
= 0V, configuration registers in reset. Limits are 100% production tested at T = +25°C,
SUP
EN
IO
IN1
I
N
2
A
limits over T = -40°C to +85°C are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FB VOLTAGE ACCURACY
V
= 12V,
SUP
I
T
= 250mA,
= +25°C
0.99
0.97
1
1.01
1.03
LOAD
External
feedback
version
A
FB Voltage Accuracy
FB Input Current
V
V
FB
V
= 3.0V to 24V,
= 0mA to 500mA,
SUP
I
1
LOAD
T
= -40°C to +85°C
A
I
V
= 1V, external feedback version
0.02
99
µA
%
FB
FB
Standby mode exit threshold,
I = 0mA, expressed as a
LOAD
OUT/FB Wake-Up
Threshold
V
WAKE
percentage of V
OUT-REG
OUT/FB Load Regulation
OUT/FB Line Regulation
0 to 300mA load, FPWM mode (Note 2)
1
%
V
= 4.5V to 24V, V
= 3.3V,
SUP
OUT
0.02
%/V
SUP
FPWM mode (Note 2)
SOFT_ST = 1
4
8
OUT/FB Soft-Start Ramp
Time
t
ms
SS
SOFT_ST = 0
High-Side MOSFET
On-Resistance
R
V
= 5V, I = 90mA
500
500
800
800
mΩ
mΩ
ON-HS
BIAS
BIAS
LX
Low-Side MOSFET
On-Resistance
R
V
= 5V, I = 90mA
LX
ON-LS
I_PEAK[1:0] = 0b00
I_PEAK[1:0] = 0b01
I_PEAK[1:0] = 0b10
I_PEAK[1:0] = 0b11
Output overloaded (V
700
800
High-Side MOSFET Peak
Current Limit
I
mA
mA
LX-PEAK
800
900
1000
1000
< 25% of V
OUT
OUT-
Low-Side MOSFET Valley
Current Threshold
I
), threshold below where
500
LX-VALLEY
REG
on-times are allowed to start
High-Side MOSFET
Minimum Current
Threshold
Inductor current ramps to at least
I
200
40
mA
mA
LX-PK-MIN
I
while skipping
LX-PK-MIN
Low-Side MOSFET
Zero-Crossing Threshold
I
ZX
Minimum On-Time (Note 3)
Maximum Duty Cycle
Switching Frequency
t
V
= 3.3V
80
99
1
ns
%
ON-MIN
OUT
D
f
MAX
Continuous conduction
0.94
1.06
MHz
SW
Spread-Spectrum
Frequency Range
∆f
Spread-spectrum enabled
±6
%
SW
Maxim Integrated
│ 4
www.maximintegrated.com
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Electrical Characteristics (continued)
(V
= V
= 12V, V = 1.8V, V
= V
= 0V, configuration registers in reset. Limits are 100% production tested at T = +25°C,
SUP
EN
IO
IN1
I
N
2
A
limits over T = -40°C to +85°C are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Soft-Short Output Voltage
Monitor Threshold
0.25 x
V
V
OUT-OVRLD
V
OUT-REG
Switching stopped because
V
< 25% of V
and 15
OUT
OUT-REG
Output-Overloaded Retry
Timer
t
consecutive switching cycles ended by
current limit, time before converter
attempts to soft-start again
15
ms
RETRY
POWER MULTIPLEXER
Minimum initial voltage to forward-bias
power MUX FET intrinsic body-diode to
activate selection logic
IN1/IN2 Minimum Initial
Operating Voltage
V
UVLO
+ 0.7
V
/V
V
IN1 IN2
IN1/IN2 QUIESCENT CURRENT
V
= 1.8V, V
= 0mA
or V
or V
or V
= 12V,
= 12V,
= 12V,
= 0mA,
OUT
IN1
IN1
IN1
IN2
38
18.5
25
100
30
I
LOAD
V
= 3.3V, V
= 0mA
OUT
IN2
I
LOAD
IN1/IN2 Quiescent Current
I
/I
μA
IN1-Q IN2-Q
V
= 5.0V, V
= 0mA
OUT
IN2
40
I
LOAD
V
or V
= 12V, I
IN1
IN2 LOAD
42
100
external feedback version
R
R
V
V
= 5.5V, I
= 5.5V, I
= 90mA
= 90mA
250
250
400
400
ON-IN1
ON-IN2
IN1
IN1
IN1/IN2 to SUP On-Resis-
tance
mΩ
IN2
IN2
V
V
= 12V,
SUP
I
Current from IN1
Current from IN2
0.003
1
1
IN1-LEAK
IN2-LEAK
= V
=
IN1
IN2
IN1/IN2 Leakage
0V, IN1/IN2 to
SUP channel
is off
μA
I
0.003
400
Channel Selection
Hysteresis
(Note 4)
mV
POWER-OK OUTPUT (POK)
V
rising, expressed as a
OUT
V
90
88
92
94
92
POK-RISING
percentage of V
OUT-REG
POK Threshold
%
V
falling, expressed as a
OUT
V
90
12
POK-FALLING
percentage of V
OUT-REG
POK Debounce Timer
POK Leakage Current
POK Low Voltage
t
μs
μA
V
POK-DB
POK = high (high impedance),
= +25°C
I
1
POK
T
A
V
POK = low, sinking 1mA
0.4
POK
Maxim Integrated
│ 5
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Electrical Characteristics (continued)
(V
= V
= 12V, V = 1.8V, V
= V
= 0V, configuration registers in reset. Limits are 100% production tested at T = +25°C,
SUP
EN
IO
IN1
I
N
2
A
limits over T = -40°C to +85°C are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
ENABLE INPUT (EN)
EN Logic-High Threshold
EN Logic-Low Threshold
EN Leakage Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
1.4
V
V
EN_HI
V
0.4
EN_LO
I
V
= V = 12V
SUP
0.1
μA
EN
EN
HIGH-SIDE CURRENT LIMIT INPUT (ILIM)
ILIM Logic-High Threshold
ILIM Logic-Low Threshold
V
1.4
V
V
ILIM_HI
V
0.4
5.5
+1
ILIM_LO
SERIAL INTERFACE/I/O STAGE
V
V
V
Voltage Range
Valid Logic Threshold
Bias Current
V
V
1.7
1.7
V
V
IO
IO
IO
IO
T
= +25°C
-1
0
μA
A
SCL, SDA Input High
Voltage
0.7 x
V
V
IH
V
IO
SCL, SDA Input Low
Voltage
0.3 x
V
IL
V
IO
0.05 x
SCL, SDA Input Hysteresis
V
V
HYS
V
IO
SCL, SDA Input Leakage
Current
I
V
= 5.5V, V
= V = 0V or 5.5V
SDA
-10
+10
0.4
μA
I
IO
SCL
SDA Output Low Voltage
SCL, SDA Pin Capacitance
V
Sinking 20mA
(Note 5)
V
OL
10
pF
Input Filter Suppressed
Spike Maximum Pulse
Width
t
(Note 5)
50
ns
SP
SERIAL INTERFACE/TIMING
Clock Frequency
f
1
MHz
μs
SCL
Bus Free Time Between
STOP and START
Condition
t
0.5
BUF
Setup Time REPEATED
START Condition
t
260
260
ns
ns
SU;STA
Hold Time REPEATED
START Condition
t
HD;STA
Maxim Integrated
│ 6
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Electrical Characteristics (continued)
(V
= V
= 12V, V = 1.8V, V
= V
= 0V, configuration registers in reset. Limits are 100% production tested at T = +25°C,
SUP
EN
IO
IN1
I
N
2
A
limits over T = -40°C to +85°C are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SCL Low Period
SYMBOL
CONDITIONS
MIN
500
260
50
TYP
MAX
UNITS
ns
t
LOW
SCL High Period
Data Setup Time
Data Hold Time
t
ns
HIGH
t
ns
SU;DAT
HD;DAT
t
0
μs
Time measured between V and V
IO
(Note 5)
OL
SDA Fall Time
t
120
ns
ns
F
Setup Time for STOP
Condition
t
260
SU;STO
THERMAL PROTECTION
Thermal Shutdown
T
Junction temperature rising
+165
+15
°C
°C
SHDN
Thermal Shutdown
Hysteresis
Note 1: See the BIAS Regulator section.
Note 2: Forced PWM (FPWM) is an internal test mode.
Note 3: Output voltage regulation is always maintained. The device skips pulses when the duty cycle needed to regulate the output
violates the minimum on-time.
Note 4: Off channel must be half of this value higher than the on channel for switch to happen.
Note 5: Design guidance only. Not production tested.
Maxim Integrated
│ 7
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Typical Operating Characteristics
(V
= V
= 12V, T = +25°C, internal feedback version, unless otherwise noted.)
INx
EN
A
SUPQUIESCENT CURRENT
vs. VOLTAGE
SUPQUIESCENT CURRENT
vs. VOLTAGE
SUPQUIESCENT CURRENT
vs.VOLTAGE
1.8VOUTPUT
5VOUTPUT
3.3VOUTPUT
toc01
toc03
toc02
16
14
12
10
8
6
5
4
3
2
1
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VOUT = 1.8V
VOUT = 5V
VOUT = 3.3V
TA = +85°C
TA = +25°C
TA = +85°C
TA = +85°C
TA = +25°C
6
TA = -40°C
4
TA = +25°C
TA = -40°C
TA = -40°C
2
0
0
10
20
30
0
10
20
30
0
0
0
10
20
30
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
INx QUIESCENT CURRENT vs.
VOLTAGE
INx QUIESCENT CURRENT vs.
VOLTAGE
SUPQUIESCENT CURRENT
vs.VOLTAGE
EXTERNAL FEEDBACK VERSION
1.8V OUTPUT
3.3V OUTPUT
toc05
toc06
toc04
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
70
60
50
40
30
20
10
0
VOUT = 1.8V
VOUT = 3.3V
VOUT = 3.3V
TA = +85°C
TA = +25°C
TA = -40°C
TA = +85°C
TA = +85°C
TA = +25°C
TA = -40°C
TA = +25°C
TA = -40°C
0
10
20
30
0
10
20
30
0
10
20
30
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
INx QUIESCENT CURRENT
vs. VOLTAGE
INx QUIESCENT CURRENT
vs. VOLTAGE
EXTERNAL FEEDBACK VERSION
SHUTDOWN CURRENT
vs. TEMPERATURE
5V OUTPUT
toc07
toc08
toc09
45
40
35
30
25
20
15
10
5
80
70
60
50
40
30
20
10
0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VOUT = 5V
TA = +85°C
TA = +25°C
TA = +85°C
TA = +85°C
TA = +25°C
TA = -40°C
TA = -40°C
TA = +25°C
TA = -40°C
V
= 0V (SHUTDOWN)
VOUT = 3.3V
OUT
0
0
10
20
30
10
20
30
0
10
20
30
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Maxim Integrated
│ 8
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Typical Operating Characteristics (continued)
(V
= V
= 12V, T = +25°C, internal feedback version, unless otherwise noted.)
INx
EN
A
EFFICIENCYvs. LOAD
1.8V OUTPUT
EFFICIENCYvs. LOAD
1.8V OUTPUT
EFFICIENCYvs. LOAD
1.8V OUTPUT
toc10
toc11
toc12
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VOUT = 1.8V
VOUT = 1.8V
VOUT = 1.8V
VSUP = 5V
VSUP = 12V
VINx = 5V
VSUP = 24V
VINx = 12V
VINx = 24V
0.0001 0.001 0.01 0.1
1
10
100 1000
0.0001 0.001 0.01 0.1
1
10
100 1000
0.0001 0.001 0.01 0.1
1
10
100 1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
EFFICIENCYvs. LOAD
3.3V OUTPUT
EFFICIENCYvs. LOAD
3.3V OUTPUT
EFFICIENCYvs. LOAD
3.3V OUTPUT
toc13
toc14
toc15
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VOUT = 3.3V
VOUT = 3.3V
VOUT = 3.3V
VSUP = 5V
VSUP = 24V
VSUP = 12V
V
INx = 12V
VINx = 24V
VINx = 5V
0.0001 0.001 0.01 0.1
1
10
100 1000
0.0001 0.001 0.01 0.1
1
10
100 1000
0.0001 0.001 0.01 0.1
1
10
100 1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
EFFICIENCYvs. LOAD
5V OUTPUT
EFFICIENCYvs. LOAD
5V OUTPUT
EFFICIENCYvs. LOAD
EXTERNAL FEEDBACK VERSION
toc16
toc17
toc18
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VOUT = 5V
VOUT = 5V
VOUT = 3.3V
VSUP = 5V
VSUP = 12V
VINx = 5V
VINx = 24V
VINx = 12V
VSUP = 24V
0.0001 0.001 0.01 0.1
1
10
100 1000
0.0001 0.001 0.01 0.1
1
10
100 1000
0.0001 0.001 0.01 0.1
1
10
100 1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Maxim Integrated
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Typical Operating Characteristics (continued)
(V
= V
= 12V, T = +25°C, internal feedback version, unless otherwise noted.)
INx
EN A
EFFICIENCYvs. LOAD
EXTERNAL FEEDBACK VERSION
EFFICIENCYvs. LOAD
EXTERNAL FEEDBACK VERSION
toc19
toc20
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VOUT = 3.3V
VOUT = 3.3V
VINx = 24V
VSUP = 12V
VINx = 12V
VSUP = 24V
0.0001 0.001 0.01 0.1
1
10
100 1000
0.0001 0.001 0.01 0.1
1
10
100 1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
LOAD REGULATION
1.8V OUTPUT
LOAD REGULATION
3.3V OUTPUT
toc21
toc22
1.90
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
1.88
1.86
1.84
1.82
1.80
1.78
1.76
V
INx = 24V
VINx = 12V
VINx = 5V
VINx = 24V
VINx = 12V
VINx = 5V
0
100
200
300
400
500
0
100
200
300
400
500
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
LOAD REGULATION
5VOUTPUT
LINE REGULATION
1.8V OUTPUT
toc23
toc24
5.10
5.08
5.06
5.04
5.02
5.00
4.98
4.96
4.94
1.82
1.82
1.81
1.81
1.80
1.80
1.79
1.79
1.78
1.78
1.77
IOUT = 100mA
IOUT = 0mA
IOUT = 250mA
VINx = 24V
VINx = 12V
IOUT = 500mA
0
100
200
300
400
500
0
10
20
30
OUTPUT CURRENT (mA)
SUPPLY VOLTAGE (V)
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Typical Operating Characteristics (continued)
(V
= V
= 12V, T = +25°C, internal feedback version, unless otherwise noted.)
INx
EN A
LINE REGULATION
3.3V OUTPUT
LINE REGULATION
5V OUTPUT
toc25
toc26
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
3.24
5.05
5.04
5.03
5.02
5.01
5.00
4.99
4.98
4.97
4.96
4.95
4.94
IOUT = 0mA
IOUT = 0mA
IOUT = 100mA
IOUT = 100mA
IOUT = 250mA
IOUT = 250mA
IOUT = 500mA
IOUT = 500mA
0
10
20
30
0
10
20
30
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
STARTUP WAVEFORM
3.3V OUTPUT (0mA LOAD)
LOAD TRANSIENT RESPONSE
1.8VOUTPUT
toc28
toc27
VINx = 12V
VEN
10V/div
3.3V
VOUT
2V/div
BIAS SWITCHOVER TO OUT
3.3V
100mV/div
(1.8V OFFSET)
0V
0V
VOUT
5V
VBIAS
5V/div
ISUP
50mA/div
400mA/div
IOUT
100µs/div
2ms/div
LOAD TRANSIENT RESPONSE
3.3VOUTPUT
LOAD TRANSIENT RESPONSE
5VOUTPUT
toc29
toc30
VINx = 12V
VINx = 12V
100mV/div
(3.3V OFFSET)
100mV/div
(5V OFFSET)
VOUT
VOUT
400mA/div
400mA/div
IOUT
IOUT
100µs/div
100µs/div
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Typical Operating Characteristics (continued)
(V
= V
= 12V, T = +25°C, internal feedback version, unless otherwise noted.)
INx
EN
A
LOAD TRANSIENT RESPONSE
EXTERNAL FEEDBACK VERSION
LINETRANSIENT RESPONSE
1.8VOUTPUT
toc31
toc33
toc35
toc32
V
INx = 12V
24V
100mV/div
VOUT
4V
5V/div
VIN
IOUT
400mA/div
50mV/div
VOUT
(1.8V OFFSET)
100µs/div
200µs/div
LINETRANSIENT RESPONSE
3.3VOUTPUT
LINETRANSIENT RESPONSE
5VOUTPUT
toc34
24V
24V
4V
4V
VIN
5V/div
VIN
5V/div
50mV/div
(3.3V OFFSET)
50mV/div
(5V OFFSET)
VOUT
VOUT
200µs/div
200µs/div
LINETRANSIENT RESPONSE
EXTERNAL FEEDBACK VERSION
IN1/IN2SWITCHOVER
toc36
24V
50mV/div
(AC-COUPLED)
VOUT
VSUP
TRACKING HIGHER
OF VIN1 VIN2
/
4V
1V/div
(7.5V OFFSET)
5V/div
VIN
V
IN2
50mV/div
(3.3V OFFSET)
VOUT
V
IN1
100µs/div
200µs/div
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Bump Configuration
MAX77756
1
2
3
4
5
+
BST
EN
LX
PGND
A
B
C
IN1
SUP
OUT/
FB
SDA
SCL
AGND
ILIM
V
IO
IN2
POK
BIAS
15 WLP
TOP VIEW (BUMP SIDE DOWN)
Bump Description
BUMP
NAME
FUNCTION
Power MUX Input 1. IN1 and IN2 have equal priority to the power selector. Selection logic is only active
when the IC is enabled through the EN pin or EN_BIT. A diode always exists between IN1 and SUP.
Connect to PGND to force PFET between IN1 and SUP off.
A1
IN1
Power MUX Input 2. IN1 and IN2 have equal priority to the power selector. Selection logic is only active
when the IC is enabled through the EN pin or EN_BIT. A diode always exists between IN2 and SUP.
Connect to PGND to force PFET between IN2 and SUP off.
C1
A3
A2
IN2
BST
SUP
High-Side FET Driver Supply. Connect a 0.1μF ceramic capacitor between BST and LX.
Power MUX Output and Buck Supply Input. Bypass with a 1μF ceramic capacitor to PGND as close as
possible to the IC. If using IN1/IN2 to power the IC, do not prebias the SUP capacitor or connect SUP to
external loads. If using SUP to power the IC, connect IN1 and IN2 to PGND.
A4
A5
B4
C5
LX
Switching Node. LX is high impedance when the converter is disabled.
PGND
AGND
POK
Power Ground. Connect to AGND on the PCB. Return the SUP and OUT bypass capacitors to PGND.
Quiet Ground. Connect to PGND on the PCB. Return the BIAS bypass capacitor to AGND.
Open-Drain Power OK Output. An external pullup resistor is required.
Low-Voltage Internal IC Supply. Bypass to AGND with a 1μF ceramic capacitor. Do not load this pin
externally.
C3
BIAS
Internal Feedback Versions (MAX77756A/B/C): Output Voltage Sense Input. Connect a 10μH inductor
between OUT and LX. Bypass OUT to PGND with a minimum 22μF ceramic capacitor.
B5
OUT/FB
External Feedback Version (MAX77756D): Feedback Input. Connect a resistor voltage divider between
the converter's output and AGND to set the output voltage. Connect a 5.6pF feed-forward capacitor
between the converter's output and FB. Do not route FB close to sources of EMI or noise.
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Bump Description (continued)
BUMP
NAME
FUNCTION
Enable Input. Enables both the step-down converter and the power MUX. EN is compatible with the SUP
voltage domain. Drive EN to PGND to disable the device. Drive EN above V
If using I C to control the buck, the enable bit (EN_BIT) interacts with the EN pin. See the Enable Control
to enable the device.
EN_HI
B3
EN
2
section.
2
B1
C2
B2
V
I C Serial Interface Voltage Supply. Connect to PGND if not used.
IO
2
SCL
SDA
I C Serial Interface Clock. This pin requires a pullup resistor to V . Connect to PGND if not used.
IO
2
I C Serial Interface Data. This pin requires a pullup resistor to V . Connect to PGND if not used.
IO
LX Peak Current Limit Setting Input. Connect to PGND to set I
to 700mA. Connect to BIAS to set
LX-PEAK
2
C4
ILIM
I
to 1000mA. I C writes to control I
are only accepted while ILIM is logic-low.
LX-PEAK
LX-PEAK
See the Peak Inductor Current Limit (ILIM) section for details.
Functional Diagram
DC INPUT 1
3V TO 24V
IN1
IN2
MAX77756
SUP
BST
C
IN1
IN2
POWER MUX
SELECT
LOGIC
C
SUP
C
BIAS
DC INPUT 2
3V TO 24V
BIAS
C
BST
1.5V TO 7.5V PROGRAMMABLE OUTPUT
1.8V, 3.3V, 5.0V FACTORY DEFAULTS
500mA MAX
BIAS LDO
AGND
L
STEP-DOWN
CONTROL
C
BIAS
LX
V
OUT
R
PU
TO HOST OR
SUPERVISOR
RESET INPUT
C
OUT
POK
EN
SUP
BIAS
ILIM
OUT/FB
2
I C
V
IO
CONTROL
&
PGND
AGND
DIGITAL
SERIAL
HOST
SDA
SCL
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Buck Regulator Control Scheme
Detailed Description
The step-down converter uses a PWM peak current-mode
control scheme with a load-line architecture. Peak cur-
rent-mode control provides precise control of the inductor
current on a cycle-by-cycle basis and inherent compensa-
tion for input voltage variation.
The MAX77756 is a small 500mA step-down DC-DC con-
verter with integrated dual-input power multiplexer (MUX).
The step-down (buck) converter uses synchronous rec-
tification and internal current-mode compensation. The
buck operates on a supply voltage from 3V to 24V.
2
Output voltage is configurable through I C (1.5V to 7.5V
in 50mV steps) or external feedback resistors (1V to 99%
On-times (MOSFET Q1 on) are started by a fixed-
frequency clock and terminated by a PWM comparator.
See Figure 1. When an on-time ends (starting an off-time)
current conducts through the low-side MOSFET (Q2 on).
Shoot-through current from SUP to PGND is avoided by
introducing a brief period of dead time between switching
events when neither MOSFET is on. Inductor current con-
ducts through Q2's intrinsic body diode during dead time.
of V
). Factory-default voltage options of 1.8V, 3.3V,
SUP
and 5.0V are available (see the Ordering Information
table). Switching frequency in continuous conduction is
1MHz. The buck utilizes an ultra-low quiescent current
mode (1.5μA typ for 3.3V
) that maintains a very high
OUT
efficiency at light loads.
The integrated dual-input power MUX automatically
selects the higher of two different voltage sources to
power the buck converter. The MUX reduces power dissi-
pation versus common-cathode Schottky arrays by using
switches (MOSFETs) instead of diodes. The output of the
power MUX is the input to the buck (SUP). Single power
source applications should bypass the power MUX and
power SUP directly.
The PWM comparator regulates V
by controlling
OUT
duty cycle. The negative input of the PWM compara-
tor is a voltage proportional to the actual output voltage
error. The positive input is the sum of the current-sense
signal through MOSFET Q1 and a slope-compensation
ramp. The PWM comparator ends an on-time when the
error voltage becomes less than the slope-compensated
current-sense signal. On-times begin again due to a fixed-
frequency clock pulse. The controller's compensation
components and current-sense circuits are integrated.
This reduces the risk of routing sensitive control signals
on the PCB.
Dual-Input Power MUX
The device integrates a 24V power multiplexer (MUX) with
two inputs (IN1 and IN2) and one output (SUP). SUP is
the supply input for the buck. The input channels consist
of P-type MOSFETs. IN1 and IN2 are the individual FET
drains and SUP is the common FET source. An intrinsic
body-diode is always present in both FETs.
A load-line architecture is present in the controller design.
The output voltage is positioned slightly above nominal
regulation at no load and slightly below nominal regulation
at full load. As the output load changes, a small but con-
trolled amount of load regulation (load line) error occurs
on the output voltage. This voltage positioning architec-
ture allows the output voltage to respond to sudden load
transients in a critically damped manner, and effectively
reduces the amount of output capacitance needed when
compared to classical integrating controllers. See the
Typical Operating Characteristics section for information
about the converter's typical voltage regulation behavior
versus load.
The MUX connects the higher of V
or V
to SUP to
IN1
IN2
power the buck. Only the higher voltage input channel is
on. The lower voltage input channel is off. The MUX logic
is only active while the buck converter is enabled. Both
channels are off when the buck is disabled.
The selection logic has switchover hysteresis to avoid
chattering. The off channel must be 200mV higher than
the on channel to cause a switchover. Switchover is auto-
matic and can happen any time while the buck is enabled.
Equal priority is given to each input. Neither channel is
prioritized over the other.
When powering IN1 or IN2, do not connect anything to
SUP besides a decoupling capacitor. To use the buck
without the power MUX, connect IN1 and IN2 to PGND
and power SUP directly.
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
SUP
BIAS
EN
BIAS LDO
AGND
BIAS
I
LX-PEAK
ILIM
BST
SLOPE
COMPENSATION
2
REGISTERS &
CONTROL
I C SERIAL
ILIM
INTERFACE
Q1
CLOCK
PWM
V
OUT-REG
REFERENCE
S
R
Q
Q
LX
LOGIC
SOFT-START
RAMP
BIAS
Q2
g
m
OUT/FB
Z
COMP
I
ZX
I
LX-VALLEY
POK
AGND
PGND
Figure 1. Buck Control Scheme Diagram
SKIP Mode Operation
Enable Control
Raise the EN pin voltage above V
enable the IC. To disable, bring EN pin voltage to PGND.
(or tie to SUP) to
The buck converter permanently operates in SKIP mode
with the added ability to transition into a lower power
mode called standby. SKIP mode causes discontinuous
inductor current at light loads by forcing the low-side
EN_HI
2
When using I C to control the MAX77756, the EN pin
interacts with the enable bit (EN_BIT). The logical rela-
tionship between the EN pin and EN_BIT is by default an
OR. The EN_CTRL bit can be used to switch this relation-
ship to a logical AND. See Table 1.
MOSFET (Q2) off if inductor current falls below I (40mA
ZX
typ) during an off-time. This prevents inductor current
from sourcing back to the input (SUP) and enables high
efficiency by reducing the total number of switching cycles
required to regulate the output voltage.
The reset state (default state) of EN_BIT and EN_CTRL
is 0. This means that the default relationship between EN
pin and EN_BIT is a logical OR.
If the output voltage is within regulation and the load is
very light then the converter automatically transitions to
standby mode. In this mode, the LX node is high imped-
ance and the converter's internal circuit blocks are deac-
Table 1. Enable Control Truth Table
EN_CTRL
(BIT)
EN_BIT
(BIT)
REGULATOR
OUTPUT
tivated to reduce I consumption. A single, low-power
Q
EN (PIN)
comparator remains on to monitor the output voltage
during standby. When V
drops below V
(99%
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
OFF
ON
OUT
WAKE
of V
typ), the converter reactivates and starts
OUT-REG
0
switching again.
(logical OR)
ON
ON
OFF
OFF
OFF
ON
1
(logical
AND)
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Connect ILIM to a voltage above V
to program I
LX-
BIAS Regulator
An integrated 5V (V
to internal circuit blocks. This regulator is used during
startup for all versions of the MAX77756. For internal
feedback versions (no external programming resistors)
ILIM_HI
to 1000mA. While ILIM is high, I
is fixed at
PEAK
LX-PEAK
) linear regulator provides power
BIAS
1000mA and the I_PEAK[1:0] bitfield is ignored.
Short-Circiut Hiccup Mode and
Thermal Protection
The device has fault protection designed to protect itself
from abnormal conditions. If the output is overloaded,
cycle-by-cycle current limit prevents inductor current from
where V
is programmed between (and includ-
OUT-REG
ing) 3.3V and 5.0V, the BIAS regulator is deactivated and
the BIAS node is internally connected to OUT after the
output voltage is within regulation. Switching BIAS to OUT
utilizes the buck converter's efficiency to power its own
internal circuit blocks (as opposed to a linear regulator)
and improves the IC's power efficiency. For the external
feedback version of the MAX77756, the BIAS regulator is
permanently active. Do not load BIAS externally for any
MAX77756 version.
increasing beyond I
.
LX-PEAK
The buck stops switching if V
falls to less than 25%
OUT
of programmed V
and 15 consecutive on-times
OUT-REG
are ended by current limit. After switching stops, the buck
waits for t (15ms typ) before attempting to soft-start
RETRY
again (hiccup mode). While V
is less than 25% of
OUT
target, the converter prevents new on-times if the inductor
current has not fallen below I (500mA typ). This
prevents inductor current from increasing uncontrollably
due to the short-circuited output.
The BIAS regulator is on whenever the EN pin is high or
LX-VALLEY
V
IO
voltage is valid (regardless of whether the buck regu-
lator is on or off). Connect a 1μF ceramic capacitor from
BIAS and GND.
Spread-Spectrum Option
Soft-Start
Enable spread-spectrum operation by setting the S_
SPECT bit to 1. When enabled, the switching frequency
is varied ±6% centered on 1MHz. The modulation signal
is a triangle wave with a period of 256μs.
The device has an internal soft-start timer (t ) that con-
trols the ramp time of V
The soft-start feature limits inrush current during startup.
SOFT_ST programs t to 8ms or 4ms. The default value
SS
as the converter is starting.
OUT
SS
is 8ms. The converter soft-starts every time the IC is
enabled, exits a UVLO condition, and/or retries from an
overcurrent or overtemperature condition.
Register Reset Condition
The device's internal configuration registers reset to
their default values if V
falls below the UVLO falling
SUP
threshold (V
minus UVLO hysteresis, 2.6V
SUP-UVLO
Power-OK (POK) Output
typ) or if the voltage on the V pin becomes invalid (<
1.7V). Connect V to PGND to ensure that configuration
registers remain in factory-configured reset. Contact the
factory to request a version of the IC that does not reset
registers when V becomes invalid.
IO
The device features an open-drain POK output to monitor
the output voltage. POK requires an external pullup resis-
tor. POK goes high (high-impedance) after the regulator
IO
output increases above 92% (V
) of the nomi-
). POK goes low when
POK-RISING
IO
nal regulated voltage (V
OUT-REG
the regulator output drops to below 90% (V
)
Serial Interface
Overview
POK-FALLING
of V
.
OUT-REG
2
Peak Inductor Current Limit (ILIM)
The MAX77756 features a revision 3.0 I C-compatible,
2-wire serial interface consisting of a bidirectional serial
data line (SDA) and a serial clock line (SCL). The
MAX77756 acts as a slave-only devices where it relies
on the master to generate a clock signal. SCL clock
The buck converter's high-side MOSFET peak cur-
rent limit (I ) is register or pin programmable.
LX-PEAK
Applications can use I
programmability to ensure
LX-PEAK
that the converter never exceeds the saturation current
rating of the inductor on the PCB.
2
rates from 0Hz to 3.4MHz are supported. I C is an open-
drain bus, and therefore, SDA and SCL require pullups.
Optional resistors (24Ω) in series with SDA and SCL
protect the device inputs from high-voltage spikes on the
bus lines. Series resistors also minimize crosstalk and
undershoot on bus signals. For additional information
Connect ILIM to PGND to set I
to 700mA. While
LX-PEAK
ILIM is logic-low, the bits in I_PEAK[1:0] can be changed
2
through I C to program I
from 700mA to 1000mA
LX-PEAK
in 100mA steps. The value of I
returns to 700mA
LX-PEAK
(I_PEAK[1:0] = 0b00) if the configuration registers reset.
2
2
on I C, refer the I C bus specification and users manual
UM10204 that is readily available and free on the internet.
Maxim Integrated
│ 17
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
between V and the next closest capacitor (≥ 0.1μF) is
Features
IO
less than 100mΩ in series with 10nH, then a local capaci-
2
● I C Revision 3-compatible serial communications
tor is not needed. Otherwise, bypass V to PGND with a
IO
channel
0.1µF ceramic capacitor.
● 0Hz to 100kHz (standard mode)
● 0Hz to 400kHz (fast mode)
● 0Hz to 1MHz (fast mode plus)
● 0Hz to 3.4MHz (high-speed mode)
V
accepts voltages from 1.7V to 5.5V. Cycling V
2
IO
IO
resets the I C registers.
2
I C Data Transfer
One data bit is transferred during each SCL clock cycle.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while SCL
is high are control signals. See the I2C Start and Stop
Conditions section. Each transmit sequence is framed by
a START (S) condition and a STOP (P) condition. Each
data packet is nine bits long: eight bits of data followed by
the acknowledge bit. Data is transferred with the MSB first.
2
● Does not utilize I C clock stretching
2
I C System Configuration
2
The I C bus is a multimaster bus. The maximum number
of devices that can attach to the bus is only limited by bus
capacitance.
2
A device on the I C bus that sends data to the bus in
called a transmitter. A device that receives data from the
bus is called a receiver. The device that initiates a data
transfer and generates the SCL clock signals to control
the data transfer is a master. Any device that is being
addressed by the master is considered a slave. The
2
I C Start and Stop Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing
a START condition. A START condition is a high-to-low
transition on SDA with SCL high. A STOP condition is
a low-to-high transition on SDA, while SCL is high. See
Figure 3.
2
MAX77756 I C-compatible interface operates as a slave
on the I C bus with transmit and receive capabilities.
2
2
I C Interface Power
A START condition from the master signals the beginning
of a transmission to the MAX77756. The master termi-
nates transmission by issuing a not acknowledge (nA)
followed by a STOP condition. See the I2C Acknowledge
Bit section for information on not acknowledge. The STOP
2
The IC's I C interface derives its power from V
Typically, a power input such as V requires a local
0.1μF ceramic bypass capacitor to ground. However,
in highly-integrated power distribution systems, a dedi-
cated capacitor might not be necessary. If the impedance
.
IO
IO
SDA
SCL
MASTER
SLAVE
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER
TRANSMITTER/
RECEIVER
RECEIVER
2
Figure 2. I C System Configuration
S
Sr
P
SDA
tSU;STA
tSU;STO
SCL
tHD;STA
tHD;STA
2
Figure 3. I C Start and Stop Conditions
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
condition frees the bus. To issue a series of commands to
the slave, the master can issue repeated start (Sr) com-
mands instead of a STOP command to maintain control of
the bus. In general, a repeated start command is function-
ally equivalent to a regular start command.
Monitoring the acknowledge bits allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communication
at a later time.
When a STOP condition or incorrect address is detected,
the IC disconnects SCL from the serial interface until
the next START condition, minimizing digital noise and
feedthrough.
The MAX77756 issues an ACK for all register addresses
in the possible address space even if the particular
register does not exist.
2
2
I C Acknowledge Bit
I C Slave Address
2
2
Both the I C bus master and the MAX77756 (slave)
The I C controller implements 7-bit slave addressing in
2
generate acknowledge bits when receiving data. The
acknowledge bit is the last bit of each nine bit data packet.
To generate an acknowledge (A), the receiving device
must pull SDA low before the rising edge of the acknowl-
edge-related clock pulse (ninth pulse) and keep it low
during the high period of the clock pulse. See Figure 4.
To generate a not acknowledge (nA), the receiving device
allows SDA to be pulled high before the rising edge of the
acknowledge-related clock pulse and leaves it high during
the high period of the clock pulse.
Table 2. An I C bus master initiates communication with
the slave by issuing a START condition followed by the
slave address. See Figure 5.
2
I C Clock Stretching
2
In general, the clock signal generation for the I C bus is
the responsibility of the master device. The I C specifica-
2
tion allows slow slave devices to alter the clock signal by
holding down the clock line. The process in which a slave
device holds down the clock line is typically called clock
stretching. The IC does not use any form of clock stretch-
ing to hold down the clock line.
NOT ACKNOWLEDGE (NA)
ACKNOWLEDGE (A)
S
SDA
tSU;DAT
tHD;DAT
1
2
8
9
SCL
Figure 4. Acknowledge Bit
2
Table 2. I C Slave Address Options
7-BIT SLAVE ADDRESS
8-BIT WRITE ADDRESS
8-BIT READ ADDRESS
0x1E, 0b 001 1110
0x3C, 0b 0011 1100
0x3D, 0b 0011 1101
S
0
1
0
2
1
3
1
4
1
5
1
6
0
7
R/W
A
9
SDA
SCL
ACKNOWLEDGE
8
Figure 5. Slave Address Example
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
2
2
● The I C slave must use a different set of input filters
I C Communication Speed
on its SDA and SCL lines to accommodate for the
faster bus.
The MAX77756 is compatible with all 4 communication
speed ranges as defined by the Revision 3 I C specification:
2
● The communication protocols need to utilize the high-
● 0Hz to 100kHz (standard mode)
● 0Hz to 400kHz (fast mode)
● 0Hz to 1MHz (fast mode)
speed master code.
At power-up and after each stop condition, the IC input
filters are set for standard mode, fast mode, or fast mode
plus (i.e., 0Hz to 1MHz). To switch the input filters for high-
speed mode, use the high-speed master code protocols
● 0Hz to 3.4MHz (high-speed mode)
Operating in standard mode, fast mode, and fast mode
plus does not require any special protocols. The main
consideration when changing the bus speed through this
range is the combination of the bus capacitance and pul-
lup resistors. Higher time constants created by the bus
capacitance and pullup resistance (C x R) slow the bus
operation. Therefore, when increasing bus speeds, the
pullup resistance must be decreased to maintain a rea-
sonable time constant. Refer to the Pullup Resistor Sizing
2
that are described in the I C Communication Protocols
section.
2
I C Communication Protocols
The IC supports both writing and reading from its registers.
Writing to a Single Register
2
Figure 6 shows the protocol for the I C master device to
write one byte of data to the MAX77756. This protocol is
the same as the SMBus specification’s write byte proto-
col. The write byte protocol is as follows:
2
section of the I C Revision 3.0 specification (UM10204)
for detailed guidance on the pullup resistor selection. In
general for bus capacitances of 200pF, a 100kHz bus
needs 5.6kΩ pullup resistors, a 400kHz bus needs about
a 1.5kΩ pullup resistors, and a 1MHz bus needs 680Ω
pullup resistors. Note that when the open-drain bus is low,
the pullup resistor is dissipating power, lower value pullup
resistors dissipate more power.
1) The master sends a start command (S).
2) The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
3) The addressed slave asserts an acknowledge (A) by
pulling SDA low.
Operating in high-speed mode requires some special
considerations. The major considerations with respect to
the IC:
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
2
● The I C bus master use current source pullups to
7) The slave updates with the new data.
shorten the signal rise.
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
NUMBER
OF BITS
1
7
1
0
1
8
1
8
1
1
S
SLAVE ADDRESS
A
REGISTER POINTER
A
DATA
A OR NA P OR SR*
R/W
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE.
SDA
SCL
B1
7
B0
A
9
ACKNOWLEDGE
8
*P FORCES THE BUS FILTERS TO
SWITCH TO THEIR ≤ 1MHZ MODE.
SR LEAVES THE BUS FILTERS IN
THEIR CURRENT STATE.
Figure 6. Writing to a Single Register with the Write Byte Protocol
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
8) The slave acknowledges or does not acknowledge the
data byte. The next rising edge on SDA loads the data
byte into its target register and the data becomes active.
3) The addressed slave asserts an acknowledge (A) by
pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
9) The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a P ensures that the bus in-
put filters are set for 1MHz or slower operation. Issuing
an Sr leaves the bus input filters in their current state.
7) The slave acknowledges the data byte. The next ris-
ing edge on SDA loads the data byte into its target
register and the data becomes active.
Writing Multiple Bytes to Sequential Registers
Figure 7 shows the protocol for writing to a sequential
registers. This protocol is similar to the write byte proto-
col above, except the master continues to write after it
receives the first byte of data. When the master is done
writing it issues a stop or repeated start.The writing to
sequential registers protocol is as follows:
8) Steps 6 to 7 are repeated as many times as the master
requires.
9) During the last acknowledge related clock pulse,
the master can issue an acknowledge or a not
acknowledge.
1) The master sends a start command (S).
10) The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a P ensures that the bus in-
put filters are set for 1MHz or slower operation. Issuing
an Sr leaves the bus input filters in their current state.
2) The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
NUMBER
OF BITS
1
7
1
0
1
8
1
8
1
S
SLAVE ADDRESS
A
REGISTER POINTER X
A
DATA X
A
Α
Α
R/W
NUMBER
OF BITS
8
1
8
1
DATA X+1
A
DATA X+2
A
Α
Α
REGISTER POINTER = X + 2
REGISTER POINTER = X + 1
8
NUMBER
OF BITS
1
8
1
1
A OR
NA
P OR
SR*
DATA N-1
A
DATA N
Β
REGISTER POINTER = X + (N-2)
REGISTER POINTER = X + (N-1)
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE.
SDA
SCL
B1
7
B0
A
9
B9
1
ACKNOWLEDGE
8
DETAIL: Α
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE.
SDA
SCL
B1
7
B0
A
9
*P FORCES THE BUS
FILTERS TO SWITCH
TO THEIR ≤ 1MHZ
MODE. SR LEAVES
THE BUS FILTERS IN
THEIR CURRENT
STATE.
ACKNOWLEDGE
8
DETAIL: Β
Figure 7. Writing to Sequential Registers X to N
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
10) The master issues a not acknowledge (nA).
Reading from a Single Register
2
Figure 8 shows the protocol for the I C master device to
read one byte of data to the MAX77756. This protocol is
the same as the SMBus specification’s read byte protocol.
The read byte protocol is as follows:
11) The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a P ensures that the bus in-
put filters are set for 1MHz or slower operation. Issuing
an Sr leaves the bus input filters in their current state.
1) The master sends a start command (S).
Note that when the the IC receives a stop, it does not
modify its register pointer.
2) The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
Reading from Sequential Registers
3) The addressed slave asserts an acknowledge (A) by
pulling SDA low.
Figure 9 shows the protocol for reading from sequential
registers. This protocol is similar to the read byte protocol
except the master issues an acknowledge to signal the
slave that it wants more data: when the master has all
the data it requires it issues a not acknowledge (nA) and
a stop (P) to end the transmission.The continuous read
from sequential registers protocol is as follows:
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a repeated start command (Sr).
7) The master sends the 7-bit slave address followed by
a read bit (R/W = 1).
1) The master sends a start command (S).
8) The addressed slave asserts an acknowledge by pull-
ing SDA low.
2) The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
9) The addressed slave places 8 bits of data on the bus
3) The addressed slave asserts an acknowledge (A) by
pulling SDA low.
from the location specified by the register pointer.
*P FORCES THE BUS FILTERS TO
SWITCH TO THEIR ≤ 1MHZ MODE.
SR LEAVES THE BUS FILTERS IN
THEIR CURRENT STATE.
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
8
NUMBER
OF BITS
1
7
1
0
1
1
1
7
1
1
1
8
1
1
S
SLAVE ADDRESS
A
REGISTER POINTER X A Sr SLAVE ADDRESS
A
DATA X
nA P OR Sr*
R/W
R/W
Figure 8. Reading from a Single Register with the Read Byte Protocol
*P FORCES THE BUS FILTERS TO
SWITCH TO THEIR ≤ 1MHZ MODE.
SR LEAVES THE BUS FILTERS IN
THEIR CURRENT STATE.
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
8
NUMBER
OF BITS
1
7
1
0
1
1
1
7
1
1
8
1
S
SLAVE ADDRESS
A
REGISTER POINTER X A SR SLAVE ADDRESS
1
A
DATA X
A
R/W
R/W
NUMBER
OF BITS
8
1
8
1
8
1
DATA X+1
A
DATA X+2
A
DATA X+3
A
REGISTER POINTER = X + 1 REGISTER POINTER = X + 2 REGISTER POINTER = X + 3
NUMBER
OF BITS
8
1
8
1
8
1
1
P OR
SR*
DATA N-2
A
DATA N-1
A
DATA N
NA
REGISTER
POINTER = N - 2
REGISTER
POINTER = N - 1
REGISTER POINTER = N
Figure 9. Reading Continuously from Sequential Registers X to N
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a repeated start command (Sr).
Note that when the the IC receives a stop it does not
modify its register pointer.
Engaging High-Speed (HS) Mode for Operation
Up to 3.4MHz
7) The master sends the 7-bit slave address followed by
a read bit (R/W = 1). When reading the RTC time-
keeping registers, secondary buffers are loaded with
the timekeeping register data during this operation.
Figure 10 shows the protocol for engaging HS mode
operation. HS mode operation allows for a bus operating
speed up to 3.4MHz.The procedure to engage HS mode
protocol is as follows:
8) The addressed slave asserts an acknowledge by pull-
ing SDA low.
● Begin the protocol while operating at a bus speed of
1MHz or lower.
9) The addressed slave places 8 bits of data on the bus
● The master sends a start command (S).
from the location specified by the register pointer.
● The master sends the 8-bit master code of 0b0000
10) The master issues an acknowledge (A) signaling the
slave that it wishes to receive more data.
1XXX where 0bXXX are don’t care bits.
● The addressed slave issues a not acknowledge (nA).
11) Steps 9 to 10 are repeated as many times as the mas-
ter requires. Following the last byte of data, the mas-
ter must issue a not acknowledge (nA) to signal that it
wishes to stop receiving data.
● The master can now increase its bus speed up to
3.4MHz and issue any read/write operation.
The master can continue to issue high-speed read/write
operations until a stop (P) is issued. Use repeated start
(Sr) to continue operations in high speed mode.
12) The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a stop (P) ensures that
the bus input filters are set for 1MHz or slower opera-
tion. Issuing an Sr leaves the bus input filters in their
current state.
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
1
8
1
1
ANY R/W PROTOCOL
FOLLOWED BY SR
ANY R/W PROTOCOL
FOLLOWED BY SR
ANY READ/WRITE
PROTOCOL
S
HS MASTER CODE
nA SR
SR
SR
P
FAST MODE
HS MODE
FAST MODE
Figure 10. Engaging HS Mode
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Register Map
MAX77756
ADDRESS
NAME
MSB
LSB
Configuration Registers
0x00
0x01
CONFIG_A[7:0]
CONFIG_B[7:0]
S_SPECT SOFT_ST
I_PEAK[1:0]
RSVD
RSVD
EN_CTRL
EN_BIT
V_OUTREG[7:0]
CONFIG_A (0x00)
BIT
7
6
5
4
3
2
1
0
EN_BIT
0
Field
S_SPECT
0
SOFT_ST
0
I_PEAK[1:0]
00
RSVD
OTP
RSVD
0
EN_CTRL
Reset
0
Access Type Write, Read Write, Read
Write, Read
Read Only
Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0 = Spread-spectrum modulation off
1 = Spread-spectrum modulation on
S_SPECT
7
Spread-spectrum modulation enable control.
Soft-start control. Sets the regulator's startup
ramp time (t ).
SS
0 = 8ms
1 = 4ms
SOFT_ST
I_PEAK
6
High-side DMOS peak current limit threshold
00 = 700mA
01 = 800mA
10 = 900mA
11 = 1000mA
control. Sets peak LX current (I
) only
LX-PEAK
5:4
while the ILIM pin is low. See Peak Inductor
Current Limit (ILIM) for details.
RSVD
RSVD
3
2
Factory-set control bit. Writes are ignored.
Reserved control bit. Write to 0.
N/A
N/A
Enable logic control bit.
Determines the logical relationship between the
EN_BIT (enable bit) and EN (enable pin).
0 = Logical OR relationship
1 = Logical AND relationship
EN_CTRL
EN_BIT
1
0
0 = Disabled
1 = Enabled
Regulator enable bit.
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
CONFIG_B (0x01)
BIT
Field
7
6
5
4
3
2
1
0
V_OUTREG[7:0]
Reset
0x06 / 0x24 / 0x46 (See Ordering Information)
Access Type
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x00 = 1.5V
0x01 = 1.55V
0x02 = 1.6V
.
.
0x24 = 3.3V
.
.
Output Voltage Control. Programmable in
50mV per LSB from 0x00 (1.5V) to 0x78 (7.5V).
Restrict writes to this register between 0x00
and 0x78. Do not program this register with
codes outside this range.
V_OUTREG
7:0
This register is a don't care for the external
feedback version (MAX77756D).
0x46 = 5.0V
.
.
0x78 = 7.5V
capacitors with X5R or X7R dielectric are highly recom-
mended due to their small size, low ESR, and small tem-
perature coefficients.
Applications Information
IN1/IN2/SUP Capacitor Selection
For dual-input applications, connect separate voltage
supplies to IN1 and IN2 and bypass IN1 (C ) and IN2
Choose the C /C /C
capacitor voltage rating to be
IN1 IN2 SUP
IN1
greater than the expected input voltage of the system. For
systems using the full input voltage range (24V max) of
the MAX77756, choose capacitors rated to 25V or greater.
(C ) to PGND with 2.2μF ceramic capacitors. Bypass
IN2
SUP to PGND with a 1μF ceramic capacitor (C
).
SUP
The C
capacitor adds with the C /C
capacitor
SUP
IN1 IN2
All ceramic capacitors derate with DC bias voltage
(effective capacitance goes down as DC bias goes up).
Generally, small case size capacitors derate heavily com-
pared to larger case sizes (0603 case size performs bet-
ter than 0402). Consider the effective capacitance value
carefully by consulting the manufacturer's data sheet.
to decouple the input of the buck. Larger values of C
SUP
improve decoupling, but increase inrush current from
IN1 or IN2 to SUP when a power source is connected.
Limit IN1/IN2 inrush current to 4.1A. See the Absolute
Maximum Ratings section for more information.
For single input applications that do not utilize IN1 and
IN2, choose C
to be a 2.2μF nominal capacitor that
Output Capacitor Selection
SUP
maintains a 1μF effective capacitance at its working volt-
age. Larger values improve the decoupling for the buck
regulator, but increase inrush current from the voltage
supply when connected. Connect IN1 and IN2 to PGND
to force the power MUX selection logic off for applications
that require no selector.
Choose the output bypass capacitance (C
) to be
OUT
22μF. Larger values of C
improve load transient
OUT
performance, but increase the input surge currents dur-
ing soft-start and output voltage changes. The output
filter capacitor must have low enough ESR to meet
output ripple and load transient requirements. The output
capacitance must be high enough to absorb the induc-
tor energy while transitioning from full-load to no load
conditions. When using high-capacitance, low-ESR
capacitors, the filter capacitor’s ESR dominates the
output voltage ripple in continuous conduction mode.
C
/C
IN1 IN2
plus C
reduces the current peaks drawn
SUP
from the input power source during buck operation and
reduces switching noise in the system. The ESR/ESL of
C
and its series PCB traces should be very low (i.e.,
SUP
< 15mΩ + < 2nH) for frequencies up to 2MHz. Ceramic
Maxim Integrated
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Therefore, the size of the output capacitor depends on the
Use Equation 2 and Equation 3 to compute I
. If
PEAK
maximum ESR required to meet the output voltage ripple
I
is greater than I
then increase the inductor
PEAK
LX-PEAK
(V
) specifications:
value. For V
≤ 5V, a 10μH inductor is suitable across
RIPPLE(P-P)
OUT
the entire input voltage range for 500mA maximum DC
load.
V
= ESR × I × LIR
LOAD
RIPPLE P − P
(
)
Equation 2:
where LIR is the inductor's ripple current to average cur-
rent ratio. Compute LIR with Equation 1.
V
× V − V
(
)
OUT
V
IN
OUT
I
=
P − P
Equation 1:
× f
× L
IN SW
Equation 3:
V
×
f
V
− V
(
)
OUT
×
IN
x
OUT
LIR
=
I
P−P
2
V
I
x
L
IN
SW
LOAD
I
= I
+
PEAK
LOAD
where I
is the buck's output current in the particular
LOAD
where I
is the buck's output current in the particular
LOAD
application (500mA max), V is the application's input
voltage, and f
IN
application (500mA max), V is the application's largest
expected input voltage (24V max), and f
IN
is 1MHz.
SW
is 1MHz.
SW
Ceramic capacitors with X5R or X7R dielectric are highly
recommended due to their small size, low ESR, and small
temperature coefficients. All ceramic capacitors derate
with DC bias voltage (effective capacitance goes down as
DC bias goes up). Generally, small case size capacitors
derate heavily compared to larger case sizes (0603 case
size performs better than 0402). Consider the effective
capacitance value carefully by consulting the manufac-
turer's data sheet.
Limiting the Peak Inrush Current
The peak inrush current from IN1 or IN2 to SUP must be
limited to less than 4.1A. This can be achieved by reduc-
ing the slew rate of the input voltage applied to IN1 or IN2,
and/or reducing the value of the SUP capacitor. The peak
inrush current through the input power MUX when voltage
is applied to IN1 or IN2 is calculated with Equation 4.
Equation 4:
Inductor Selection
Choose an inductor with a saturation current that is
greater than or equal to the the maximum peak current
dV
IN
dt
I
=
C
SUP
INRUSH
where I
is the peak inrush current, C
SUP capacitance value, and dV /dt is the slew rate of the
input voltage on IN1 or IN2. For example, given the fol-
lowing conditions, the peak input current (I
voltage application is 500mA:
is the
SUP
INRUSH
limit setting (I
). Inductors with lower saturation
LX-PEAK
IN
current and higher DCR ratings are physically small.
Higher values of DCR reduce buck efficiency. Choose the
RMS current rating of the inductor (the current at which
the temperature rises appreciably) based on the system's
expected load current.
) upon
INRUSH
Given:
● C
= 1μF
Choose an inductor value based on the V
See Table 3.
setting.
SUP
OUT
● dV /dt = 500mV/μs
IN
The chosen inductor value should ensure that the peak
inductor ripple current (I ) is below the high-side
Calculation:
500mV
μs
= 500mA
PEAK
● I
● I
=
1μF
INRUSH
MOSFET peak current limit (I
can maintain regulation.
) so that the buck
LX-PEAK
INRUSH
It is not recommended to "hot insert" the input with a
precharged voltage source. The voltage slew rate of a
hot insertion is very fast and can cause inrush currents in
excess of 4.1A.
Table 3. Inductor Value vs. Output Voltage
MINIMUM INDUCTOR
V
RANGE
OUT
VALUE (μH)
V
≤ 5V
10
15
22
33
47
OUT
5V < V
≤ 7.5V
OUT
7.5V < V
≤ 11V
≤ 17V
OUT
11V < V
OUT
V
OUT
> 17V
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MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Setting the Output Voltage (MAX77756D)
PCB Layout Guidelines
The external feedback version of the device (MAX77756D)
uses resistors to set the output voltage between 1V and
99% of the input voltage. Connect a resistor divider
Careful circuit board layout is critical to achieve low-
switching power losses and clean, stable operation.
Figure 12 shows a sketch of an example PCB top-metal
layout.
between V
, OUT/FB, and AGND as shown in Figure
OUT
11. Choose R
equal to 100kΩ. Calculate the value of R
OUT/FB) for a desired output voltage with Equation 5.
(OUT/FB to AGND) to be less than or
BOT
When designing the PCB, follow these guidelines:
(V
to
TOP
OUT
1) The SUP capacitor should be placed immediately next
to the SUP pin of the device. Since the device oper-
ates at 1MHz switching frequency, this placement is
critical for effective decoupling of high-frequency
noise from the SUP pin.
Equation 5:
V
OUT
R
= R
×
− 1
TOP
BOT
V
FB
2) Similarly, the input capacitors (C
C
) should be
IN1/ IN2
placed immediately next to their respective input pins.
where V is 1V and V
is the desired output voltage.
FB
OUT
3) Place the inductor and output capacitor close to the
part and keep the loop area small.
For the internal feedback versions (MAX77756A/
MAX77756B/MAX77756C) change the bits in V_
OUTREG[7:0] to program the output voltage between 1V
and 7.5V in 50mV steps per LSB.
4) Make the trace between LX and the inductor short and
wide. Do not to take up an excessive amount of area.
The voltage on this node is switching very quickly and
additional area creates more radiated emissions.
V
OUT
R
MAX77756D
5) Connect PGND and AGND together at the return ter-
minal of the output capacitor. Do not connect them
anywhere else.
TOP
OUT/FB
6) Keep the power traces and load connections short
R
BOT
and wide. This practice is essential for high efficiency.
7) Place the BIAS capacitor ground next to the AGND
pin and connect with a short and wide trace.
Figure 11. External Feedback Resistors
LX
OUT
10μH
2520
IN1
C
SUP
GND
C
IN1
OUT
GND
C
VIO
LEGEND
0603
C
IN2
POK
C
BIAS
IN2
R
PU
0402
0201
Figure 12. PCB Top-Metal and Component Layout Example
Maxim Integrated
│ 27
www.maximintegrated.com
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
● Low IQ consumption (19μA typ for dual-input) enables
the device to remain always-on. This extends battery
life and functionality by enabling the PD port control-
ler to monitor plug attachment while the gadget is in
sleep/hibernate state.
Powering USB Type-C Power Delivery
Port Controllers
The MAX77756 is ideal for battery-powered systems/
gadgets that use USB type-C with power delivery (PD)
to charge. These systems require a PD port controller to
monitor device attachment to the USB port, determine
roles of the attached device, and negotiate for PD volt-
ages. See Figure 13. Applications that use the MAX77756
to power the PD controller benefit in the following ways:
● 3V–24V input voltage range allows the device to
power the port controller over the entire PD voltage
range.
● Hardware or software enable allows flexible control
● Dual-input power MUX allows the device to power
from VBUS or BATT ensuring the load is always
powered. This enables PD negotiation even if the gad-
get battery is dead.
from a host processor.
For more information on USB type-C PD, refer to the
USB website and specification documents that are readily
available and free on the internet.
5V, 9V, 12V, 20V TYPICAL
VBUS
D+
2.2μF
D−
TO HOST
SYSTEM
TXn
RXn
SUP
BUS INPUT
1μF
IN1
IN2
EN
3.0V TO 24V
BST
BATT INPUT
0.1μF
OUTPUT
3.3V, 500mA MAX
2.2μF
MAX77756B
10μH
CC1
CC2
LX
VDD
USB TYPE-C
OUT
3x22μF
PORT CONTROLLER WITH
POWER-DELIVERY (PD)
PGND
100kΩ
ILIM
POK
nRST
GND
1S, 2S, 3S
OR 4S Li+
BATTERY
BIAS
1μF
V
IO
TO HOST
SYSTEM
SCL
SDA
AGND
Figure 13. USB Type-C PD Port Controller Power Supply
Maxim Integrated
│ 28
www.maximintegrated.com
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Backup Power for Always-On Clocks and Sensors
The MAX77756’s integrated dual-input power MUX is ideal for providing backup power to critical always-on circuits such
as motion sensors, light curtains, and real-time clocks (RTCs). See Figure 14. If primary power is suddenly removed, the
buck input seamlessly transitions to backup power. V
is nearly unaffected by the transition. See Figure 15.
OUT
18V SOLAR CELL ARRAY
OR 12V PRIMARY BATTERY STACK
SUP
EN
PRIMARY INPUT
BACKUP INPUT
1μF
IN1
IN2
3.0V TO 24V
BST
2.2μF
0.1μF
OUTPUT
2.2μF
MAX77756B
10μH
3.3V, 500mA MAX
LX
VDD
OUT
3x22μF
6V BACKUP
BATTERY
COIN CELL STACK
REAL-TIME CLOCK (RTC)
PGND
MOTION SENSOR
ALWAYS-ON CIRCUIT
ILIM
POK
BIAS
GND
1μF
V
IO
SCL
SDA
AGND
Figure 14. Uninterruptible Power Supply for Always-On Circuit
Figure 15. Switchover to Backup Power after Sudden Unplug
Maxim Integrated
│ 29
www.maximintegrated.com
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Select a battery charger with automatic input-current
limiting (AICL) or minimum input-voltage regulation. The
MAX8971 switch-mode charger with AICL regulates a
minimum input (USB) voltage by reducing the charge cur-
rent into the cell. This preserves a stable USB source for
the device while charging the battery with residual power
not used by the load.
Creating an Instant-On System
The MAX77756 can be used to implement an instant-on
battery charging system. See Figure 16.
● The battery charger (MAX8971 or similar) charges the
cell from USB power.
● The dual-input power MUX selects the higher-voltage
(USB) to power the buck.
This system can be extended beyond a single Li+ cell in
USB type-C power delivery applications.
● USB continues to power the buck even after the bat-
tery is finished charging.
● The the device switches over to BATT power when
USB disconnects.
VBUS
BUS INPUT
2.2μF
SUP
1μF
IN1
IN2
EN
3.0V TO 24V
BST
BATTERY CHARGER
MAX8971 OR SIMILAR
0.1μF
OUTPUT
3.3V, 500mA MAX
MAX77756B
10μH
LX
OUT
3x22μF
BATT INPUT
PGND
LOAD
2.2μF
ILIM
POK
Li+ BATTERY
BIAS
1μF
V
IO
SCL
SDA
AGND
Figure 16. Simple Instant-On Battery System
Maxim Integrated
│ 30
www.maximintegrated.com
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Typical Application Circuits
Always-On (EN = SUP), Dual-Input, Internal Voltage Feedback
SUP
DC SOURCE 1
DC SOURCE 2
IN1
IN2
C
1μF
SUP
3V TO 24V
2.2μF
25V (0603)
V
BST
OUT
1.8V/3.3V/5.0V
C
BST
MAX77756A
MAX77756B
MAX77756C
L 10μH
C
2.2μF
C
IN1
IN2
0.1μF 10V
(0402)
25V (0402)
25V (0402)
1A (2520)
SAT
LX
C
3x22μF
OUT
SUP
10V (0603)
OUT
BIAS
EN
V
IO
C
BIAS
1μF
6V (0402)
R
PU
SDA
SCL
100k (0402)
ILIM
POK
POWER OK
AGND
PGND
I2C Control, Dual-Input, Internal Voltage Feedback
SUP
BST
DC SOURCE 1
DC SOURCE 2
IN1
IN2
C
1μF
SUP
V
OUT
3V TO 24V
2.2μF
25V (0603)
1.8V/3.3V/5.0V OR
PROGRAMMABLE 1.5V – 10V
C
BST
MAX77756A
MAX77756B
MAX77756C
L 10μH
C
2.2μF
C
IN1
IN2
0.1μF 10V
(0402)
25V (0402)
25V (0402)
1A (2520)
SAT
LX
C
3x22μF
OUT
C
0.1μF
VIO
10V (0603)
OUT
BIAS
6V (0402)
EN
V
IO
C
1μF
BIAS
6V (0402)
SERIAL
HOST
R
PU
SDA
SCL
100k (0402)
ILIM
POK
POWER OK
AGND
PGND
Maxim Integrated
│ 31
www.maximintegrated.com
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Typical Application Circuits (continued)
EN Pin Control, Single-Input (Power MUX Bypassed), Internal Voltage Feedback
3.0V TO 24V
DC SOURCE
SUP
IN1
IN2
C
2.2μF
SUP
25V (0603)
V
OUT
1.8V/3.3V/5.0V
BST
C
BST
MAX77756A
MAX77756B
MAX77756C
L 10μH
0.1μF 10V
(0402)
1A (2520)
SAT
LX
C
3x22μF
OUT
10V (0603)
OUT
BIAS
EN
ENABLE
V
IO
C
BIAS
1μF
6V (0402)
R
PU
SDA
SCL
100k (0402)
ILIM
POK
POWER OK
AGND
PGND
EN Pin Control, Dual-Input, External Voltage Feedback
SUP
DC SOURCE 1
DC SOURCE 2
IN1
IN2
C
1μF
SUP
3V TO 24V
2.2μF
25V (0603)
V
OUT
1V – 99%VSUP
BST
C
BST
L 10μH
C
2.2μF
C
IN1
IN2
0.1μF 10V
(0402)
MAX77756D
1A (2520)
SAT
25V (0402)
25V (0402)
LX
C
OUT
R
varies
(0402)
TOP
C
5pF
FF
3x22μF 10V
(0603)
(0402)
FB
R
50kΩ
(0402)
BOT
ENABLE
EN
BIAS
C
1μF
BIAS
VIO
6V (0402)
R
PU
SDA
SCL
100k (0402)
ILIM
POK
POWER OK
AGND
PGND
Maxim Integrated
│ 32
www.maximintegrated.com
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Ordering Information
PART
VOLTAGE FEEDBACK
Internal
OUTPUT VOLTAGE (V
)
OUT-REG
MAX77756AEWL+
MAX77756BEWL+
MAX77756CEWL+
MAX77756DEWL+
1.8V
3.3V
5.0V
Internal
Internal
External
N/A (set by feedback resistors)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Maxim Integrated
│ 33
www.maximintegrated.com
MAX77756
24V Input, 500mA Buck Regulator
with Dual-Input Power MUX
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
4/17
Initial release
—
Updated Benefits and Features, added Note 3, updated Figure 9, updated Inductor
Selection section and added Table 3, replaced Figure 12, added three new sections
with application diagrams to Applications Information section, replaced Typical
Application Circuits
1–7, 15, 17,
22, 25–31
1
10/17
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2017 Maxim Integrated Products, Inc.
│ 34
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