MAX77813 [MAXIM]
5.5V Input, 2A, High-Efficiency Buck-Boost Converter;
| 型号： | MAX77813 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 5.5V Input, 2A, High-Efficiency Buck-Boost Converter |
| 文件： | 总30页 (文件大小：1169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
General Description
Features and Benefits
The MAX77813 is a high-efficiency step-up/step-down
(buck-boost) converter targeted for single-cell Li+/Li-ion
battery powered applications. The device maintains a
regulated output voltage from 2.6V to 5.14V across an
input voltage range of 2.3V to 5.5V. The device supports
up to 2A of output current in boost mode and up to 3A in
buck mode.
● V Range: 2.30V to 5.5V
IN
● V
Range: 2.60V to 5.14V
OUT
2
(I C Programmable in 20mV Steps)
● Up to 2A Output Current in Boost Mode
(V = 3.0V, V
= 3.4V, ILIM = High)
IN
OUT
● Up to 3A Output Current in Buck Mode (ILIM = High)
● Up to 97% Peak Efficiency
The device seamlessly transitions between buck and
boost modes. A unique control algorithm allows high-
efficiency, outstanding load, and line transient response.
● SKIP Mode for Optimal Light Load Efficiency
● 55µA (Typ) Low Quiescent Current
Dedicated enable and power-OK pins allow simple hard-
2
● 3.4MHz High Speed I C Serial Interface
2
ware control. An I C serial interface is optionally used for
● Input Current Limit Selection Pin
● Power-OK Output
dynamic voltage scaling, system power optimization, and
fault read-back. The device supports two inductor current
limit options selected by the ILIM pin.
● 2.5MHz Switching Frequency
The MAX77813 is available in a 20-bump, 1.83mm x
2.13mm wafer-level package (WLP).
● Protection Features
• Soft-Start
• Thermal Shutdown
• Overvoltage Protection
• Overcurrent Protection
Applications
● Single-Cell Li+/Li-ion Battery Powered Devices
● Handheld Scanners, Mobile Payment Terminals,
Security Cameras
● 1.827mm x 2.127mm, 20-Bump WLP
● AR/VR Headsets
Ordering Information appears at end of data sheet.
Typical Application Circuit
1μH
BOOST TO BUCK
LINE TRANSIENT RESPONSE
LX1
MAX77813
LX2
IOUT = 1.5A
DC INPUT
2.3V TO 5.5V
IN
V
OUT
V
OUT
VOUT = 3.3V
3.4V
2.6V TO 5.14V
2A (BOOST MODE)
3A (BUCK MODE)
10μF
SYS
47μF
2.9V
OUTS
PGND
1μF
500mV/div
20mV/div
V
IN
BOOST
MODE
BOOST
MODE
BUCK MODE
V
IO
SERIAL
HOST
SDA
SCL
EN
V
OUT
POWER-OK
POK
ILIM
CURRENT LIMIT
SELECT
ENABLE
100µs/div
HIGH-EFFICIENCY BUCK-BOOST CONVERTER
2
WITH OPTIONAL I C CONTROL IN TINY 20-BUMP WLP
19-8238; Rev 2; 3/19
MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Absolute Maximum Ratings
SYS, V to GND .................................................-0.3V to +6.0V
LX2 to PGND..........................................-0.3V to (V
+ 0.3V)
IO
OUT
IN, OUT to PGND.................................................-0.3V to +6.0V
PGND to GND......................................................-0.3V to +0.3V
LX1/LX2 Continuous RMS Current (Note 1)........................3.2A
Operating Junction Temperature Range .......... -40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -65°C to +150°C
Soldering Temperature (Reflow)......................................+260°C
SCL, SDA to GND..................................... -0.3V to (V + 0.3V)
IO
EN, ILIM, POK to GND........................... -0.3V to (V
FB to GND..............................................-0.3V to (V
+ 0.3V)
+ 0.3V)
SYS
OUT
LX1 to PGND..............................................-0.3V to (V + 0.3V)
IN
Note 1: LX1 and LX2 nodes have internal clamp diodes to PGNDBB and INBB. Applications that forward bias to these diodes should
ensure that the total power loss does not exceed the power dissipation limit of the IC package.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
WLP
Package Code
W201F2+1
Outline Number
21-0771
Land Pattern Number
Refer to Application Note 1891
Thermal Resistance, Four-Layer Board:
Junction to Ambient Thermal Resistance (θ
)
55.49°C/W
JA
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Buck-Boost Electrical Characteristics
(V
= V = +3.8V, V
= V
= +3.3V, T = -40°C to +125°C, typical values are at T ≈ T = +25°C, unless otherwise noted.)
SYS
IN
OUTS
OUT J A J
(Note 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL
Input Voltage Range
V
2.30
5.50
V
IN
I
EN = low, T = +25°C
0.1
1
SHDN_25C
J
Shutdown Supply Current
Input Supply Current
µA
I
EN = low, T = +125°C
J
SHDN_125C
SKIP mode, no switching,
T = -40° to +85°C
J
I
55
70
µA
Q_SKIP
I
FPWM mode, no load
6
mA
Ω
Q_PWM
Active Discharge Resistance
Thermal Shutdown Threshold
H-BRIDGE
R
100
+165
DISCHG
T
Rising, +20°C hysteresis
°C
SHDN
2
Output Voltage Range
V
I C programmable (20mV Step)
2.60
-1.0
5.14
+1.0
V
OUT
FPWM mode, VOUT[6:0] = 0x28, no load,
V
OUT_ACC1
T = +25°C
J
Output Voltage Accuracy
%
SKIP mode, VOUT[6:0] = 0x28,
no load, T = +25°C
V
-1.0
+4.5
OUT_ACC2
J
Line Regulation
Load Regulation
V
= 2.63V to 5.5V
0.200
0.125
%/V
%/A
IN
(Note 5)
I
= 1.0A, V changes from 3.4V to
OUT
IN
V
V
OS1
US1
Line Transient Response
Load Transient Response
2.9V in 25µs (20mV/µs),
L = 1µH, C = 47µF (Note 5)
50
50
mV
mV
OUT_NOM
V
= 3.4V, I
changes from 10mA to
OUT
IN
V
V
OS2
US2
1.5A in 15µs, L = 1µH, C
(Note 5)
= 47µF
OUT_NOM
BB_RU_SR = 0
BB_RU_SR = 1
BB_RD_SR = 0
BB_RD_SR = 1
20
40
5
Output Voltage Ramp-Up
Slew Rate
mV/µs
mV/µs
Output Voltage Ramp-Down
Slew Rate
10
95
97
4.50
Typical Condition Efficiency
η
I
= 100mA (Note 5)
OUT
%
%
TYP
Peak Efficiency
η
(Note 5)
PK
ILIM = high
ILIM = low
3.70
1.2
5.70
2.65
LX1/2 Current Limit
I
A
LIM_LX
1.80
40
High-Side PMOS ON
Resistance
R
R
I
I
= 100mA per switch
= 100mA per switch
mΩ
DSON(PMOS)
LX
LX
Low-Side NMOS ON
Resistance
55
mΩ
DSON(NMOS)
Switching Frequency
f
PWM mode, T = +25°C
2.25
2.50
2.75
MHz
SW
J
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Buck-Boost Electrical Characteristics (continued)
(V
= V = +3.8V, V
= V
= +3.3V, T = -40°C to +125°C, typical values are at T ≈ T = +25°C, unless otherwise noted.)
SYS
IN
OUTS
OUT J A J
(Note 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
From EN asserting to LX switching with
bias ON
Turn-On Delay Time
Soft-Start Timer
t
100
µs
ON_DLY
I
I
= 10mA, ILIM = high
= 10mA, ILIM = low
120
800
OUT
OUT
t
µs
SS
Minimum Effective Output
Capacitance
C
0A < I
< 2000mA
16
0.1
0.2
µF
EFF(MIN)
OUT
V
V
= 0V or 5.5V, V
= 5.5V,
OUT
LX1/2
SYS
I
1
LK_25C
= V = 5.5V, T = +25°C
IN
J
LX1, LX2 Leakage Current
µA
V
V
= 0V or 5.5V, V
= 5.5V,
LX1/2
SYS
OUT
I
LK_125C
= V = 5.5V, T = +125°C
IN
J
POWER-OK COMPARATOR
Rising threshold
Falling threshold
80
75
Output POK Trip Level
%
V
V
UNDERVOLTAGE LOCKOUT
SYS
V
V
V
rising
falling
2.375
2.50
2.05
2.625
0.4
UVLO_R
SYS
V
Undervoltage Lockout
SYS
Threshold
V
UVLO_F
SYS
LOGIC AND CONTROL INPUTS
Input Low Level
V
EN, ILIM, V
EN, ILIM, V
= 3.8V, T = +125°C
V
V
V
IL
SYS
J
Input High Level
V
= 3.8V, T = -40°C
1.2
-1
IH
SYS
J
POK Output Low Voltage
V
I
= 1mA
SINK
0.4
+1
OL
I
T = +25°C
J
OZH_25C
POK Output High Leakage
µA
I
T = +125°C
0.1
OZH_125C
J
INTERNAL PULLDOWN RESISTANCE
EN
R
Pulldown resistance to GND
400
800
1600
kΩ
PD
Note 2: Limits are 100% production tested at T = +25°C. The device is tested under pulsed load conditions such that T ≈ T
A.
J
J
Limits over the operating temperature range are guaranteed through correlation using statistical quality control methods.
Note 3: Guaranteed by design. Not production tested.
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
2
I C Electrical Characteristics
(V
= 3.8V, V
= 1.8V, T = -40°C to +125°C, typical values are at T ≈ T = +25°C, unless otherwise noted.) (Note 4)
SYS
VIO J A J
PARAMETER
POWER SUPPLY
Voltage Range
SYMBOL
CONDITIONS
MIN
1.7
TYP
MAX
UNITS
V
V
3.6
V
IO
VIO
SDA AND SCL I/O STAGES
0.7 x
SCL, SDA Input High Voltage
V
V
V
V
IH
V
IO
0.3 x
SCL, SDA Input Low Voltage
SCL, SDA Input Hysteresis
V
IL
V
IO
0.05 x
V
HYS
V
IO
SCL, SDA Input Current
SDA Output Low Voltage
I
V
= 3.8V
-10
+10
0.4
µA
V
I
VIO
V
I
= 20mA
OL
SINK
SCL, SDA Input Capacitance
C
10
pF
ns
I
Output Fall Time from V
to
VIO
t
120
OF
0.3 x V
VIO
2
I C-COMPATIBLE INTERFACE TIMING (STANDARD, FAST, AND FAST-MODE PLUS) (Note 5)
Clock Frequency
f
1000
kHz
µs
SCL
Hold Time (REPEATED)
START Condition
t
0.26
HD;STA
SCL Low Period
SCL High Period
t
0.5
µs
µs
LOW
t
0.26
HIGH
Setup Time REPEATED
START Condition
t
0.26
µs
SU_STA
DATA Hold Time
DATA Setup Time
t
0
µs
ns
HD_DAT
t
50
SU_DAT
Setup Time for STOP
Condition
t
0.26
0.5
µs
µs
pF
SU_STO
Bus-Free Time Between
STOP and START
t
BUF
Capacitive Load for Each
Bus Line
C
550
B
Maximum Pulse Width
of Spikes that must be
suppressed by the input filter
50
ns
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
2
I C Electrical Characteristics (continued)
(V
= 3.8V, V
= 1.8V, T = -40°C to +125°C, typical values are at T ≈ T = +25°C, unless otherwise noted.) (Note 4)
SYS
VIO J A J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
I C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, C = 100pF) (Note 5)
B
Clock Frequency
f
3.4
MHz
ns
SCL
Setup Time REPEATED
START Condition
t
160
160
SU_STA
Hold Time (REPEATED)
START Condition
t
ns
HD_STA
CLK Low Period
t
160
60
ns
ns
ns
ns
ns
LOW
CLK High Period
DATA Setup Time
DATA Hold Time
t
HIGH
t
10
SU_DAT
HD_DAT
t
35
SCL Rise Time (Note 3)
t
T = +25°C
10
10
10
40
80
RCL
J
Rise Time of SCL Signal after
REPEATED START Condition
and after Acknowledge Bit
t
T = +25°C
ns
RCL1
J
SCL Fall Time
SDA Rise Time
SDA Fall Time
t
T = +25°C
40
80
80
ns
ns
ns
FCL
J
t
T = +25°C
J
RDA
t
T = +25°C
J
FDA
Setup Time for STOP
Condition
t
160
ns
SU_STO
Bus Capacitance
C
100
1.7
pF
B
Maximum Pulse Width
of Spikes that must be
suppressed by the input filter
10
ns
2
I C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, C = 400pF) (Note 5)
B
Clock Frequency
f
MHz
ns
SCL
Setup Time REPEATED
START Condition
t
160
160
SU_STA
Hold Time (REPEATED)
START Condition
t
ns
HD_STA
SCL Low Period
SCL High Period
DATA Setup Time
DATA Hold Time
t
320
120
10
ns
ns
ns
ns
LOW
t
HIGH
t
SU_DAT
t
75
HD_DAT
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
2
I C Electrical Characteristics (continued)
(V
= 3.8V, V
= 1.8V, T = -40°C to +125°C, typical values are at T ≈ T = +25°C, unless otherwise noted.) (Note 4)
SYS
VIO J A J
PARAMETER
SCL Rise Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
t
T = +25°C
20
80
ns
RCL
J
Rise Time of SCL Signal after
REPEATED START Condition
and after Acknowledge Bit
t
T = +25°C
20
20
160
ns
RCL1
J
SCL Fall Time
SDA Rise Time
SDA Fall Time
t
T = +25°C
80
ns
ns
ns
FCL
J
t
T = +25°C
160
160
RDA
J
t
T = +25°C
J
FDA
Setup Time for STOP
Condition
t
160
ns
SU_STO
Bus Capacitance
C
400
pF
B
Maximum Pulse Width
of Spikes that Must be
t
10
ns
SP
Suppressed by the Input Filter
Note 4: Limits are 100% production tested at T = +25°C. The device is tested under pulsed load conditions such that T ≈ T .
J
J
A
Limits over the operating temperature range are guaranteed through correlation using statistical quality control methods.
Note 5: Guaranteed by design. Not production tested.
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Typical Operating Characteristics
(V
= 3.8V, V
= 3.3V, I
= 0A, FPWM = 0, T = +25°C, unless otherwise noted.)
SYS
OUT
OUT
A
QUIESCENT CURRENT vs.
SUPPLY VOLTAGE
SHUTDOWN CURRENT vs.
SUPPLY VOLTAGE
EFFICIENCY vs. LOAD
2.8V OUTPUT
toc01
toc02
toc03
70
65
60
55
50
45
40
35
30
2.0
1.5
1.0
0.5
0.0
-0.5
100
90
80
70
60
50
40
30
20
10
0
VIN = 3V
TA = +85°C
VIN = 3.8V
VIN = 4.5V
VOUT = 2.8V
VOUT = 3.3V
VOUT = 5V
TA = +25°C
TA = -40°C
VIN = 3.8V (FPWM = 1)
2
3
4
5
6
2
3
4
5
6
0.001
0.01
0.1
LOAD (A)
1
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
EFFICIENCY vs. LOAD
3.3V OUTPUT
EFFICIENCY vs. LOAD
5V OUTPUT
LOAD REGULATION
2.8V OUTPUT
toc04
toc05
toc06
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
2.85
2.84
2.83
2.82
2.81
2.80
2.79
2.78
2.77
VIN = 3V
VIN = 3V
VIN = 3.8V
VIN = 4.5V
VIN = 3.3V
VIN = 3.8V
VIN = 4.5V
VIN = 3V
VIN = 3.8V
VIN = 4.5V
VIN = 3.8V (FPWM = 1)
VIN = 3.8V (FPWM = 1)
0.001
0.01
0.1
LOAD (A)
1
0.001
0.01
0.1
LOAD (A)
1
0.0
0.5
1.0
1.5
2.0
LOAD (A)
LOAD REGULATION
3.3V OUTPUT
LOAD REGULATION
5V OUTPUT
LINE REGULATION
2.8V OUTPUT
toc07
toc08
toc09
3.39
5.16
2.80
2.79
2.78
2.77
2.76
2.75
2.74
3.38
3.37
3.36
3.35
3.34
3.33
3.32
3.31
3.30
3.29
5.14
5.12
5.10
5.08
5.06
5.04
5.02
5.00
4.98
4.96
IOUT = 500mA
IOUT = 1A
IOUT = 2A
VIN = 3V
VIN = 3.8V
VIN = 4.5V
VIN = 3V
VIN = 3.3V
VIN = 3.8V
VIN = 4.5V
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.5
4.5
5.5
LOAD (A)
LOAD (A)
SUPPLY VOLTAGE (V)
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Typical Operating Characteristics (continued)
(V
= 3.8V, V
= 3.3V, I
= 0A, FPWM = 0, T = +25°C, unless otherwise noted.)
SYS
OUT
OUT A
LINE REGULATION
3.3V OUTPUT
LINE REGULATION
5V OUTPUT
toc10
toc11
3.32
3.31
3.30
3.29
3.28
3.27
3.26
5.04
5.02
5.00
4.98
4.96
4.94
4.92
IOUT = 500mA
IOUT = 1A
IOUT = 2A
IOUT = 500mA
IOUT = 1A
IOUT = 2A
2.5
3.5
4.5
5.5
2.5
3.5
4.5
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
STARTUP WAVEFORM
3.3V OUTPUT
MAXIMUM OUTPUT CURRENT vs.
SUPPLY VOLTAGE
toc12
toc13
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VOUT = 2.8V
VOUT = 3.3V
2V/div
2V/div
VEN
EN = 1
VOUT
VOUT = 5V
200mV/div
2A/div
VLX
IIN
ILIM = HIGH
VIN = 3.8V
2
3
4
5
6
40µs/div
SUPPLY VOLTAGE (V)
LOAD TRANSIENT RESPONSE
2.8V OUTPUT
LOAD TRANSIENT RESPONSE
3.3V OUTPUT
toc14
toc15
1A
1A
500mA/div
100mV/div
500mA/div
100mV/div
IOUT
IOUT
10mA
10mA
VOUT
VOUT
SLEW RATE = 0.99A/15µs
100µs/div
SLEW RATE = 0.99A/15µs
100µs/div
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Typical Operating Characteristics (continued)
(V
= 3.8V, V
= 3.3V, I
= 0A, FPWM = 0, T = +25°C, unless otherwise noted.)
SYS
OUT
OUT
A
LOAD TRANSIENT RESPONSE
5V OUTPUT
LINE TRANSIENT RESPONSE
2.8V OUTPUT
toc16
toc17
toc19
toc21
IOUT = 1.5A
1A
3.4V
500mA/div
100mV/div
IOUT
2.9V
10mA
500mV/div
20mV/div
VIN
VOUT
VOUT
SLEW RATE = 20mV/µs
100µs/div
SLEW RATE = 0.99A/15µs
100µs/div
LINE TRANSIENT RESPONSE
5V OUTPUT
BOOST TO BUCK
LINE TRANSIENT RESPONSE
toc18
IOUT = 1.5A
IOUT = 1.5A
VOUT = 3.3V
2.9V
3.9V
3.4V
3.4V
500mV/div
20mV/div
500mV/div
20mV/div
VIN
VIN
VOUT
VOUT
SLEW RATE = 20mV/µs
100µs/div
SLEW RATE = 20mV/µs
100µs/div
SWITCHING WAVEFORM
3.3V OUTPUT
OUTPUT RIPPLE IN SKIP MODE
3.3V OUTPUT (IOUT = 100mA)
toc20
IOUT = 1A
IOUT = 100mA
1V/div
VLX
20mV/div
VOUT
FSW = 2.5MHz
100µs/div
4µs/div
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Typical Operating Characteristics (continued)
(V
= 3.8V, V
= 3.3V, I
= 0A, FPWM = 0, T = +25°C, unless otherwise noted.)
SYS
OUT
OUT
A
OUTPUT RIPPLE IN PWM
3.3V OUTPUT (IOUT = 1A)
SHORT-CIRCUIT HICCUP AND RECOVERY
3.3V OUTPUT (ILIM = LOW)
toc22
toc23
IOUT = 1A
SHORT APPLIED
VOUT
2V/div
RECOVERY/
SHORT REMOVED
10mV/div
VOUT
HICCUP/RETRY
ILX
1A/div
20µs/div
20ms/div
SHORT-CIRCUIT AND RECOVERY
3.3V OUTPUT (ILIM = HIGH)
toc24
SHORT APPLIED
VOUT
2V/div
RECOVERY/
SHORT REMOVED
HICCUP/RETRY
ILX
2A/div
20ms/div
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Bump Configuration
TOP VIEW
(BUMP SIDE DOWN)
1
2
3
4
5
+
A
B
ILIM
POK
LX2
LX2
GND
V
SDA
SCL
SYS
OUTS
OUT
GND
GND
EN
LX1
LX1
VIO
IN
C
D
OUT
GND
IN
20 WLP
(2.13mm x 1.83mm, 0.4mm PITCH)
Bump Description
PIN
NAME
FUNCTION
System (Battery) Voltage Input. Bypass to GND with a 1µF capacitor.
Current Limit Selection Input. Connect to GND to set I to 1.8A. Connect to V
A1
V
SYS
to set
VIO
LIM_BB
A2
A3, B3
A4
ILIM
GND
SDA
I
to 4.5A. Do not leave this pin unconnected.
LIM_BB
Ground. Connect to PGND on the PCB. See the PCB Layout Guidelines.
2
I C Serial Interface Data. This pin requires a pullup resistor (1.5k to 2.2k) to V
.
IO
Connect to GND if not used.
2
I C Serial Interface Clock. This pin requires a pullup resistor (1.5k to 2.2k) to V
Connect to GND if not used.
.
IO
A5
SCL
B1
B2
OUTS
POK
EN
Output sense.
Open-Drain Power-OK Output. Asserts high (high-Z) when buck-boost output reaches 80% of target.
B4
Active-High Enable Input. This pin has an 800kΩ internal pulldown to GND.
2
B5
VIO
I C Supply Voltage Input. Bypass to GND with a 0.1µF capacitor. Connect to GND if not used.
C1, D1
C2, D2
C3, D3
C4, D4
C5, D5
OUT
LX2
Output. Bypass to PGND with a 10V 47µF ceramic capacitor.
Switching Node 2
PGND
LX1
Power Ground. Connect to GND on the PCB. See the PCB Layout Guidelines.
Switching Node1
IN
Input. Bypass to PGND with a 10V 10µF capacitor.
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
1µH
LX1
LX2
IN
HS1
HS2
OUT
10µF
CS
CS
47µF
LS1
LS2
DRIVER
DRIVER
PGND
OUTS
MAX77813
CONTROL LOGIC
ETR
OSC
PROT.
CF
R1
R2
COMP.
REF
SLOPE COMP.
PSM
REGISTER
CONTROL
Figure 1. Simplified Block Diagram
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
The H-bridge topology has three switching phases. See
Figure 2 for details.
Detailed Description
The MAX77813 is a synchronous step-up/down (buck-
boost) DC-DC converter with integrated switches. The
buck-boost operates on a supply voltage between 2.3V
● Φ1 Switch period (Phase 1: HS1 = ON, LS2 = ON)
stores energy in the inductor. Inductor current ramps
up at a rate proportional to the input voltage divided by
2
and 5.5V. Output voltage is configurable through I C from
inductance: V / L.
2.60V to 5.14V in 20mV steps. Factory-default startup
voltage options of 3.3V and 3.4V are available (see the
Ordering Information table). The ILIM pin sets the buck-
boost switch current capacity.
IN
● Φ2 Switch period (Phase 2: HS1 = ON, HS2 = ON)
ramps inductor current up or down depending on the
differential voltage across the inductor: (V - V
IN
OUT) / L.
● Strap ILIM high to set 4.5A (typ) switch current. This
configuration supports up to 2A out in boost mode
and up to 3A out in buck mode.
● Φ3 Switch period (Phase 3: LS1 = ON, HS2 = ON)
ramps inductor current down at a rate proportional to
the output voltage divided by inductance: (-V
/ L).
OUT
● Strap ILIM low to set 1.8A (typ) switch current. This
configuration supports up to 650mA in boost mode
and up to 800mA in buck mode.
Boost operation (V < V
) utilizes phase 1 and phase
IN
OUT
2 within a single clock period. See the representation of
inductor current waveform for boost mode operation in
Figure 2.
Buck-Boost Control Scheme
Buck operation (V > V
) utilizes phase 2 and phase
OUT
IN
The buck-boost converter operates using a 2.5MHz fixed-
frequency pulse-width modulated (PWM) control scheme
with current-mode compensation. The buck-boost utilizes
an H-bridge topology using a single inductor and output
capacitor.
3 within a single clock period. See the representation of
inductor current waveform for buck mode operation in
Figure 2.
BOOST OPERATION
BUCK-BOOST H-BRIDGE
TOPOLOGY
Ф2
Ф2
IN
OUT
Ф3
Ф3
TSW
TSW
Ф2
HS1
HS2
Charge/Discharge L
CLK
CLK
CLK
BUCK OPERATION
L
Ф1
Ф2
Ф1
Ф2
Ф3
Discharge L
Ф1
Charge L
LS1
LS2
TSW
TSW
CLK
CLK
CLK
Figure 2. Buck-Boost Block Diagram
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Enable Control (EN)
Raise the EN pin voltage above V threshold to enable
Peak Inductor Current
Limit Selection (ILIM)
IH
the buck-boost output. Lower EN below V threshold to
Select the buck-boost’s cycle-by-cycle inductor current
IL
disable. EN has an internal 800kΩ (typ) pulldown resistor
to GND. Clear the EN bit using the I C interface to disable
limit (I
to set I
) with the ILIM pin. Connect ILIM to V
to 4.5A (typ). Connect ILIM to GND to set
LIM_LX
LIM_LX VIO
2
the internal pulldown (making EN high-impedance). The
EN_PD bit reset value is 1 (pulldown enabled). Therefore,
the internal pulldown resistor is present whenever the
MAX77813 starts up.
I
to 1.8A (typ).
LIM_LX
The device automatically changes I
following events:
during the
LIM_LX
● Soft-start (I
is temporarily reduced.). See Soft-
LIM_LX
Start for details.
After the initial buck-boost startup, clear the EN bit
2
through I C to disable the buck-boost output. Table 1
● Burst mode (I
is temporarily increased.). See
LIM_LX
details the interaction between the EN pin and the EN bit.
Burst Mode (Enhanced Load Response) for details.
Provide a valid V and set the EN pin logic-high to
IO
Always drive the ILIM pin logic-high or low. Do not leave
ILIM unconnected.
2
enable the I C serial interface. Serial reads and writes to
the EN bit may happen only while V is valid and EN is
IO
logic-high. Lowering EN logic-low disables the buck-boost
(regardless of EN) and causes all registers to reset to
default values.
Soft-Start
The device implements a soft-start by reducing the peak
inductor current limit (I
) for a fixed time. The soft-
LIM_LX
start time begins immediately after the startup delay
(t ). See Table 2 for details.
Table 1. EN Logic
ON_DLY
2
I C SERIAL
INTERFACE
BUCK-BOOST
OUTPUT
I
reduces (according to Table 2) for t
after the
LIM_LX
SS
EN
EN BIT
buck-boost enables through either the EN pin or EN bit.
Reducing the inductor current limit during startup controls
inrush current from the supply input (I ) and prevents
Low
High
High
X
0
Disabled
Enabled
Enabled
Disabled
Disabled
Enabled
IN
droop caused by upstream source impedance.
1 (default)
EN
V
OUT
T
T
ON_DLY
SS
ILIM_NORMAL
ILIM_SS
IL
Figure 3. Soft-Start
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Table 2. Soft-Start ILIM
I
AFTER
I
DURING
t
SS
SOFT-START TIME
(µS)
LIM_LX
LIM_LX
ILIM (PIN)
SOFT-START (A)
SOFT-START (A)
High
Low
4.5
1.8
1.8
1.8
120
800
inductor current limit from I
(See Table 3.)
to I
.
Burst Mode (Enhanced Load Response)
LIM_LX
LIM_LX_HIGH
The device implements a burst mode to service short-
duration heavy load transients (burst loads). A summary
of burst mode operation follows:
●
If the heavy load causes peak inductor current >
for longer than 800µs(typ), then burst mode
I
LIM_LX
deactivates and peak inductor current limit returns to
●
If a heavy load transient happens that requires peak
inductor current > I to maintain regulation,
I
.
LIM_LX
LIM_LX
then the buck-boost temporarily increases the peak
Table 3. ILIM Levels
INDUCTOR CURRENT LIMIT DURING
NORMAL OPERATION
INDUCTOR CURRENT LIMIT DURING
BURST MODE
ILIM (PIN)
I
(A)
I
(A)
LIM_LX
LIM_LX_HIGH
High
Low
4.5
5.5
2.3
1.8
EN
V
OUT
T
T
SS
ON_DLY
ILIM_LX
ILIM_LX_SS
IL
Figure 4. Short Circuit Waveform
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Disable OVP by programming OVP_TH[1:0] to 0b00
using I C. The default OVP threshold is 0b11 (120% of
Power-OK (POK) Output
2
The device features an open-drain POK output to monitor
the output voltage. POK requires an external pullup resis-
tor (typically 10kΩ to 100kΩ).
the target V
).
OUT
The OVP status bit continuously mirrors the status of the
OVP circuit. See the Register Map for details.
POK is active-high by default. Use the POK_POL bit to
change the POK polarity to active-low. See the Register
Map for details.
Thermal Shutdown
The device has an internal thermal protection circuit
which monitors die temperature. The buck-boost disables
While POK_POL = 1 (active-high, default state), POK
goes high (high-impedance) after the buck-boost output
increases above 80% of the target regulation voltage.
POK goes low when the output drops below 75% of the
target or when the buck-boost is disabled.
if the die temperature exceeds T
(165°C typ). The
SHDN
buck-boost enables again after the die temperature cools
by approximately 20°C.
The T
status bit continuously mirrors the status of
SHDN
the thermal protection circuit. See the Register Map for
details.
Output Voltage Selection and
Slew Rate Control
Write the VOUT[6:0] bitfield through I C to configure the
2
2
I C Serial Interface
The device features a revision 3.0 I C-compatible, 2-wire
target output voltage (V
) between 2.60V and 5.14V
OUT
2
in 20mV steps. The default value of VOUT[6:0] is factory-
programmable. See the Ordering Information for the
serial interface consisting of a bidirectional serial data line
(SDA) and a serial clock line (SCL). The MAX77813 is a
slave-only device that that relies on an external bus mas-
ter to generate SCL. SCL clock rates from 0Hz to 3.4MHz
default V
associated with each orderable part num-
2
OUT
ber. Overwriting the default value through I C sets a new
target V
until registers reset.
OUT
2
are supported. I C is an open-drain bus, and therefore,
Changing the VOUT[6:0] bitfield while the buck-boost
output is enabled causes the device to respond in the
following way:
SDA and SCL require pullups (500Ω or greater).
2
The device’s I C communication controller implements
2
7-bit slave addressing. An I C bus master initiates com-
●
V
OUT
ramps up at a rate set by RU_SR (20mV/μs or
munication with the slave by issuing a START condition
followed by the slave address. The slave address of the
device is shown in Table 4.
40mV/μs) when the V
target is increased.
OUT
●
V
OUT
ramps down at a rate set by RD_SR (5mV/μs
or 10mV/μs) when the V
target is decreased.
OUT
The device uses 8-bit registers with 8-bit register address-
ing. They support standard communication protocols: (1)
Writing to a single register (2) Writing to multiple sequen-
tial registers with an automatically incrementing data
pointer (3) Reading from a single register (4) Reading
from multiple sequential registers with an automati-
cally incrementing data pointer. For additional informa-
See the Register Map for details about the RU_SR and
RD_SR bits.
Output Overvoltage Protection (OVP)
The device has an internal output overvoltage protection
(OVP) circuit which monitors V
The buck-boost disables if the output exceeds the over-
voltage threshold set by the OVP_TH[1:0] bitfield.
for overvoltage faults.
OUT
2
2
tion on the I C protocols, refer to the MAX77813 I C
2
Implementer’s Guide and/or the I C specification that is
freely available on the internet.
2
Table 4. I C Slave Address
INDUCTOR CURRENT LIMIT DURING
NORMAL OPERATION
INDUCTOR CURRENT LIMIT DURING
BURST MODE
ILIM (PIN)
I
(A)
I
(A)
LIM_LX
LIM_LX_HIGH
High
Low
4.5
5.5
2.3
1.8
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Output Capacitor Selection
Applications Information
Sufficient output capacitance (C
) is required to keep
OUT
Inductor Selection
the output voltage ripple small and the regulation loop
stable. Choose the effective C to be 16uF, minimum.
Choose a 1μH inductor with a saturation current of 7A or
higher for ILIM = HIGH and a saturation current of 3.39A
or higher for ILIM = LOW.
OUT
Considering the DC bias characteristic of ceramic capaci-
tors, a 47μF 10V capacitor is recommended for most
applications.
Table 5 lists recommended inductors for the MAX77813.
Always choose the inductor carefully by consulting the
manufacturer’s latest released data sheet.
Effective C
is the actual capacitance value seen by
OUT
the buck-boost output during operation. Choose effec-
tive C carefully by considering the capacitor’s initial
OUT
Input Capacitor Selection
tolerance, variation with temperature, and derating with
DC bias.
Choose the input capacitor (C ) to be a 10μF ceramic
IN
capacitor that maintains at least 2μF of effective capaci-
Ceramic capacitors with X5R or X7R dielectric are highly
recommended due to their small size, low ESR, and small
temperature coefficients. All ceramic capacitors derate
with DC bias voltage (effective capacitance goes down as
DC bias goes up). Generally, small case size capacitors
derate heavily compared to larger case sizes (0603 case
size performs better than 0402). Consider the effective
capacitance value carefully by consulting the manufac-
turer’s data sheet.
tance at its working voltage. Larger values improve the
decoupling of the buck-boost. C reduces the current
IN
peaks drawn from the battery or input power source and
reduces switching noise in the device. Ceramic capaci-
tors with X5R or X7R dielectric are highly recommended
due to their small size, low ESR, and small temperature
coefficients.
All ceramic capacitors derate with DC bias voltage
(effective capacitance goes down as DC bias goes up).
Generally, small case size capacitors derate heavily com-
pared to larger case sizes (0603 case size performs bet-
ter than 0402). Consider the effective capacitance value
carefully by consulting the manufacturer’s data sheet.
Table 5. Suggested Inductors for Buck Boost
NOMINAL
TYPICAL DC
CURRENT
CURRENT
DIMENSIONS
L x W x H
[mm]
ILIM
MFGR.
SERIES
INDUCTANCE RESISTANCE RATING [A]
RATING [A]
SETTING
[µH]
[mΩ]
-30% (ΔL/L) ΔT = 40°C RISE
TFM201610GHM -
1R0MTAA
TDK
1.0
50
3.8
3.0
2.0 x 1.6 x 1.0
Low
TOKO
DFE322512C
1.0
1.0
34
13
4.6
8.7
3.7
9.6
3.2 x 2.5 x 1.2
4.0 x 4.0 x 2.1
Low
Coilcraft XAL4020-102MEB
High
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
2
Figure 5 shows an example of a typical I C system. A
Serial Interface
The I C-compatible 2-wire serial interface is used for
regulator on/off control, setting output voltages, and other
functions. See the Register Map for details.
2
device on I C bus that sends data to the bus in called
2
a “Transmitter”. A device that receives data from the
bus is called a “Receiver”. The device that initiates a
data transfer and generates SCL clock signals to control
the data transfer is a “Master”. Any device that is being
addressed by the master is considered a “Slave”. When
2
The I C serial bus consists of a bidirectional serial-data
2
line (SDA) and a serial clock (SCL). I C is an open-drain
bus. SDA and SCL require pullup resistors (500Ω or
greater). Optional 24Ω resistors in series with SDA and
SCL help to protect the device inputs from high voltage
spikes on the bus lines. Series resistors also minimize
crosstalk and undershoot on the bus lines.
2
2
the MAX77813 I C-compatible interface is operating, it is
a slave on the I C bus and it can be both a transmitter
and a receiver.
Bit Transfer
One data bit is transferred for each SCL clock cycle. The
data on SDA must remain stable during the high portion of
SCL clock pulse. Changes in SDA while SCL is high are
control signals (START and STOP conditions).
System Configuration
The I C bus is a multi-master bus. The maximum number
of devices that can attach to the bus is only limited by bus
capacitance.
2
SDA
SCL
MASTER
SLAVE
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER /
RECEIVER
SLAVE
TRANSMITTER
TRANSMITTER /
RECEIVER
RECEIVER
Figure 5. Functional Logic Diagram for Communications Controller
SDA
SCL
DATA LINE STABLE DATA VALID
CHANGE OF DATA
ALLOWED
2
Figure 6. I C Bit Transfer
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
interface until the next START condition, minimizing digital
noise and feed-through.
START and STOP Conditions
When I C serial interface is inactive, SDA and SCL idle
2
high. A master device initiates communication by issuing
a START condition. A START condition is a high-to-low
transition on SDA with SCL high. A STOP condition is a
low-to-high transition on SDA, while SCL is high.
Acknowledged
Both the I C bus master and the device (slave) generate
2
acknowledge bits when receiving data. The acknowledge
bit is the last bit of each nine-bit data packet. To gener-
ate an ACKNOWLEDGE (A), the receiving device must
pull SDA low before the rising edge of the acknowledge-
related clock pulse (ninth pulse) and keep it low during
the high period of the clock pulse. To generate a NOT-
ACKNOWLEDGE (nA), the receiving device allows SDA
to be pulled high before the rising edge of the acknowl-
edge-related clock pulse and leaves it high during the
high period of the clock pulse.
A START condition from the master signals the beginning
of a transmission to the device. The master terminates
transmission by issuing a NOT-ACKNOWLEDGE fol-
lowed by a STOP condition.
A STOP condition frees the bus. To issue a series of com-
mands to the slave, the master may issue REPEATED
START (Sr) commands instead of a STOP command
in order to maintain control of the bus. In general, a
REPEATED START command is functionally equivalent
to a regular START command.
Monitoring the acknowledge bits allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communication
at a later time.
When a STOP condition or incorrect address is detected,
2
the device internally disconnects SCL from the I C serial
Slave Address
The I C slave address of the device is shown in Table 6.
S
Sr
P
2
SDA
SCL
2
t
t
SU;STO
SU;STA
Table 6. I C Slave Address
SLAVEADDRESS SLAVEADDRESS SLAVEADDRESS
(7 BIT)
(WRITE)
(READ)
t
t
HD;STA
HD;STA
001 1000
0x30 (0011 0000)
0x31 (0011 0001)
Figure 7. START and STOP Conditions
S
SDA
0
0
2
1
3
1
4
0
5
0
6
0
7
R/nW
A
9
ACKNOWLEDGE
SCL
1
8
Figure 8. Slave Address Byte Example
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
2
section of the I C revision 3.0 specification for detailed
Clock Stretching
In general, the clock signal generation for the I C bus is
the responsibility of the master device. I C specification
allows slow slave devices to alter the clock signal by
holding down the clock line. The process in which a slave
device holds down the clock line is typically called clock
stretching. The device does not use any form of clock
stretching to hold down the clock line.
guidance on the pullup resistor selection. In general, for
bus capacitances of 200pF, a 100kHz bus needs 5.6kΩ
pullup resistors, a 400kHz bus needs about 1.5kΩ pullup
resistors, and a 1MHz bus needs 680Ω pullup resistors.
Note that the pullup resistor is dissipating power when the
open-drain bus is low. The lower the value of the pullup
2
2
2
resistor, the higher the power dissipation (V /R).
Operating in high-speed mode requires some special con-
siderations. For the full list of considerations, see the I C
3.0 specification. The major considerations with respect to
the MAX77813 are:
General Call Address
The device does not implement I C specification “General
Call Address.” If the device sees “General Call Address
(00000000b)” it does not issue an ACKNOWLEDGE (A).
2
2
2
● I C bus master use current source pullups to shorten
the signal rise times.
Communication Speed
The device provides I C 3.0-compatible (3.4MHz) serial
2
2
● I C slave must use a different set of input filters on
interface.
its SDA and SCL lines to accommodate for the higher
bus speed.
2
● I C Revision 3 Compatible Serial Communications
Channel
● The communication protocols need to utilize the high-
• 0Hz to 100kHz (Standard mode)
• 0Hz to 400kHz (Fast mode)
• 0Hz to 1MHz (Fast-mode plus)
• 0Hz to 3.4MHz (High-speed mode)
speed master code.
At power-up and after each STOP condition, the device
input filters are set for standard mode, fast mode, or
fast-mode plus (i.e., 0Hz to 1MHz). To switch the input
filters for high-speed mode, use the high-speed master
code protocols that are described in the Communication
Protocols section.
2
● Does not utilize I C Clock Stretching
Operating in standard mode, fast mode, and fast-mode
plus does not require any special protocols. The main
consideration when changing the bus speed through
this range is the combination of the bus capacitance and
pullup resistors. Higher time constants created by the
bus capacitance and pullup resistance (C x R) slow the
bus operation. Therefore, when increasing bus speeds,
the pullup resistance must be decreased to maintain a
reasonable time constant. See the Pullup Resistor Sizing
Communication Protocols
The device supports both writing and reading from its reg-
isters. The following sections show the I C communica-
tion protocols for each functional block. The power block
uses the same communication protocols.
2
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
Writing to a Single Register
2
Figure 9 shows the protocol for the I C master device to
write one byte of data to the device. This protocol is the
same as SMBus specification’s “Write Byte” protocol.
7) The slave acknowledges the data byte. At the rising
edge of SCL, the data byte loads into its target regis-
ter and the data becomes active.
The “Write Byte” protocol is as follows:
1) The master sends a START command (S).
2) The master sends the 7-bit slave address followed
by a write bit (R/nW = 0).
8) The master sends a STOP condition (P) or a RE-
PEATED START condition (Sr). Issuing a P ensures
that the bus input filters are set for 1MHz or slower
operation. Issuing a REPEATED START (Sr) leaves
the bus input filters in their current state.
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
LEGEND
*P FORCES THE BUS FILTERS TO SWITCH
TO THEIR ≤1MHz MODE. Sr LEAVES THE
BUS FILTERS IN THEIR CURRENT STATE.
MASTER TO
SLAVE
SLAVE TO
MASTER
NUMBER
OF BITS
1
7
1
0
1
8
1
8
1
1
S
SLAVE ADDRESS
A
REGISTER POINTER
A
DATA
A
P or Sr*
R/nW
THE DATA IS LOADED INTO
THE TARGET REGISTER AND
BECOMES ACTIVE DURING
THIS RISING EDGE.
SDA
SCL
B1
7
B0
8
A
9
ACKNOWLEDGE
Figure 9. Writing to a Single Register with “Write Byte” Protocol
Maxim Integrated
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
Writing to Sequential Registers
Figure 10 shows the protocol for writing to sequential
registers. This protocol is similar to the “Write Byte” proto-
col, except the master continues to write after it receives
the first byte of data. When the master is done writing, it
issues a STOP or REPEATED START.
7) The slave acknowledges the data byte. At the rising
edge of SCL, the data byte loads into its target regis-
ter and the data becomes active.
8) Steps 6 to 7 are repeated as many times as the
master requires.
The “Writing to Sequential Registers” protocol is as follows:
1) The master sends a START command (S).
9) During the last acknowledge related clock pulse, the
slave issues an ACKNOWLEDGE (A).
2) The master sends the 7-bit slave address followed
by a write bit (R/nW = 0).
10) The master sends a STOP condition (P) or a RE-
PEATED START condition (Sr). Issuing a P ensures
that the bus input filters are set for 1MHz or slower
operation. Issuing a REPEATED START (Sr) leaves
the bus input filters in their current state.
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
4) The master sends an 8-bit register pointer.
LEGEND
*P FORCES THE BUS FILTERS TO SWITCH TO THEIR
≤1MHZ MODE. SR LEAVES THE BUS FILTERS IN
THEIR CURRENT STATE.
MASTER TO SLAVE
SLAVE TO MASTER
NUMBER
OF BITS
1
S
7
1
0
1
8
REGISTER POINTER X
1
8
1
SLAVE ADDRESS
A
A
DATA X
A
α
α
R/nW
NUMBER
OF BITS
8
1
8
1
DATA X+1
A
DATA X+2
A
α
REGISTER POINTER = X + 2
REGISTER POINTER = X + 1
NUMBER
OF BITS
8
1
8
1
1
DATA n-1
A
DATA n
A
P or Sr*
β
REGISTER POINTER = X + (N-2)
REGISTER POINTER = X + (N-1)
α
THE DATA IS LOADED INTO THE
TARGET REGISTER AND BECOMES
ACTIVE DURING THIS RISING
EDGE.
SDA
SCL
B1
7
B0
8
A
9
B9
ACKNOWLEDGE
1
DETAIL: α
THE DATA IS LOADED INTO THE
TARGET REGISTER AND BECOMES
ACTIVE DURING THIS RISING
EDGE.
SDA
SCL
B1
7
B0
8
A
9
ACKNOWLEDGE
DETAIL: β
Figure 10. Writing to Sequential Registers
Maxim Integrated
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
the slave that it wants more data – when the master has all
the data it requires, it issues a NOT-ACKNOWLEDGE (nA)
and a STOP (P) to end the transmission.
Reading from a Single Register
The I C master device reads one byte of data to the
device. This protocol is the same as SMBus specifica-
tion’s “Read Byte” protocol.
2
The “Continuous Read from Sequential Registers” proto-
col is as follows:
The “Read Byte” protocol is as follows:
1) The master sends a START command (S).
1) The master sends a START command (S).
2) The master sends the 7-bit slave address followed
by a write bit (R/nW = 0).
2) The master sends the 7-bit slave address followed
by a write bit (R/nW = 0).
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a REPEATED START command
(Sr).
6) The master sends a REPEATED START command
(Sr).
7) The master sends the 7-bit slave address followed
by a read bit (R/nW = 1).
7) The master sends the 7-bit slave address followed
by a read bit (R/nW = 1).
8) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
8) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
9) The addressed slave places 8-bits of data on the bus
9) The addressed slave places 8-bits of data on the bus
from the location specified by the register pointer.
from the location specified by the register pointer.
10) The master issues an ACKNOWLEDGE (A) signaling
the slave that it wishes to receive more data.
10) The master issues a NOT-ACKNOWLEDGE (nA).
11) The master sends a STOP condition (P) or a RE-
PEATED START condition (Sr). Issuing a P ensures
that the bus input filters are set for 1MHz or slower
operation. Issuing a REPEATED START (Sr) leaves
the bus input filters in their current state.
11) Steps 9 to 10 are repeated as many times as the
master requires. Following the last byte of data, the
master must issue a NOT-ACKNOWLEDGE (nA) to
signal that it wishes to stop receiving data.
12) The master sends a STOP condition (P) or a RE-
PEATED START condition (Sr). Issuing a STOP (P)
ensures that the bus input filters are set for 1MHz or
slower operation. Issuing a REPEATED START (Sr)
leaves the bus input filters in their current state.
Reading from Sequential Registers
Figure 11 shows the protocol for reading from sequential
registers. This protocol is similar to the “Read Byte” protocol
except the master issues an ACKNOWLEDGE (A) to signal
LEGEND
*P FORCES THE BUS FILTERS TO SWITCH TO
THEIR ≤ 1MHz MODE. SR LEAVES THE BUS
FILTERS IN THEIR CURRENT STATE.
MASTER TO
SLAVE
SLAVE TO
MASTER
NUMBER
OF BITS
1
7
1
0
1
8
1
1
7
1
1
1
8
1
S
SLAVE ADDRESS
A
REGISTER POINTER X A Sr SLAVE ADDRESS
A
DATA X
A
R/
nW
R/
nW
NUMBER
OF BITS
8
1
8
1
8
1
DATA X+1
A
DATA X+2
A
DATA X+3
A
Register Pointer = X + 1
Register Pointer = X + 2
Register Pointer = X + 3
NUMBER
OF BITS
8
1
8
1
8
1
1
P or
Sr*
DATA n-2
A
DATA n-1
A
DATA n
nA
Register Pointer =
X + (n-3)
Register Pointer =
X + (n-2)
Register Pointer =
X + (n-1)
Figure 11. Reading Continuously from Sequential Registers
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
3) The master sends the 8-bit master code of
Engaging HS-Mode for Operation
up to 3.4MHz
00001xxxb where xxxb are don’t care bits.
Figure 12 shows the protocol for engaging HS-mode
operation. HS-mode operation allows for a bus operating
speed up to 3.4MHz.
4) The addressed slave issues a NOT-ACKNOWL-
EDGE (nA).
5) The master may now increase its bus speed up to
3.4MHz and issue any read/write operation.
The “Engaging HS-Mode” protocol is as follows:
1) Begin the protocol while operating at a bus speed of
1MHz or lower.
The master may continue to issue high-speed read/write
operations until a STOP (P) is issued. Issuing a STOP
(P) ensures that the bus input filters are set for 1MHz or
slower operation.
2) The master sends a START command (S).
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
1
8
1
1
ANY READ/WRITE PROTOCOL
FOLLOWED BY Sr
ANY READ/WRITE PROTOCOL
FOLLOWED BY Sr
S
HS-MASTER CODE
nA Sr
Sr
Sr ANY READ/WRITE PROTOCOL
P
FAST- MODE
HS-MODE
FAST-MODE
Figure 12. Engaging HS-Mode
Register Map
Register Reset Condition
Registers reset to their default values when either of the following conditions become true:
● Undervoltage Lockout (V
< V
)
SYS
UVLO_F
● Device Disabled (EN = logic low)
MAX77813 Registers
2
I C Device Address: 0x18 (7-bit)
ADDRESS
0x00
NAME
DEVICE_ID
STATUS
CONFIG1
CONFIG2
VOUT
ACCESS
R
MSB
LSB
RESET
RESERVED
—
̶
0x01
R
RESERVED
RESERVED RESERVED RU_SR
TSHDN POK OVP OCP
OVP_TH[1:0] AD FPWM
RESERVED
0x00
0x0E
0x70
varies
0x02
R/W
R/W
R/W
RD_SR
EN_PD POK_POL
VOUT[6:0]
0x03
RESERVED
RESERVED
EN
0x04
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Register Details
DEVICE ID (0x00)
BIT
Field
7
6
5
4
3
2
1
0
RESERVED[7:0]
—
Reset
Access
Read Only
BITFIELD
RESERVED
BITS
DESCRIPTION
DECODE
7:0
Reserved. Bits for internal use only.
N/A
STATUS (0x01)
BIT
Field
7
6
5
4
3
2
POK
1
OVP
0
OCP
RESERVED[3:0]
0b0000
TSHDN
0b0
Reset
Access
0b0
0b0
0b0
Read Only
Read Only
Read Only
Read Only
Read Only
BITFIELD
BITS
DESCRIPTION
DECODE
RESERVED
TSHDN
3:0
Reserved. Reads are don’t care.
N/A
0 = Junction temperature OK (T < T
1 = Thermal shutdown (T ≥ T
)
SHDN
J
3
2
Thermal Shutdown Status
)
J
SHDN
0 = Output not OK (V
OUT
1 = Output OK (V
< 75% of target) or disabled.
> 80% of target)
POKn
Power-OK Status
OUT
0 = Output OK (V
< the OVP threshold set by
OUT
OVP_TH[1:0]) or disabled.
OVP
OCP
1
0
Output Overvoltage Status
Overcurrent Status
1 = Output overvoltage. V
set by OVP_TH[1:0].
> the OVP threshold
OUT
0 = Current OK
1 = Overcurrent
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
CONFIG1 (0x02)
BIT
Field
7
6
5
4
3
2
1
AD
0
RESERVED
0b00
RU_SR
0b0
RD_SR
0b0
OVP_TH[1:0]
0b11
FPWM
0b0
Reset
Access
0b1
Read, Write
Read, Write
Read, Write
Read, Write
Read, Write
Read, Write
BITFIELD
BITS
DESCRIPTION
Reserved. Bit is a don’t care.
DECODE
RESERVED
7:6
N/A
V
V
Rising Ramp Rate Control.
increases with this slope
OUT
OUT
0 = +20mV/µs
1 = +40mV/µs
RU_SR
5
whenever the output voltage target is
modified upwards while the converter is
enabled.
V
V
Falling Ramp Rate Control.
decreases with this slope
OUT
OUT
0 = -5mV/µs
1 = -10mV/µs
RD_SR
4
whenever the output voltage target
is modified downwards while the
converter is enabled.
00 = No OVP (protection disabled)
01 = 110% of V
10 = 115% of V
11 = 120% of V
target
target
target
V
Overvoltage Protection (OVP)
OUT
OUT
OUT
OUT
OVP_TH[1:0]
3:2
Threshold Control
Output Active Discharge Resistor
Enable
0 = Disabled
1 = Enabled
AD
1
0
0 = SKIP mode
1 = Forced PWM (FPWM) mode
FPWM
Converter Mode Control
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
CONFIG2 (0x03)
BIT
Field
Reset
7
6
5
4
3
2
1
0
RESERVED
0b0
BB_EN
0b1
EN_PD
0b1
POK_POL
0b1
RESERVED
0b0000
Access Read, Write
Read, Write
Read, Write
Read, Write
Read, Write
BITFIELD
BITS
DESCRIPTION
DECODE
RESERVED
7
Reserved. Bit is a don’t care.
N/A
While EN (pin) = logic low:
0 or 1 = Output disabled
While EN (pin = logic high:
0 = Output disabled
Buck-boost output software enable
control. See Table 1.
EN
6
1 = Output enabled
EN input pulldown resistor enable
control.
0 = Pulldown disabled
1 = Pulldown enabled
PD
5
0 = Active-low
1 = Active-high
Power-OK (POK) output polarity
control.
POK_POL
4
RESERVED
3:0
Reserved. Bitfield is a don’t care.
N/A
V
OUT
(0x04)
BIT
7
6
5
4
3
2
1
0
Field
RESERVED
0b0
VOUT[6:0]
Reset
Varies (See the Ordering Information table)
Access Read, Write
Read, Write
BITFIELD
BITS
DESCRIPTION
DECODE
RESERVED
7
Reserved. Bit is a don’t care.
N/A
0x00 = 2.60V
0x01 = 2.62V
0x02 = 2.64V
…
0x23 = 3.30V
…
0x28 = 3.40V
…
0x7E = 4.12V
0x7F = 5.14V
Output Voltage Control.
Sets the V
target. Configurable
OUT
in 20mV per LSB from 0x00
(2.60V) to 0x7F (5.14V).
VOUT
6:0
The default value of this register is
preset. See the Ordering Information
table. Overwriting the default value
sets a new target output voltage.
Maxim Integrated
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Ordering Information
DEFAULT
PART
PIN-PACKAGE
V
OUT
20-Bump (5 x 4)
0.4mm Pitch
MAX77813EWP33+T
MAX77813EWP+T
3.3V
3.4V
20-Bump (5 x 4)
0.4mm Pitch
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Maxim Integrated
│ 29
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MAX77813
5.5V Input, 2A, High-Efficiency
Buck-Boost Converter
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
10/18
1/19
0
1
Initial release
—
Grammar and content fixes
1–27
Updated the Electrical Characteristics table, Bump Description table, and Figure 1;
added the following sections: Burst Mode (Enhanced Load Response), Output Voltage
Selection and Slew Rate Control, Output Overvoltage Protection (OVP), Thermal
4, 12, 13,
16–18, 26
2
3/19
2
Shutdown, I C Serial Interface, and Applications Information, updated Register Details
table
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2019 Maxim Integrated Products, Inc.
│ 30
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