MAX77863AEWT_技术文档

EVALUATION KIT AVAILABLE

Click here for production status of speciﬁc part numbers.

MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

General Description

The MAX77863 is a complete power management IC

(PMIC) for mobile devices using multicore application

processors.

Beneﬁts and Features

● Operates from a 2.6V to 5.5V Source

● Allows for Low-Cost PCB Technology

● Includes 4 DC-to-DC Step-Down Regulators

● Includes 9 Low-Dropout Linear Regulators

● No External MOSFETs Required

It is available in a wafter-level package (WLP) to be used

in space-constrained applications.

The IC offers a total of 13 regulators. Two regulators have

differential remote sensing and are rated for both continu-

ous and peak output current.

● Consumes just 12µA in its Lowest-Power State

● Low-Power Modes on all Regulators Reduces Power

Consumption

Numerous factory-programmable options allow the IC to

be tailored for many applications. Contact the factory for

more information about programmable options; minimum

order quantities may apply.

● LDOs are Stable with only the Point-of-Load

Capacitor

2

● I C 3.0 Compatible Interface

● nIRQ Interrupt Output

● Eight GPIOs

Applications

● Netbooks

● Tablet PCs

● Real-Time Clock (RTC)

• Backup Battery Charger

• Timing Clock Output

● Personal Internet Viewer

● Digital Photo Frames

● Set-Top Boxes

● Smartphones

● GPS

● System Watchdog Timer

2

● I C Watchdog Timer

● Automotive Aftermarket Accessories

● Bidirectional Reset I/O

● Flexible Power Sequencer (FPS)

● Thermal Shutdown

Ordering Information appears at end of data sheet.

19-7424; Rev 1; 2/20

MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

TABLE OF CONTENTS

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Electrical Characteristics—SD0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Electrical Characteristics—SD1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Electrical Characteristics—SD2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Electrical Characteristics—SD3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Electrical Characteristics—150mA PMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Electrical Characteristics—300mA PMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Electrical Characteristics—150mA NMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Electrical Characteristics—300mA NMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Electrical Characteristics—450mA NMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Electrical Characteristics—GPIOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Electrical Characteristics—RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Electrical Characteristics—32kHz Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Electrical Characteristics—Backup Battery Charger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Electrical Characteristics—On-Off Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Electrical Characteristics—FPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

2

Electrical Characteristics—I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

2

Electrical Characteristics—I C (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Bump Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Bump Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Simplified Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Voltage References, Bias Currents, and Timing References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Voltage Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Thermal Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Bidirectional Reset Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Global Shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Global Shutdown Events with Sequenced Shutdown and Automatic Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Global Shutdown Events with Sequenced Shutdown to the Off State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Global Shutdown Events with Immediate Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Maxim Integrated

│ 2

www.maximintegrated.com

MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

(

)

TABLE OF CONTENTS CONTINUED

Global Low-Power Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Status and Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

System Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Step-Down Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Efficiency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Step-Down Regulator Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Buck Regulator Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Step-Down Regulator Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Output Voltage Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Dynamic Voltage Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Remote Output Voltage Sensing (ROVS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Out-of-Phase Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

SKIP/FPWM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Power-OK Comparators for Step-Down Regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Active-Discharge Resistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

SD3 Default Voltage (D_SD3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Linear Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Basic LDO Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

LDO Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Soft-Start and Dynamic Voltage Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Power-OK Comparators for Linear Regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Active-Discharge Resistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Overvoltage Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

P-Channel Linear Regulator Output Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

N-Channel Linear Regulator Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

BIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Maxim Integrated

│ 3

www.maximintegrated.com

MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

(

)

TABLE OF CONTENTS CONTINUED

GPO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

GPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

GPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Alternate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Real-Time Clock (RTC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Read/Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Reading from RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

SMPL (Sudden Momentary Power Loss) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

32kHz Crystal Oscillator and Buffered Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Backup Battery Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

ON/OFF Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

EN0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

Manual Reset with EN0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

EN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

EN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

ACOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

LID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

SMPL, ALARM1, and ALARM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

SHDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

MBATT_OK and MBATTLOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

FPS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

FPS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Nonvolatile Power-OFF Event Recorder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Flexible Power Sequencer (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

Commitment Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Changing Regulator Enable Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

2

I C Interface and Interrupt Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

2

I C System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

2

I C Interface Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

2

I C Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

2

I C Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

2

I C Acknowledge Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

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Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

(

)

TABLE OF CONTENTS CONTINUED

2

I C Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

2

I C Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

2

I C General Call Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

2

I C Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

2

I C Communication Speed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

2

I C Communication Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Writing to a Single Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Writing to Sequential Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Writing Multiple Bytes Using Register-Data Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Reading from a Single Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Reading from Sequential Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Engaging HS-Mode for Operation up to 3.4MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Factory OTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

SFT_RST and PWR_OFF Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

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Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

LIST OF FIGURES

Figure 1. Global Resource Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 2. Simplified Interrupt, Status, and Mask Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 3. Interrupt Service Routine Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 4. Global Shutdown State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 5. Simplified Logic for Global Shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 6. Simplified Timing Diagram for Global Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 7. Simplified Timing Diagram for Global Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 8. Simplified Logic for Global Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 9. Buck Control Scheme Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 10. Linear Regulator Functional Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 11. LDO Bias Enable Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 12. GPIO Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 13. RTC Simplified Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 14. Backup Battery Charger, 32kHz Crystal Oscillator and RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 15. Functional Block Diagram for ACOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 16. Functional Block Diagram for LID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 17. Functional Block Diagram for SHDN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 18. Simplified Block Diagram: ON/OFF Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 19. State Diagram: ON/OFF Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 20. EN0 Simplified Input Stage: Active-High or Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 21. EN1 Simplified Input Stage: Active-High or Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 22. EN2 Simplified Input Stage: Active-High or Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 23. ACOK Simplified Input Stage: Active-High or Low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 24. LID Simplied Input Stage: Active-High or Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 25. SHDN Simplified Input Stage: Active-High or Low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 26. Application Processor Power-Up and Power-Down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 27. Application Processor Entering and Exiting Sleep Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 28. Example Timing Diagram: Flexible Power Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Figure 29. Functional Logic Diagram: Communications Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Figure 30. Functional Logic Diagram: Communications Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Figure 31. START and STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

Figure 32. Acknowledge Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

Figure 33. Slave Address Byte Example Using the Power Management Slave Address. . . . . . . . . . . . . . . . . . . . . .114

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

(

)

LIST OF FIGURES CONTINUED

Figure 34. Writing to a Single Register with the “Write Byte” Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

Figure 35. Writing to Sequential Register “x” to “n”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

Figure 36. Writing to Multiple Registers with the “Multiple Byte Register-Data Pair” Protocol . . . . . . . . . . . . . . . . . .118

Figure 37. Reading from a Single Register with the “Read Byte” Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Figure 38. Reading Continuously from Sequential Registers “x” to “n”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 39. Engaging HS-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 40. MAX77863 Typical Application Circuit for 1s Battery Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Figure 41. MAX77863 Typical Application Circuit for 2s Battery Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

LIST OF TABLES

Table 1. Regulator Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 2. Register Type Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 3. Out-of-Phase Switching Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 4. D_SD3 Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 5. Basic LDO Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 7. GPIO Programming Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 6. Alternate Modes for GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 8. 32kHz Crystal Oscillator Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 9. SD0 Power Mode Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 10. ON/OFF Controller State Diagram Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 11. Example Configuration of the Flexible Power Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Table 12. Changing Enable Sources Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

2

Table 13. MAX77863 I C Slave Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

2

Table 14. I C Communication Protocols Supported by Different Functional Blocks. . . . . . . . . . . . . . . . . . . . . . . . . .115

Table 15. OTP Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Absolute Maximum Ratings

LDO and Step-Down Output

Maximum DC current for 1 year is 20mA

Short-Circuit Duration............................................Continuous

Maximum AC current is 20mA/duty where the peak must be less

than 200mA (Note 1)

Continuous Power Dissipation at T = +70°C)

A

(Derate 28.6mW/°C above +70°C, Multilayer PCB)... 2.353W

Operating Ambient Temperature Range............. -40°C to +85°C

Operating Junction Temperature Range .......... -40°C to +150°C

Storage Temperature Range............................ -65°C to +150°C

Soldering Temperature (reflow).......................................+260°C

IN_LDO0-1, IN_LDO2, IN_LDO3-5, IN_LDO4-6,

nRST_IO to GND .................................................-0.3V to +6.0V

Maximum DC current for 1 year is 20mA

Maximum AC current is 20mA/duty where the peak must be less

than 200mA (Note 1)

GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5,

GPIO6, GPIO7 to GND ....................................-0.3V to +6.0V

(when open-drain GPO with internal pullup disabled)

IN_LDO7-8, MBATT, MON, BBAT, INI2C, SCL,

-0.3V to lower of (V

+0.3V) and +6.0V

(when otherwise)

EN0, EN1, SHDN, ACOK, LID,

GPIO_INA to GND............................................-0.3V to +6.0V

GPIO_INx

Maximum 1-year DC source current is 12mA for each GPO

Maximum 1-year total GPO source current is 100mA for GPO0-3

and 100mA for GPIO4-7

Maximum AC source current for each GPO is 12mA/duty where

the peak must be less than 200mA (Note 1)

Maximum 1-year DC sink current is 20mA for each GPO

Maximum 1-year total GPO sink current is 100mA for all GPO

combined

Maximum AC sink current for each GPO is 20mA/duty where the

peak must be less than 200mA (Note 1)

GPIO_INB to GND ............................. -0.3V to (V

OUT_LDO0,

+ 0.3V)

MBATT

OUT_LDO1 to GND..................-0.3V to (IN_LDO0-1 + 0.3V).

Output short-circuit duration is continuous.

OUT_LDO2 to GND ........................ -0.3V to (IN_LDO2 + 0.3V).

Output short-circuit duration is continuous.

OUT_LDO3,

OUT_LDO5 to GND..................-0.3V to (IN_LDO3-5 + 0.3V).

Output short-circuit duration is continuous.

OUT_LDO4,

OUT_LDO6 to GND..................-0.3V to (IN_LDO4-6 + 0.3V).

Output short-circuit duration is continuous.

OUT_LDO7,

OUT_LDO8 to GND..................-0.3V to (IN_LDO7-8 + 0.3V).

Output short-circuit duration is continuous.

AVSD to GND................. -0.3V to +6.0V. AVSD and all INy_SDx

must be within ±0.3V from each other.

INA_SD0 to PGA_SD0, INB_SD0 to PGB_SD0,

IN_SD1 to PG_SD1, IN_SD2 to PG_SD2,

IN_SD3 to PG_SD3.........................................-0.3V to +6.0V.

Within ±0.3V from AVSD

RMS current must not exceed 3.0A per bump at 110°C for 10k

hours out of 100k hours of operating life

PGA_SD0, PGB_SD0, PG_SD1, PG_SD2, PG_SD3 to

(PGy_SDx, GND, and XGND).............................Within ±0.3V

RMS current must not exceed 3.0A per bump at 110°C

for 10k hours out of 100k hours

XOUT to XGND.......-0.3V to lower of (V

XIN to XGND....... -0.3V to lower of (V

D_SD3 to GND....-0.3V to lower of (V

+ 0.3V) and +6.0V

RTC

BBATT

MBATT

FB_SD0, FB_SD1, FB_SD2, FB_SD3 to

32K_OUT0 to GND ...........-0.3V to lower of (V

+ 0.3V)

and +6.0V

GPIO_INB

GND...................-0.3V to lower of (V

+ 0.3V) and +4.5V

AVSD

SNSP_SD0, SNSP_SD1, F4, SNSN_SD0, SNSN_SD1, F3 to

GND...................-0.3V to lower of (V + 0.3V) and +6.0V

LXA_SD0, LXB_SD0, LX_SD1, LX_SD2,

Maximum DC current for 1 year is 20mA

Maximum AC current is 20mA/duty where the peak must be less

than 200mA (Note 1)

AVSD

LX_SD3 ...... RMS current must not exceed 3.0A per bump at

110°C for 10k hours out of 100k hours (Note 2)

SDA to GND.........................................................-0.3V to +6.0V

Maximum DC current for 1 year is 25mA

GND................ Within ±0.3V from PG_SDx grounds and XGND

XGND ................Within ±0.3V from PG_SDx grounds and GND

Maximum AC current is 25mA/duty where the peak must be less

than 200mA (Note 1)

nIRQ to GND......................Lower of (V

+ 0.3V) and +6.0V

INI2C

Note 1: Maximum AC current capability is rated as some current divided by a duty cycle with a maximum peak value. For example,

given an AC current capability of “20mA/duty where the peak must be less than 200mA”, a pin can withstand 100mA pulses

at a 20% duty cycle (20mA/20% = 100mA).

Note 2: LXx has internal clamp diodes to PG_SDx and PVx. Applications that forward bias these diodes must take care not to

exceed the current limit and package power dissipation.

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Package Thermal Characteristics

WLP

PACKAGE CODE

Outline Number

W703A4+1

21-100187

Land Pattern Number

Refer to Application Note 1891

Thermal Resistance, Four-Layer Board:

Junction to Ambient (θ

)

37.43°C/W

NA

JA

Junction to Case (θ

)

JC

Note 3: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer

board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Electrical Characteristics

(V

= 3.6V, I

= 0µA, T = -40°C to +85°C, unless otherwise specified, typical values are at T = +25°C.) (Note 4)

MBATT

BBATT

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

MAIN-BATTERY POWER INPUT (MBATT)

V

MBATT

IN_SDx

MBATT/AVSD Operating

Voltage Range

AVSD and SDx must be connected

together

2.6

5.5

V

AVSD

MBATT Undervoltage-

Lockout Threshold

V

falling, 200mV hysteresis

2.5

MBATTUVLO

MBATT

AVSD Undervoltage-

Lockout Threshold

V

falling, 25mV hysteresis

falling, 200mV hysteresis

2.5

3

V

AVSDUVLO

V

AVSD_LOW

AVSD

AVSD Low Threshold

AVSD

MBATT/AVSD

Overvoltage-Lockout

Threshold

V

rising, 200mV hysteresis

5.70

5.85

12

6.00

25

V

MBATTOVLO

MBATT

All regulators oﬀ, 32kHz oscillator in low-

power mode (PWR_MD_32k = 0b00),

V

= 3.6V, I

= 0µA

MBATT

BBATT

I

+

Q_MBATT

All regulators oﬀ, 32kHz oscillator in

low-power mode (PWR_MD_32k = 0b00),

internal reference and bias circuitry active

Quiescent Supply Current

µA

I

Q_AVSD

42

(L_B_EN = 1), V

= 3.6V,

MBATT

I

= 0µA

BBATT

AVSD Low Threshold

Comparator Quiescent

Supply Current

AVSD low is enabled whenever SD1 or

SD2 is enabled

6.5

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Electrical Characteristics (continued)

(V

= 3.6V, I

= 0µA, T = -40°C to +85°C, unless otherwise specified, typical values are at T = +25°C.) (Note 4)

MBATT

BBATT

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Current into M

BATT

and all LDO power

inputs, V = 3.6V.

MBATT

All LDO power inputs

are 3.6V,

Normal mode, all

LDOs enabled

265

I

= 0µA, LDOs

BBATT

set to minimum output

voltage, all step-down

regulators disabled,

32kHz clock buﬀer

disabled, 32kHz

No-Load LDO Supply

Current

µA

oscillator in low-power

mode (PWR_MD_32k

Low-power

mode, LDO2-

LDO6 enabled

(PMOS)

= 0b00), V

=

GPIOA-IN

58

V

= 0V; this

GPIOB_IN

does not include any

current into nRST_IO

or nIRQ

Current into M

,

BATT

AVSD, and all step-

down power inputs,

Normal mode,

all step-downs

enabled

V

= 3.6V, all

MBATT

145

regulator inputs are

3.6V, I = 0µA, all

BBATT

step-downs enabled

with their minimum

output voltages, all

remote feedback

disabled, all LDOs

disabled, 32kHz clock

buﬀer disabled, 32kHz

oscillator in

No-Load Step-Down

Supply Current

µA

Low-power

mode, all

step-downs

enabled

low-power mode

(PWR_MD_32k =

82.5

0b00), V

=

GPIOA_IN

V

= 0V. This

GPIOB_IN

does not include any

current into nRST_IO

or nIRQ

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Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

Electrical Characteristics (continued)

(V

= 3.6V, I

= 0µA, T = -40°C to +85°C, unless otherwise specified, typical values are at T = +25°C.) (Note 4)

MBATT

BBATT

A

PARAMETER

SYMBOL

CONDITIONS

Current into M

MIN

TYP

MAX

UNITS

,

BATT

AVSD all step-down

power inputs, and all

LDO power inputs,

Normal mode,

all regulators

enabled

375

520

V

= 3.6V,

MBATT

all regulator inputs

are 3.6V, I

=

BBATT

0µA, regulators set

to minimum output

voltage, all remote

feedback disabled,

32kHz clock buﬀer

disabled, 32kHz

No-Load LDO and

Step-Down Supply

Current

µA

Low-power

mode, all

regulators except

LDO0/1/7/8

(NMOS)

oscillator in low-power

mode (PWR_MD_32k

110

165

= 0b00), V

=

GPIOA-IN

VG

= 0V; this

PIOB_IN

does not include any

current into nRST_IO

or nIRQ

BACKUP-BATTERY POWER INPUT

BBATT Current

THERMAL ALARMS AND SHUTDOWN

V

= 2.45V

= 3.00V

2.0

2.2

BBATT

V

= 0V,

MBATT

I

µA

BBATT

PWR_MD_32k = 0b00

4.2

BBATT

Thermal Alarm 1

Thermal Alarm 2

T

T rising, 5°C hysteresis

120

140

°C

J120

J140

J

T rising, 5°C hysteresis

J

Thermal Shutdown

Temperature

T

T rising, 15°C hysteresis

J

165

°C

JSHDN

VOLTAGE MONITOR (MON)

LBHYST[1:0] = 0b00

LBHYST[1:0] = 0b01

LBHYST[1:0] = 0b10

LBHYST[1:0] = 0b11

100

200

300

400

Low-Battery Hysteresis

V

mV

HYSL

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Electrical Characteristics (continued)

(V

= 3.6V, I

= 0µA, T = -40°C to +85°C, unless otherwise specified, typical values are at T = +25°C.) (Note 4)

MBATT

BBATT

A

PARAMETER

SYMBOL

CONDITIONS

LBDAC[2:0] = 0b000

MIN

TYP

2.7

2.8

2.9

3.00

3.1

3.2

3.3

3.4

0

MAX

UNITS

LBDAC[2:0] = 0b001

LBDAC[2:0] = 0b010

LBDAC[2:0] = 0b011

LBDAC[2:0] = 0b100

LBDAC[2:0] = 0b101

LBDAC[2:0] = 0b110

LBDAC[2:0] = 0b111

2.95

3.05

Low-Battery Threshold

V

falling

V

MONL

MON

T

= +25°C

= +85°C

-125

+125

A

MON Input Bias Current

I

= 3.0V

nA

µs

MON

0.5

10

A

Response Time

100mV threshold overdrive

INTERRUPT TIMING

Interrupt Event to

nIRQ-Low Time

10

ns

°C

Interrupt Register Read to

nIRQ-Deassert Time

Thermal Shutdown

Temperature

T

T rising, 15°C hysteresis

165

JSHDN

J

BIDIRECTIONAL RESET INPUT/OUTPUT (nRST_IO)

OTP_TRSTO[1:0] = 0b00

1.02

1.28

10.24

40.96

81.92

1.54

OTP_TRSTO[1:0] = 0b01

OTP_TRSTO[1:0] = 0b10

OTP_TRSTO[1:0] = 0b11

Reset Output Deassert

Delay Time

t

ms

RST-O

Reset Input Debounce

Timer

t

24

30

1

36

DBNC

Minimum V

for

MBATT

V

nRST_IO Assertion

Output Voltage Low

V

I

= 4mA, RSO = 1

SINK

0.4

1

OL

V

= 5.5V,

MBATT

T

= +25°C

= +85°C

0.001

0.01

A

Output High Leakage

Current

= 0V

nRST_IO

I

µA

OZH

and 5.5V,

RSO = 0

T

Input Voltage Low

Input Voltage High

Input Hysteresis

V

RSO = 0

0.4

1

V

IL

V

1.4

IH

V

0.05

HYS

V

= 5.5V,

= 0V and

T

= +25°C

0.001

MBATT

A

Input Leakage Current

I

µA

i

nRST_IO

= +85°C

0.01

5.5V, RSO = 0

A

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Complete System PMIC, Featuring 13 Regulators,

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Electrical Characteristics (continued)

(V

= 3.6V, I

= 0µA, T = -40°C to +85°C, unless otherwise specified, typical values are at T = +25°C.) (Note 4)

MBATT

BBATT

A

PARAMETER

LOGIC

DEDICATED ACTIVE-LOW OPEN-DRAIN OUTPUTS—nIRQ

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Output Voltage Low

V

I

= 4mA

SINK

0.4

1

V

OL

T

= +25°C

= +85°C

0.001

0.01

A

Output High Leakage

Current

I

V

= 5.5V

µA

OZH

MBATT

A

DEDICATED INPUT—EN0, EN1, EN2, SHDN, ACOK, LID

Input Voltage Low

Input Voltage High

Input Hysteresis

V

0.4

V

IL

V

1.4

IH

V

0.05

10

HYS

R

EN0, OTP_EN0AL = 1, Figure 22

ACOK, OTP_ACOKAL = 1, Figure 25

LID, OTP_LIDAL = 1, Figure 26

PUEN0

R

100

10

PUACOK

Internal Pullup Resistance

kΩ

R

PULID

R

SHDN, OTP_SHDNAL = 1, Figure 27

EN0, OTP_EN0AL = 0, Figure 22

ACOK, OTP_ACOKAL = 0, Figure 25

LID, OTP_LIDAL = 0, Figure 26

PUSHDN

R

PDEN0

R

100

PDACOK

Internal Pulldown

Resistance

R

PDLID

R

SHDN, OTP_SHDNAL = 0, Figure 27

PDSHDN

TIMING CLOCK OUTPUT—32K_OUT0

Output Voltage Low

V

I

= 4mA, V = 1.7V

GPIO_INB

0.4

1

V

OL

SINK

= 2mA, OTP_32K = 0,

0.7 x

V

GPIO-INB

SOURCE

Output Voltage High

V

OH

V

= 1.7V

GPIO_INB

Output High Leakage

Current

T = +25°C, OTP_32K = 1,

A

V

I

0.001

µA

OZH

= 1.7V

GPIO_INB

GPIO INPUT—GPIO0-GPIO7

GPIO0-3

GPIO4-7

0.5

Input Voltage Low

V

IL

0.7 x

GPIO0-3

GPIO4-7

V

GPIO_INA

Input Voltage High

V

IH

0.7 x

V

GPIO_INB

Input Hysteresis

0.25

V

HYS

V

= 5.5V

GPIO_INB

= 0V and 5.5V

T

= +25°C

= +85°C

0.001

1

GPIO_INA

A

Input Leakage Current

I

µA

i

0.01

V

A

IN

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

Electrical Characteristics (continued)

(V

= 3.6V, I

= 0µA, T = -40°C to +85°C, unless otherwise specified, typical values are at T = +25°C.) (Note 4)

MBATT

BBATT

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

GPIO PUSH-PULL OUTPUT—GPIO0-GPIO7

I

= 4mA

0.08

0.25

SINK

Output Voltage Low

Output Voltage High

V

OL

= 12mA

0.7 x

GPIO0-3, I

= 4mA

SOURCE

V

GPIO_INA

V

OH

0.7 x

GPIO4-7, I

V

GPIO_INB

GPIO OPEN-DRAIN OUTPUT—GPIO0-GPIO7

I

= 4mA

0.08

0.25

SINK

Output Voltage Low

V

OL

= 12mA

V

= 5.5V, T = +25°C

GPIO_INx

A

0.01

0.1

1.0

internal pullup/pulldown disabled

Output High Leakage

Current

I

µA

OH

V

= 5.5V, T = +85°C

GPIO_INx

A

internal pullup/pulldown disabled

GPIO PULL RESISTANCES—GPIO0-GPIO7

Pullup Resistance

R

Note 5

50

100

160

kΩ

PU

PD

Pulldown Resistance

SDA AND SCL I/O STAGES—SDA, SCL

SCL, SDA Input High

Voltage

0.7 x

V

INI2C

V

IH

SCL, SDA Input Low

Voltage

0.3 x

V

IL

V

INI2C

0.05 x

SCL, SDA Input Hysteresis

V

HYS

V

INI2C

SCL, SDA Input Current

SDA Output Low Voltage

I

V

= 3.6V or 0V

-10

+10

0.4

μA

i

I2CIN

V

Sinking 20mA

V

OL

Note 4: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed through

A

correlation using statistical quality control methods.

Note 5: The min/max variation that is shown is based on process statistics. These parameters are not production tested.

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Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

Electrical Characteristics—SD0

(V

= 3.6V, V

= 1.0V, C

= 2 x 22µF, L0A = L0B = 1.0µH, T = -40°C to +85°C. Typical specifications are at T = +25°C,

IN_

SD0

A

unless otherwise noted.) (Note 26)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STEP-DOWN REGULATOR

V

AVSD

AVSD, INA_SD0, and INB_SD0 must be

connected together

Input Voltage Range

V

2.6

5.5

V

INA_SD0

INB_SD0

V

= 1.2V, accuracy includes

SD0

T

= +25°C

-1.5

-2.5

0

+1.5

+2.5

A

static variations in line and

temperature, no load, PWM

mode, normal-power mode

= -40°C to

A

+85°C

V

from 0.8V to 1.4V,

SD0

T

= +25°C

-2.0

-3.0

0

+2.0

+3.0

A

accuracy includes static

variations in line and

temperature, no load, PWM

mode, normal-power mode

T

= -40°C to

A

+85°C

V

from 1.0V to 1.4V,

Output Voltage

Accuracy

SD0

V

%

SD0

accuracy includes transient

variations in line, load, and

temperature during dynamic

load transients from 0mA to

1.4A with a transient rate of

3.2A/µs, PWM mode or skip

mode, normal-power mode

T

= -40°C to

A

±5

+85°C

T

= -5°C to

A

-4.0

-5.0

0

+4.0

+5.0

Low-power mode,

+85°C

I

= 0mA to 5mA,

SD0

T

= -40°C to

A

any output voltage

+85°C

Load Regulation

Line Regulation

LDREG

-0.25

0.08

%/A

%/V

SD0

V

= 2.6V to 5V

MBATT

Shutdown Supply

Current

I

0.1

µA

SHDN

I

No switching, remote output voltage sensing oﬀ

Switching, no load, skip mode

Low-power mode

32

40

10

Q_SD0

I

Q_LPM_SD0

µA

Additional current consumed

by SD0 remote output voltage

sense circuitry total in normal

ROVS_EN_

SD0 = 1

Supply Quiescent

Current

10

Q_SNS_EN0

mode is I = I

+

ROVS_EN_

SD0 = 0

Q

Q_SD0

0.1

20

I

Q_SNS_EN0

I

Switching, no load, forced PWM mode

mA

Q_PWM_SD0

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Electrical Characteristics—SD0 (continued)

(V

= 3.6V, V

= 1.0V, C

= 2 x 22µF, L0A = L0B = 1.0µH, T = -40°C to +85°C. Typical specifications are at T = +25°C,

IN_

SD0

A

unless otherwise noted.) (Note 26)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Output Voltage Range

12.5mV steps

< V

0.6000

1.4000

4.84

V

< 5.5V

AVSD

8000

6000

5

AVSD_LOW

Maximum Output

Current (Note 9)

I

2.6V < V < V

AVSD_LOW

mA

MAX_SD0

IN

Low-power mode

Switching Frequency

Peak Current Limit

f

Normal operation

3.96

4.4

MHz

mA

SW

I

Per phase, FPWM mode, V

FPWM mode

> V

< V

> V

< V

4400

3600

1500

60

LIMPP_HIGH0

AVSD

AVSD_LOW

I

LIMPP_LOW0

I

LIMNV_HIGH0

Valley Current Limit

mA

I

LIMNV_LOW0

Negative Current Limit

PMOS On-Resistance

NMOS On-Resistance

I

mA

mΩ

LIMNN0

R

IN_ = 3.6V, each phase

ON_PCH0

50

ON_NCH0

NMOS Zero-Crossing

Threshold

Skip mode

20

mA

Skip mode, no load, C

= 2 x 22µF

= 4 x 22µF

40

20

SD0

V

Ripple in Skip

SD0

mV

P-P

Mode (Note 8)

V

Ripple in PWM

FPWM mode, ESR = 1.5mΩ,

ESL = 0.2nH, C = 2 x 22µF

SD0

2

Mode

SD0

T

= +25°C

= +85°C

0.1

1

±1

A

LX0 Leakage Current

LX_ = PG_ or IN_

µA

A

Output disabled, V

FB_SD0 to PG_SD0, active discharge disabled

(nADE_SD0 = 1)

= 1V, current from

OUT

FB_SD0 Disabled

Leakage Current

0.1

µA

Output disabled, resistance from FB_SD0 to

PGx_SD0, active discharge enabled

(nADE_SD0 = 0)

FB_SD0 Active

Discharge Resistance

50

44

Ω

Nominal capacitor value

Minimum capacitor value

Minimum Output

Capacitance for Stable

Operation

0µA < I

6000mA,

MAX ESR = 20mΩ

<

OUT0

after deration for initial

accuracy, temperature

coeﬃcient, DC bias

voltage, and aging

C

µF

µH

OSD0

30

Output Inductor

L

MAX DCR = 100mΩ

1.0

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MAX77863

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Electrical Characteristics—SD0 (continued)

(V

= 3.6V, V

= 1.0V, C

= 2 x 22µF, L0A = L0B = 1.0µH, T = -40°C to +85°C. Typical specifications are at T = +25°C,

IN_

SD0

A

unless otherwise noted.) (Note 26)

PARAMETER SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

All other regulators are

oﬀ and L_B_EN = 0

(i.e., central bias oﬀ and

buck bias is oﬀ)

185

At least one LDO is on

Time from the enable or L_B_EN = 1 and all

Turn-On Time

t

signal to the output

starting to increase

step-down are oﬀ

(i.e., central bias is on

and buck bias is oﬀ)

135

µs

ONSD0

At least one other

step-down regulator is

on (i.e., central bias is on

and buck bias is on)

22

After the regulator is disabled; the output voltage

discharges based on load and C . To ensure

fast discharge times, enable the active-discharge

OUT

Turn-Oﬀ Time

t

0.1

µs

OFFSD0

resistor

SR_SD0 [1:0] = 0b01

SR_SD0 [1:0] = 0b00

27.5

13.75

55

Dynamic Voltage

Change Ramp Rate

Note 10

mV/µs

SR_SD0 [1:0] = 0b10

SR_SD0 [1:0] = 0b11

(Note 11)

100

OTP_SD_SS = 1

OTP_SD_SS = 0

25

14

dV/dt_SS_

SD0

Soft-Start Slew Rate

mV/µs

mV

Maximum Remote

Sense Compensation

Range

Voltage drop through power and ground plane,

V

430

RSR

V

= V

- (V

- V

)

RSR

SD0

FB_SD0

SNSP_SD0

SNSN_SD0

Output POK Threshold

V

falling, 3% hysteresis, T = +25°C

A

70

75

8

80

%V

SD0

POK_SD0

Power-OK Noise

Pulse Immunity

t

pulsed from 100% to 80% of regulation

µs

POKNFSD0

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

Electrical Characteristics—SD1

(V

= 3.6V, V

= 1.0V, C

= 22µF, L1 = 1.0µH, T = -40°C to +85°C. Typical specifications are at T = +25°C, unless

IN_

SD1

SD1 A A

otherwise noted.) (Note 26)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

STEP-DOWN REGULATOR

V

AVSD

Input Voltage Range

AVSD and IN_SD1 must be connected together

2.6

-1.5

-2.5

-2.0

-3.0

5.5

V

IN_SD1

V

= 1.2V, accuracy includes

SD1

T

= +25°C

0

+1.5

+2.5

+2.0

+3.0

A

static variations in line and

temperature, no load, PWM mode,

normal-power mode

= -40°C to

A

+85°C

V

from 0.8V to 1.5V, accuracy

SD1

T

= +25°C

A

includes static variations in line

and temperature, no load,

PWM mode, normal-power mode

T

= -40°C to

A

+85°C

Output Voltage

Accuracy

V

from 1.0V to 1.5V, accuracy

SD1

V

%

SD1

includes transient variations in

line, load, and temperature during

dynamic load transients from

0mA to 1.4A with a transient rate

of 3.2A/µs, PWM mode or skip

mode, normal-power mode

T

= -40°C to

A

±5

+85°C

T

= -5°C to

A

-4.0

-5.0

0

+4.0

+5.0

Low-power mode

+85°C

I

= 0mA to 5mA,

SD1

T

= -40°C to

A

any output voltage

+85°C

Load Regulation

Line Regulation

LDREG

-0.25

0.08

%/A

%/V

SD1

V

= 2.6V to 5V

MBATT

Shutdown Supply

Current

I

0.1

µA

SHDN

I

No switching, remote output voltage sensing oﬀ

Switching, no load, skip mode

Low-power mode

16

20

5

Q_SD1

I

Q_LPM_SD1

µA

Supply Quiescent

Current

ROVS_EN_

SD1 = 1

Additional current consumed by

SD0 remote output voltage sense

circuitry total in normal mode is

10

Q_SNS_EN1

ROVS_EN_

SD1 = 0

0.1

10

I

= I

+ I

Q

Q_SD0 Q_SNS_EN0

I

Switching, no load, forced PWM mode

12.5mV steps

mA

V

Q_PWM_SD1

Output Voltage Range

0.60

1.55

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

Electrical Characteristics—SD1 (continued)

(V

= 3.6V, V

= 1.0V, C

= 22µF, L1 = 1.0µH, T = -40°C to +85°C. Typical specifications are at T = +25°C, unless

IN_

SD1

SD1 A A

otherwise noted.) (Note 26)

PARAMETER

SYMBOL

CONDITIONS

< 5.5V

MIN

TYP

MAX UNITS

V

< V

AVSD

AVSD_LOW

3000

2500

Maximum Output

Current (Note 9)

I

2.6V < V < V

AVSD_LOW

mA

MAX_SD1

IN

Low-power mode

Normal operation

5

Switching Frequency

f

3.96

4.4

4.84

MHz

mA

SW

I

FPWM mode, V

FPWM mode

IN_ = 3.6V

> V

< V

> V

< V

3750

3050

3150

3050

775

80

LIMPP_HIGH1

AVSD

AVSD_LOW

Peak Current Limit

Valley Current Limit

I

LIMPP_LOW1

I

LIMNV_HIGH1

mA

I

LIMNV_LOW1

Negative Current Limit

PMOS On-Resistance

NMOS On-Resistance

I

mA

mΩ

LIMNN1

R

ON_PCH1

ON_NCH1

R

IN_ = 3.6V

60

NMOS Zero-Crossing

Threshold

Skip mode

20

mA

Skip mode, no load, C

= 22µF

= 44µF

40

20

SD1

V

Ripple in Skip

SD1

Mode (Note 8)

mV

P-P

V

Mode

Ripple in PWM

FPWM mode, ESR = 3.0mΩ, ESL = 0.4nH,

C = 22µF

SD1

4

T

= +25°C

= +85°C

0.1

1

±1

A

LX_SD1 Leakage

Current

LX_SD1 = PG_SD1

or IN_SD1

µA

T

Output disabled, V

= 1V, current from

FB_SD1 to PG_SD1, active discharge disabled

OUT

FB_SD1 Disabled

Leakage Current

0.1

(nADE_SD1 = 1)

Output disabled, resistance from FB_SD1 to PGA_

SD1, active discharge enabled

(nADE_SD1 = 0)

FB_SD1 Active

Discharge Resistance

100

22

Ω

Nominal capacitor value

Minimum capacitor value

Minimum Output

Capacitance for Stable

Operation

0µA < I

3000mA,

MAX ESR = 20mΩ

<

OUT1

after deration for initial

accuracy, temperature

coeﬃcient, DC bias voltage,

and aging

C

µF

µH

OSD1

15

Output Inductor

L

MAX DCR = 100mΩ

1.0

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

Electrical Characteristics—SD1 (continued)

(V

= 3.6V, V

= 1.0V, C

= 22µF, L1 = 1.0µH, T = -40°C to +85°C. Typical specifications are at T = +25°C, unless

IN_

SD1

A

otherwise noted.) (Note 26)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

All other regulators are oﬀ and

L_B_EN = 0

(i.e., central bias oﬀ and buck

bias is oﬀ)

185

At least one LDO is on or

L_B_EN = 1 and all

step-down are oﬀ

(i.e., central bias is on and

buck bias is oﬀ)

Time from the

enable signal to

the output starting

to increase

Turn-On Time

t

135

µs

ONSD1

At least one other step-down

regulator is on

(i.e., central bias is on and

buck bias is on)

22

After the regulator is disabled, the output voltage

discharges based on load and C . To ensure fast

Turn-Oﬀ Time

t

0.1

µs

OFFSD1

OUT

discharge times, enable the active-discharge resistor

SR_SD1 [1:0] = 0b01

27.5

13.75

55

SR_SD1 [1:0] = 0b00

Note 10

Dynamic Voltage

Change Ramp Rate

mV/µs

SR_SD1 [1:0] = 0b10

SR_SD1 [1:0] = 0b11 (Note 11)

OTP_SD_SS = 1

100

25

dV/dt_SS_

SD1

Soft-Start Slew Rate

mV/µs

mV

OTP_SD_SS = 0

14

Maximum Remote

Sense Compensation

Range

Voltage drop through power and ground plane,

V

430

RSR

V

= V

- (V

- V

)

RSR

SD1

FB_SD1

SNSP_SD1

SNSN_SD1

Output POK Threshold

V

falling, 3% hysteresis, T = +25°C

A

71

75

8

79

%V

SD1

POK_SD1

Power-OK Noise Pulse

Immunity

t

pulsed from 100% to 80% of regulation

µs

POKNFSD1

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

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Electrical Characteristics—SD2

(V

= 3.6V, V

= 1.8V, C

= 22µF, L2 = 1.0µH, T = -40°C to 85°C. Typical specifications are at T = +25°C, unless

IN_

SD2

SD2 A A

otherwise noted.) (Note 26)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STEP-DOWN REGULATOR

V

AVSD and IN_SD2 must be connected

together

AVSD

Input Voltage Range

2.6

5.5

V

IN_SD2

V

= 1.8V, accuracy

SD2

T

= +25°C

-1.5

0

+1.5

A

includes static variations in

line and temperature, no load,

PWM mode, normal-power

mode

T

= -40°C

A

-2.5

-2.0

-3.0

+2.5

+2.0

+3.0

to +85°C

V

from 1.2V to 2.8V,

SD2

T

= +25°C

A

accuracy includes static

variations in line and

temperature, no load, PWM

mode, normal-power mode

T

= -40°C

A

to +85°C

Output Voltage

Accuracy

V

from 1.2V to 2.8V,

V

%

SD2

accuracy includes transient

variations in line, load, and

temperature during dynamic

load transients from 0mA to

1.4A with a transient rate of

3.2A/µs, PWM mode or skip

mode, normal-power mode

T

= -40°C

A

±5

to +85°C

T

= -5°C to

A

-4.0

-5.0

0

+4.0

+5.0

Low-power mode

+85°C

I

= 0mA to 5mA, any

SD2

T

= -40°C

A

output voltage

to +85°C

Load Regulation

Line Regulation

LDREG

-0.25

0.04

%/A

%/V

SD2

V

= 2.6V to 5V

MBATT

Shutdown Supply

Current

I

0.1

16

µA

SHDN

No switching, remote output voltage

sensing oﬀ

I

Q_SD2

µA

Supply Quiescent

Current

Switching, no load, skip mode

20

5

I

Low-power mode, V

= 1.8V

Q_LPM_SD2

OUT

I

Switching, no load, forced PWM mode

12.5mV steps

10

mA

V

Q_PWM_SD2

Output Voltage Range

0.6000

3.96

3.3875

4.84

Normal operation

2000

5

Maximum Output

Current

I

mA

MAX_SD2

Low-power mode

Switching Frequency

f

Normal operation

4.4

MHz

SW

Maxim Integrated

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

Electrical Characteristics—SD2 (continued)

(V

= 3.6V, V

= 1.8V, C

= 22µF, L2 = 1.0µH, T = -40°C to 85°C. Typical specifications are at T = +25°C, unless

IN_

SD2

SD2 A A

otherwise noted.) (Note 26)

PARAMETER

Peak Current Limit

SYMBOL

CONDITIONS

FPWM mode, T = +25°C

MIN

2500

2000

TYP

3000

2500

620

MAX

3600

3000

UNITS

mA

I

LIMPP2

LIMNV2

LIMNN2

A

Valley Current Limit

Negative Current Limit

PMOS On-Resistance

NMOS On-Resistance

FPWM mode, T = +25°C

A

mA

I

FPWM mode

IN_ = 3.6V

mA

R

100

mΩ

ON_PCH2

ON_NCH2

R

75

mΩ

NMOS Zero-Crossing

Threshold

Skip mode

20

mA

No load, C

= 10µF

= 20µF

40

20

SD2

V

Ripple in SKIP

SD2

mV

P-P

Mode (Note 8)

V

Ripple in PWM

SD2

No load, ESR = 3.0 mΩ, ESL = 0.4 nH

2

Mode

T

= +25°C

= +85°C

0.1

1

±1

A

LX_SD2 Leakage

Current

LX_SD2 = PG_

SD2 or IN_SD2

µA

T

A

Output disabled, V

FB_SD2 to PG_SD2, active discharge

disabled (nADE_SD2 = 1)

= 1V, current from

OUT

FB_SD2 Disabled

Leakage Current

0.1

µA

Output disabled, resistance from FB_SD2 to

PG_SD2, active discharge enabled

(nADE_SD2 = 0)

FB_SD2 Active

Discharge Resistance

100

22

Ω

Nominal capacitor

value

Minimum capacitor

Minimum Output

Capacitance for Stable

Operation

0µA < I

2000mA, MAX ESR

= 20mΩ

<

OUT1

value after deration

for initial accuracy,

temperature

C

µF

µH

OSD1

14

coeﬃcient, DC bias

voltage, and aging

Output Inductor

L

MAX DCR = 100mΩ

1.0

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

Electrical Characteristics—SD2 (continued)

(V

= 3.6V, V

= 1.8V, C

= 22µF, L2 = 1.0µH, T = -40°C to 85°C. Typical specifications are at T = +25°C, unless

IN_

SD2

A

otherwise noted.) (Note 26)

PARAMETER

SYMBOL

CONDITIONS

All other regulators are

MIN

TYP

MAX

UNITS

oﬀ and L_B_EN = 0

(i.e., central bias oﬀ and

buck bias is oﬀ)

185

At least one LDO is on

or L_B_EN = 1 and all

step-down are oﬀ

(i.e., central bias is on

and buck bias is oﬀ)

Time from the

enable signal to the

output starting to

increase

Turn-On Time

t

135

µs

ONSD2

At least one other step-

down regulator is on

(i.e., central bias is on

and buck bias is on)

22

After the regulator is disabled, the output

voltage discharges based on load and C

To ensure fast discharge times, enable the

.

OUT

Turn-Oﬀ Time

t

0.1

µs

OFFSD0

active-discharge resistor

SR_SD2 [1:0] = 0b01

27.5

13.75

55

SR_SD2 [1:0] = 0b00

SR_SD2 [1:0] = 0b10

Dynamic Voltage

Change Ramp Rate

Note 10

mV/µs

SR_SD2 [1:0] = 0b11

(Note 11)

100

OTP_SD_SS = 1

OTP_SD_SS = 0

25

14

90

dV/dt_SS_

SD2

Soft-Start Slew Rate

Output POK Threshold

V

falling, 3% hysteresis, T = +25°C

A

86

94

%V

SD2

POK_SD2

SD2

Power-OK Noise Pulse

Immunity

t

V

pulsed from 100% to 80% of regulation

8

µs

POKNFSD

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

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Electrical Characteristics—SD3

(V

= 3.6V, V

= 1.5V, C

= 22µF, L3 = 1.0µH, T = -40°C to 85°C. Typical specifications are at T = +25°C, unless

IN_SD3

SD3

A

otherwise noted.) (Note 26)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STEP-DOWN REGULATOR

V

AVSD

Input Voltage Range

AVSD and IN_SD3 must be connected together

2.6

-1.5

-2.5

-2.0

-3.0

5.5

V

IN_SD3

V

= 1.8V, accuracy includes

SD3

T

= +25°C

0

+1.5

+2.5

+2.0

+3.0

A

static variations in line and

temperature, no load, PWM

mode, normal-power mode

T

= -40°C to

A

+85°C

V

from 1.2V to 2.8V, accuracy

SD3

T

= +25°C

A

includes static variations in line

and temperature, no load,

PWM mode, normal-power mode

T

= -40°C to

A

+85°C

Output Voltage

Accuracy

V

from 1.2V to 2.8V, accuracy

SD3

V

%

SD3

includes transient variations in

line, load, and temperature during

dynamic load transients from

0mA to 1.4A with a transient rate

of 3.2A/µs, PWM mode or skip

mode, normal-power mode

T

= -40°C to

A

±5

+85°C

T

= -5°C to

A

-4.0

-5.0

0

+4.0

+5.0

Low-power mode

+85°C

I

= 0mA to 5mA,

SD3

T

= -40°C to

any output voltage

A

+85°C

Load Regulation

Line Regulation

LDREG

-0.25

0.04

%/A

%/V

SD3

V

= 2.6V to 5V

MBATT

Shutdown Supply

Current

I

0.1

µA

SHDN

I

No switching, remote output voltage sensing oﬀ

16

20

5

Q_SD3

Switching, no load, skip mode

µA

Supply Quiescent

Current

I

Low-power mode, V

= 1.8V

Q_LPM_SD3

OUT

I

Switching, no load, forced PWM mode

12.5mV steps

10

mA

V

Q_PWM_SD3

Output Voltage Range

Default Output Voltage

0.6000

3.3875

D_SD3 = GND

1.2

D_SD3 = unconnected; this value is set by OTP;

see the Register Map for more information

OTP

1.35

V

D_SD3 = MBATT

Maxim Integrated

│ 24

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—SD3 (continued)

(V

= 3.6V, V

= 1.5V, C

= 22µF, L3 = 1.0µH, T = -40°C to 85°C. Typical specifications are at T = +25°C, unless

IN_SD3

SD3

A

otherwise noted.) (Note 26)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

2000

5

MAX

UNITS

Normal operation

Low-power mode

Normal operation

Maximum Output

Current

I

mA

MAX_SD3

Switching Frequency

Peak Current Limit

f

3.96

2500

2000

4.4

4.84

3600

3000

MHz

mA

mΩ

SW

I

FPWM mode, T = +25°C

3000

2500

620

100

75

LIMPP3

LIMNV3

LIMNN3

A

Valley Current Limit

Negative Current Limit

PMOS On-Resistance

NMOS On-Resistance

FPWM mode, T = +25°C

A

I

FPWM mode

R

V

= 3.6V

ON_PCH3

IN_SD3

ON_NCH3

NMOS Zero-Crossing

Threshold

Skip mode

20

mA

No load, C

= 10µF

= 20µF

40

20

SD3

V

Ripple in SKIP

SD3

mV

P-P

Mode (Note 8)

V

Ripple in PWM

SD3

No load, ESR = 3.0mΩ, ESL = 0.4nH

2

Mode

T

= +25°C

= +85°C

0.1

1

±1

A

LX_SD3 Leakage

Current

LX_SD3 = PG_SD3 or IN_SD3

Output disabled, V

µA

T

A

= 1V, current from

FB_SD3 to PG_SD3, active discharge disabled

OUT

FB_SD3 Disabled

Leakage Current

0.1

µA

(nADE_SD3 = 1)

Output disabled, resistance from FB_SD3 to

PG_SD3, active discharge enabled

(nADE_SD3 = 0)

FB_SD3 Active

Discharge Resistance

100

22

Ω

Nominal capacitor value

Minimum capacitor value

Minimum Output

Capacitance for Stable

Operation

0µA < I

2000mA,

MAX ESR = 20mΩ

<

OUT3

after deration for initial

accuracy, temperature

coeﬃcient, DC bias

voltage, and aging

C

µF

µH

OSD3

14

Output Inductor

L

MAX DCR = 100 mΩ

1.0

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

Electrical Characteristics—SD3 (continued)

(V

= 3.6V, V

= 1.5V, C

= 22µF, L3 = 1.0µH, T = -40°C to 85°C. Typical specifications are at T = +25°C, unless

IN_SD3

SD3

A

otherwise noted.) (Note 26)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

All other regulators are oﬀ and

L_B_EN = 0

(i.e., central bias oﬀ and buck

bias is oﬀ)

185

Time from the

enable signal

to the output

starting to

At least one LDO is on or

L_B_EN = 1 and all step-down

are oﬀ

(i.e., central bias is on and

buck bias is oﬀ)

Turn-On Time

t

135

µs

ONSD3

increase

At least one other step-down

regulator is on

(i.e., central bias is on and

buck bias is on)

22

After the regulator is disabled, the output voltage

discharges based on load and C . To ensure

fast discharge times, enable the active-discharge

OUT

Turn-Oﬀ Time

t

0.1

µs

OFFSD0

resistor

SR_SD3 [1:0] = 0b01

27.5

13.75

55

SR_SD3 [1:0] = 0b00

Note 10

Dynamic Voltage

Change Ramp Rate

mV/µs

SR_SD3 [1:0] = 0b10

SR_SD3 [1:0] = 0b11 (Note 11)

OTP_SD_SS = 1

100

25

dV/dt_SS_

SD3

Soft-Start Slew Rate

OTP_SD_SS = 0

14

Output POK Threshold

V

falling, 3% hysteresis, T = +25°C

A

86

90

94

%V

SD3

POK_SD3

SD3

Power-OK Noise Pulse

Immunity

t

V

pulsed from 100% to 80% of regulation

8

2

µs

POKNFSD3

D_SD3 TRI-LEVEL LOGIC INPUT

Maximum D_SD3 to

Ground Resistance

to Achieve the “LOW”

Logic Level

The impedance from D_SD3 to ground must be

less than 2kΩ to set the “LOW” state; Maxim

recommends that D_SD3 be connected directly to

ground to achieve the “LOW” state

kΩ

Maximum D_SD3 to

Ground Resistance

to Achieve the

“UNCONNECTED”

Logic Level

The impedance at D_SD3 must be larger than

200kΩ to set the “UNCONNECTED” state; Maxim

recommends that D_SD3 be left unconnected

(ﬂoating) to achieve the “UNCONNECTED” state

200

Maxim Integrated

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

Electrical Characteristics—SD3 (continued)

(V

= 3.6V, V

= 1.5V, C

= 22µF, L3 = 1.0µH, T = -40°C to 85°C. Typical specifications are at T = +25°C, unless

IN_SD3

SD3

A

otherwise noted.) (Note 26)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Maximum D_SD3 to

Ground Resistance to

Achieve the “HIGH”

Logic Level

The impedance from D_SD3 to MBATT must be

less than 2kΩ to set the “HIGH” state; Maxim

recommends that D_SD3 be connected directly to

ground to achieve the “HIGH” state

2

kΩ

From MBATT okay until the D_SD3 detects its

state; after state detection, D_SD3 becomes

high-impedance

D_SD3 Force Time

t

22

µs

DSD3LTCH

D_SD3 Input Leakage

Current

T

= +25°C, after the force time has expired

0.01

µA

A

Note 6: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed through

A

correlation using statistical quality control methods.

Note 7:

SD0 and SD1 have remote output voltage sensing. When enabled, the remote output voltage sensing compensates for

voltage drops (up to VRSR) in a PCBs power path due to parasitic resistance. As a result of this compensation, the

output voltage directly at the output of SD0 and SD1 may vary up to VRSR, but the voltage at the remote sense point

complies with the load regulation specifications. When the remote sensing feature is disabled, the output voltage is

sensed at FB_SDx.

Note 8: Skip mode output voltage ripple decreases as the output capacitance increases. Typically a system’s point-of-load

capacitance contributes to the step-down regulators local output capacitance to decrease the overall skip-mode output

voltage ripple.

Note 9: Maximum output current refers to the maximum current that the step-down regulator is electrically capable of delivering.

Thermal and reliability limits can reduce the maximum sustainable output current and/or the operation time at maximum

output current.

Note 10: During a DVS transition, the regulators output current increases by COUT x dV/dt. In the event that the load current plus

the additional current imposed by the DVS transition reaches the regulator’s current limit, the current limit is enforced.

When the current limit is enforced, the advertised DVS transition rate (dV/dt) does not occur.

Note 11: For the 0b00, 0b01, and 0b10 settings, the device actively controls the slew rate. For the 0b11 setting, the device drives

the output voltage as fast as possible and the slew rate is limited by the current limit and the output capacitance.

Maxim Integrated

│ 27

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—150mA PMOS

(V

= V = 3.7V, C

= 1.0µF, T = -40°C to +85°C, unless otherwise noted.) (Note 12)

MBATT

IN

OUT A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

OPERATIONAL SPECIFICATIONS

Input Voltage Range

Undervoltage Lockout

Battery Voltage Range

V

Guaranteed by output accuracy

Rising, 100mV hysteresis

1.7

5.5

1.7

5.5

V

IN_LDOx

V

1.6

UVLOxx

V

Guaranteed by main bias testing

2.45

0.8

MBATT

50mV/Step (6-bit),

LDO2, LDO5, LDO6

V

is the

INxx

3.95

Output Voltage Range

V

maximum of 3.7V

V

OUTxx

MAXxx

or V +0.3V

OUT

12.5mV Step (6-bit), LDO4

Normal mode

0.8

150

5

1.5875

Maximum Output

Current

Guaranteed by

output accuracy

I

mA

Low-power mode

Nominal capacitor value

1.0

0.7

1.0

0.7

Minimum capacitor value after

deration for initial accuracy,

temperature coeﬃcient,

Normal mode

Minimum Output

Capacitance for Stable

Operation

DC bias voltage, and aging

C

µF

OUTxx

Nominal capacitor value

(Note 13, Note 14)

Minimum capacitor value after

deration for initial accuracy,

temperature coeﬃcient,

Low-power mode

DC bias voltage, and aging

BIAS

Time to enable LDO bias only; central bias is

already enabled

Bias Enable Time

Bias Enable Currents

t

90

10

µs

LBIAS

I

LDO bias enabled; L_B_EN = 1

µA

QBIAS

CORE PERFORMANCE SPECIFICATIONS

V

= V

+ 0.3V to 5.5V

NOM

IN

with 1.7V minimum,

Normal mode

-3

-5

+3

+5

I

= 0.1mA to I

,

MAX

OUT

V

set to any voltage

NOM

Output Voltage

Accuracy

%

V

= V

+ 0.3V to 5.5V

NOM

IN

Low-power

mode

with 1.7V minimum,

I

= 0.1mA to 5mA,

OUT

V

set to any voltage

NOM

I

= 0.1mA to I

,

MAX

OUT

V

= V

+ 0.3V with 1.7V

IN

NOM

Normal mode

0.05

minimum, V

voltage

set to any

NOM

Load Regulation

(Note 14)

%

I

= 0.1mA to 5mA,

= V

OUT

Low-power

mode

V

+ 0.3V with 1.7V

IN

NOM

minimum, V

set to any

NOM

voltage

Maxim Integrated

│ 28

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—150mA PMOS (continued)

(V

= V = 3.7V, C

= 1.0µF, T = -40°C to +85°C, unless otherwise noted.) (Note 12)

MBATT

IN

OUT A

PARAMETER

SYMBOL

CONDITIONS

= V

MIN

TYP

MAX

UNITS

V

+0.3V to 5.5V

NOM

IN

with 1.7V minimum;

Normal mode

0.01

I

= 0.1mA,

OUT

V

set to any voltage

NOM

Line Regulation

(Note 14)

%/V

V

= V

+0.3V to 5.5V

NOM

IN

with 1.7V minimum;

= 0.1mA,

Low-power mode

0.01

I

OUT

V

set to any voltage

NOM

V

= 3.7V

= 1.7V

50

100

300

250

IN

I

=

OUT

MAX

Normal mode

Dropout Voltage

V

150

180

mV

%

DOxx

Low-power mode

I

= 5mA, V = 3.7V

OUT IN

Output Current Limit

I

V

= 0V, percentage of I

110

LIMxx

OUT

MAX

COMP_Lx = 0b00,

C

= 50mΩ,

= 5nH

55

66

ESR

ESL

Normal mode,

= V

+0.3V to 5.5V

with 1.7V absolute

minimum.

V

IN

NOM

COMP_Lx = 0b01,

C

= 150mΩ,

= 10nH

ESR

ESL

I

= 1% to

OUT

COMP_Lx = 0b10,

100% to 1% of

Output Load Transient

(OVCLMP_EN_Lxx = 1)

(Note 14)

C

= 500mΩ,

= 35nH

99

I

, V set

ESR

ESL

MAX NOM

mV

to any voltage,

t

C

= t = 1µs,

R

F

COMP_Lx = 0b11,

C

= 1.0µF

OUT

= 1000mΩ,

= 50nH

125

ESR

ESL

Low-power mode, V = V

+ 0.3V to 5.5V with

NOM

IN

1.7V absolute minimum. I

= 0.05mA to 5mA

OUT

25

5

to 0.05mA, V

set to any voltage;

NOM

t

= t = 1µs, C

= 1.0µF

OUT

R

F

Normal mode, V = V

+ 0.3V to V

+ 0.8V

NOM

IN

NOM

to V

+ 0.3V with 1.7V absolute minimum; t =

NOM

R

t

= 1µs, I

= I

, V

set to any voltage

F

OUT

MAX NOM

Output Line Transient

(Note 14)

mV

Low-power mode, V = V

+0.3V to V

NOM

IN

NOM

+0.8V to V

+0.3V with 1.7V absolute

NOM

minimum. t = t = 1µs, I = 5mA,

OUT

5

R

F

V

set to any voltage

NOM

Maxim Integrated

│ 29

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—150mA PMOS (continued)

(V

= V = 3.7V, C

= 1.0µF, T = -40°C to +85°C, unless otherwise noted.) (Note 12)

MBATT

IN

OUT A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

79

68

50

39

35

81

71

52

45

39

52

43

38

33

28

MAX

UNITS

f = 1kHz

f = 10kHz

V

=

+1V

= 50mV

INDC

NOM

INAC

f = 100kHz

f = 1000kHz

f = 4450kHz

f = 1kHz

Rejection from

f = 10kHz

V

=

INDC

NOM

INAC

V

to V

IN

OUT

+0.5V

= 50mV

f = 100kHz

f = 1000kHz

f = 4450kHz

f = 1kHz

I

= 10% of

OUT

MAX

Power Supply

Rejection

PSRRxx

dB

f = 10kHz

V

=

INDC

NOM

INAC

+0.1V

= 10mV

f = 100kHz

f = 1000kHz

f = 4450kHz

Low-power mode, I

rejection from V to V

IN

= 1mA, f = 1kHz,

OUT

50

OUT

V

= 0.8V

= 1.8V

= 3.7V

45

60

OUT

f = 10Hz to

Output Noise

100kHz, I

=

V

µV

RMS

OUT

10% of I

MAX

Soft-Start and Dynamic

Voltage Change Ramp

Rate

Lxx_SS = 0

Lxx_SS = 1

100

5

After enabling,

Note 17

t

mV/µs

µA

SSxx

Output disabled, V

= 1V, current from

OUT

Output Disabled

Leakage Current

OUT_LDOx to GND, active discharge disabled

0.1

65

(Lxx_ADE = 0)

Output disabled, V

= 1V, resistance from

OUT

Active-Discharge

Resistance

OUT_LDOx to GND, active discharge enabled

Ω

(Lxx_ADE = 1)

OVERVOLTAGE CLAMP

Clamp Active

Regulation Voltage

Clamp active (OVCLMP_EN_Lxx = 1),

LDO output sinking 0.1mA

V

NOM

2.2

Clamp Disabled

Overvoltage Sink

Current

V

= V

× 110%

NOM

µA

OUTxx

Maxim Integrated

│ 30

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—150mA PMOS (continued)

(V

= V = 3.7V, C

= 1.0µF, T = -40°C to +85°C, unless otherwise noted.) (Note 12)

MBATT

IN

OUT A

PARAMETER

TIMING

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Time from LDO enable

Lxx_SS = 0

Lxx_SS = 1

10

60

command received

to the output starting

to slew, LDO bias

enabled

Turn-On Time

t

µs

LON

After LDO is disabled, the LDO output voltage

discharges based on load and C

To ensure fast discharge times, enable the active

.

OUT

Turn-Oﬀ Time

0.1

50

µs

discharge resistor.

Transition Time from

Low-Power Mode to

Normal Mode

THERMAL SHUTDOWN

Thermal Shutdown

POWER-OK

T Rising

165

150

J

Output Disabled or

Enabled

°C

T Falling

J

V

Rising

Falling

92

87

95

OUT

V

when V

POK

OUT

Power-OK Threshold

V

%

POKTHL

switches

84

OUT

Power-OK Noise Pulse

Immunity

t

V

pulsed from 100% to 80% of regulation

25

µs

POKNFLDO

OUT

Maxim Integrated

│ 31

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—300mA PMOS

(V

= V = 3.7V, T = -40°C to +85°C, unless otherwise noted.) (Note 12)

MBATT

IN A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

OPERATIONAL SPECIFICATIONS

Input Voltage Range

Undervoltage Lockout

Battery Voltage Range

V

Guaranteed by output accuracy

Rising, 100mV hysteresis

1.7

5.5

1.7

5.5

V

IN_LDOx

V

1.6

UVLOxx

V

Guaranteed by main bias testing

2.45

0.8

MBATT

V

is the

INxx

maximum of 3.7V

or V +0.3V.

50mV/Step

(6-bit), LDO3

Output Voltage Range

V

3.95

V

OUTxx

OUT

Normal mode

300

5

Maximum Output

Current

Guaranteed by

output accuracy

I

mA

MAXxx

Low-power mode

Nominal capacitor value

2.2

1.5

2.2

1.5

Minimum capacitor value after

deration for initial accuracy,

temperature coeﬃcient, DC bias

voltage, and aging

Normal mode

Minimum Output

Capacitance for Stable

Operation

C

µF

OUTxx

Low-power mode Nominal capacitor value

(Note 13, Note 14)

Minimum capacitor value after

deration for initial accuracy,

temperature coeﬃcient, DC bias

voltage, and aging

BIAS

Time to enable LDO bias only; central bias is already

enabled

Bias Enable Time

Bias Enable Currents

t

90

10

µs

LBIAS

I

LDO bias enabled; L_B_EN = 1

µA

QBIAS

CORE PERFORMANCE SPECIFICATIONS

V

= V

+0.3V to 5.5V with

IN

NOM

Normal mode

1.7V minimum, I

= 0.1mA to

-3

-5

+3

+5

OUT

I

, V

set to any voltage

MAX NOM

Output Voltage

Accuracy

%

V

= V

NOM

+0.3V to 5.5V with

IN

Low-power

mode

1.7V minimum, I

= 0.1mA to

OUT

5mA, V

set to any voltage

NOM

I

V

= 0.1mA to I ,

MAX

OUT

Normal mode

= V

+0.3V with 1.7V

0.05

IN

NOM

minimum, V

set to any voltage

NOM

Load Regulation

(Note 14)

I

= 0.1mA to 5mA,

OUT

Low-power

mode

V

= V

+0.3V with 1.7V

set to any voltage

IN

NOM

minimum, V

NOM

Maxim Integrated

│ 32

www.maximintegrated.com

MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—300mA PMOS (continued)

(V

= V = 3.7V, T = -40°C to +85°C, unless otherwise noted.) (Note 12)

MBATT

IN A

PARAMETER

SYMBOL

CONDITIONS

= V +0.3V to 5.5V with

MIN

TYP

MAX

UNITS

V

IN

NOM

Normal mode

1.7V minimum; I

= 0.1mA,

0.01

OUT

V

set to any voltage

NOM

Line Regulation

(Note 14)

%/V

V

= V

+0.3V to 5.5V with

IN

NOM

Low-power

mode

1.7V minimum; I

= 0.1mA,

0.01

OUT

V

set to any voltage

NOM

V

= 3.7V

= 1.7V

IN

50

150

100

450

Normal mode

I

= I

MAX

OUT

IN

Dropout Voltage

V

mV

%

DOxx

Low-power

mode

= 5mA, V = 3.7V

150

180

300

250

IN

Output Current Limit

I

OUT = 0V

110

LIMxx

Normal mode,

COMP_Lx = 0b00,

= 50mΩ, C

55

66

V

= V

C

= 5nH

ESL

IN

NOM

ESR

+0.3V to 5.5V

with 1.7V

absolute

minimum.

COMP_Lx = 0b01,

= 150mΩ, C

C

= 10nH

= 35nH

= 50nH

ESR

ESL

I

= 1% to

OUT

COMP_Lx = 0b10,

= 500mΩ, C

Output Load Transient

100% to 1% of

99

C

ESR

(OVCLMP_EN_Lxx = 1)

(Note 14)

mV

I

, V set

MAX

NOM

to any voltage,

COMP_Lx = 0b11,

= 1000mΩ, C

t

= t = 1µs,

R

F

125

C

= 2.2µF

ESR

ESL

OUT

Low-power mode, V = V

+0.3V to 5.5V with

= 0.05mA to 5mA to

IN

NOM

1.7V absolute minimum. I

OUT

25

0.05mA, V

set to any voltage;

NOM

t

= t = 1µs, C

= 2.2µF

R

F

OUT

Normal mode, V = V

+0.3V to V

+0.8V to

IN

NOM

V

+0.3V with 1.7V absolute minimum;

5

NOM

t

= t = 1µs, I

= I

, V

set to any voltage

R

F

OUT

MAX NOM

Output Line Transient

(Note 14)

mV

Low-power mode, V = V

to V

+0.3V to V

+0.8V

IN

NOM

+0.3V with 1.7V absolute minimum;

NOM

t

= t = 1µs, I

= 5mA, V

set to any voltage

R

F

OUT

NOM

Maxim Integrated

│ 33

www.maximintegrated.com

MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—300mA PMOS (continued)

(V

= V = 3.7V, T = -40°C to +85°C, unless otherwise noted.) (Note 12)

IN A

MBATT

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

79

68

50

39

35

81

71

52

45

39

52

43

38

33

28

MAX

UNITS

f = 1kHz

f = 10kHz

V

=

+1V

= 50mV

INDC

f = 100kHz

f = 1000kHz

f = 4450kHz

f = 1kHz

NOM

INAC

Rejection from

f = 10kHz

V

= V

NOM

INDC

V

to V

IN

OUT

+0.5V

f = 100kHz

f = 1000kHz

f = 4450kHz

f = 1kHz

I

= 10% of

OUT

MAX

V

= 50mV

INAC

Power Supply Rejection

PSRRxx

dB

f = 10kHz

V

= V

INDC

NOM

+0.1V

f = 100kHz

f = 1000kHz

f = 4450kHz

V

= 10mV

INAC

Low-power mode, I

rejection from V to V

IN

= 1mA, f = 1kHz,

OUT

50

OUT

V

= 0.8V

= 1.8V

= 3.7V

45

60

OUT

f = 10Hz to 100kHz,

Output Noise

µV

RMS

I

= 10% of I

MAX

OUT

Soft-Start and Dynamic

Voltage Change Ramp

Rate

Lxx_SS = 0

100

5

t

After enabling, Note 17

mV/µs

µA

SSxx

Lxx_SS = 1

Output Disabled

Leakage Current

Output disabled, V

= 1V, current from OUT_LDOx

to GND, active discharge disabled (Lxx_ADE = 0)

OUT

0.1

65

Output disabled, V = 1V, resistance from

OUT_LDOx to GND, active discharge enabled

OUT

Active-Discharge

Resistance

Ω

(Lxx_ADE = 1)

OVERVOLTAGE CLAMP

Clamp Active Regulation

Voltage

Clamp active (OVCLMP_EN_Lxx = 1),

LDO output sinking 0.1mA

V

NOM

2.2

Clamp Disabled

Overvoltage Sink

Current

V

= V

x 110%

µA

OUTxx

NOM

Maxim Integrated

│ 34

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—300mA PMOS (continued)

(V

= V = 3.7V, T = -40°C to +85°C, unless otherwise noted.) (Note 12)

IN A

MBATT

PARAMETER

TIMING

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Time from LDO enable command

received to the output starting to

slew, LDO bias enabled

Lxx_SS = 0

Lxx_SS = 1

10

60

µs

Turn ON Time

Turn OFF Time

t

LON

After LDO is disabled, the LDO output voltage

discharges based on load and C . To ensure fast

0.1

50

µs

OUT

discharge times, enable the active-discharge resistor

Transition time from Low

Power mode to Normal

Mode

THERMAL SHUTDOWN

Thermal Shutdown

POWER-OK

T rising

165

150

J

Output disabled or enabled

°C

T falling

J

V

rising

falling

92

87

95

OUT

Power-OK Threshold

V

when V switches

POK

%

POKTHL

OUT

84

OUT

Power-OK Noise Pulse

Immunity

t

pulsed from 100% to 80% of regulation

25

µs

POKNFLDO

OUT

Maxim Integrated

│ 35

www.maximintegrated.com

MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—150mA NMOS

(V

= V = 3.7V, T = -40°C to +85°C, unless otherwise noted) (Note 12)

MBATT

IN A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

OPERATIONAL SPECIFICATIONS

Input Voltage Range

V

Note 15

Guaranteed by main bias testing (Note 16)

V

5.5

V

INxx

OUT

Battery Voltage Range

V

MBATT

2.45

V

is the

INxx

25mV/step

(6-bit)

Output Voltage Range

V

maximum of 3.7V

or V +0.3V

0.8

2.375

V

OUTxx

OUT

Normal mode

150

Guaranteed by

output accuracy

Maximum Output Current

I

mA

MAXxx

Low-power mode

Nominal capacitor value

5

0

Normal mode

(1.0µF is

recommended for

“nice” transient

performance)

Minimum capacitor value after

deration for initial accuracy,

temperature coeﬃcient, DC bias

voltage, and aging

0

1

Minimum Output

Capacitance for Stable

Operation

C

µF

OUTxx

Nominal capacitor value

(Note 13, Note 14)

Minimum capacitor value after

deration for initial accuracy,

temperature coeﬃcient, DC bias

voltage, and aging

Low-power

mode

0.7

BIAS

Time to enable LDO bias only; central bias is already

enabled

Bias Enable Time

Bias Enable Currents

t

90

10

µs

LBIAS

I

LDO bias enabled. L_B_EN = 1

µA

QBIAS

CORE PERFORMANCE SPECIFICATIONS

V

= V

+0.3V to 5.5V,

IN

NOM

I

= 0.1mA to I

,

OUT

MAX

Normal mode

V

set to any voltage,

-3

-5

+3

+5

NOM

= V

+1.5V with

MBATT

NOM

Output Voltage

Accuracy

2.45V minimum

%

V

= V +0.3V to 5.5V

NOM

MBATT

Low-power

mode

with 2.45V minimum, I

0.1mA to 5mA, V

=

OUT

set to any

NOM

voltage, V = V

+0.3V

IN

NOM

I

= 0.1mA to I

,

OUT

MAX

V

= V

+0.3V

IN

NOM

= V

Normal mode

0.05

+1.5V with

MBATT

NOM

2.45V minimum

Load Regulation

(Note 14)

%

I

= 0.1mA to 5mA,

OUT

Low-power

mode

V

= V

+0.3V,

IN

NOM

= V

+0.3V with

MBATT

NOM

2.45V minimum

Maxim Integrated

│ 36

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—150mA NMOS (continued)

(V

= V = 3.7V, T = -40°C to +85°C, unless otherwise noted) (Note 12)

MBATT

IN A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

V

= V

= 0.1mA

+0.3V to 5.5V,

IN

NOM

Normal mode

0.01

I

OUT

Line Regulation

(Note 14)

%/V

V

= V

+0.3V to 5.5V

MBATT

NOM

Low-power mode

with 2.45V minimum, V

=

0.01

IN

V

+0.3V I

= 0.1mA

NOM

OUT

V

-

MBATT

50

100

= 2.5V

OUT

Normal mode

I

= I

MAX

OUT

Dropout Voltage

V

mV

V

-

DOxx

MBATT

150

300

= 1.5V

OUT

Low-power mode

= 5mA, V = 3.7V

150

180

300

OUT

IN

Output Current Limit

I

V

= 0V, percentage of I

103

250

%

LIMxx

OUT

MAX

Normal mode, V = V

+0.3V to 5.5V;

IN

NOM

I

= 1% to 100% to 1% of I

, V

set to any

60

25

5

OUT

MAX NOM

voltage, t = t = 1µs, C = 1µF

OUT

R

F

Output Load Transient

(Note 14)

mV

Low-power mode, V = V

I

voltage. t = t = 1µs, C = 1µF

OUT

+0.3V to 5.5V;

IN

NOM

= 0.05mA to 5mA to 0.05mA, V

set to any

OUT

NOM

R

F

Normal mode, V = V

V

+0.3V to V

+0.8V to

IN

NOM

+0.3V; t = t = 1µs, I

set to any voltage

= I

,

NOM

R

F

OUT

MAX

Output Line Transient

(Note 14)

mV

Low-power mode, V = V

+0.3V to V

+0.8V

IN

NOM

to V

+0.3V; t = t = 1µs, I = 5mA,

5

NOM

R

F

OUT

V

set to any voltage, C

= 1µF

NOM

OUT

f = 1kHz

88

65

51

22

15

85

63

49

21

14

45

30

18

10

f = 10kHz

V

=

+1V

= 50mV

INDC

f = 100kHz

f = 1000kHz

f = 4450kHz

f = 1kHz

NOM

INAC

Rejection from

f = 10kHz

V

to V

V

= V

INDC NOM

IN

OUT

I

C

= 10% of

+0.5V

f = 100kHz

f = 1000kHz

f = 4450kHz

f = 1kHz

OUT

MAX

Power Supply

Rejection

V

= 50mV

INAC

PSRRxx

dB

= 1µF

OUT

f = 10kHz

V

=

INDC

NOM

INAC

+0.1V

= 10mV

f = 100kHz

f = 1000kHz

f = 4450kHz

Low-power mode, I

= 1mA, f = 1kHz,

to V

OUT

50

rejection from V

MBATT

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—150mA NMOS (continued)

(V

= V = 3.7V, T = -40°C to +85°C, unless otherwise noted.) (Note 12)

MBATT

IN A

PARAMETER

Output Noise

SYMBOL

CONDITIONS

MIN

TYP

55

MAX UNITS

V

= 0.8V

= 1.8V

OUT

f = 10Hz to 100kHz,

= 10% of I

µV

RMS

I

OUT

MAX

65

Soft-Start and Dynamic

Voltage Change Ramp

Rate

Lxx_SS = 0

100

5

t

After enabling, Note 17

mV/µs

µA

SSxx

Lxx_SS = 1

Output Disabled Leakage

Current

Output disabled, V

= 1V, current from OUT_LDOx

to GND, active discharge disabled (Lxx_ADE = 0)

OUT

0.1

65

Output disabled, V = 1V, resistance from

OUT_LDOx to GND, active discharge enabled

OUT

Active-Discharge

Resistance

Ω

(Lxx_ADE = 1)

OVERVOLTAGE CLAMP

Clamp Active Regulation

Voltage

Clamp active (OVCLMP_EN_Lxx = 1),

LDO output sinking 0.1mA

V

NOM

2.5

Clamp Disabled

Overvoltage Sink Current

V

= V

x 110%

µA

OUTxx

NOM

TIMING

Time from LDO enable

command received to the

output starting to slew, LDO

bias enabled

Lxx_SS = 0

Lxx_SS = 1

15

µs

Enable Delay

t

LON

140

After LDO is disabled, the LDO output voltage

discharges based on load and C . To ensure fast

discharge times, enable the active discharge resistor

Disable Delay

t

0.1

50

µs

LDD

OUT

Transition Time from Low-

Power Mode to Normal

Mode

THERMAL SHUTDOWN

Thermal Shutdown

POWER-OK

T Rising

165

150

J

Output disabled

or enabled

°C

T Falling

J

V

Rising

Falling

92

87

95

OUT

Power-OK Threshold

V

when V switches

POK

%

POKTHL

OUT

84

Power-OK Noise Pulse

Immunity

t

pulsed from 100% to 80% of regulation

25

µs

POKNFLDO

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—300mA NMOS

(V

= V = 3.7V, T = -40°C to +85°C, unless otherwise noted.) (Note 12)

MBATT

IN A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

OPERATIONAL SPECIFICATIONS

Input Voltage Range

V

Note 15

Guaranteed by main bias testing

V

5.5

V

IN_LDO

OUT

Battery Voltage Range

V

MBATT

2.45

V

is the

INxx

50mV/Step

(6-bit)

Output Voltage Range

V

maximum of 3.7V

or V +0.3V.

0.8

3.95

V

OUTxx

OUT

Normal mode

300

Maximum Output

Current

Guaranteed by

output accuracy

I

mA

MAXxx

Low-power mode

Nominal capacitor value

5

0

Normal mode

(2.2µF is

recommended for

“nice” transient

performance)

Minimum capacitor value after

deration for initial accuracy,

temperature coeﬃcient,

0

1

Minimum Output

Capacitance for Stable

Operation

DC bias voltage, and aging

C

µF

OUTxx

Nominal capacitor value

(Note 13, Note 14)

Minimum capacitor value after

deration for initial accuracy,

temperature coeﬃcient,

Low-power

mode

0.7

DC bias voltage, and aging

BIAS

Time to enable LDO bias only; central bias is

already enabled

Bias Enable Time

Bias Enable Currents

t

90

10

µs

LBIAS

I

LDO bias enabled; L_B_EN = 1

µA

QBIAS

CORE PERFORMANCE SPECIFICATIONS

V

= V

+0.3V to 5.5V,

IN

NOM

Normal mode

I

V

= 0.1mA to I

,

-3

-5

+3

+5

OUT

MAX

set to any voltage

NOM

Output Voltage Accuracy

%

V

= V

+0.3V to 5.5V

IN

NOM

Low-power

mode

with 1.7V minimum,

I

= 0.1mA to 5mA,

OUT

V

set to any voltage

NOM

I

= 0.1mA to I

,

OUT

MAX

Normal mode

V

= V

+0.3V,

0.05

IN

NOM

set to any voltage

NOM

Load Regulation

(Note 14)

%

I

= 0.1mA to 5mA,

OUT

Low-power

mode

V

= V

+0.3V with 1.7V

IN

NOM

minimum, V

set to any

NOM

voltage

Maxim Integrated

│ 39

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—300mA NMOS (continued)

(V

= V = 3.7V, T = -40°C to +85°C, unless otherwise noted.) (Note 12)

MBATT

IN A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

V

= V

+0.3V to 5.5V,

IN

NOM

Normal mode

I

= 0.1mA, V

set to

0.01

OUT

NOM

any voltage

Line Regulation

(Note 14)

%/V

V

= V

+0.3V to 5.5V with

= 0.1mA,

IN

NOM

Low-power

mode

1.7V minimum, I

0.01

OUT

set to any voltage

V

NOM

V

-

MBATT

= 2.5V

OUT

50

150

100

450

mV

Normal mode

I

= I

MAX

OUT

V

-

Dropout Voltage

V

MBATT

DOxx

= 1.5V

OUT

Low-power mode

OUT = 0V

= 5mA, V = 3.7V

150

180

300

IN

Output Current Limit

I

110

250

%

LIMxx

Normal mode, V = V

+0.3V to 5.5V;

IN

NOM

I

= 1% to 100% to 1% of I

, V set to

60

25

5

OUT

MAX NOM

any voltage, t = t = 1µs, C = 2.2uF

OUT

R

F

Output Load Transient

(Note 14)

mV

Low-power mode, V = V

I

any voltage. t = t = 1µs, C = 2.2µF

OUT

+0.3V to 5.5V;

IN

NOM

= 0.05mA to 5mA to 0.05mA, V

set to

OUT

NOM

R

F

Normal mode, V = V

to V

+0.3V to V

+0.8V

IN

NOM

+0.3V; t = t = 1µs, I

= I

,

NOM

R

F

OUT

MAX

V

set to any voltage

NOM

Output Line Transient

(Note 14)

mV

Low-power mode, V = V

+0.3V to

IN

NOM

V

+0.8V to V

+0.3V. t = t = 1µs,

5

NOM

R

F

I

= 5mA, V

set to any voltage

OUT

NOM

f = 1kHz

88

65

51

22

15

85

63

49

21

14

45

30

18

10

f = 10kHz

V

=

+1V

= 50mV

INDC

NOM

INAC

f = 100kHz

f = 1000kHz

f = 4450kHz

f = 1kHz

Rejection from

f = 10kHz

V

=

INDC

NOM

INAC

V

to V

IN

OUT

+0.5V

= 50mV

f = 100kHz

f = 1000kHz

f = 4450kHz

f = 1kHz

I

= 10% of

OUT

MAX

Power Supply Rejection

PSRRxx

dB

f = 10kHz

V

=

INDC

NOM

INAC

+0.1V

= 10mV

f = 100kHz

f = 1000kHz

f = 4450kHz

Low-power mode, I

= 1mA, f = 1kHz,

to V

OUT

50

rejection from V

BATT

Maxim Integrated

│ 40

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—300mA NMOS (continued)

(V

= V = 3.7V, T = -40°C to +85°C, unless otherwise noted.) (Note 12)

MBATT

IN A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

V

= 0.8V

= 1.8V

55

OUT

f = 10Hz to 100kHz,

= 10% of I

Output Noise

µV

RMS

I

OUT

MAX

65

100

5

Soft-Start and Dynamic

Voltage Change Ramp

Rate

Lxx_SS = 0

Lxx_SS = 1

After enabling,

Note 17

t

mV/µs

µA

SSxx

Output disabled, V

= 1V, current from

OUT_LDOx to GND, active discharge disabled

OUT

Output Disabled Leakage

Current

0.1

65

(Lxx_ADE = 0)

Output disabled, V

= 1V, resistance from

OUT_LDOx to GND, active discharge enabled

OUT

Active-Discharge

Resistance

Ω

(Lxx_ADE = 1)

OVERVOLTAGE CLAMP

Clamp Active Regulation

Voltage

Clamp active (OVCLMP_EN_Lxx = 1),

LDO output sinking 0.1mA

V

NOM

Clamp Disabled

Overvoltage Sink Current

V

= V

x 110%

2.2

µA

OUTxx

NOM

TIMING

Time from LDO enable

command received to

the output starting to

slew, LDO bias enabled

Lxx_SS = 0

Lxx_SS = 1

15

µs

Turn-On Time

t

LON

140

After LDO is disabled, the LDO output voltage

discharges based on load and C . To ensure

fast discharge times, enable the active-discharge

OUT

Turn-Oﬀ Time

0.1

50

µs

resistor

Transition Time from Low-

Power Mode to Normal

Mode

THERMAL SHUTDOWN

Thermal Shutdown

POWER-OK

T rising

165

150

J

Output disabled

or enabled

°C

T falling

J

92

87

95

V

rising

falling

V

when V

POK

OUT

Power-OK Threshold

V

%

POKTHL

switches

84

V

OUT

Power-OK Noise Pulse

Immunity

t

V

pulsed from 100% to 80% of regulation

OUT

25

µs

POKNFLDO

Maxim Integrated

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—450mA NMOS

(V

= V = 3.7V, T = -40°C to +85°C, unless otherwise noted.) (Note 12)

MBATT

IN A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

OPERATIONAL SPECIFICATIONS

Input Voltage Range

V

Note 15

Guaranteed by main bias testing

is the maximum 50mV/step

+0.3V. (6-bit)

V

5.5

V

INxx

OUT

Battery Voltage Range

V

MBATT

2.45

V

INxx

Output Voltage Range

V

0.8

3.95

V

OUTxx

of 3.7V or V

OUT

Normal mode

450

Maximum Output

Current

Guaranteed by output

accuracy

I

mA

MAXxx

Low-power mode

Nominal capacitor value

5

0

Normal mode

Minimum capacitor value

after deration for initial

accuracy, temperature

coeﬃcient, DC bias voltage,

and aging

(4.7µF is recommended

for “nice” transient

performance)

0

1

Minimum Output

Capacitance for Stable

Operation

C

µF

OUTxx

Nominal capacitor value

(Note 13, Note 14)

Minimum capacitor value

after deration for initial

accuracy, temperature

coeﬃcient, DC bias voltage,

and aging

Low-power mode

0.7

BIAS

Time to enable LDO bias only, central bias is already

enabled

Bias Enable Time

Bias Enable Currents

t

90

10

µs

LBIAS

I

LDO bias enabled; L_B_EN = 1

µA

QBIAS

CORE PERFORMANCE SPECIFICATIONS

V

= V

+0.3V to 5.5V,

IN

NOM

Normal mode

I

V

= 0.1mA to I

,

-3

-5

+3

+5

OUT

MAX

set to any voltage

NOM

Output Voltage

Accuracy

V

= V

+1.5V to

MBATT

NOM

%

5.5V with 2.45V minimum,

Low-power

mode

I

= 0.1mA to 5mA,

OUT

V

set to any voltage;

NOM

V

= V

+0.3V

IN

NOM

Maxim Integrated

│ 42

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—450mA NMOS (continued)

(V

= V = 3.7V, T = -40°C to +85°C, unless otherwise noted.) (Note 12)

MBATT

IN A

PARAMETER

SYMBOL

CONDITIONS

= 0.1mA to I

MIN

TYP

MAX

UNITS

I

,

MAX

OUT

Normal mode

0.05

V

= V

+0.3V

IN

NOM

Load Regulation

(Note 14)

%

I

V

= 0.1mA to 5mA,

OUT

Low-power

mode

= V

+0.3V with

0.05

0.01

IN

NOM

1.7V minimum

V

= V

+0.3V to 5.5V,

IN

NOM

Normal mode

I

= 0.1mA

OUT

Line Regulation

(Note 14)

%/V

V

= V

+0.3V to 5.5V

IN

NOM

Low-power mode

with 1.7V minimum,

I

= 0.1mA

OUT

V

-

MBATT

50

100

450

= 2.5V

OUT

I

=

OUT

MAX

Normal mode

Dropout Voltage

V

mV

%

V

-

DOxx

MBATT

150

= 1.5V

OUT

Low-power mode

OUT = 0V

I

= 5mA, V = 3.7V

150

180

300

250

OUT

IN

Output Current Limit

I

105

LIMxx

Normal mode, V = V

+0.3V to 5.5V;

IN

NOM

I

= 1% to 100% to 1% of I

, V

set to any

60

25

5

OUT

MAX NOM

voltage, t = t = 1µs, C = 4.7µF

OUT

R

F

Output Load Transient

(Note 14)

mV

Low-power mode, V = V

I

voltage. t = t = 1µs, C = 4.7µF

OUT

+0.3V to 5.5V;

IN

NOM

= 0.05mA to 5mA to 0.05mA, V

set to any

OUT

NOM

R

F

Normal mode, V = V

to V

+0.3V to V

+0.8V

IN

NOM

+0.3V; t = t = 1µs, I

= I

,

NOM

R

F

OUT

MAX

V

set to any voltage

NOM

Output Line Transient

(Note 14)

Low-power mode, V = V

+0.3V to V

+0.8V

IN

NOM

to V

+0.3V; t = t = 1µs, I = 5mA,

5

NOM

R

F

OUT

V

set to any voltage

NOM

Maxim Integrated

│ 43

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—450mA NMOS (continued)

(V

= V = 3.7V, T = -40°C to +85°C, unless otherwise noted.) (Note 12)

MBATT

IN A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

88

65

51

22

15

85

63

49

21

14

45

30

18

10

MAX

UNITS

f = 1kHz

V

=

+1V

=

f = 10kHz

INDC

NOM

INAC

f = 100kHz

f = 1000kHz

f = 4450kHz

f = 1kHz

50mV

V

=

f = 10kHz

INDC

Rejection from

V

+0.5V

=

NOM

V

to V

f = 100kHz

f = 1000kHz

f = 4450kHz

f = 1kHz

IN

OUT

V

INAC

Power Supply

Rejection

I

= 10% of I

MAX

OUT

PSRRxx

dB

50mV

V

=

f = 10kHz

INDC

V

+0.1V

=

NOM

f = 100kHz

f = 1000kHz

f = 4450kHz

V

INAC

10mV

Low-power mode, I

= 1mA, f = 1kHz,

to V

OUT

50

rejection from V

MBATT

V

= 0.8V

= 1.8V

55

65

OUT

f = 10Hz to 100kHz,

= 10% of I

Output Noise

µV

RMS

I

OUT

MAX

V

Soft-Start and Dynamic

Voltage Change

Ramp Rate

Lxx_SS = 0

Lxx_SS = 1

100

5

t

After enabling, Note 17

mV/µs

µA

SSxx

Output disabled, V

= 1V, current from

OUT_LDOx to GND, active-discharge disabled (Lxx_

ADE = 0)

OUT

Output Disabled

Leakage Current

0.1

65

Output Disabled, V

= 1V, resistance from

OUT_LDOx to GND, active-discharge enabled

OUT

Active-Discharge

Resistance

Ω

(Lxx_ADE = 1)

OVERVOLTAGE CLAMP

Clamp Active

Regulation Voltage

Clamp active (OVCLMP_EN_Lxx = 1),

LDO output sinking 0.1mA

V

NOM

Clamp Disabled

Overvoltage Sink

Current

V

= V

x 110%

2.2

µA

OUTxx

NOM

Maxim Integrated

│ 44

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—450mA NMOS (continued)

(V

= V = 3.7V, T = -40°C to +85°C, unless otherwise noted.) (Note 12)

MBATT

IN A

PARAMETER

TIMING

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Time from LDO enable

Lxx_SS = 0

Lxx_SS = 1

15

µs

command received to

the output starting to

slew, LDO bias enabled

Turn-On Time

t

LON

140

After LDO is disabled, the LDO output voltage

discharges based on Load and C . To ensure fast

discharge times enable the active-discharge resistor

Turn-Oﬀ Time

0.1

50

µs

OUT

Transition Time from

Low-Power Mode to

Normal Mode

THERMAL SHUTDOWN

Thermal Shutdown

POWER-OK

T rising

165

150

J

Output disabled or

enabled

°C

T falling

J

V

rising

falling

92

87

95

OUT

V

when V

POK

OUT

Power-OK Threshold

V

%

POKTHL

switches

84

OUT

Power-OK Noise

Pulse Immunity

t

V

pulsed from 100% to 80% of regulation

25

µs

POKNFLDO

OUT

Note 12: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed through

A

correlation using statistical quality control (SQC) methods.

Note 13: For stability requirements, refer to the Remote Capacitor Design with the Register Adjustable Compensation section.

Note 14: Does not include ESR of the capacitance or trace resistance of the PCB.

Note 15: Input voltage range is guaranteed from V

+0.3V to 5.5V by output accuracy specifications. Inputs between V

OUT

and V

+0.3V are guaranteed by design and subject to drop-out resistance limitations [V (min) = V

+ I

x

OUT

IN

OUT

R

] and may have reduced PRSS and transient performance. For example, with V

= 0.8V and V

= 2.7V,

= 0.8V +

DO

OUT

MBATT

= 0.5Ω therefore with I

= 0.2A, the input voltage must be at least 0.9V (V ≥ V

+I

x R

OUT

IN

OUT OUT

0.2A x 0.5Ω = 0.9V).

Note 16: Battery Voltage Range is guaranteed from V

+1.5V to 5.5V by the Dropout Voltage specification. Inputs between

OUT

V

+1.0V and V

+1.5V are guaranteed by design and subject to drop-out resistance limitations

OUT

(see Typical Operating Characteristics). Absolute minimum battery voltage range for LDOs is 2.45V.

Note 17: During a soft-start event or a DVS transition, the regulators output current increases by C x dV/dt. In the event that

OUT

the load current plus the additional current imposed by the soft-start or DVS transition reach the regulator’s current limit,

the current limit is enforced. When the current limit is enforced, the advertised transition rate (dV/dt) does not occur.

Maxim Integrated

│ 45

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—GPIOs

(V

= V

= 3.6V, I

= 0µA, circuit of Simplified Functional Diagram, T = -40°C to +85°C, unless oth-

MBATT

GPIO_INA

GPIO_INB

BBATT A

erwise specified, typical values are at T = +25°C.) (Note 18)

A

PARAMETER

SUPPLY

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Voltage

Supply Current

GPIO INPUT

V

1.7

5.5

1

V

GPIO_INx

I

µA

GPIO_INx

GPIO0-3, V

GPIO4-7, V

= 1.7V to 5.5V

0.5

GPIO_INA

Input Voltage Low

V

IL

= 1.7V to 5.5V

GPIO_INB

0.7 x

GPIO0-3, V

GPIO_INA

GPIO_INB

V

GPIO_INA

Input Voltage High

V

IH

0.7 x

GPIO4-7, V

= 1.7V to 5.5V

V

GPIO_INB

Input Hysteresis

V

0.25

V

hys

V

= 5.5V

GPIO_INB

= 0V and 5.5V

T

= +25°C

0.001

0.01

1

GPIO_INA

A

Input Leakage Current

I

µA

i

= +85°C

V

A

IN

GPIO PUSH-PULL OUTPUT—GPIO0-GPIO7

I

= 4mA

0.08

0.25

SINK

Output Voltage Low

V

OL

= 12mA

0.7 x

GPIO0-3, I

= 4mA

SOURCE

V

GPIO_INA

Output Voltage High

V

OH

0.7 x

GPIO4-7, I

V

GPIO_INB

GPIO OPEN-DRAIN OUTPUT—GPIO0-GPIO7

I

= 4mA

0.08

0.25

SINK

Output Voltage Low

V

OL

= 12mA

V

= 5.5V, T = +25°C,

GPIO_INx

A

0.01

0.1

1.0

internal pullup/pulldown disabled

Output High Leakage Current

I

µA

OH

V

= 5.5V, T = +85°C,

GPIO_INx

A

internal pullup/pulldown disabled

GPIO PULL RESISTANCES—GPIO0-GPIO7

Pullup Resistance

R

Note 19

50

100

160

kΩ

PU

PD

Pulldown Resistance

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

Electrical Characteristics—GPIOs (continued)

(V

= V

= 3.6V, I

= 0µA, circuit of Simplified Functional Diagram, T = -40°C to +85°C, unless oth-

MBATT

GPIO_INA

GPIO_INB

BBATT A

erwise specified, typical values are at T = +25°C.) (Note 18)

A

PARAMETER

REFERENCE OUTPUT—GPIO7

Output Voltage

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V

0µA < I

< 160µA

1.225

1.250

2

1.272

V

REF

REFOUT

V

= 5.5V, 2.6V < V

= 0µA

< 5.5V,

MBATT

GPIO_INB

Line Regulation

mV

I

REFOUT

Load Regulation

Ripple Rejection

0µA < I

< 160µA

2

mV

dB

REFOUT

f = 1kHz

70

V

= 5.5V, 2.6V < V

= 0µA

MBATT

GPIO_INB

Output Current

160

µA

I

REFOUT

Output Noise Voltage

10Hz to 100kHz, C

= 20pF

55

µV

RMS

REFOUT

Note 18: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed through

A

correlation using statistical quality control methods.

Note 19: The min/max variation shows it is based on process statistics. This parameter is not production tested.

Electrical Characteristics—RTC

(V

= 3.6V, V

= 2.5V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 20)

MBATT

BBATT

A

PARAMETER

Operating Voltage Range

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V

Note 21

1.65

5.5

V

RTC

V

= 0V,

V

= 2.45V

= 3.00V

2.0

MBATT

BBATT

B

Current

I

PWR_MD_32k =

0b00

µA

BATT

BBATT

V

2.2

2

4.2

BBATT

Time Accuracy

Per day (Note 21)

s

Hz

V

32KCLK Input Frequency

32KCLK Voltage

f

32768

32KCLK

V

RTC

32KCLK

Note 20: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed through

A

correlation using statistical quality control methods.

Note 21: Design guidance only, not tested during final test.

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Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Electrical Characteristics—32kHz Crystal Oscillator

(V

= 3.6V, V

= 2.5V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 20)

MBATT

RTC

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

CRYSTAL OSCILLATOR

Minimum Oscillator Supply

Voltage

V

1.5

23

V

RTCUVLO

Low-jitter mode

(PWR_MD_32K[1:0]

= 0b11)

V

= 3.6V,

= 2.55V,

MBATT

BBATT

backup battery

charger target

voltage = 2.5V

Oscillator Supply Current

I

µA

BBATT

Low-power mode

(PWR_MD_32K[1:0]

= 0b00)

2.0

(BBCRS[1:0] = 0b00)

Oscillator Voltage

Temperature Coeﬃcient

V

= 1.5V to 3.4V

20

90

3

ppm/V

kΩ

OLTCO

OSC

Maximum Crystal ESR

Parasitic XIN/XOUT

Pin Capacitance

C

From XIN to XGND and from XOUT to XGND

pF

PAR

32KLOAD = 0x03

32KLOAD = 0x00

32KLOAD = 0x01

6.5

7.5

Crystal Loading

pF

12.5

Maximum Oscillator

Start-Up Time

t

1000

ms

OSU

32K OUTPUT BUFFERS

Output Frequency

f

I

32768

1.8

Hz

V

32K_OUTx

32k Output Buﬀer Supply

Voltage

Buﬀer is internally supplied by GPIO_INB

1.7

C

= 25pF, f

= 32768Hz,

32K_OUTx

Supply Current

3.7

64

µA

µs

(Note 22)

Maximum 32K_OUTx

Enable Time

Clock input = 32768Hz

Low-power mode (PWR_MD_32K[1:0] = 0b00)

40

45

60

55

32K_OUT0 Duty Cycle

%

Low-jitter mode (PWR_MD_32K[1:0] = 0b11)

push-pull output (OTP_32K = 0)

32K_OUT0 Rise/Fall Time

C

= 25pF

20

ns

V

32K_OUTx

32K_OUT0 Output

Voltage High

V

= 1.7V, I

= 4mA,

0.7 x

V

GPIO_INB

SOURCE

V

OH

push-pull output (OTP_32K = 0)

Output High Leakage

Current (Note 22)

I

T

= +25°C, open-drain output (OTP_32K = 1)

0.001

1

µA

V

OZH

A

32K_OUT0 Output

Voltage Low

V

= 1.7V, I = 4mA

SINK

0.4

OL

GPIO_INB

Note 22: The MAX77863 internal clock buffer consumes 1uA. To drive a 25pF capacitor at 32kHz consumes 2.7µA

(C x V x F losses). Therefore, enabling a single 32kHz clock buffer consumes approximately 3.7µA.

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MAX77863

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Multicore Applications

Electrical Characteristics—Backup Battery Charger

(Operating conditions (unless otherwise specified) V

= 3.7V, V

= 3.0V, T = -40°C to +85°C.)

MBATT

BBATT A

PARAMETER

CONDITIONS

MIN

TYP

MAX

2.580

3.090

3.400

3.605

UNITS

BBCVS[1:0] = 0x00

BBCVS[1:0] = 0x01

BBCVS[1:0] = 0x02

BBCVS[1:0] = 0x03

2.420

2.910

3.200

3.395

2.500

3.000

3.300

3.500

Programmable Output

Voltage Range

I

= 1µA

V

LOAD

BBCCS[1:0] = 0x00,

0x01, 0x02

50

BBCLOWIEN

= 0

BBCCS[1:0] = 0x01

BBCCS[1:0] = 0x00

BBCCS[1:0] = 0x01

BBCCS[1:0] = 0x02

BBCCS[1:0] = 0x03

100

200

600

800

400

0.1

1

V

BBATT

Constant Current Limit

short to

GND

µA

BBCLOWIEN

= 1

BBCRS[1:0] = 0x00

BBCRS[1:0] = 0x01

BBCRS[1:0] = 0x02

BBCRS[1:0] = 0x03

Output Resistance

kΩ

3

6

T

= +25°C

= +85°C

0.01

0.1

5

10

A

Reverse Leakage Current

Input = 0V, V

= 3.0V

µA

BBATT

from BBATT to V

MBATT

Charger Ground Current

I

= 1µA (Note 1)

LOAD

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Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

Electrical Characteristics—On-Oﬀ Controller

(V

= 3.6V, I

= 0µA, T = -40°C to +85°C, unless otherwise specified, typical values are at T = +25°C.) (Note 23)

MBATT

BBATT A A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

EN0

Input Voltage Low

Input Voltage High

Input Hysteresis

Debounce Time

EN0_1SEC Time

V

0.4

V

IL

V

1.4

24

IH

V

0.05

30

1

V

HVS

t

36

ms

s

DBEN0

t

1SECEN0

MRT[2:0] = 0b000

2

MRT[2:0] = 0b001

MRT[2:0] = 0b010

MRT[2:0] = 0b011

MRT[2:0] = 0b100

MRT[2:0] = 0b101

MRT[2:0] = 0b110

MRT[2:0] = 0b111

MRT[2:0] = 0b000

MRT[2:0] = 0b001

MRT[2:0] = 0b010

MRT[2:0] = 0b011

MRT[2:0] = 0b100

MRT[2:0] = 0b101

MRT[2:0] = 0b110

MRT[2:0] = 0b111

3

4

5

Manual Reset Time

t

s

HRDRST

6

8

10

12

2

3

4

Manual Reset Warning

Time (MRWRN)

t

s

MRWRN

5

6

8

10

Internal Pullup

Resistance

Only available with OTP_EN0AL = 1,

Figure 20

R

10

kΩ

PUEN0

Internal Pulldown

Resistance

Only available with OTP_EN0AL = 0,

Figure 20

R

PDEN0

Note 23: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed through

A

correlation using statistical quality control methods.

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

Electrical Characteristics—FPS

(V

= 3.6V, I

= 0µA, circuit of Simplified Functional Diagram, T = -40°C to +85°C, unless otherwise specified, typical val-

MBATT

BBATT A

ues are at T = +25°C.) (Note 24)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

The MAX77863 reference is already powered

up prior to the enable command (Note 25)

0.01

Flexible Power

Sequencer Enable Delay

t

µs

FSDON

The MAX77863 reference is powered down

prior to the enable command

30

Flexible Power

Sequencer Disable Delay

t

0.01

µs

FPSDOFF

TFPSx[2:0] = 0b000

TFPSx[2:0] = 0b001

TFPSx[2:0] = 0b010

40

80

160

320

640

1280

2560

5120

TFPSx[2:0] = 0b011

Figure 28

Flexible Power

Sequencer Event Period

t

FST

TFPSx[2:0] = 0b100

TFPSx[2:0] = 0b101

TFPSx[2:0] = 0b110

TFPSx[2:0] = 0b111

Flexible Power

Sequencer Event Period

Timer Accuracy

Accuracy of the ﬂexible power sequencer clock

-15

+15

%

Note 24: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed through

A

correlation using statistical quality control methods.

Note 25: The MAX77863 reference is powered up if any of the step-down regulators or any of the low dropout linear regulators

are enabled.

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

2

Electrical Characteristics—I C

(V

= 3.6V, V

= 1.8V, circuit of Simplified Functional Diagram, T = -40°C to +85°C, unless otherwise specified, typical

MBATT

INI2C A

values are at T = +25°C.) (Note 26)

A

PARAMETER

POWER SUPPLY

SYMBOL

CONDITIONS

MIN

1.7

TYP

MAX

UNITS

INI2C Voltage

V

3.6

V

INI2C

SDA AND SCL I/O STAGES

0.7 x

SCL, SDA Input High Voltage

SCL, SDA Input Low Voltage

SCL, SDA Input Hysteresis

V

= 1.7V to 3.6V

V

IH

INI2C

V

INI2C

0.3 x

V

IL

INI2C

V

INI2C

0.05 x

V

HYS

V

INI2C

SCL, SDA Input Current

II

V

= 3.6V or 0V

-10

+10

0.4

μA

V

I2CIN

SDA Output Low Voltage

SCL, SDA Pin Capacitance

Output Fall Time from VIH to VIL

V

Sinking 20mA

OL

Ci

10

pF

ns

t

Note 27

120

OF

2

Electrical Characteristics—I C (continued)

(V

= 3.6V, V

= 1.8V, circuit of Simplified Functional Diagram, T = -40°C to +85°C, unless otherwise specified, typical

MBATT

INI2C A

values are at T = +25°C.) (Note 27)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

2

I C-COMPATIBLE INTERFACE TIMING FOR STANDARD, FAST, AND FAST-MODE PLUS

Clock Frequency

f

1000

kHz

µs

SCL

Hold Time (Repeated)

START Condition

t

0.26

HD;STA

CLK Low Period

CLK High Period

t

0.5

µs

LOW

t

0.26

HIGH

Set-Up Time Repeated

START Condition

t

0.26

µs

SU;STA

HD:DAT

DATA Hold Time

t

0

µs

ns

µs

DATA Set-Up time

t

50

SU;DAT

Set-Up Time for STOP Condition

t

0.26

SU;STO

Bus-Free Time Between STOP

and START

t

0.5

µs

pF

BUF

Capacitive Load for Each Bus Line

C

550

B

Maximum Pulse Width of Spikes

that Must be Suppressed by the

Input Filter

50

ns

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

2

Electrical Characteristics—I C (continued)

(V

= 3.6V, V

= 1.8V, circuit of Simplified Functional Diagram, T = -40°C to +85°C, unless otherwise specified, typical

MBATT

INI2C A

values are at T = +25°C.) (Note 27)

A

C

= 100pF

C = 400pF

B

PARAMETER

SYMBOL

CONDITIONS

UNITS

MIN

MAX

MIN

MAX

2

I C-COMPATIBLE INTERFACE TIMING FOR HS-MODE

Clock Frequency

f

3.4

1.7

MHz

ns

SCL

Set-Up Time Repeated

START Condition

t

160

SU;STA

Hold Time (Repeated)

START Condition

t

ns

HD;STA

CLK Low Period

CLK High Period

DATA Set-Up time

DATA Hold Time

SCL Rise Time

t

160

60

10

0

320

120

10

0

ns

LOW

t

HIGH

t

SU;DAT

HD:DAT

t

70

40

150

80

t

10

20

RCL

Rise Time of SCL Signal After a

Repeated START Condition and

after an Acknowledge Bit

t

10

80

20

80

ns

rCL1

SCL Fall Time

SDA Rise Time

SDA Fall Time

t

10

40

80

20

80

ns

fCL

t

160

rDA

t

fDA

Set-Up Time for STOP

Condition

t

160

ns

SU;STO

Capacitive Load for Each

Bus Line

C

100

10

400

10

pF

B

Maximum Pulse Width of

Spikes that Must be Suppressed

by the Input Filter

ns

Note 26: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed through

A

correlation using statistical quality control methods.

Note 27: System design guidance only. Not production tested.

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

Typical Operating Characteristics

(IN_SDx = MBATT, FPWM Mode, L = 1μH (TOKO 2520 case size) ,remote sense disabled, T = +25°C unless otherwise noted.)

A

SD1

SD0

SD2

EFFICIENCY vs. LOAD CURRENT

toc02

toc01

toc03

100

90

80

70

60

50

40

30

100

90

80

70

60

50

40

30

100

90

80

70

60

50

40

30

V

= 2.7V

IN

V

= 2.7V

V

= 2.7V

= 3.8V

IN

V

= 3.8V

= 5.5V

IN

V

= 3.8V

= 5.5V

IN

V

= 5.5V

IN

V

= 1.15V, FORCED PWM DISABLED,

1µH (TOKO DFE201612P-1R0M),

REMOTE SENSE DISABLED

V

= 1.35V, FORCED PWM DISABLED,

1µH (TOKO DFE201612P-1R0M),

REMOTE SENSE DISABLED

V

= 1.0V, FORCED PWM DISABLED,

1µH (TOKO DFE252012F-1R0M),

REMOTE SENSE DISABLED

OUT

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

LOAD CURRENT (A)

POWER-SUPPLY REJECTION RATIO

vs. INPUT FREQUENCY

SD3

EFFICIENCY vs. LOAD CURRENT

150mA PMOS LDO

toc04

toc05

100

90

80

70

60

50

40

30

20

10

0

V

AVERAGE = 3.5V

AVERAGE = 2.8V

IN_LDO2

90

80

70

60

50

40

30

IN_LDO2

V

= 2.7V

= 3.8V

= 5.5V

IN

V

LDO POWERED EXTERNALLY

V

= 1.8V, FORCED PWM DISABLED,

1µH (TOKO DFE201612P-1R0M),

REMOTE SENSE DISABLED

OUT

V

I

= 1.6V

= 15mA

OUT2

0.001

0.01

0.1

1

10

0.1

1

10

100

1000

LOAD CURRENT (A)

INPUT FREQUENCY (kHz)

POWER-SUPPLY REJECTION RATIO

vs. INPUT FREQUENCY

150mA PMOS LDO

toc06

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

I_OUT2= 30mA

I_OUT2= 90mA

I_OUT2= 150mA

V_{IN_LDO3}AVERAGE = 3.5V

V_{IN_LDO3}AVERAGE = 3.0V

LDO POWERED EXTERNALLY

V_OUT2= 1.6V

V_{IN_LDO2}AVERAGE = 3.5V

V_OUT3= 1.8V

I_OUT3= 30mA

0.1

1

10

100

1000

0.1

1

10

100

1000

INPUT FREQUENCY (kHz)

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MAX77863

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Multicore Applications

Typical Operating Characteristics (continued)

(IN_SDx = MBATT, FPWM Mode, L = 1μH (TOKO 2520 case size) ,remote sense disabled, T = +25°C unless otherwise noted.)

A

POWER-SUPPLY REJECTION RATIO

vs. INPUT FREQUENCY

300mA PMOS LDO

toc08

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

I_OUT3= 30mA

I_OUT3= 120mA

I_OUT3= 240mA

V_{IN_LDO0}AVERAGE = 3.5V

_{IN_LDO0}AVERAGE = 3.0V

I_OUT0= 15mA

I_OUT0= 30mA

I_OUT0= 60mA

V

LDO POWERED EXTERNALLY

V_OUT0= 1.8V

V_OUT3= 1.8V

V_{IN_LDO3}AVERAGE = 3.5V

V_OUT0= 1.8V

V_{IN_LDO0}AVERAGE = 3.5V

I_OUT0= 15mA

0.1

1

10

100

1000

0.1

1

10

100

1000

0.1

1

10

100

1000

INPUT FREQUENCY (kHz)

POWER-SUPPLY REJECTION RATIO

vs. INPUT FREQUENCY

300mA NMOS LDO

toc11

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V

_{IN_LDO8}AVERAGE = 3.5V

_{IN_LDO8}AVERAGE = 3.0V

I_OUT8= 30mA

I_OUT8= 120mA

I_OUT8= 300mA

V

LDO POWERED EXTERNALLY

V_OUT8= 1.8V

V_{IN_LDO8}AVERAGE = 3.5V

I_OUT8= 30mA

0.1

1

10

100

1000

0.1

1

10

100

1000

INPUT FREQUENCY (kHz)

POWER-SUPPLY REJECTION RATIO

vs. INPUT FREQUENCY

450mA NMOS LDO

toc13

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V_{IN_LDO7}AVERAGE = 3.5V

_{IN_LDO7}AVERAGE = 3.0V

I_OUT7= 45mA

I_OUT7= 225mA

I_OUT7= 450mA

V

LDO POWERED EXTERNALLY

V_OUT7= 1.8V

V_{IN_LDO7}AVERAGE = 3.5V

I_OUT7= 45mA

0.1

1

10

100

1000

0.1

1

10

100

1000

INPUT FREQUENCY (kHz)

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Bump Conﬁguration

TOP VIEW

(BUMP SIDE DOWN)

MAX77863

1

2

3

4

5

6

7

8

9

10

+

OUT_

LDO3

IN_LD

O3-5

OUT_

LDO5

IN_

LDO2

OUT_

LDO7

IN_LD

O7-8

OUT_

LDO8

NIC0

MON

NIC1

A

B

C

D

IN_

SD3

OUT_

LDO4

IN_LD

O4-6

OUT_

LDO6

OUT_

LDO2

OUT_

LDO0

IN_LD

O0-1

OUT_

LDO1

AVSD

XIN

LX_

SD3

LX_

SD3

FB_

SD3

MBA TT

EN1

GND

EN2

GND

EN0

GND

ACOK

XGND

XOUT

PG_

SD3

FB_

SD2

FB_

SD1

32K_

OUT0

nIRQ

D_SD3

BBATT

PG_

SD2

SNSN

_SD1

SNSP

_SD1

E

SCL

SDA

INI2C

GND

LID

GND

SHDN

PG_

SD2

FB_

SD0

FB_

SD0

SNSP

_SD0

SNSN

_SD0

nRST

_IO

PG_

SD1

F

G

H

J

LX_

SD2

LX_

SD2

GPIO

_INB

GPIO

_INA

LX_

SD1

LX_

SD1

GPIO4

GPIO5

GPIO6

GPIO7

GPIO0

GPIO1

GPIO2

GPIO3

IN_

SD2

INB_

SD0

PGB_

SD0

PGA_

SD0

INA_

SD0

IN_

SD1

INB_

SD0

LXB_

SD0

LXB_

SD0

PGB_

SD0

PGA_

SD0

LXA_

SD0

LXA_

SD0

INA_

SD0

NIC2

NIC3

WLP

(4.1mm x 3.8mm X 0.7mm)

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Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

Bump Description

NAME

DESCRIPTION

LINEAR REGULATORS

B8

A6

IN_LDO0-1 Linear regulator 0 and 1 power input. Bypass IN_LDO0 to GND with a 1.0µF ceramic capacitor.

IN_LDO2

Linear regulator 2 power input. Bypass IN_LDO2 to GND with a 1.0µF ceramic capacitor.

Linear regulator 3 and 5 power input. Bypass IN_LDO3-5 to GND with a 1.0µF ceramic capacitor.

A4

B4

IN_LDO3-5 A single IN_LDO3-5 and IN_LDO4-6 input bypass capacitor can be shared between LDOs 3, 4, 5,

and 6 if they are powered from the same input supply.

Linear regulator 4 and 6 power input. Bypass IN_LDO4-6 to GND with a 1.0µF ceramic capacitor.

IN_LDO4-6 A single IN_LDO3-5 and IN_LDO4-6 input bypass capacitor can be shared between LDOs 3, 4, 5,

and 6 if they are powered from the same input supply.

A8

B7

B9

B6

A3

B3

A5

B5

A7

A9

IN_LDO7-8 Linear regulator 7 and 8 power input. Bypass IN_LDO7-8 to GND with a 1.0µF ceramic capacitor.

OUT_LDO0 LDO0 power output. LDO0 is an N-channel linear regulator.

OUT_LDO1 LDO1 power output. LDO1 is an N-channel linear regulator.

OUT_LDO2 LDO2 power output. LDO2 is a P-channel linear regulator.

OUT_LDO3 LDO3 power output. LDO3 is a P-channel linear regulator.

OUT_LDO4 LDO4 power output. LDO4 is a P-channel linear regulator.

OUT_LDO5 LDO5 power output. LDO5 is a P-channel linear regulator.

OUT_LDO6 LDO6 power output. LDO6 is a P-channel linear regulator.

OUT_LDO7 LDO7 power output. LDO7 is a N-channel linear regulator.

OUT_LDO8 LDO8 power output. LDO8 is a N-channel linear regulator.

GLOBAL RESOURCES

C3

A2

MBATT

MON

Low-noise PMIC power input. Bypass MBATT with a 0.1µF ceramic capacitor to ground.

Low-battery monitor analog input.

D5, D6, D7,

E4, E6, E7

GND

BBATT

XOUT

Ground. All GND pins must be connected together.

D10

C10

Backup battery connection. Bypass BBATT with a 0.1µF ceramic capacitor to ground.

32.768kHz crystal oscillator output. XOUT has on-chip programmable load capacitors for the

crystal oscillator.

32.768kHz crystal oscillator input. XIN has on-chip programmable load capacitors for the crystal

oscillator.

B10

XIN

C9

XGND

NIC1

Crystal oscillator ground. All XGND pins must be connected together.

A10

Not internally connected #1. However, for best PCB routing, connect NIC1 to XGND.

32.768kHz crystal oscillator output. 32K_OUT0 is a 50% duty cycle square wave buﬀered

version of TXIN.

D9

32K_OUT0

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Bump Description (continued)

NAME

DESCRIPTION

2

I C SERIAL INTERFACE

E3

F2

E2

D2

INI2C

SDA

SCL

Internal logci supply for SDA and SCl.

Serial interface data bidirectional open-drain.

Serial interface clock input. Open-drain output.

Active-low interrupt output. nIRQ is an open-drain output.

nIRQ

ON/OFF CONTROLLER AND FLEXIBLE POWER SEQUENCER

Enable input 0 to the ﬂexible power sequencer. EN0 is typically connected to the system’s ONKEY.

See the EN0 section for more information.

C7

C5

EN0

EN1

Enable input 1 to the ﬂexible power sequencer. EN1 is typically connected to the system’s AP.

See the EN1 section for more information.

Enable input 2 to the ﬂexible power sequencer. EN2 is typically connected to the system’s AP.

See the EN2 section for more information.

C6

E10

C8

EN2

SHDN

ACOK

Shutdown digital input.

ACOK is a digital input to the ON/OFF controller that typically comes from

the system’s battery charger .

LID is a digital input to the ON/OFF controller that typically comes from the system’s

battery charger.

E5

LID

STEP-DOWN REGULATORS

Step-down regulator analog power input. AVSD powers the analog portions of all step-down

regulators. INy_SDx, and AVSD are typically connected to MBATT in the typical applications

circuit for a 1s battery conﬁguration as shown in Figure 40. For applications with 2s

(or higher) battery conﬁguration AVSD can be connected to an external step-down regulator

as shown in Figure 41 and all INy_SDx must be connected together.

B2

D4

AVSD

D_SD3 default output voltage select input. D_SD3 is a tri-level logic input. Connect D_SD3 as

described in Table D_SD3 Logic. The logic level of D_SD3 is latched each time the MBATT

D_SD3

voltage rises above the main-battery under voltage lockout threshold (V

> V

).

MBATT

MBATTUVLO

Changes to D_SD3 after the logic level has been latched have no eﬀect.

Power input for phase “A” of the step-down regulator 0. Connect AVSD and all INA_SD0 together.

Bypass INA_SD0 to GND with a 4.7µF ceramic capacitor.

H9, J9

H2, J2

H10

J10

INA_SD0

INB_SD0

IN_SD1

NIC3

MAX77863 power input for phase “B” of the step-down regulator 0. Connect AVSD and

all INB_SD0 together. Bypass INB_SD0 to GND with a 4.7µF ceramic capacitor.

Power input for step-down regulator 1. Connect AVSD and all IN_SD1 together. All IN_SD1 pins

must be connected together. Bypass IN_SD1 to GND with a 2.2µF ceramic capacitor.

Not internally connected #3. J10 is not internally connected. However, for best PCB routing,

connect NIC3 to IN_SD1.

Power input for step-down regulator 2. Connect AVSD and all IN_SD2 together. All IN_SD2 pins

must be connected together. Bypass IN_SD2 to GND with a 2.2µF ceramic capacitor.

H1

IN_SD2

NIC2

Not internally connected #2. J1 is not internally connected. However, for best PCB routing,

connect NIC2 to IN_SD2.

J1

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Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

Bump Description (continued)

NAME

DESCRIPTION

Power input for step-down regulator 3. Connect AVSD and all IN_SD3 together. All IN_SD3 pins

must be connected together. By pass IN_SD3 to GND with a 2.2µF ceramic capacitor.

B1

IN_SD3

Not internally connected #0. A1 is not internally connected. However, for best PCB routing,

connect NIC0 to IN_SD3.

A1

NIC0

Inductor switching node for phase “A” of step-down regulator 0. When the regulator is enabled,

the inductor switching node drives between INA_SD0 and PGA_SD0 to maintain FB_SD0 at its

regulation threshold. All LXA_SD0 pins must be connected together.

J7, J8

LXA_SD0

Inductor switching node for phase “B” of step-down regulator 0. When the regulator is enabled,

the inductor switching node drives between INB_SD0 and PGB_SD0 to maintain FB_SD0 at its

regulation threshold. All LXB_SD0 pins must be connected together.

J3, J4

G9, G10

G1, G2

C1, C2

LXB_SD0

LX_SD1

LX_SD2

LX_SD3

Inductor switching node for step-down regulator 1. When the regulator is enabled, the inductor

switching node drives between IN_SD1 and PG_SD1 to maintain FB_SD1 at its regulation

threshold. All LX_SD1 pins must be connected together.

Inductor switching node for step-down regulator 2. When the regulator is enabled, the inductor

switching node drives between IN_SD2 and PG_SD2 to maintain FB_SD2 at its regulation

threshold. All LX_SD2 pins must be connected together.

Inductor switching node for step-down regulator 3. When the regulator is enabled, the inductor

switching node drives between IN_SD3 and PG_SD3 to maintain FB_SD3 at its regulation

threshold. All LX_SD3 pins must be connected together.

Power ground for phase “A” of step-down regulator 0. All PGA_SD0 pins must be connected

together.

H6, J6

H5, J5

PGA_SD0

PGB_SD0

Power ground for phase “B” of step-down regulator 0. All PGB_SD0 pins must be connected

together.

F10

E1, F1

D1

PG_SD1

PG_SD2

PG_SD3

Power ground for step-down regulator 1. All PG_SD1 pins must be connected together.

Power ground for step-down regulator 2. All PG_SD2 pins must be connected together.

Power ground for Step-down regulator 3.

Step-down regulator 0 output voltage feedback node. Connect FB_SD0 directly to the

step-down regulator output capacitor.

F6

D8

D3

C4

F5

F7

E9

FB_SD0

FB_SD1

Step-down regulator 1 output voltage feedback node. Connect FB_SD1 directly to the

step-down regulator output capacitor.

Step-down regulator 2 output voltage feedback node. Connect FB_SD2 directly to the

step-down regulator output capacitor.

FB_SD2

Step-down regulator 3 output voltage feedback node. Connect FB_SD3 directly to the

step-down regulator output capacitor.

FB_SD3

Step-down regulator 0 output voltage feedback node. Connect FB_SD0 directly to the

step-down regulator output capacitor.

FB_SD0

Output voltage remote sense positive input for step-down regulator 0. Connect SNSP_SD0

directly to the point-of-load positive terminal.

SNSP_SD0

SNSP_SD1

Output voltage remote sense positive input for step-down regulator 1. Connect SNSP_SD1

directly to the point-of-load positive terminal.

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Bump Description (continued)

NAME

DESCRIPTION

F4

GND

Unused pin that is internally connected. Connect to ground for the lowest thermal impedance.

Output voltage remote sense negative input for step-down regulator 0.

Connect SNSN_SD0 directly to the point-of-load ground terminal.

F8

SNSN_SD0

Output voltage remote sense negative input for step-down regulator 1.

Connect SNSN_SD1 directly to the point-of-load ground terminal.

E8

F3

SNSN_SD1

GND

Unused pin that is internally connected. Connect to ground for the lowest thermal impedance.

GPIO

GPIO power input for the lower nibble. Bypass GPIO_INA to GND with a 0.1µF ceramic capacitor.

However, for the MAX77863, if GPIO_INA is supplied by one of the on-chip regulators, the

regulators output capacitor is suﬃcient bypass capacitance for GPIO_INA.

G6

G5

GPIO_INA

GPIO_INB

GPIO power input for the upper nibble. Bypass GPIO_INB to GND with a 0.1µF ceramic capacitor.

However, for the MAX77863, if GPIO_INB is supplied by one of the on-chip regulators, the

regulators output capacitor is suﬃcient bypass capacitance for GPIO_INB.

G7

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

H7

G8

H8

General purpose input/output.

G3

H3

G4

H4

RESET I/O

F9

nRST_IO

Bidirectional active-low open-drain reset input/output.

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Simpliﬁed Functional Diagram

IN_LDO0-1

AVSD

OUT_LDO0

INA_SD0

IN

LDO0, 150mA, NMOS

OUT_LDO1

LDO1, 150mA, NMOS

LXA_SD0

IN_LDO2

DCDC0

CONTROL

PGA_SD0

INB_SD0

LXB_SD0

PGB_SD0

OUT_LDO2

LDO2, 150mA, PMOS

PGND

8A PEAK

6A CONT.

IN_LDO3-5

MAX77863

OUT_LDO3

OUT_LDO5

LDO3, 300mA, PMOS

LDO5, 150mA, PMOS

IN_LDO4-6

OUT_LDO4

OUT_LDO6

FB_SD0

SNSP_SD0

SNSN_SD0N

LDO4, 150mA, PMOS

LDO6, 150mA, PMOS

LOAD

IN_LDO7-8

OUT_LDO7

OUT_LDO8

IN_SD1

LX_SD1

PG_SD1

IN

DCDC1

CONTROL

LDO7, 450mA, NMOS

LDO8, 300mA, NMOS

V

DCDC1

3A

MON

PGND

LOW-BATTERY MONITOR

FB_SD1

SNSP_SD1

SNSN_SD1

MBA TT

GND

BIAS, REF, UVLO, OVLO,

THERMAL SHUTDOWN

LOAD

GND

BBATT

GND

IN_SD2

LX_SD2

PG_SD2

FB_SD2

IN_SD3

LX_SD3

PG_SD3

BACKUP BATTERY CHARGER

IN

DCDC2

CONTROL

V

DCDC2

2A

XOUT

XIN

XGND

PGND

IN

RTC

GND

WATCHDOG

GPIO_INB

32k_OUT0

GND

DCDC3

CONTROL

V

DCDC3

2A

INI2C

SDA

SCL

PGND

FB_SD3

D_SD3

2

I C INTERFACE

AND

TRI-STATE

INPUT LATCH

INTERRUPT OUTPUT

nIRQ

EN0

GPIO_INA

GPIO0

GPIO1

GPIO

LOWER NIBBLE

EN1

ON/OFF

CONTROLLER

GPIO2

GPIO3

EN2

AND

ACOK

LID

GPIO_INB

GPIO4

GPIO5

FLEXIBLE POWER

SEQUENCER

GPIO

UPPER NIBBLE

SHDN

GPIO6

GPIO7

NICx

nRST_IO

BIDIRE CTIONAL RES ET

INPUT/OUTPUT

GND XGND PGND

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Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

ers the global resources of the IC through MBATT and

GPIO band “A”. With AON5V0 applied to MBATT, the

Detailed Description

The MAX77863 is a complete power management IC

(PMIC) for mobile devices that use multicore appli-

cation processors. The IC works well with many

different series/parallel (s/p) configurations of a Li+/

Li-Poly battery pack. Figure 40 shows the MAX77863 in

its Typical Application Circuit for systems with 1s configu-

ration batteries.

on/off controller monitors its inputs for a wakeup event.

When a wakeup event occurs, the IC begins its wakeup

sequence by enabling the external step-down regulator

such as the MAX15066 with GPIO2. The MAX15066

generates SD5V0 which powers all of the step-down

regulators and a few of its LDOs which are required to

complete the wakeup sequence. The concepts used in

Figure 41 can be utilized to create solutions for 3s and 4s

configurations. Other devices such as the MAX17085B,

MAX17005/6, MAX17015, and MAX17020 are also good

candidates for support devices in this series battery con-

figuration.

Figure 41 shows the IC in its typical applications circuit

for a system with a 2s1p (two series one parallel) battery

configuration. This applications circuit for systems with

series battery configurations adds three components that

are not shown in Figure 40: battery charger, low-I LDO,

and step-down regulator. A battery charger charges the

series configured battery pack and generates a system

Q

Simplified Functional Diagram: where appropriate, further

details of each functional block are shown within the

dedicated chapter for that function.

voltage (V

) that is derived from the adapter and/

MBATT

or the battery pack. V

is regulated down to an

MBATT

Table 1 provides a regulator summary for the IC.

always on voltage (AON5V0) by a low-I linear regulator

Q

such as the MAX1725 or the MAX8881. AON5V0 pow-

Table 1. Regulator Summary

V

OUTPUT

IN

OUT

REGULATOR

TOPOLOGY

MAXIMUM

OUTPUT

NOISE

SPECIAL

FEATURES

RANGE

(V)

RANGE RESOLUTION CAPACITOR

(V)

I

OUT

(mV)

(C

)

OUTX

8.0A Peak

6.0A

Continuous

Diﬀerential remote

output voltage

sensing

3.0 to 5.5

Step-Down

Regulator

0.6 to

1.4

SD0

12.5

2x22µF

N/A

6.0A

3.0A

2.6 to 3.0

3.0 to 5.5

Diﬀerential remote

output voltage

sensing

Step-Down

Regulator

0.6 to

1.55

SD1

SD2

12.5

22µF

N/A

2.5A

2.0A

2.6 to 3.0

2.6 to 5.5

Step-Down

Regulator

0.6 to

3.3875

Capable of 100%

duty-cycle

• Capable of

100% duty-cycle

• Three default

output voltage

options via pin

strap (D_SD3)

Step-Down

Regulator

0.6 to

3.3875

SD3

2.0A

2.6 to 5.5

12.5

22µF

N/A

N-Channel

LDO (NDRV1)

0.8 to

2.35

LDO0

LDO1

LDO2

150mA

0.8 to 5.5

1.7 to 5.5

25

50

1.0µF

65µV

45µV

N/A

RMS

N-Channel

LDO (NDRV1)

0.8 to

2.35

P-Channel

LDO (PDRV1)

0.8 to

3.95

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Complete System PMIC, Featuring 13 Regulators,

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Table 1. Regulator Summary (continued)

V

OUTPUT

IN

OUT

REGULATOR

TOPOLOGY

MAXIMUM

OUTPUT

NOISE

SPECIAL

FEATURES

RANGE

(V)

RANGE RESOLUTION CAPACITOR

(V)

I

OUT

(mV)

(C

)

OUTX

P-Channel

LDO (PDRV2)

0.8 to

3.95

LDO3

LDO4

LDO5

LDO6

LDO7

LDO8

300mA

150mA

450mA

300mA

1.7 to 5.5

0.8 to 5.5

50

2.2µF

1.0µF

45µV

65µV

N/A

RMS

P-Channel

LDO (PDRV1)

0.8 to

1.5875

12.5

50

P-Channel

LDO (PDRV1)

0.8 to

3.95

1.0µF

P-Channel

LDO (PDRV1)

0.8 to

3.95

50

1.0µF

N-Channel

LDO (NDRV3)

0.8 to

3.95

50

4.7µF

N-Channel

LDO (NDRV2)

0.8 to

3.95

50

2.2µF

*Output noise is proportional to output voltage. The specified noise values are for V

= 0.8V.

OUT_LDOx

**Quiescent supply current is the sum of the main battery current (I

), the step-down regulator analog input supply current

MBATT

(I

), and the regulator’s power input current.

AVSD

voltage (V ) is not within the acceptable window

AVSD

Global Resources

of operation (2.6V to 5.5V). Disabling the IC when the

supply is outside of its acceptable range ensures reliable

consistent behavior when the supply voltage is removed/

applied and it prevents overvoltage stress to the device.

The global resources encompasses a set of circuits that

serve the entire device and ensures safe, consistent,

and reliable operation. These resources include voltage

reference, bias currents, timing references, voltage

monitors, and thermal monitors. See Figure 1 for more

information.

In addition to the fixed threshold, UVLO and OVLO com-

parators and adjustable threshold low-battery monitor

monitors the battery voltage through the MON input and

provides the system with a signal that the main-battery is

low through a MBATTLOW status bit and MBATTLOW_R

Voltage References, Bias Currents,

and Timing References

Centralized voltage references, bias current, and timing

references support all the functional blocks within the

IC. These resources are automatically enabled when

any of the peripherals functions within the device require

them. The supply current associated with the minimum

set of these resources make up the quiescent current

interrupt bit. When V

< V

, MBATTLOW is 1.

MON

MONL

The main-battery low signal is also available through the

nRST_IO signal when LBRSTEN = 1. With all peripheral

blocks of the IC disabled, the quiescent current of the

device is 12µA (I

). The “low-battery” compara-

Q_MBATT

tor’s threshold and hysteresis are register programmable.

(I

).

Q_MBATT

For a single-cell (i.e., 1s) battery configuration (Figure

40), MON is intended to connect directly to the MBATT

pin externally. For multi-cell (i.e., 2s, 3s, 4s) configura-

tions (Figure 41), MON is intended to connect to the

main system power source (i.e., battery or system node)

Voltage Monitors

The MBATT undervoltage lockout (UVLO) and MBATT

overvoltage lockout (OVLO) comparators force the entire

device off when the supply voltage (V

) is not

MBATT

through a resistive divider. Although V

can inde-

MON

within the acceptable window of operation (2.6V to

5.5V). Similarly, the AVSD undervoltage lockout (UVLO)

and AVSD overvoltage lockout (OVLO) comparators

force the IC step-down regulators off when the supply

pendently swing from -0.3V to +6.0V, systems should be

designed such that V is less than or equal to MBATT.

MON

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Example 1: Setting the low-battery cutoff threshold to

5.6V and the battery valid threshold to 6.0V for a 2s

battery configuration

an issue because the valid battery operating range

is from 2.6V to 5.5V. However, it could be possible

that the battery capacity is not enough to support the

system when the voltage is lower than 2.9V. In this

situation, the low-battery threshold would be set for

2.9V falling.

● A system with two series batteries has a maximum

charge voltage of 8.4V and a low battery cutoff volt-

age of 5.6V (i.e., 2.8V per cell). A 400mV hysteresis

is desired before the system recognizes the battery

as valid.

● Some systems may need to choose the low-battery

threshold based on backup time: Consider the case

where a 2000mAh battery supports a system where

the highest step-down regulator output voltage is

2.5V (no dropout issues), the battery can support the

system when the voltage is down to 2.7V (no capacity

issues), but the system must have a backup time of

one year. In this case, the low-battery threshold must

be set sufficiently high so that the main battery has

enough capacity to support the system in its backup

mode for one year. In a situation like this, the low-

battery threshold may be set to 3.3V falling.

● The LBDAC[2:0] = 0b001 setting is chosen (2.8V) to

get a falling cutoff voltage of 5.6V for the two series

cell battery configuration.

● The LBHSYT[1:0] = 0b01 setting is chosen (200mV)

to get 400mV of hysteresis (i.e., 200mV per cell) and

a battery valid threshold of 6.0V.

● Adivide-by-two resistive divider using two 402kΩ resis-

tors is used from the system voltage (either battery or

adapter) to ground with the center tap connected at

MON. The low MON bias current (I

) allows for

MON

The V

LHYST[1:0]. Choose V

peak currents and battery impedance. Set V

sufficiently high to avoid oscillation in and out of the

low-battery state due to system peak currents.

hysteresis (V

) is configurable using

LBHYST

MONL

the use of a large resistor to minimize the drain on the

system. Limiting the top of the resistive divider to

< 402kΩ limits the total error due to bias current to

50mV. When using high-impedance resistive dividers,

make sure to isolate them from noise sources in the

PCB layout.

based on your system

LBHYST

● For example, consider a system that has maximum

peak currents of 1A with an internal battery imped-

ance of 100mΩ, a connector impedance of 50mΩ,

and a fuse impedance of 50mΩ. The total impedance

of 200mΩ combined with the 1A peak currents results

in the battery voltage varying by 200mV. In this case,

Example 2: Optimizing the low-battery threshold and

hysteresis

The default low-battery threshold is 3.0V falling with

200mV hysteresis. A system with a low battery cannot

start until its battery has charged above 3.2V.

V

needs to be set to 300mV (>200mV).

LBHYST

The following bullet points give some examples of

Example 3: Charging a dead battery with a 3.0V falling

situations where the low-battery falling threshold (V

can be optimized:

)

threshold and 200mV of hysteresis.

MONL

● A device with a 2.5V battery is off and does not start

when the user presses the “on key” because the

battery is too low. The user plugs the device into the

charger and presses the “on key” to find out that it still

does not start because the battery voltage is too low.

Three minutes later, the battery voltage rises above

3.2V and the device starts up with no user intervention.

● Some systems may need to choose the low-battery

threshold based on step-down regulator dropout:

Consider the case where an 800mAh battery supports

a system where the highest step-down regulator out-

put voltage is 2.8V, the step-down regulator output can

be prevented from going into dropout by setting the

low-battery threshold to 3.0V falling. This assumes

that 200mV (3.2V-3.0V) is sufficient for the step-down

regulator to stay out of dropout.

Thermal Monitors

Several on-chip thermal sensors force the IC to shut down

if the junction temperature exceeds 165°C (T

addition to the 165°C shutdown threshold, these thermal

sensors also provide interrupts when the temperature

exceeds 120°C (thermal alarm 1) and 140°C (thermal

alarm 2).

). In

JSHDN

● Some systems may need to choose the low-battery

threshold based on the battery capacity: Consider the

case where a 2000mAh battery supports a system

where the highest step-down regulator output voltage

is 2.5V, then the step-down regulator dropout is not

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● FPS0 (flexible power sequencer 0) has gotten past

Bidirectional Reset Input/Output

power up cycle 5 (FSO_RSO).

The MAX77863 has a bidirectional, active-low, open-

drain, reset input/output (nRST_IO) as shown in Figure

1. The RSO signal within the bidirectional reset IO logic

in Figure 1 is asserted by the IC when it needs to drive

nRST_IO low. If the IC is not driving nRST_IO low (i.e.,

RSO is low), and an external device such as a reset

button (Figure 1) pulls nRST_IO low, then the RSI signal

within the bidirectional reset IO logic is asserted. If RSI is

● t

expired.

RST_O

● No external device such as a reset button (Figure 40

)

are pulling nRST_IO low.

Global Shutdown

This document uses the term “global shutdown” to refer to

any event that causes a shutdown of all regulators and a

reset for most of the registers within the IC. The NVERC

register records the source of a “global shutdown” event.

Figure 4 shows the global shutdown state machine.

Figure 5 is the simplified logic diagram for the global shut-

down. Figure 6 and Figure 7 shows the simplified timing

diagram for the global shutdown events. In addition to

the state machine, the various conditions that causes a

global shutdown are also shown in the bulleted list below:

asserted for longer than t

, then a global shutdown

DBNC

event is triggered (GLBALSHDN). A global shutdown due

to RSI is recorded in the NVERC register such that when

the system’s microprocessor recovers from the reset it

can recognize that the cause of the power down was due

to RSI. If a global shutdown event is triggered by RSI,

then the IC automatically generates a wakeup event after

the global shutdown event has completed. See the Global

Shutdown section for more information.

● Reset input (i.e., RSI event)

The reset output is a programmable slave to the flexible

power sequencer. Allowing the RSO to respond to the flexible

power sequencer gives it the capability to drive the nRST_IO

line low as the first action in the power down sequence

(Figure 26). The FPS_RSO register configures how nRST_IO

behaves with respect to the flexible power sequencer.

• nRST_IO externally pulled low for t

is deasserted.

after RSO

DBNC

● Software Reset (i.e., SFT_RST event)

• SFT_RST bit is set.

● Main-Battery Undervoltage

(V

< V

)

MBATT

MBATTUVLO

Once all conditions for allowing the reset output to go

high-impedance have been met, a reset delay timer is

● Main-Battery Low when MBLPD is set

(V

< V

)

initiated before RSO is deasserted (t

).

MON

MONL

RST_O

● Overvoltage (V

> V

)

or

MBATTOVLO

The following bulleted list summarizes all the conditions

required for the MAX77863 to set RSO low and allow

nRST_IO to go high-impedance.

MBATT

V

AVSD

> V

MBATTOVLO

● Thermal Overload (T > T

)

JSHDN

J

● The IC must not be in a global shutdown state. See

the Global Shutdown section for more information.

● Manual Reset

• EN0 low for more than the time programmed by

MRT[2:0] and MREN is set.

● The low-battery monitor must be satisfied (V

>

MON

V

) if LBRSTEN is set. See the Voltage Monitors

MONL

● System Watchdog Timeout

● SHDN Pin

section for more information.

● The 32kHz oscillator must be stable (32K_

OK). See the 32kHz Crystal Oscillator and

Buffered Outputs section for more information.

● PWR_OFF Bit

After a global shutdown occurs, the device may be

powered up normally as long as the main-battery voltage

and the die temperature are within their valid ranges.

Although all regulators are forced off in response to

a global shutdown, the RTC remains powered and

continues to record the calendar.

● The flexible power sequencer (FPS_RSO) must be

satisfied.

● Reset timer has expired (t

).

RST_O

An example configuration that allows nRST_IO to go

high-impedance is:

From any state there are three ways of implementing a

“global shutdown”. The source of the global shutdown

event determines how the global shutdown is implemented

and is described as follows.

● No global shutdown events.

● The main-battery voltage is within the valid region.

● The 32kHz clock is stable.

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The 32kHz oscillator power mode is configured with

PWR_MD_32K[1:0]. When any of these power mode bits

are programmed to 0b01 (PWR_MD_xx[1:0] = 0b01), the

given peripheral are in low-power mode.

Global Shutdown Events with Sequenced

Shutdown and Automatic Wakeup

As shown in Figure 4, three events initiate “sequenced

global shutdown and automatic wakeup.” The events in

this category are associated with faulty system states

where the software may not be working properly but the

system could potentially recover by powering down the

microprocessor, resetting all the “global shutdown” reg-

isters, and then powering up the microprocessor again.

The logic shown in Figure 8 allows EN1 to control the

low-power mode bus (LPM_BUS). With LPM_BUS = 1,

any peripheral (32kHz oscillator (OSC), linear regulator

(LDO), or step-down regulator (SD)) with its power mode

bits programmed to 0b01 (PWR_MD_xx[1:0] = 0b01) are

in low-power mode when LPM_BUS = 1.

Global Shutdown Events with

Sequenced Shutdown to the Oﬀ State

When the IC is asserting its reset output (RSO = 1), the

EN1 signal cannot control the active-low sleep mode

signal (i.e., EN1_LPM is forced low). However, if the IC is

not asserting RSO and the low-power mode during sleep

mask bit (nSLP_LPM_MSK) is clear, the EN1 signal can

affect EN1_LPM and LPM_BUS.

As shown in Figure 4, five events initiate “sequenced

global shutdown to the off state.” With the exception of

PWR_OFF which is a normal system function, the events

in this category are associated with undesirable system

states that may occur in a “normally” functioning product.

Powering down the microprocessor and resetting all the

“global shutdown” registers helps the system resolve

these undesirable events. In general, a wakeup event

such as an on-key press is required to power up the

microprocessor again.

Logic

2

The IC includes an I C interface as well as several other

logic signals. All logic level specifications for the IC are

consolidated within the “Logic” section of the Electrical

Characteristics table.

In the case of a software reset input (SFT_RST) with

SFT_RST_WK = 0, the global shutdown state machine

results in the “default state” with the device off and wait-

ing for a wakeup event. It is possible for the system

software to program a wakeup event based on an RTC

alarm. For example, once the state machine lands in the

“default state” it waits there until the RTC alarm generates

the wakeup event.

Status and Interrupts

The IC contains several status, interrupt, and interrupt

mask registers. Table 2 shows the various register types

within the IC along with a brief description. Figure 2

shows the simplified interrupt, status, and mask logic for

the entire device; see each section for more information.

Status, interrupt, and interrupt mask functions are typi-

cally provided in a block of three registers and register

blocks are typically associated with a single device func-

tion.

Global Shutdown Events with

Immediate Shutdown

As shown in Figure 4, five events initiate an “immedi-

ate shutdown.” The events in this category are associ-

ated with potentially hazardous system events. Powering

down the microprocessor and resetting all the IC regis-

ters helps mitigate any issues that can occur due to these

potentially hazardous system events.

An elegant interrupt structure design minimizes proces-

sor time. This structure allows the applications processor

to quickly find the interrupt of interest. It achieves this

through a top-level interrupt register that sub-divides the

interrupt sources into eight different categories.

Figure 3 provides a guideline for processing the interrupt

information. The following bulleted list reviews the basic

details of this diagram:

Global Low-Power Mode

All step-down regulators, linear regulators, and the 32kHz

oscillator have low-power modes. Each block containing

low-power mode allows for the power mode to be con-

trolled individually or for the power mode to be controlled

globally with the global low-power mode bit (GLBL_LPM),

or GPIO0 when it is set in its alternative mode, or the EN1

hardware input. See Figure 8 for the simplified logic.

● The starting point is that the processor is powered but

it could be in normal operating mode or sleep mode

and its global interrupt is unmasked.

● Upon the interrupt hardware line going low (nIRQ = 0),

the software is switched to the priority decoder which

decides in what order all interrupts to the processor

are serviced and therefore, transfers control to the

PMIC interrupt service routine appropriately.

For the step-down regulators, the power modes are con-

figured with PWR_MD_SDx[1:0]. For the linear regulators,

the power modes are configured with PWR_MD_Lx[1:0].

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● The first task for the processor is to mask the PMIC

interrupt by setting GLBLM (not to be confused with

IRQ_GLBLM).

● If an additional PMIC sub-block interrupt occurs after

the top level interrupt register (IRQTOP) has been

read but prior to the sub-block being serviced, it is

serviced in the routine although it did not cause the

original interrupt.

• This forces nIRQ to go high-impedance in which

case it is pulled high by the external pullup resistor.

• Forcing nIRQ to go high-impedance ensures that

any interrupts that occur within the PMIC while the

PMIC interrupt service routine is being executed

causes a subsequent falling edge on the processor

interrupt line.

• For example, if GPIO0 rising edge caused the

original interrupt but GPIO1 had a rising edge before

the GPIO sub-block’s interrupts were serviced, both

GPIO0 and GPIO1 interrupts would get serviced.

● If an additional PMIC sub-block interrupt occurs after

the top level interrupt register (IRQTOP) has been

read and after the sub-block being serviced, it is

serviced the next time the interrupt service routine is

called.

● The next task is to read the IRQTOP register and

maintain a local copy. Note that IRQTOP is cleared

when read.

● Based on the value of the IRQTOP register, the

service routing branches to individual functions that

service interrupts from each of the PMIC sub-blocks.

• Using the same example, if GPIO1 has a rising

edge subsequent to the GPIO sub-block being ser-

viced, it gets stored in the GPIO block interrupt ﬂag

and in the global interrupt register (IRQTOP) which

then causes an interrupt once GLBLM is unmasked.

• Note that at this point, subsequent interrupts that

occur on the PMIC are masked from reaching the

processor. They are however, not lost since they

are stored on the local interrupt registers and global

interrupt register on the PMIC.

● If a PMIC sub-block that did not cause an interrupt has

an interrupt while the interrupt service routine is being

executed (due to another sub-block), it gets stored

and serviced the next time the routine is called.

● Once all interrupts have been checked and serviced,

the interrupt service routine unmasks the hardware

interrupt line by clearing GLBLM (not to be confused

with IRQ_GLBLM).

• For example, if the service routine was called due to

the GPIO sub-block but the RTC sub-block has an

interrupt while the service routine is being executed,

it gets stored in its local interrupt ﬂag (RTCINT) and

the bit in the top level interrupt register (IRQTOP)

also gets set. This subsequently causes an interrupt

when GLBLM is unmasked after the present inter-

rupt service routine has completed.

• If any interrupts occurred on the PMIC during the

process of servicing the PMIC interrupts, and these

interrupts are unmasked, the nIRQ line now gets

pulled low causing an interrupt on the processor.

The process now repeats.

The above bulleted list reviews the basic details of Figure

3. The following bulleted list is of second-level interrupt

service routine concerns:

Table 2. Register Type Description

REGISTER TYPES

DESCRIPTION

Interrupt registers are read only and provide indications that a particular event has occurred. When an

interrupt event has occurred, the corresponding bit is set in the interrupt register. Each interrupt event has

a corresponding interrupt mask that determines whether an interrupt event aﬀects the hardware interrupt

output. Interrupt registers are cleared when read.

Interrupt

Interrupt mask registers allow for preventing (masking) an interrupt event from aﬀecting the hardware

interrupt output. Note that the interrupt mask settings have no eﬀect on the interrupt registers. If an interrupt

mask is set, then when an interrupt event happens it does not get reported on the hardware interrupt

output, however, that interrupt is still reported in the interrupt register.

Interrupt Mask

Status

Data

Status registers are read only and reﬂect the actual condition of a particular event or input.

Data registers provide information. One example is the RTCs minutes register (RTCMIN).

Conﬁguration registers allow for the adjustment of device parameters.

Conﬁguration

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down condition, and sets the WDT bit in the nonvolatile

event recorder.

System Watchdog Timer

The IC contains a system watchdog timer to ensure

safe and reliable operation. The system watchdog timer

prevents the device from powering a system in the event

that the system controller hangs or otherwise isn’t com-

municating correctly. The default state of the system

watchdog timer enable bit (WDTEN) can be factory

programmed with an OTP bit (OTP_WDTED). To use

the watchdog timer feature, enable the feature by setting

WDTEN. While enabled, the system controller must reset

the system watchdog timer within the timer period (t

for the charger to operate normally. Reset the system

watchdog timer by programming WDTC[1:0] = 0b01. t

is programmable from 2s to 128s with TWD[1:0].

To prevent the system watchdog timer from initiating a

global shutdown event and disabling the IC, a properly

operating processor clears the system watchdog timer

within the timer period programmed by TWD[1:0]. The

system watchdog timer is cleared by setting WDTC[1:0]

= 0b01. See the Global Shutdown section for more infor-

mation.

The system watchdog timer can be set to automatically

clear when the AP enters its sleep or off states. The

device interprets the AP sleep state as FPS1 is being

disabled. The device interprets the off state as FPS1 and

FPS2 being disabled.

)

WD

With WDTEN set, an internal counter is incremented with

the internal oscillator. When the internal counter matches

a value programmed by TWD[1:0], the IC asserts nRST_

IO, powers down all of its regulators with a global shut-

Note that the IC contains both a system watchdog timer

and an I C watchdog timer. See the I C Watchdog Timer

section for more information.

2

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AVSD

Overvoltage

Lockout

V_MBATTOVLO

AVSD_OK must be high for

any step-down regulator to

be on.

AVSDUVLO

To step-down

regulator analog

blocks.

V_MBATTUVLO

AVSD

Undervoltage

Lockout

To RTC based shutdown

event register.

T_J

VCC

Thermal

Overload

T_{JS HDN}

. . . .

Other

Interrupts

Sources

TJALRM2M

RET*

TJALRM2_R

MASK

Thermal

Alarm # 2

100k

T_J140

nIRQ

GPIOA

TJALRM1M

MASK

GLBLM

MASK

TJALRM1_R

Thermal

Alarm # 1

T_J120

IRQ

MBATT

To RTC based shutdown

event register.

To the ON/OFF

controller

Cleared by FPS0

being initiated.

Microprocessor

MBATT_OK

MBATT

Overvoltage

Lockout

V_MBATTOVLO

RSI Wakeup

Generator

WK_RSI

MBATTUVLO

To RTC based shutdown

event register.

V_MBATTUVLO

MBATT

Undervoltage

Lockout

DEBOUNCE

Rising/Falling

t_DBNC

RESET_IN

100k

RSI

To bias circuits,

voltage references,

and timing references

Debounce output during

POR is low.

RESET_IN

GLBLSHDN

nRESET_OUT

nRESET_IN

SFT_RST

nRST_IO

WTCHDG

HRDPO

SHDN

RESET Timer

Falling Edge Delay

(t_{RST_O}

Reset

Button

RSO

nRSO

)

Low-Battery Monitor

MBLPD

GND

MBLSD

Low-Battery Hysteresis

Register (LBHYST)

RET*

MBATTLOW_R

MASK

LBM

OTP_TRSTO[1:0]

MBATTLOW

Low-Battery DAC

Register (LBDAC)

Low-Battery DAC

V_MONL

MON

LBRSTEN

32K_OK

FPS_RSO

*RET= Rising Edge Trigger

Figure 1. Global Resource Logic

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GLOBAL RESOURCES

INTERRUPT LOGIC EXAMPLE

TJALRM1_R

V_IO

100kΩ

nIRQ

MAX77863

TJALARM1

T

J

RISING EDGE LATCH

CLEARED BY

READING INTERRUPT

REGISTER

IRQ

nIRQ

T

J120

TJALRM1_IRQ

GLBLM

TJALRM1M

TJALARM2 (INTERRUPT LOGIC)

TJALRM2_IRQ

IRQ_GLBL

IRQ_GLBLM

MBATTLOW_R (INTERRUPT LOGIC)

MBATTLOW_R_IRQ

STEP-DOWN REGULATORS

STEP-DOWN REGULATOR POK INTERRUPT LOGIC EXAMPLE

POK_SDx

nPOK_SDx

PFI_SDx

V

SDx

GLITCH FILTER

RISING EDGE LATCH

CLEARED BY READING

INTERRUPT REGISTER

t

POKNFSDx

V

POK_SDx

t

SS_SDx

PFIM_SDx

t

DVS_SDx

PFI_SD0_IRQ

SD1 POK (INTERRUPT LOGIC)

SD2 POK (INTERRUPT LOGIC)

SD3 POK (INTERRUPT LOGIC)

PFI_SD1_IRQ

PFI_SD2_IRQ

PFI_SD3_IRQ

IRQ_SD

IRQ_SDM

LINEAR REGULATORS

LINEAR REGULATOR POK INTERRUPT LOGIC EXAMPLE

nPOK_Lx

GLITCH

FILTER

V

RISING EDGE LATCH

Lxx

IRQ_LVL2_Lx

IRQ_MSK_Lx

CLEARED BY

READING INTERRUPT

REGISTER

t

V

POKNFLDOx

POKTHLx

t

SS_Lx

POK_Lx

t

DVS_Lx

PFI_L0_IRQ

PFI_L1_IRQ

PFI_L2_IRQ

PFI_Ln_IRQ

PFI_L9_IRQ

L1 POK (INTERRUPT LOGIC)

L2 POK (INTERRUPT LOGIC)

LN POK (INTERRUPT LOGIC)

L9 POK (INTERRUPT LOGIC)

IRQ_LDO

IRQ_LDOM

IRQ_GPIO

IRQ_GPIOM

GPIO

IRQ_RTC

IRQ_RTCM

RTC

IRQ_32K

IRQ_32KM

32KHz OSCILLATOR

ON/OFF CONTROLLER

IRQ_ONOFF

IRQ_ONOFFM

IRQ_NVER

IRQ_NVERM

NON-VOLATILE EVENT RECORDER

Figure 2. Simplified Interrupt, Status, and Mask Logic

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nIRQ FROM PMIC

GOES LOW

NORMAL/SLEEP

PROCESSOR

OPERATING STATE

INTERRUPT

PRIORITY

DECODER

START ISR FOR PMIC

INTERRUPT

MASK PMIC GLOBAL INTERRUPT BIT

(GLBLM)

READ IRQTOP REGISTER FROM

PMIC AND KEEP LOCAL COPY

YES

READ GLOBAL

INTERRUPTS REGISTER

IS BIT 7 SET?

PROCESS APPROPRIATE

INTERRUPT

NO

READ STEP-DOWN

INTERRUPTS REGISTER

IS BIT 6 SET?

PROCESS APPROPRIATE

INTERRUPT

NO

READ LDO INTERRUPTS

REGISTER

IS BIT 5 SET?

PROCESS APPROPRIATE

INTERRUPT

NO

READ GPIO

INTERRUPTS REGISTER

IS BIT 4 SET?

PROCESS APPROPRIATE

INTERRUPT

NO

READ RTC INTERRUPTS

REGISTER

IS BIT 3 SET?

PROCESS APPROPRIATE

INTERRUPT

NO

READ 32K INTERRUPTS

REGISTER

IS BIT 2 SET?

PROCESS APPROPRIATE

INTERRUPT

NO

READ ON/OFF

INTERRUPTS REGISTER

IS BIT 1 SET?

PROCESS APPROPRIATE

INTERRUPT

NO

UN-MASK PMIC GLOBAL INTERRUPT

BIT (GLBLM)

Figure 3. Interrupt Service Routine Example

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GLOBAL SHUTDOWN EVENTS WITH SEQUENCED

SHUTDOWN AND AUTOMATIC WAKEUP ARE ANY

OF THE FOLLOWING:

ANY STATE

GLOBAL SHUTDOWN EVENTS WITH

SEQUENCED SHUTDOWN TO THE OFF

STATE ARE ANY OF THE FOLLOWING:

GLOBAL SHUTDOWN EVENTS WITH

IMMEDIATE SHUTDOWN TO THE OFF

STATE ARE ANY OF THE FOLLOWING:

•

RSI EVENT (HARDWARE RESET INPUT)

SFT_RST EVENT IF SFT_RST_WK=1

(SOFTWARE RESET INPUT)

•

WATCHDOG TIMER EXPIRE IF WD_RST_WK=1

“MANUAL RESET” EVENT IF OTP_MR=1

•

V

SET

<V

WHEN MBLPD IS

•

V

<V

MON MONL

MBATT MBATTUVLO

(MAIN-BATTERY UNDERVOLTAGE)

SET WAKEUP

(MAIN-BATTERY LOW)

WATCHDOG TIMER EXPIRE IF

WD_RST_WK=0

“MANUAL RESET” EVENT IF

OTP_MR=0

SFT_RST EVENT IF

SFT_RST_WK=0

(SOFTWARE RESET INPUT)

PWR_OFF=1

•

T >T

J

JSHDN

FLAG

•

(THERMAL OVERLOAD)

SHDN INPUT EVENT

•

V

>V

MBATT MBATTOVLO

GS_ST0

START SEQUENCED

GLOBAL SHUTDOWN

GLBLSHDN=0

(MAIN-BATTERY OVERVOLTAGE)

V >V

AVSD MBATTOVLO

(STEP-DOWN INPUT

OVERVOLTAGE)

•

RESET=0

•

ALL OTHER CASES EXCEPT

PWR_OFF=1 & SFT_RST=0

GS_ST1

TURN OFF ALL REGULATORS THAT ARE NOT ASSIGNED TO

FPS0 OR FPS1.

NOTE THAT THIS IS NOT RESET,

IT IS FORCE OFF.

GS_ST10

•

SDx = OFF IF FPSSRCx1=1

LDOx = OFF IF FPSSRCx1=1

TURN OFF ALL REGULATORS IMMEDIATELY

(I.E., NO SEQUENCE SHUTDOWN)

GLBLSHDN=1

RESET=0

GLBLSHDN=1

RESET=1

FPS0 HAS NOT REACHED ITS

8^thPOWER DOWN EVENT.

GS_ST2

INITIATE THE FPS0 AND FPS1 POWER DOWN EVENT.

GLBLSHDN=1

RESET=0

FPS0 HAS REACHED ITS 8^thPOWER DOWN EVENT.

GS_ST3

30ms DELAY

GLBLSHDN=1

RESET=0

ALL OTHER CASES EXCEPT

PWR_OFF=1 & SFT_RST=0

IF WAKEUP FLAG IS SET AND GLOBAL

SHUTDOWN EVENT IS FINISHED

GS_ST4

RESET ALL “GLOBAL SHUTDOWN” REGISTERS

GLBLSHDN=1

RESET=1

GS_ST5

100ms DELAY AND

CLEAR WAKEUP FLASH

GLBLSHDN=0

GS_ST9

PWR_OFF=0

RESET=0

IF WAKEUP FLAG IS CLEAR AND GLOBAL

SHUTDOWN EVENT IS FINISHED

GS_ST6

GENERATE WAKE UP EVENT

GLBLSHDN=0

RESET=0

GS_ST7

AWAKE STATE (i.e. NORMAL)

GLBLSHDN=0

GS_ST8

DEFAULT STATE (i.e. OFF AND WAITING FOR A WAKEUP EVENT)

GLBLSHDN=0

RESET=0

Figure 4. Global Shutdown State Diagram

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SEQUENCED GLOBAL SHUTDOWN CONTROL (LDOx)

SEQUENCED GLOBAL SHUTDOWN CONTROL (SDx)

FPSSRC_Lx1

GLBLSHDN

FPSSRC_SDx1

OFFSDx

OFFLDOx

GLBLSHDN

LDOx

SDx

FPS0

FPS1

FPS2

FPS0

FPS1

FPS2

(LDO0 THROUGH

LDO8)

(SD0 THROUGH

SD3)

RESET

SEQUENCED GLOBAL SHUTDOWN CONTROL (GPIOx)

RESET

GLOBAL

GPIOx

RESOURCES

GLBLSHDN

RSTGPIOx

(GPIO0, GPIO4

THROUGH GPIO7)

RTC

SEQUENCED GLOBAL SHUTDOWN CONTROL (GPIOy)

AMEx

GLBLSHDN

RSTGPIOy

GPIOy

I²C INTERFACE

RESET

(GPIO1, GPIO2,

GPIO3)

FPS0

FPS1

FPS2

ON/OFF

CONTROLLER

AND FLEXIBLE

POWER

RESET

SEQUENCER

RSI

RESET I/O

FPS0

FPS1

FPS2

Figure 5. Simplified Logic for Global Shutdown

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GLOBAL SHUTDOWN EVENT WITH SEQUENCED SHUTDOWN AND AUTOMATIC WAKEUP:

GS_ST1 GS_ST2 GS_ST3

GS_ST4

GS_ST5

GS_ST6

GS_ST7

SFT_RST

SF T_RST_W K = 1

RESET LATCH

(INTERNAL SIGNAL)

t

(1ns)

t

DGSDRSTCLR

DGSD

t

GLBLSHDN

(INTERNAL

SIGNAL)

FPSDON

FPS1

(INTERNAL

SIGNAL)

t

FPSDON

FPS0

(INTERNAL

SIGNAL)

t

DGSD100msA

DGSD30ms

DELAY

(INTERNAL

SIGNAL)

30m s

DGSDRST

100ms

t

RESET

(INTERNAL

SIGNAL)

t

DGSD100msB

WAKE

(INTERNAL

SIGNAL)

t

DGSWK

GLOBAL SHUTDOWN EVENT WITH SEQUENCED SHUTDOW N TO THE OFF STATE:

GS_ST1 GS_ST2 GS_ST3

GS_ST4

GS_ST8

SFT_RST

SF T_RST_W K = 0

RESET LATCH

(INTERNAL

SIGNAL)

t

(1ns)

t

DGSDCLR

DGSD

t

GLBLSHDN

(INTERNAL

SIGNAL)

FPSDON

FPS1

(INTERNAL

SIGNAL)

FPS0

(INTERNAL

SIGNAL)

t

DGSD30ms

DELAY

(INTERNAL

SIGNAL)

30ms

t

DGSDRST

RESET

(INTERNAL

SIGNAL)

WAKE

(INTERNAL

SIGNAL)

Figure 6. Simplified Timing Diagram for Global Shutdown

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GLOBAL SHUTDOWN EVENT WITH IMMEDIATE SHUTDOWN TO THE OFF STATE:

GS_ST4

GS_ST8

SHDN

ACTIVE HIGH

RESET LATCH

(INTERNAL SIGNAL)

t

(1ns)

DGSDCLR

DGSD

t

GLBLSHDN

(INTERNAL SIGNAL)

FPSDON

FPS1

(INTERNAL SIGNAL)

FPS0

(INTERNAL SIGNAL)

DELAY

(INTERNAL SIGNAL)

t

(1ns)

DGSDRSTCLR

DGSD

RESET

(INTERNAL SIGNAL)

WAKE

(INTERNAL SIGNAL)

Figure 7. Simplified Timing Diagram for Global Shutdown

GPIO0 IS MASKED FROM THE

GLOBAL LOW-POWER MODE

CONTROL BUS WITH AME0 = 0

GPIO0

LOGIC

LPM_BUS = 1 → LOW-POWER MODE

LPM_BUS = 0 → NORMAL-POWER MODE

GLBL_LPM

LPM_BUS

EN1

RSO

EN1_LPM

LDOx

(LDO0 to LDO8)

SDx

(SD0 to SD3)

32 kH z

OSCILLATOR

nSLP_LPM_MSK

PWR_MD_Lx[1:0]

PWR_MD_SDx[1:0]

PWR_MD_32K[1:0]

OFF

Figure 8. Simplified Logic for Global Low-Power Mode

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● Dynamically programmable output voltage

Step-Down Regulators

The IC features four ultra-low I step-down regulators

● Programmable output voltage slew rate during

Q

(SD0, SD1, SD2, SD3). Table 1 summarizes the basic

characteristics of the step-down regulators in addition to

the other regulators on the device. Figure 40 shows the

external component values for the step-down regulators.

Figure 2 shows a Simplified Functional Diagram of the

step-down regulators.

dynamic voltage changes.

● Low-power mode Increases light-load efficiency

● Forced PWM operation selectable through serial

interface

● Remote output voltage sensing (SD0, SD1)

● ±1% steady-state accuracy and ±5% transient

In normal operation, these step-down regulators consume

only 16µA of quiescent current except for SD0 which

consumes 32µA. In standby mode, the quiescent current

is reduced to 5µA per step-down regulator, with reduced

load capability (10µA for SD0). Each step-down regulator

can be independently put into standby mode by writing a

bit in a control register.

accuracy (SD0, SD1)

● Power-OK interrupt

● Soft-start into prebiased output

Eﬃciency

The typical efficiencies for the IC step-down regulators

are shown in the Typical Operating Characteristics sec-

tion. Note that the inductors used to get the efficiency

shown are physically small and therefore the ESR is high.

Physically larger inductors achieve efficiencies that are 1

to 3% higher than what is shown.

Each step-down regulator features internal feedback,

minimizing external component count by allowing all

step-down regulator output voltages to be programmed

through the serial interface. A 4.4MHz switching

frequency minimizes the external component size. All

step-down regulators feature dynamic voltage scaling

Step-Down Regulator

Input Voltage Range

2

(DVS) through the I C serial interface. Additionally, all

step-down regulators automatically transition from PFM to

PWM operation (FPWM_SDx = 0). Forced PWM opera-

tion can be independently enabled for each step-down

regulator by setting FPWM_SDx.

All step-down regulators share a single analog power

input (AVSD). Additionally, each step-down regulator has

a dedicated power input that is connected to the source

of its high-side p-channel MOSFET (INy_SDx) as shown

in the Simplified Functional Diagram. All INy_SDx pins

and AVSD must be connected together. For applications

with 1s battery configurations, typically AVSD, INY_SDx,

MBATT, and MON are connected together (Figure 40).

For applications with 2s (or higher) battery configurations,

INy_SDx and AVSD can be connected to an external

SD1 and SD3 switching is interleaved to minimize the

input capacitance requirement. Each phase of SD0 are

also interleaved. SD2 switching is independent of the

other step-down regulators

Features

● 16µA quiescent current in normal mode

step-down regulator as shown in Figure 41

.

(SD1, SD2, SD3)

The valid operating input voltage range for AVSD and

INy_SDx is 2.6V to 5.5V. AVSD undervoltage lockout

(UVLO) and AVSD overvoltage lockout (OVLO) compara-

tors force the MAX77863 step-down regulators off when

the supply voltage (VAVSD) is not within the acceptable

window of operation (2.6V to 5.5V). See Figure 1 and the

Voltage Monitors section for more information.

● 25µA quiescent current in normal mode (SD0)

● 5µA quiescent current in low-power mode

(SD1, SD2, SD3)

● 10µA quiescent current in low-power mode (SD0)

● Four step-down regulators

• SD0: 6.0A continuous, 8.0A peak

• SD1: 3.0A

SD0 is capable of operating across the full AVSD and

INy_SDx range of 2.6V to 5.5V. The peak output current

of 8.0A is guaranteed only for AVSD and INy_SDx greater

than 3.0V. From 2.6V to 3.0V, the rated output current

derates to 6.0A.

• SD2: 2.0A

• SD3: 2.0A

● 100% duty-cycle operation for SD2 and SD3

● No external MOSFETs, synchronous rectifiers, or

current sense resistors are required

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begin again due to a fixed-frequency clock pulse. The

controller’s compensation components and current-sense

Buck Regulator Control Scheme

The step-down converter uses a PWM peak current-mode

control scheme with a high-gain architecture. Peak cur-

rent mode control provides precise control of the inductor

current on a cycle-by-cycle basis and inherent compensa-

tion for supply voltage variation. On-times (MOSFET Q1

on) are started by a fixed-frequency clock and terminated

by a PWM comparator. See Figure 9. When an on-time

ends (starting an off-time) current conducts through the

low-side MOSFET (Q2 on). Shoot-through current from

IN_SDx to PG_SDx is avoided by introducing a brief peri-

od of dead time between switching events when neither

MOSFET is on. Inductor current conducts through Q2’s

intrinsic body diode during dead time. The PWM compar-

ator regulates VOUT by controlling duty cycle. The nega-

tive input of the PWM comparator is a voltage proportional

to the actual output voltage error. The positive input is the

sum of the current-sense signal through MOSFET Q1 and

a slope-compensation ramp. The PWM comparator ends

an on-time when the error voltage becomes less than

the slope-compensated current-sense signal. On-times

circuits are integrated. This reduces the risk of routing

sensitive control signals on the PCB. A high-gain architec-

ture is present in the controller design. The feedback uses

an integrator to eliminate steady-state output voltage error

while the converter is conducting heavy loads.

Step-Down Regulator Power Modes

Step-down regulators and linear regulators have very

similar power mode controls. Each step-down regulator

is independently controlled with PWR_MD_SDx[1:0] and

each linear regulator is independently controlled with

PWR_MD_Lx[1:0] (see the Linear Regulator section for

more information). In addition, to enable and disable con-

trol, each step-down regulator has a special low-power

mode that reduced the quiescent current to 5µA for SD1-

SD2 and 10µA for SD0. In low-power mode, each regula-

tor supports a load of up to 5mA (IMAX_SDx). Remote

output voltage sensing (ROVS) is disabled in low-power

mode and the load regulation performance degrades pro-

portionally with the reduced load current.

IN_SDx

SCL

I²C INTERFACE

SDA

+

Σ

I

LX-PEAK

+

SDx REFERENCE/REMOTE

SENSE

LIM

REGISTERS &

CONTROL

SLOPE COMPENSATION

SOFT-START RAMP

Q1

Q2

S

R

Q

LXx

LOGIC

PWM

gm

OUT/FB

R

C

COMP

LIM

I

LX-VALLEY

POK_SDx

GS

PG_SDx

Figure 9. Buck Control Scheme Diagram

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Several usage options are available for low-power mode.

To force individual regulators to low-power mode, set

PWR_MD_SDx to 0b10. To force a group of regulators

to enter and exit low-power mode in unison, set their

individual PWR_MD_SDx_ bits to 0b10. When set for this

“group and/or dynamic” low-power mode, the low-power

mode is enabled when the global low-power mode signal

is high. The global low-power mode signal is driven by

the GLBL_LPM bit or though GPIO0 (see the Global Low-

Power Mode section for more information).

Soft-Start

The step-down regulators have an OTP programmable

(OTP_SD_SS) soft-start rate of either 25mV/µs or 12.5mV/

µs. The controlled soft-start rate and the step-down

regulator current limit (I

rent to the output capacitor (I

) limit the input inrush cur-

LIMP

). I

= min

INRUSH

(I

LIMP

& C

x dV/dt). Note that the input current on the

OUT

step-down converter is lower than the inrush current to

the output capacitor by the ratio of output to input voltage.

The step-down regulators support starting into a pre-

biased output. For example, if the output capacitor has an

initial voltage of 0.4V when the regulator is enabled, the

regulator gracefully increases the capacitor voltage to the

required target voltage such as 1.2V. This is unlike other

regulators without the start into prebias feature where

they may force the output capacitor voltage to 0V before

the soft-start ramp begins.

When a step-down regulator is configured to be part of

a flexible power sequence (FPSSRC_SDx), the power

mode bits (PWR_MD_SDx) are still used to configure

low-power mode and normal-power mode, but the flexible

power sequencer itself controls weather the regulator

is enabled or disabled. See the Step-Down Regulator

Configuration—Register 1 table for complete information

on PWR_MD_SDx[1:0] bit descriptions.

During the soft-start period, the POK comparator is

masked to prevent false POK interrupts.

SD0 is unique in that it has a hardware enable pin called

EN2. When EN2 is high, SD0 is enabled. See the Step-Down

Regulator Configuration—Register 1 table for PWR_MD_

SDx[1:0] bit descriptions and Table 9 for the full details.

Example 4: What is the inrush current when starting SD0

with an output capacitance (C

) of 100µF?

OUT

● I

= min(I

and C

x dV/dt)

INRUSH

LIMP

OUT

Output Voltage Settings

● SD0 is a two-phase regulator with a high PMOS

current limit (I ) of 4.4A per phase. For

SD2 and SD3 are independently programmable from

0.6V to 3.3875V in 12.5mV increments. SD0 is program-

mable from 0.6V to 1.4V in 12.5mV increments. SD1 is

programmable from 0.6V to 1.55V in 12.5mV increments.

The main target voltage registers are programmed with

VSDx[7:0]. The DVS registers for SD0 and SD1 are pro-

grammed with VDVSSDx[7:0].

LIMPP_HIGH0

I

in the above equation we use 2 x 4.4A = 8.8A.

LIMP

● SD0 has a typical soft-start rate (dV/dt_SS_SD0) of

25mV/µs when OTP_SD_SS = 1. For dV/dt in the

above equation we use 25mV/µs.

● I

= min (8.8A & 100µF x 25mV/µs)

= min (8.8A and 2.5A)

= 2.5A

INRUSH

Output Current

The output current rating of each step-down regulator are

slightly conservative numbers based on the typical appli-

cation for the devices:

Example 5: What is the inrush current when starting SD1

with an output capacitance (C ) of 20µF?

OUT

● SD0: 6.0A continous, 8.0A peak

● SD1: 3.0A

● I

= min (I

and C

x dV/dt)

INRUSH

LIMP

OUT

● SD1 is a single-phase regulator with a high PMOS

current limit (I ) of 3.75A per phase. For

● SD2: 2.0A

LIMPP_HIGH1

in the above equation we use 3.75A.

I

LIMP

● SD3: 2.0A

● SD1 has a typical soft-start rate (dV/dt_SS_SD1) of

25mV/µs when OTP_SD_SS = 1. For dV/dt in the

above equation we use 25mV/µs.

These output current ratings vary with output voltage set-

ting, inductor, switching frequency, and device current limits.

● I

= min (3.75A and 20µF x 25mV/µs)

= min (3.75A and 0.5A)

= 0.5A

INRUSH

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Example 6: What is the inrush current when starting SD3

with an output capacitance (C ) of 200µF?

During a DVS transition, the regulators output current

increases by C x dV/dt. In the event that the load

OUT

current plus the additional current imposed by the DVS

transition reach the regulator’s current limit, the current

limit is enforced. When the current limit is enforced, the

advertised DVS transition rate (dV/dt) does not occur.

● I

= min (I

and C

x dV/dt)

INRUSH

LIMP

OUT

● SD3 is a single-phase regulator with a typical PMOS

current limit (I ) of 1.8A per phase. For I in

LIMPP3

LIMP

the above equation we use 1.8A.

The POK comparator is masked to prevent false POK

interrupts during the DVS period.

● SD3 has a typical soft-start rate (dV/dt_SS_SD3)

of 25mV/µs with OTP_SD_SS = 1. For dV/dt in the

above equation we use 25mV/µs.

Remote Output Voltage Sensing (ROVS)

SD0 and SD1 feature remote output voltage sensing

(ROVS) for improved output voltage accuracy. The SNSN

and SNSP inputs connect directly across the load, with

the SNSN pin connected to a quiet analog ground near

the load, and SNSP connected directly to the load’s

power input. The ROVS can be independently disabled

through software order to reduce quiescent current

consumption (ROVS_EN_SDx). When SD0 or SD1 is

placed in low-power mode, the ROVS is automatically

disabled. Although the ROVS is automatically disabled,

the ROVS_EN_SDx bits are not automatically cleared.

If ROVS_EN_SDx is set when SDx enters normal-power

mode, the ROVS feature is automatically re-enabled.

● I

= min (3.0A and 200µF x 25mV/µs)

= min (3.0A and 5.0A)

= 3.0A

INRUSH

Dynamic Voltage Scaling

All step-down regulators feature dynamic voltage scaling

(DVS). DVS allows the system controller to issue a new

output voltage request to a regulator without managing

the output voltage slew rate of that regulator. In other

words, the system controller may change a regulator out-

put voltage from 0.8V to 1.1V by writing the target voltage

register to 1.1V. The DVS function then ramps the output

voltage in a controlled manner to the new target voltage.

Out-of-Phase Switching

DVS for all step-down regulators is achieved through the

I C interface. Additionally, GPIO5 can control DVS for

2

The IC has five step-down converter power stages.

Enabling the high-side switches of each power stages

on alternate clock edges (i.e., out-of-phase) minimizes

input current ripple, thus reducing the input capacitance

required. Table 3 shows how the IC step-down converter

power stages are assigned to alternate phases of the

step-down converter’s master clock.

SD0. Similarly, GPIO6 can control DVS for SD1. To control

DVS for SD0 or SD1 through GPIO5 or GPIO6, the GPIO

must be set in its alternative mode (AME5 = 1 or AME6

= 1). When in their alternative mode, DIRx determines

whether the GPIO input is active high or active low. With

the GPIO input active, the step-down regulator’s target

voltage is set by VDVSSDx. With the GPIO input inactive,

the step-down regulator’s target voltage is set by VSDx.

SKIP/FPWM Operation

In the normal IC operating state, all step-down regulators

automatically transition between skip mode and fixed-

frequency operation as load current varies (i.e., skip

mode with low load current and fixed-frequency with

high load current). For operating modes where lowest

output ripple is required at low load currents, forced PWM

switching behavior can be independently enabled by

setting FPWM_SDx. Note that forcing PWM behavior at

light loads decreases the regulator efficiency.

The rising and falling slew-rate during DVS is adjustable

with SR_SDx[1:0] and nFSRAD_SDx. The typical use

case for SR_SDx[1:0] and nFSRAD_SDx bits is to set

them to the desired value during system initialization and

then leave them that way during the normal operation

of the system. These bits should not be changed while

their associated step-down regulators are in the middle

of an output voltage slew-rate event. When determining

the ideal settings for these bits, consider the required

transition time, the output capacitance on the regulator,

the regulator output current needed to slew that output

capacitance at the designated rate, and required input

current. In general, larger output capacitances should use

slower transition rates.

Table 3. Out-of-Phase Switching Details

HIGH-SIDE SWITCH ENABLE SIGNAL

RISING EDGE

FALLING EDGE

SD0A, SD1

SD2, SD3, SD0B

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Power-OK Comparators for

Step-Down Regulators

Input Capacitor Selection

The input capacitor in a step-down converter reduces

Each step-down regulator includes a power-OK (POK)

comparator. The POK comparator signals (nPOK_SDx)

indicate when each output has lost regulation (i.e., the

current peaks drawn from the power source and reduces

switching noise in the controller. The impedance of the

input capacitor at the switching frequency must be less

than that of the source impedance of the supply so that

high-frequency switching currents do not pass through

the input source.

output voltage is below V

). The POK signal has

POK_SDx

a noise immunity filter (t ). The POK comparator

POKNFSD

is also masked during the soft-start time and during the

DVS time to prevent false POK interrupts.

The step-down regulator power inputs are critical dis-

continuous current paths that require careful bypassing.

In the PCB layout, place the step-down regulator input

bypass capacitors as close as possible to each pair of

switching regulator power input pins (IN_SDx to PG_SDx)

on the same side of the PCB as the IC (i.e., don’t make

input capacitor connections through vias).

When any of the POK signals (nPOK_Lx) go high, a

maskable interrupt is generated. POK is the only interrupt

available for the IC step-down regulators. The block level

step-down interrupt register is IRQSD and the top level

LDO interrupt is IRQ_SD. See the Status and Interrupts

section for more information.

The input capacitor must meet the input ripple cur-

rent requirement imposed by the step-down converter.

Ceramic capacitors are preferred due to their low ESR

and resilience to power-up surge currents. Choose the

input capacitor so that its temperature rise due to input

ripple current does not exceed about +10°C. For a step-

down DC-DC converter, the maximum input ripple current

is half of the output current. This maximum input ripple

current occurs when the step-down converter operates at

Inductor Selection

Choose the step-down regulator inductance to be 1.0μH

for all step-down regulators as shown in Figure 40 and

Figure 41. The IC works well with physically small induc-

tors, however, care must be taken when choosing the

proper inductor saturation current and equivalent series

resistance (ESR).

The minimum recommended saturation current require-

ment is 600mA, however, typical applications require-

larger saturation current to support their loads. The

peak-to-peak inductor ripple current (I ) during PWM

operation is calculated as shown in Equation 1. The

50% duty factor (V = 2 x V

).

IN

OUT

Bypass each step-down regulator input with a 4.7μF or

2.2μF ceramic capacitor from IN_SDx to PG_SDx as

shown in Figure 40 and Figure 41. Use capacitors that

maintain their capacitance over temperature and DC

bias. Ceramic capacitors with an X7R or X5R tempera-

ture characteristic generally perform well. The capacitor

voltage rating should be 6.3V or greater.

P-P

inductor’s peak ripple current (I

) due to the load

L-PEAK

(I

) is shown in Equation 2. A well-designed system

LOAD

need only have an inductor saturation current of I

.

L-PEAK

Note that is some cases, the maximum expected system

current can occur based on the step-down regulator

startup, dynamic voltage slew-rate, or output short circuit.

Output Capacitor Selection

Equation 1. Inductor Peak-to-Peak Ripple Current

The step-down regulator output capacitance keeps output

ripple small and ensures control loop stability. The output

capacitor must have low impedance at the switching

frequency. Ceramic capacitors are recommended due

to their low equivalent series resistance (ESR) and good

frequency response impedance. The required output

capacitance for each of the IC step-down regulators are

shown in their respective Electrical Characteristics tables

(COSDx). The typical value shown corresponds to the

capacitors nominal output capacitance. The minimum

value shown corresponds to the output capacitance that

is required for stability.

V

( V − V

)

OUT

V

IN

I

=

P−P

× f

×L

SW

IN

Equation 2. Inductor Peak Ripple Current

I

P−P

2

I

= I

+

LOAD

L−PEAK

Reduce the inductor’s series resistance for maximum

efficiency. For designs that require a small solution size,

the step-down regulators tolerate relatively high series

resistance (~100mΩ). Using an inductor with high series

resistance reduces the overall efficiency of the buck and

causes additional thermal dissipation.

As the case sizes of ceramic surface-mount capacitors

decrease, their capacitance vs. DC bias voltage char-

acteristic becomes poor. Due to this characteristic, it is

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possible for 0805 capacitors to perform well while 0603

capacitors of the same value might not. The nominal out-

put capacitor requirement for the IC is shown in the “typi-

cal” value of the Electrical Characteristics table; however,

after their DC bias voltage derating, the output capaci-

tance must have at least the “minimum” value shown in

the Electrical Characteristics table.

Linear Regulator

The IC has nine linear regulators (LDOs).

Table 1 summarizes the basic characteristics of the linear

regulators in addition to the other regulators on the device.

Figure 40 shows the external component values for the

linear regulators. Figure 2 shows a Simplified Functional

Diagram of the entire device including the linear regula-

tors. Figure 10 shows a more detailed functional diagram

of just linear regulators. The nine LDOs of the MAX77863

are derived of five basic topologies as shown in Table 5.

In applications where the parasitic impedance between

the step-down regulator’s local output capacitance and its

point-of-load (POL) input capacitor is small (i.e., <10mΩ),

the POL’s input capacitor contributes to the step-down

regulator’s stability. This means that with respect to SD2’s

output capacitor, it is possible to use one local 10µF

output capacitor and one 10µF POL input capacitor

to satisfy the typical 20µF requirement for SD2 output

capacitance.

The four NMOS regulators are capless designs that are

stable with or without an output decoupling capacitor.

Additionally, the PMOS regulators have adjustable com-

pensation that allows for the use of remote output capaci-

tors.

All regulators can be operated in low-power mode, where

the no load quiescent current drops to 1.5µA. In low-pow-

er mode, each output supports a maximum load of 5mA.

Active-Discharge Resistors

Each step-down regulator has an active-discharge resis-

tor feature that can be enabled/disabled with nADE_

SDx_. Enabling the active discharge feature helps ensure

a complete and timely power down of all system peripher-

als. The default condition of the active-discharge resistor

All regulators have an output voltage power-OK interrupt

signal that is integrated into the IC interrupt architecture.

Features

● Nine Linear Regulators

feature is enabled such that whenever V

is below

MBATT

V

all regulators are disabled with their active-

MBATTUVLO

● General Performance

discharge resistors turned on. When V

1.0V, the NMOS transistors that control the active-dis-

charge resistors lose their gate drive and become open.

is less than

MBATT

• ±3% Output Accuracy Over Load/Line/Temperature

• 50mV Drop-Out at Full Load

• 70dB PSRR at 10kHz

• 1.5µA Low-Power Mode

SD3 Default Voltage (D_SD3)

• Short-Circuit and Thermal-Overload Protection

• Dynamically Programmable Output Voltage

• Power-OK Interrupt

• Programmable Soft-Start Rate: 100mV/µs or

5mV/µs

The default output voltage of SD3 is pin programmable

with the D_SD3 tri-level logic input. As shown in Table

4, it programs either 1.2V, 1.35V, or a factory OTP

setting. The logic level of D_SD3 is latched each time

the MBATT voltage rises above the main-battery under-

• Soft-Start into Pre-Biased Output

voltage-lockout threshold (V

> V

). The

MBATTUVLO

MBATT

time required for the D_SD3 to latch in the correct logic

state is t . Changes to D_SD3 after the logic

level is latched have no effect.

● Four N-Channel Regulators (LDO0/1/7/8)

DSD3LTCH

• 0.8V to 5.5V Input Range

• 29µA Quiescent Supply Current

• No Output Capacitor Required in Normal Operating

Mode (Cap Required for Low-Power Mode)

Table 4. D_SD3 Logic

D_SD3 LOGIC LEVEL

MBATT (logic high)

Unconnected

SD3 DEFAULT VOLTAGE

● Five Standard P-Channel Regulators (LDO2/3/4/5/6)

• 1.7V to 5.5V Input Range

• 20µA Quiescent Supply Current

• Remote Capacitor Design with Register Adjustable

Compensation to Optimize Transient Performance

1.35V

Factory OTP setting such as 1.5V

1.2V

GND (logic low)

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Basic LDO Topologies

The nine LDOs of the IC are derived of five basic topolo-

gies as shown in Table 5.

IN_LDO2

LOCAL

LDO

BIAS

GLOBAL

BIAS

LDO2

150mA

PMOS

The PMOS regulators (PDRVx) operate and draw power

from their power inputs (IN_LDOxx), which have a

OUT_LDO2

minimum operating supply voltage of 1.7V (V

).

IN_LDOx

The control registers and some input circuitry operate

from the main system supply (MBATT) and hold their

IN_LDO0-1

OUT_LDO0

MBATT

contents when the regulator input voltage (V

drops to 0V.

)

IN_LDOx

LDO0

150mA

NMOS

The NMOS regulators (NDRVx) gate drive operates from

the main system supply (MBATT), while the load current

is provided by the regulator input (IN_LDOxx). The input

MBATT

voltage (V

) for the NMOS regulators extends

IN_LDOx

LDO1

150mA

NMOS

OUT_LDO1

FPS

down to 0.8V. To provide adequate gate drive for the

NMOS output device, the NMOS output voltage should

be more than 1.5V lower than the main system supply

IN_LDO3-5

OUT_LDO3

voltage (V

). The control registers are also powered

MBATT

from MBATT.

LDO3

300mA

PMOS

NMOS regulators work into dropout with the V

to

IN_LDOx

V

voltage determined by I

x R

where

OUT_LDOx

LOAD

DO

R

is the dropout resistance (typically 200mΩ). As drop-

DO

out voltage decreases (by reducing load) below 0.3V, the

PSRR and load regulation degrades.

LDO5

150mA

PMOS

OUT_LDO5

All PMOS regulators are compensated at their output

and require a remote output capacitance large enough

to prevent oscillation, as specified in the Electrical

IN_LDO4-6

OUT_LDO4

Characteristics table (C

). The NMOS regulators are

OUTx

LDO4

150mA

PMOS

internally compensated, but an additional output capacitor

can be added to improve immunity to high-frequency

noise and allow stable low-power mode operation.

LDO6

150mA

PMOS

Table 5. Basic LDO Topologies

OUT_LDO6

NAME

DESCRIPTION

LDO

Power device: PMOS

Output current: 150mA

LDO2, LDO4, LDO5,

LDO6

IN_LDO7-8

OUT_LDO7

PDRV1

MBATT

LDO7

450mA

NMOS

Power device: PMOS

Output current: 300mA

PDRV2

NDRV1

NDRV2

NDRV3

LDO3

Power device: NMOS

Output current: 150mA

LDO0, LDO1

LDO8

MBATT

Power device: NMOS

Output current: 300mA

LDO8

300mA

NMOS

OUT_LDO8

I²C and IRQ

Power device: NMOS

Output current: 450mA

LDO7

Figure 10. Linear Regulator Functional Diagram

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the regulator gracefully increases the capacitor voltage

to the required target voltage such as 1.2V. This is unlike

other regulators without the start into prebias feature

where they can force the output capacitor voltage to 0V

before the soft-start ramp begins.

LDO Power Modes

Linear regulators and step-down regulators have very

similar power mode controls. Each linear regulator is

independently controlled with PWR_MD_Lx[1:0] and

each step-down regulator is independently controlled with

PWR_MD_SDx[1:0] (see the Dynamic Voltage Scaling

section for more information about step-down regulators).

In addition, to enable and disable control each linear

regulator has a special low-power mode that reduced

the quiescent current to 1.5µA. In low-power mode, each

During a soft-start event or a DVS transition, the regula-

tors output current increases by C

x dV/dt. In the

OUT

event that the load current, plus the additional current

imposed by the soft-start or DVS transition, reach the

regulator’s current limit, the current limit is enforced.

When the current limit is enforced, the advertised transi-

tion rate (dV/dt) does not occur.

regulator supports a load of up to 5mA (I

load regulation performance degrades proportionally with

the reduced load current.

). The

MAXxx

Power-OK Comparators for

Linear Regulators

Each linear regulator includes a power-OK (POK) com-

parator. The POK comparator signals (POK_Lx) indicate

when each output has lost regulation (i.e., the output

Several usage options are available for low-power mode.

To force individual regulators to low-power mode, set

PWR_MD_Lx to 0b10. To force a group of regulators

to enter and exit low-power mode in unison, set their

individual PWR_MD_Lx_ bits to 0b10. When set for this

“group and/or dynamic” low-power mode, the low-power

mode is enabled when the global low-power mode signal

is high. The global low-power mode signal is driven by

the GLBL_LPM bit or through a GPIO0 (see the Global

Low-Power Mode section for more information).

voltage is below V

). The POK signal has a 25µs

POKTHL

noise immunity filter (t

).

POKNFLDO

When any of the POK signals (POK_Lx) go low, a mask-

able interrupt is generated. POK is the only interrupt

available for the MAX77863 LDOs. The block level LDO

interrupt register is IRQ_LVL2_Lx and the top level LDO

interrupt is IRQ_LDO. See the Status and Interrupts

section for more information.

When a linear regulator is configured to be part of a flex-

ible power sequence (FPSSRC_Lx), the power mode

bits (PWR_MD_Lx) are still used to configure low-power

mode and normal-power mode, but the flexible power

sequencer itself controls weather the regulator is enabled

or disabled. See the PWR_MD_Lx[1:0] bit descriptions

for complete information.

Active-Discharge Resistors

Each linear regulator has an active-discharge resistor

feature that can be enabled/disabled with ADE_Lx_.

Enabling the active discharge feature helps ensure a

complete and timely power down of all system peripher-

als. The default condition of the active-discharge resistor

Soft-Start and

Dynamic Voltage Scaling

feature is enabled such that whenever V

is below

MBATT

The linear regulators have a programmable soft-start rate.

When a linear regulator is enabled, the output voltage

ramps to its final voltage at a slew rate of either 5mV/µs

or 100mV/µs, depending on the state of the SS_Lx bit.

The 5mV/µs ramp rate limits the input inrush current to

around 10mA on a 300mA regulator with a 2.2µF output

capacitor and no load. The 100mV/µs ramp rate results

in a 200mA inrush current on a 300mA regulator with a

2.2µF output capacitor and no load, but achieves regula-

tion within 50µs. The soft-start ramp rate is also the rate of

change at the output when changing dynamically between

two output voltages while enabled (dynamic voltage scal-

ing: DVS).

V

all regulators are disabled with their active-

MBATTUVLO

discharge resistors turned on. When V

1.0V, the NMOS transistors that control the active-dis-

charge resistors lose their gate drive and become open.

is less than

MBATT

Overvoltage Clamp

Each LDO has an overvoltage clamp that allows it to

sink current when the output voltage is above its target

voltage. This overvoltage clamp for a given LDO is

disabled when that LDO is in low-power mode. If an

LDO is in normal-power mode, then the overvoltage

clamp is enabled/disabled with OVCLMP_EN_Lx (default

enabled). The following bulleted list briefly describes

three typical application scenarios that pertain to the

overvoltage clamp.

The LDO soft-start circuitry supports starting into a

prebiased output. For example, if the output capacitor has

an initial voltage of 0.4V when the regulator is enabled,

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Typical application scenarios for the overvoltage clamp:

designing the PCB and placing the output capacitor. The

default compensation is factory programmable; addition-

ally, the compensation is register adjustable when the

LDO is off. For each LDOs output capacitor recommen-

● LDOs Load Leaking Current into the LDOs Output:

Some LDO loads leak current into an LDO output

during certain operating modes. This is typically seen

with microprocessor loads. For example, a micropro-

cessor with 3.3V, 2.5V, 1.8V, and 1.0V supply rails

is running in standby mode. In this mode, the higher

voltage rails can leak currents of several milliamps

into the lower voltage rails. If the 1.0V rail is supplied

by an LDO, the LDO output voltage rises based on the

amount of leakage current. With the LDO overvoltage

clamp enabled, when the output voltage rises above

its target regulation voltage, the overvoltage clamp

sinks current from the output capacitor, which brings

the output voltage back within regulation.

dation (C

) see Table 1.

OUTx

In many LDO designs, there is little-to-no flexibility in

the physical placement of the output capacitor on the

PCB. However, the LDO implementation within the IC

provides adjustable compensation for the P-channel

LDOs. This adjustable compensation allows flexibility

in the placement of the output capacitor on the PCB,

however, as the output capacitor is placed farther from

the device, slower compensation values are required

to maintain stability; these slower compensation values

decrease performances.

● Negative Load Transient to 0A: When the LDO load

current quickly ramps to 0A (i.e., 300mA to 0A load

transient with 1µs transition time), the output voltage

can overshoot (i.e., sore). Since the LDO cannot turn

off its pass device with an intently fast load transition,

the LDO output voltage overshoots. In this instance,

when the output voltage sores above target regulation

voltage, the overvoltage clamp sinks current from the

output capacitor, which brings the output voltage back

within regulation.

For optimum p-channel LDO performance, place the

output capacitor as close to the LDO output as possible

and program COMP_Lx = 0b00. In situations where the

full LDO performance is not required, the output capacitor

can be place farther away from the LDO output with slow-

er compensation values. This option becomes especially

useful when the LDO output capacitor can be eliminated

and the load’s local input capacitor becomes the only

capacitance on the LDO output node. See the COMP_Lx

bit descriptions for more information.

● Negative Dynamic Voltage Transition: When the LDO

output target voltage is decreased (i.e., 1.2V to 0.8V)

when the system loading is light, the energy in the

output capacitor tends to hold the output voltage up.

When the output voltage is above its target regulation

voltage, the overvoltage clamp sinks current from the

output capacitor, which brings the output voltage back

within regulation.

Warning: The COMP_Lx bits should only be changed

when the LDO is disabled. If the compensation bits are

changed when the LDO is enabled, the output voltage

glitches as the compensation changes.

N-Channel Linear Regulator

Output Capacitor

N-channel LDOs (NDRVx as shown in Table 5) techni-

cally do not require any output capacitor to maintain sta-

ble output voltage regulation if they are in normal mode

(i.e., they can be capless). However, an n-channel LDO

does require an output capacitor to maintain stable output

voltage regulation in low-power mode. In either mode

(normal or low-power) the LDO performs best with an

Output Capacitor Selection

The output capacitor selection differs slightly between a

P-channel and an N-channel LDO.

P-Channel Linear Regulator

Output Capacitor

P-channel LDOs (PDRx as shown in Table 5) require an

output capacitor to maintain stable output voltage regula-

tion. Adjustable compensation allows for flexibility when

output capacitor (C

) as recommended in Table 1.

OUTx

Note that the COMP_Lx[1:0] bits for n-channel LDOs

must be set to 0b00.

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programming matrix. Each GPIO is programmable to

operate in a special alternative mode as shown in Table 6.

BIAS

A small section of bias circuitry is required to be on

when any of the LDOs are enabled. Figure 11 shows

that any LDO enable signal OR the L_B_EN enables the

LDO bias circuits. In addition, whenever the LDO bias is

enabled, the global bias for the IC is also enabled. The

Features

● Eight GPIO

● Two Input Power Sources

• 4 GPIOs per input

LDO bias circuitry takes t

to turn on. If the LDO bias

LBIAS

• Input Voltage Range from 1.7V to 5.5V

circuit is off and an LDO is enabled, the total time before

the output starts slewing up is t + t . If the LDO

bias is on and an LDO is enabled, the total time before

LBIAS

LON

● GPI

• GPI to Global Low-Power Mode Control

the output starts slewing is t

.

LON

• GPI to SD0 DVS Signal

• GPI to SD1 DVS Signal

• GPI to Interrupt

If the sequencing of a group of regulators is particularly

important, it may be desirable to force the LDO bias to

be on with the L_B_EN bit to ensure that LDOs enable in

a consistent manner with the shortest latency. Note that

whenever L_B_EN is set, the global bias circuits and LDO

bias circuits are enabled. The combined bias circuitry

• GPI to Flexible Power Sequencer

• Flexible Edge Trigger Support

• Selectable Debounce Time

• Optional Pullup/Pulldown

current is I

. To ensure that the system always

QBIAS

operates with the lowest quiescent current possible, it is a

good idea to clear L_B_EN when it is not needed.

● GPO

General Purpose Input/Output (GPIO)

• Push-Pull

• Open-Drain

• Buﬀered Reference Output

• GPO to 32kHz Output Option

• 12mA Sink Current Allows for LED Drive

The IC has eight GPIO channels. The Simplified

Functional Diagram shows a simplified functional diagram

of the GPIO functional block. Figure 12 shows a detailed

functional diagram of the GPIOs. Table 7 is the GPIO

ENABLE FOR ANY

OTHER FUNCTION

PWR_MD0_L0

PWR_MD1_L0

GLOBAL

EN

BIAS

PWR_MD0_L1

PWR_MD1_L1

L_B_EN

PWR_MD0_L7

PWR_MD1_L7

LDO

BIAS

EN

PWR_MD0_L8

PWR_MD1_L8

Figure 11. LDO Bias Enable Circuitry

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GPIO_INx

PUEx

DVS_SD0

DVS_SD1

IRQ

GPIO

CONTROL

R_PU

PPDRVx

FPS

LPM

DBNCx

REFE_IRQx

EDGEx

RET

I²C

FET*

GPIOx

RESET

DIx

*DB

DIRx

DOx

LOGIC

R_PD

PDEx

DGND

ABUF_EN

GPIO_INx

REF

*DB = DEBOUNCE

RET = RISING EDGE TRIGGER

FET = FALLING EDGE

TRIGGER

Figure 12. GPIO Simplified Block Diagram

See the “GPIOx GPI” section of Table 7 for the full details

of how to program a GPI.

GPO

When configured as a general-purpose output (GPO), the

GPO is programmable to be push-pull or open-drain. See

the “GPIOx GPO” section of Table 7 for the full details of

how to program a GPO.

GPI Interrupts

The GPI edge(s) that triggers interrupts are selectable

with REFE_IRQx. When a GPI interrupt is enabled and

the selected edge(s) are detected, EDGEx is set in the

IRQ_LVL2_GPIO register and IRQ_GPIO is set in the

top-level interrupt register. If the top-level interrupt mask

is cleared (IRQ_GPIOM), the external interrupt signal

nIRQ is asserted.

GPI

When configured as a general-purpose input (GPI), the

GPI is programmable to have either a high-impedance,

100kΩ pulldown, or 100kΩ pullup. Additionally, interrupt

inputs with programmable debounce timers are available.

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Alternate Mode

Table 6. Alternate Modes for GPIOs

In addition to the GPO and GPI configurations, each

GPIO has an alternate mode as shown in Table 7 and

AME_GPIO: Alternate Mode Enable GPIO Configuration

Register register description.

GPIOx

ALTERNATE MODES

Low-power mode control input

GPIO0

Active-high, open-drain,

ﬂexible power sequencer output

GPIO1

GPIO2

GPIO3

When a GPIO is in an alternate mode the device may

internally force the direction (i.e., output or input) and or

logic level of the GPIO. However other options such as

debounce times and rising/falling edge triggered interrupt

settings are still valid in alternate mode. See the register

descriptions and “alternative mode” sections of the Table 7

for the full details of how to program an alternative mode.

Active-high, open-drain,

ﬂexible power sequencer output

Active-high, open-drain,

ﬂexible power sequencer output

GPIO4

GPIO5

GPIO6

32kHz output (32K_OUT1)

When GPIO7 is an alternative mode it is a 1.25V refer-

ence output. As a reference output, the GPIO7 output

drivers are high-z, the input buffer is disabled to prevent

leakage, and the interrupt feature is disabled. It is recom-

mended that user disable the pullup and pulldown resis-

tors for GPIO7 when it operates in alternate mode. Note

that when using GPIO7 as a reference output, minimize

the capacitance at this node. The maximum acceptable

capacitance is 0.1µF.

SD0 dynamic voltage scaling input

SD1 dynamic voltage scaling input

Reference output 1.25V buﬀered reference

output

GPIO7

Table 7. GPIO Programming Matrix

GPIOx GPI

Comment

DBNCx[1:0]

REFE_IRQx[1:0]

Interrupt options

DOx

0

DIx

DIRx

PPDRVx

0

PUEx

0

PDEx

0

AMEx

0

Debounce

times

Input logic

level

GPI

1 = GP1

GPI with Internal

Pullup

Debounce

times

Input logic

level

Interrupt options

0

1

1 = GP1

0

1

0

1

0

GPI with Internal

Pulldown

Debounce

times

Input logic

level

GPIOx GPO

Output

logic

level

1-push-

pull

GPO Push-Pull

0

0 = GPO

0

Output

logic

level

0-open-

drain

GPO Open-Drain

GPIO0 ALTERNATIVE MODE LOW-POWER MODE CONTROL INPUT

Comment

DENC0[1:0]

REFE_IRQ0[1:0]

DO0

DI0

DIR0

PPDRV0 PUE0

PDE0

0

AME0

1

GPI1 Low-Power

Mode Input,

Low-Power Mode

Debounce

times

0 =

active-low

Interrupt options

0

GPI1 Low-Power

Mode Input, Low-

Power Mode,

Debounce

times

0 =

active-low

Interrupt options

0

1

0

1

Internal Pullup

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Table 7. GPIO Programming Matrix (continued)

GPIO0 ALTERNATIVE MODE LOW-POWER MODE CONTROL INPUT (continued)

GPI1 Low-Power

Mode Input,

Normal-Power

Mode

Debounce

times

0 =

active-low

Interrupt options

0

1

0

1

0

1

0

1

GPI1 Low-Power

Mode Input,

Normal-Power

Mode, Internal

Pullup

Debounce

times

0 =

active-low

GPI1 Low-Power

Mode Input,

Normal-Power

Mode

1 =

active-

high

Debounce

times

GPI1 Low-Power

Mode Input,

Normal-Power

Mode, Internal

Pullup

1 =

active-

high

Debounce

times

GPI1 Low-Power

Mode Input,

Low-Power Mode

1 =

active-

high

Debounce

times

Interrupt options

0

1

0

1

0

1

GPI1 Low-Power

Mode Input,

Low-Power Mode,

Internal Pullup

1 =

active-

high

Debounce

times

GPIO1/2/3 ALTERNATIVE MODE ACTIVE-HIGH FLEXIBLE POWER SEQUENCER OUTPUT

Comment

DENCx[1:0]

REFE_IRQx[1:0]

DOx

DIx

DIRx

PPDRVx

PUEx

0

PDEx

0

AMEx

1

GPO Flexible

Power Sequencer

Output, Push-Pull

1 =

push-

pull

Set by

FPS

0

GPO Flexible

Power Sequencer

Output, Open-Drain

0 =

open-

drain

Set by

FPS

0

1

GPIO4 ALTERNATIVE MODE 32kHz OUTPUT (32K_OUT1)

Comment

DBNC4[1:0]

REFE_IRQ4[1:0]

DO4

DI4

0

DIR4

0

PPDRV4 PUE4

1 =

PDE4

0

AME4

1

GPO 32kHz

Output, Push-Pull

Set by

XIN

0

push-

pull

0

GPO 32kHz

Output,

Open-Drain

0 =

open-

drain

Set by

XIN

0

1

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Table 7. GPIO Programming Matrix (continued)

GPIO5 ALTERNATIVE MODE SD0 DYNAMIC VOLTAGE SCALING INPUT

Comment

DBNC5[1:0]

REFE_IRQ5[1:0]

Interrupt options

DO5

0

DI5

DIR5

PPDRV5 PUE5

PDE5

0

AME5

1

GPI SD0 DVS

Input, VSD0 =

VDVSSD0

Debounce

times

0 =

active-low

0

1

0

1

0

1

0

1

GPI SD0 DVS

Input, VSD0

= VDVSSD0,

Internal Pullup

Debounce

times

0 =

active-low

Interrupt options

0

1

0

1

0

1

GPI SD0 DVS

Input, VSD0 =

VSD0

Debounce

times

0 =

active-low

GPI SD0 DVS

Input, VSD0 =

VSD0, Internal

Pullup

Debounce

times

0 =

active-low

GPI SD0 DVS

Input, VSD0 =

VSD0

1 =

active-

high

Debounce

times

GPI SD0 DVS

Input, VSD0 =

VSD0, Internal

Pullup

1 =

active-

high

Debounce

times

GPI SD0 DVS

Input, VSD0 =

VDVSSD0

1 =

active-

high

Debounce

times

GPI SD0 DVS

Input, VSD0

= VDVSSD0,

Internal Pullup

1 =

active-

high

Debounce

times

GPIO6 ALTERNATIVE MODE SD1 DYNAMIC VOLTAGE SCALING INPUT

Comment

DBNC6[1:0]

REFE_IRQ6[1:0]

DO6

DI6

DIR6

PPDRV6 PUE6

PDE6

0

AME6

1

GPI SD1 DVS

Input, VSD1 =

VDVSSD1

Debounce

times

0 =

active-low

Interrupt options

0

1

0

GPI SD1 DVS

Input, VSD1

= VDVSSD1,

Internal Pullup

Debounce

times

0 =

active-low

Interrupt options

0

1

0

1

GPI SD1 DVS

Input, VSD1 =

VSD1

Debounce

times

0 =

active-low

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Table 7. GPIO Programming Matrix (continued)

GPIO6 ALTERNATIVE MODE SD1 DYNAMIC VOLTAGE SCALING INPUT (continued)

GPI SD1 DVS

Input, VSD1 =

VSD1, Internal

Pullup

Debounce

times

0 =

active-low

Interrupt options

0

1

0

1

0

1

0

1

0

1

0

1

GPI SD1 DVS

Input, VSD1 =

VSD1

1 =

active-

high

Debounce

times

GPI SD1 DVS

Input, VSD1 =

VSD1, Internal

Pullup

1 =

active-

high

Debounce

times

GPI SD1 DVS

Input, VSD1 =

VDVSSD1

1 =

active-

high

Debounce

times

GPI SD1 DVS

Input, VSD1

= VDVSSD1,

Internal Pullup

1 =

active-

high

Debounce

times

GPIO7 ALTERNATIVE MODE REFERENCE OUTPUT 1.25V BUFFERED REFERENCE OUTPUT

Comment

DBNC7[1:0]

0

REFE_IRQ7[1:0]

0

DO7

0

DI7

0

DIR7

0

PPDRV7 PUE7

PDE7

0

AME7

1

GPIO7 = 1.25V

Output

0

Real-Time Clock (RTC)

Features

The real-time clock (RTC) is responsible for keeping track

of the time. It records seconds, minutes, hours, days,

months, and years with a calendar structure that accounts

for leap years. The RTC is further equipped with two

alarms and has a host of maskable interrupt capabilities.

● Gregorian calendar with leap year correction

● Two alarms

● Maskable interrupts

• 1s and 60s

• Alarm 1 and 2

• SMPL

Through a set of configuration registers, various modes of

operation are possible. RTC supports both “Binary” and

“Binary Coded Decimal”, and supports features such as

AM/PM and 24/12 modes of operation. Additional sudden

momentary power loss (SMPL) is available.

● Binary and BCD Modes

● 12/24 hour modes

● Sudden momentary power loss (SMPL)

● Double buffered read/write registers allow asynchro-

nous register access

● Operates down to 1.65V

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Multicore Applications

Read/Write Operations

The RTC has double buffered read/write registers that allow the register access to be asynchronous to the RTC

Figure 13).

(

WRITE BUFFERS

TIMEKEEPER COUNTERS

READ BUFFERS

SEC

MIN

HOUR

MUX

SHARED BUS

YEAR

RBUDF

RBUDR

UDF

UDR

UDR_SYNC

SYNCHRONIZERS

RBUDR_SYNC

DATA FROM WRITE BUFFERS TRANSFERRED TO

TIMEKEEPER COUNTERS WHEN UDR_SYNC IS HIGH

DATA FROM TIMEKEEPER COUNTERS TRANSFERRED

TO READ BUFFERS WHEN RBUDR_SYNC IS HIGH

CLOCK

DIVIDER

32kHz

256Hz

SMPL

Figure 13. RTC Simplified Functional Diagram

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In order to safely write to various registers on-board the RTC, all RTC registers (except RTCINT register, bit 0 of

UPDATE0 the register, and bit 4 of UPDATE0 the register) have a corresponding “Write Buffer”. When the user writes to

the RTC, the user is actually performing a write to these “Write Buffers”. Therefore, in writing to RTC there are two steps

needed to update a particular register or set of registers:

1) User writes desired value(s) to the register(s) located between 0x07 and 0x1B. Behind the scenes, only the “Write

Buﬀers” are updated with these new values.

2) The user then writes a 1 to UDR bit 0 of the “UPDATE0 register” at address 0x04 to transfer the modiﬁed “Write Buf-

fers” to the corresponding time registers.

The logic subsequently would perform a transfer of data from the “Write Buffers” to the actual registers and then clears

the “UDR” bit automatically as well as clearing the “Write Buffers” (marking them as not modified).

Under the hood, the logic first does a double synchronization of the UDR bit to the 32.768kHz clock before using it as an

enable bit (UDR_sync in Figure 13) to transfer from “Write buffers” to the actual registers thus allowing a safe update of

these two unsynchronized clock events.

Example 7. Pseudo code for setting clock to Saturday, Jan 01, 2011, 1:00:00 PM

Set RTCCNTL to 0x01

Set RTCUPDATE0 to 0x01

Set RTCSEC to 0x00

//12hr mode, BCD mode

// transfer RTCCNTL modification to RTC

// 0 second

Set RTCMIN to 0x00

// 0 minute

Set RTCHOUR to 0x41

Set RTCDOW to 0x40

Set RTCMONTH to 0x01

Set RTCYEAR to 0x11

Set RTCDOM to 0x01

Set RTCUPDATE0 to 0x01

Wait 16ms for write to complete

// 1 PM

// Saturday

// January

// 11

// First

// transfer write buffers to counters

Set RTCSEC to 0x…

//new write

Example 8. Pseudo code for setting ALARM1 to every Wednesday at 7:30:00 AM

Set RTCCNTL to 0x01

//12hr mode, BCD mode

// transfer RTCCNTL modification to RTC

//0 sec, enabled

Set RTCUPDATE0 to 0x01

Set RTCSECA1 to 0x80

Set RTCMINA1 to 0xB0

Set RTCHOURA1 to 0x87

Set RTCDOWA1 to 0x08

Set RTCMONTHA1 to 0x00

Set RTCYEARA1 to 0x00

Set RTCDOMA1 to 0x00

Set RTCUPDATE0 to 0x01

Wait 16ms for write to complete

//30 minute, enabled

//7 AM, enabled

//Wednesday, enabled

//Disabled

// transfer write buffers to counters

Set RTCSEC to 0x…

//new write

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Reading from RTC

Corresponding to most timing registers there are a series of “Read Buffers”.

In order to safely read from various registers on-board the RTC, all RTC registers (except RTCINT register and bit 0 and

4 of UPDATE0 register) have a corresponding “Read Buffer”. When the user reads from the RTC, the user is actually

performing a read from these “Read Buffers”. Therefore, there are two steps needed to read a particular register or set

of registers:

1. The user writes a 1 to RBUDR bit 4 of the “UPDATE0 Register” at address 0x04 to transfer most timing registers to

the “Read Buffers”. Behind the scenes, the “Read Buffers” are updated.

2. The user then reads from the desired register location.

After step 1, the logic subsequently performs a transfer of data from the actual registers to the “Read Buffers” and then

clears the “RBUDR” bit.

Under the hood, the logic first does a double synchronization of the RBUDR bit to the 32.768kHz clock before using it as

a clock (RBUDR_sync in Figure 13) to transfer from the actual registers to the “Read Buffers” thus allowing a safe update

of these two unsynchronized clock events.

Example 9. Pseudo code for reading the time

Set RTCUPDATE0 to 0x10

Wait 16ms for read to complete

Read RTCSEC

// transfer timekeeper counters to read buffers

// second

// minute

Read RTCMIN

Read RTCHOUR

// hour

Read RTCDOW

// Day of Week

// Month

Read RTCMONTH

Read RTCYEAR

// Year

Read RTCDOM

// Day of Month

Example 10. Pseudo code for reading ALARM1 setting

Set RTCUPDATE0 to 0x10

Wait 16ms for read to complete

Read RTCSECA1

// transfer timekeeper counters to read buffers

// sec

Read RTCMINA1

// minute

// hour

Read RTCHOURA1

Read RTCDOWA1

// Day of Week

// Month

Read RTCMONTHA1

Read RTCYEARA1

Read RTCDOMA1

// Year

// Day of Month

SMPL (Sudden Momentary Power Loss)

The SMPL function allows the system to recover if power is briefly lost due to a poor battery connection. If V

MBATT

falls below and returns above the UVLO threshold within the SMPL timer threshold (SMPLT[1:0]) and SMPL is enabled

(SMPL_EN = 1), SMPL initiates a power-up sequence and the SMPL interrupt bit is set. If the SMPL timer expires before

V

returns, the SMPL enable bit is automatically cleared in order to prevent power-up on subsequent SMPL events.

MBATT

To ensure proper operation of the SMPL state machine, initialization software should clear and set SMPL_EN after each

power-on event.

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32kHz Crystal Oscillator and

Buﬀered Outputs

Features

● Low-jitter mode provides 15ns cycle-by-cycle jitter

The IC contains a crystal oscillator driver with internal

load capacitance selectable by 32KLOAD[1:0] (Figure

14). PWR_MD_32K controls whether the crystal driver is

in low-power mode or low-jitter mode. In low-power mode,

the oscillator quiescent current is 1.5µA and in low-jitter

mode the cycle-by-cycle jitter is 15ns. The crystal driver

● On-chip crystal oscillator load capacitors

● 32kHz digital outputs

● Oscillator OK status

● Operates down to 1.5V

Backup Battery Charger

is supplied from the internal V

node which is equal to

.

RTC

V

if V

> V

The backup battery charger is a constant voltage (CV)

and constant current (CC) style charger with a series out-

put resistance as shown in Figure 14. The backup battery

charger is enabled and disabled with BBCEN. The charge

current, charger voltage, output current, and output resis-

tance are adjustable with the BBCCTRL register. The

backup-battery charger is suitable for the following types

of backup cells:

MBATT

MBATT MBATTUVLO

The crystal driver generates two 32kHz buffered outputs.

One 32kHz output has a dedicated pin (32K_OUT0). The

other output (32K_OUT1) is available through GPIO4

and is useful for peripherals such as BT/WLAN chipsets

(see AME4). The configuration of the output stage for

32K_OUT0 is factory programmable with OTP. The pri-

mary OTP option (OTP_32K_OUT = 0) configures the

output stage for a push-pull output between ground and

GPIO_INB. OTP_32K_OUT = 1 sets 32K_OUT0 for an

open-drain output. The output stage for 32K_OUT1 is

determined by their respective GPIO blocks.

● Super capacitor (a.k.a., gold cap, double-layer

electrolytic)

● Standard capacitors (tantalum … etc.)

● Rechargeable lithium manganese cells

There are three options for the internal load capacitance

from XIN to XGND and XOUT to XGND: 10pF, 12pF, and

22pF. XIN and XOUT each have approximately 3pF of

parasitic capacitance. The total load capacitance on the

crystal is shown in Table 1.

Features

● 800µA maximum CC-CV backup battery charger

● 2.5V—3.5V adjustable backup battery setting with

± 3% tolerance

The crystal driver also generates a status bit (32K_OK),

when the 32kHz clock is OK (typically 1 second after initial

start up).

● Seamless transition of RTC supply from V

to

MBATT

drops below V

MBATT MBATT_UVLO

V

when V

BBATT

threshold

Table 8. 32kHz Crystal Oscillator Load Capacitance

PARASITIC

CAPACITANCE FROM

XIN TO XGND AND XOUT XIN TO XGND AND XOUT XIN TO XGND AND XOUT

INTERNAL LOAD

CAPACITANCE FROM

EXTERNAL LOAD

CAPACITANCE FROM

TOTAL LOAD

CAPACITANCE ON THE

32kLOAD

CRYSTAL (pF)

TO XGND (pF)

0x00

0x01

0x02

0x03

3

12

None

10

7.5

12.5

6.5

22

None

10

12

7.5

22

12.5

6.5

22

None

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V_MBATTUVLO

V_MBATTOK

MBATT

LDO WITH REVERSE

CURRENT BLOCKING

BBCVS[1:0]

V_RTCUVLO

VRTC

SELECT LDO

IF AND ONLY IF

V_RTCOK

BBCEN

BBCLOWIEN

BBCCS[1:0]

V

_MBATT> V_BBATT

AND

_BBATT< V_BBCVS

BACKUP BATTERY

CHARGER

CURRENT LIMIT

BBCRS[1:0]

BBATT

32kLOAD

GPIO_INB

32K_OUT0_EN

32K_OK

CRYSTAL

LOAD

CAPACITORS

32kHz

RTC

RST

STABILITY

DETECTOR +

1ms DELAY

CRYSTAL

DRIVER

*

XIN

**32k_OUT0

GPIO

XOUT

RST

XGND

GND

PWR_MD_32K[1:0]

THE CRYSTAL DRIVER IS SUPPLIED BY V_RTC.

*OPTIONAL CRYSTAL OSCILLATOR LOAD CAPACITORS

**THE PUSH-PULL OUTPUT DRIVER STAGE IS SHOWN (OTP_32K = 0)

Figure 14. Backup Battery Charger, 32kHz Crystal Oscillator and RTC

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Result:

ON/OFF Controller

The ON/OFF controller monitors multiple wakeup sources

to intelligently enable all resources that are necessary

for the AP to boot (i.e., FPS0 and FPS1). As shown in

Figure 18, the on/off controller monitors wakeup events on

the EN0, EN1, EN2, ACOK, nRST_IO, and LID hardware

inputs. Additionally, internal wakeup events are also moni-

tored: SMPL, ALARM1, and ALARM2 internal signals.

Wakeup events go through logic to affect flexible power

sequencers 0 and 1 (FPS0, FPS1). Many wakeup signals

can be masked (WK_ACOK, WL_LID, WK_ALARM1,

WL_ALARM2, WK_EN0).

● At 0s, EN0 is asserted.

● After the debounce time (30ms), an EN0 assertion

interrupt is generated.

● After the 1s, the EN0 1s interrupt is generated.

● After 6s, the MRWRN is generated.

● After 8s, the manual reset event is initiated and all the

regulators shutdown.

● After 8.03s, the registers are reset.

● After 8.13s, a wakeup event is generated and the non-

volatile event recorder’s (NVERC) HDRST is set.

Many signals within the on/off controller generate inter-

rupts and are recorded in status registers.

● After 12s, the EN0 is deasserted.

● After the debounce time (30ms) an EN0 deassertion

EN0

interrupt is generated.

EN0 is a digital input to the ON/OFF controller that

Example 12: 20s EN0 assertion with an 8s manual reset

time.

(

Figure 18) typically comes from the system’s on key.

The EN0 polarity is factory programmable with OTP

(OTP_EN0AL) to be active-high or active-low (Figure 20).

Comments:

EN0 is internally debounced (t

). Programming

● A 20s EN0 assertion with an 8s manual reset time

DBEN0

EN0DLY allows an additional delay in the EN0 signal path

(t ).

causes the part to turn off ONCE and restart.

1SECEN0

Settings:

Manual Reset with EN0

● Manual reset is enabled (MREN = 1) and manual reset

time is set for 8s (MRT[2:0] = 0b101).

An extended EN0 event forces MRO high which activates

a global shutdown (see the Global Resources section for

more information on global shutdown). Note that an OTP

bit OTP_MR sets what the device does after the shut-

down. With OTP_MR = 1, the device automatically wakes

up after a manual reset event.

Stimulus:

● EN0 is asserted for 20s and then deasserted.

Result:

● At 0s, EN0 is asserted.

The extended EN0 event duration on EN0 is program-

mable from 2s to 12s with MRT[2:0]. A warning interrupt

(MRWRN) is generated one timer interval before the

manual reset time (i.e., MRT[2:0]-1).

● After the debounce time (30ms), an EN0 assertion

interrupt is generated.

● After the 1s, the EN0 1s interrupt is generated.

● After 6s, the MRWRN is generated.

Example 11: 12s EN0 assertion with an 8s manual reset

time.

● After 8s, the manual reset event is initiated and all the

regulators shutdown.

Comments:

● After 8.03s, the registers are reset.

● A 12s EN0 assertion with an 8s manual reset time

● After 8.13s, a wakeup event is generated and the non-

causes the part to turn off once and restart.

volatile event recorder’s (NVERC) HDRST is set.

Settings:

● After 20s, the EN0 is deasserted.

● Manual reset is enabled (MREN = 1) and manual reset

● After the debounce time (30ms), an EN0 deassertion

time is set for 8s (MRT[2:0] = 0b101).

interrupt is generated.

Stimulus:

● EN0 is asserted for 12s and then deasserted.

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Example 13: 20s EN0 assertion with an 8s manual reset

● After 8.13s, a wakeup event is generated and the non-

time followed by a 20s EN0 assertion.

volatile event recorder’s (NVERC) HDRST is set.

Comments:

● After 20s, the EN0 is deasserted.

● The initial 20s EN0 assertion causes the part to turn

● After the debounce time (20.03s) an EN0 deassertion

off and restart once.

interrupt is generated.

● The second EN0 assertion causes the part to turn off

● After 20.1, EN0 is asserted again.

and restart again.

● This causes the process to repeat from step #1.

Settings:

EN1

● Manual reset is enabled (MREN = 1) and manual reset

EN1 is a digital input to the ON/OFF controller (Figure 18

)

time is set for 8s (MRT[2:0] = 0b101).

that typically comes from the system’s AP. EN1 is used

to control sleep modes as shown in Figure 27. The EN1

polarity is factory programmable with OTP (OTP_EN1AL)

to be active-high or active-low (Figure 21).

Stimulus:

● EN0 is asserted for 20s and then deasserted for

100ms.

● EN0 is asserted again for 20s and then deasserted.

EN2

Result:

EN2 is an active-high digital input to the ON/OFF con-

troller (Figure 18, Figure 22) that typically comes from

● At 0s, EN0 is asserted.

the system’s AP. Generally, EN2 can directly control the

enable for SD0 when configured correctly. To configure

EN2 to control the enable of SD0, set FPSSCR_SD0[1:0]

= 0b00, PWR_MD_SD0[1:0] = 0b00, and then drive EN2

logic-low or logic-high to move between case 2 vs. case 5

as shown in Table 9. If EN2 is not needed to control SD0,

then connect it to ground and use the other flexible power

sequencer and/or registers to control SD0 as shown in

Table 9.

● After the debounce time (30ms), an EN0 assertion

interrupt is generated.

● After the 1s, the EN0 1s interrupt is generated.

● After 6s, the MRWRN is generated.

● After 8s, the manual reset event is initiated and all the

regulators shutdown.

● After 8.03s, the registers are reset.

Table 9. SD0 Power Mode Logic

CASE

OFF STATE

EN2

X

0

FPSx

PWR_MD_SD0[1:0] FPSSRC_SD0[1:0]

SD0 POWER MODE

0

1

0

X

Disabled

X

0b00

0b01

0b10

0b11

0b00

0b01

0b10

0b11

X

= 0b11

X

2

X

1

X

Group and/or dynamic low power mode

Low-power mode

3

X

4

X

Normal operating mode

Group and/or dynamic low-power mode

Low-power mode

5

X

6

1

X

7

1

X

8

1

X

Normal operating mode

Disabled

9

0

≠0b11

10

11

12

13

X

1

0b00

0b01

0b10

0b11

Normal operating mode

Group and/or dynamic low-power mode

Low-power mode

1

Normal operating mode

FPSx = 0 means that the specific FPS is disabled through software.

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ACOK

SMPL, ALARM1, and ALARM2

ACOK is a digital input to the ON/OFF controller

Figure 15) that typically comes from the system’s battery

SMPL, ALARM1, and ALARM2 are signal generated from

the RTC and used by the ON/OFF controller as shown in

(

charger. ACOK indicates the presence/absence of the

external charge adapter. The ACOK polarity is factory

programmable with OTP (OTP_ACOKAL) to be active-

high or active-low with the appropriate internal pullup/

down (Figure 23).

(Figure 18). See the Real-Time Clock (RTC) section for

more information on these signals.

SHDN

The shutdown input (SHDN) is a digital input to the ON/

OFF controller that causes the IC to reset through a global

shutdown event (Figure 1). The signal for SHDN typically

comes from a temperature sensor that measures the inter-

nal die temperature of the AP. The SHDN polarity is factory

programmable with OTP (OTP_SHDNAL) to be active-high

or active-low with the appropriate internal pullup/down

LID

LID is a digital input to the ON/OFF controller (Figure 18

)

that typically comes from the system’s battery door. LID

indicates whether the battery door is open or closed. The

LID polarity is factory programmable with OTP (OTP_

LIDAL) to be active-high or active-low with the appropriate

internal pullup/down (Figure 24).

(Figure 25). A system shutdown based on SHDN is record-

ed in the non-volatile power-off event recorder (NVREC).

ACOK_F (Rising Edge Triggered)

ACOK_R (Rising Edge Triggered)

VDD

Q

WAKEUP

Other Wakeup

Signals

ACOK

ACOK_TTL

MBATT_OK

DFF

ACOK_POL

MASK_ACOK

ACOK_POL = ‘0’

ACOK_POL = ‘1’

Rising Edge Trigger

Falling Edge Trigger

Figure 15. Functional Block Diagram for ACOK

LID_F (Rising Edge

Triggered)

One-Shot

WAKEUP

Other Wakeup

Signals

LID_R (Rising Edge

Triggered)

R

Q

SR

LATCH

S

VDD

QB

DFF

LID

LID_TTL

MBATTOK

LID_POL

MASK_ACOK

LID_POL = ‘0’

LID_POL = ‘1’

Rising Edge Trigger

Falling Edge Trigger

Figure 16. Functional Block Diagram for LID

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SHDN_TTL

GLBLSHDN

SHDN

SHDN_POL

SHDN_POL = ‘0’

SHDN_POL = ‘1’

Rising Edge Trigger

Falling Edge Trigger

Figure 17. Functional Block Diagram for SHDN

● FPS0 and FPS1 are enabled on ALARM2_R if WK_

ALRM1R is high, MBATT_OK is high, MBATTLOW

is low, MBLPD is high, and the IC is not in global

shutdown.

MBATT_OK and MBATTLOW

MBATT_OK and MBATTLOW are digital signals

that come from the systems’ main-battery monitor

(

Figure 1). MBATT_OK gates several wakeup sources

such that they cannot enable FPS0, FPS1, and SD0 until

the battery is above the system undervoltage-lockout

● FPS0 and FPS1 are enabled on ALARM2_R if WK_

ALRM1R is high, MBATT_OK is high, MBLPD is low

and the IC is not in global shutdown.

threshold (V

). MBATTLOW prevents FPS0,

MBATTUVLO

FPS1, and SD0 from being enabled when the main-

battery is below a programmed minimum voltage.

● FPS0 and FPS1 are enabled on SMPL_EVENT if

SMPL_EN is high, MBATT_OK is high, MBATTLOW

is low, MBLPD is high, and the IC is not in global

shutdown.

FPS0

Flexible Power Sequencer 0 is the enable signal for the

resources that need to be enabled when the AP is in its

normal operating mode and its sleep mode. When the AP

is in normal operating mode, both FPS0 and FPS1 are

● FPS0 and FPS1 are enabled on SMPL_EVENT if

SMPL_EN is high, MBATT_OK is high, MBLPD is low

and the IC is not in global shutdown.

enabled and FPS2 is cycled on/off as needed. Figure 18

Figure 19 and Table 10 describe the behavior of FPS0 in

addition to the following text description:

,

● FPS0 and FPS1 are enabled on LID if WK_LID is high,

MBATT_OK is high, MBATTLOW is low, MBLPD is

high, and the IC is not in global shutdown.

● FPS0 and FPS1 are enabled on EN0 rising edge if

MBATTLOW is low, MBLPD is high, and the IC is not

in global shutdown.

● FPS0 and FPS1 are enabled on LID if WK_LID is high,

MBATT_OK is high, MBLPD is low and the IC is not in

global shutdown.

● FPS0 and FPS1 are enabled on EN0 rising edge if

MBLPD is low and the device is not in global shut-

down.

● FPS0 and FPS1 are enabled on ACOK if WK_ACOK

is high, MBATT_OK is high, MBATTLOW is low,

MBLPD is high, and the IC is not in global shutdown.

● FPS0 and FPS1 are enabled on ALARM1_R if WK_

ALRM0R is high, MBATT_OK is high, MBATTLOW

is low, MBLPD is high, and the IC is not in global

shutdown.

● FPS0 and FPS1 are enabled on ACOK if WK_ACOK

is high, MBATT_OK is high, MBLPD is low and the IC

is not in global shutdown.

● FPS0 is disabled on global shutdown.

● FPS0 is disabled when PWR_OFF is set.

● FPS0 and FPS1 are enabled on ALARM1_R if WK_

ALRM0R is high, MBATT_OK is high, MBLPD is low

and the IC is not in global shutdown.

● FPS0 is disable if MBLPD is high and MBATTLOW is

high.

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● FPS1 is enabled on EN1 rising edge if, MBATTLOW

FPS1

is low, MBLPD is high, and the IC is not in global

shutdown.

Flexible Power Sequencer 1 is the enable signal for the

resources that need to be enabled when the AP is in its

normal operating mode and disabled when the AP is in

sleep mode. When the AP is in normal operating mode,

both FPS0 and FPS1 are enabled and FPS2 is cycled on/

off as needed.

● FPS1 is enabled on EN1 rising edge if MBLPD is low,

and the IC is not in global shutdown.

● FPS1 is disabled on global shutdown.

● FPS1 is disabled on EN1 falling edge if SLPEN is high.

● FPS1 is disabled when PWR_OFF is set.

Figure 18, Figure 19, and Table 10 describe the behavior

of FPS1 in addition to the following text description:

● FPS1 is disabled if MBLPD is high and MBATTLOW

● See all FPS1 enable conditions listed in the FPS0

section. Note that if only FPS0 is on but a wakeup

event occurs, then FPS1 is enabled.

is high.

Table 10. ON/OFF Controller State Diagram Transitions

TRANSITION

CONDITION

The fundamental system voltages and resources are available. Move to the OFF state.

1

• The battery voltage is not undervoltage (V

> V

)

MBATT

MBATTUVLO

A wakeup signal has been received. Move the “OK?” state to check to see if the system is okay to wakeup.

• A debounced EN0 press (i.e., edge) has been detected OR

• ALARM1_R event occurs and WK_ALRM0R is set OR

• ALARM2_R event occurs and WK_ALRM1R is set OR

• SMPL_EVENT occurs and SMPL_EN is set OR

2

• LID event (i.e., edge) occurs and WK_LID is set OR

• ACOK event (i.e., edge) occurs and WK_ACOK is set OR

• WAKEUP ﬂag is set by the previous sequenced shutdown

The basic system resources are okay.

• All ‘2B’ transition conditions are not true AND all ‘2C’ transition conditions are not true AND MBATTLOW = 0

2A

Failed attempt to power up because the battery voltage is too low.

The battery voltage is low (MBATTLOW = 1) AND the ‘2’ transition was not ACOK. OR

The battery voltage monitor is set for main-battery low power down (MBLPD = 1) AND the battery voltage is low

(MBATTLOW = 1) AND the ‘2’ transition is ACOK. OR

The battery voltage monitor is AND not set for main-battery low power down (MPLPD = 0) AND the battery voltage

is low (MBATTLOW = 1) AND the ‘2’ transition was ACOK, then the machine remains in the “OK?” state waiting for

MBATTLOW = 0. Once MBATTLOW = 0, then a transition along path ‘2A’ occurs.

2B

This ‘2B’ transition condition cancels the wakeup requests that occurred in transition ‘2’.

Failed attempt to power up because a basic system resource was not okay.

• The battery voltage is undervoltage (V

< V

) OR

MBATT

MBATTUVLO

• The battery voltage is overvoltage (V

> V

) OR

MBATT

MBATTOVLO

2C

• AVSD input is overvoltage (V

> V

) OR

AVSD

MBATTOVLO

• The junction temperature is too high (T > T

J

JSHDN

• SHDN pin is asserted (SHDN = 1)

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Table 10. ON/OFF Controller State Diagram Transitions (continued)

TRANSITION

CONDITION

Enter sleep mode.

3

• Sleep mode is enabled (SLPEN = 1) and EN1 transitions from high to low.

Exit sleep mode.

• Sleep mode is enabled (SLPEN = 1) and EN1 transitions from low to high.

• A debounced EN0 press has been detected OR

• ALARM1_R event occurs and WK_ALRM0R is set OR

• ALARM2_R event occurs and WK_ALRM1R is set OR

• LID event occurs and WK_LID is set OR

4

• ACOK event occurs and WK_ACOK is set

Enter the power-down sequence with register reset (see Figure 4).

• The low battery power-down is enabled (MBLPD = 1) AND the battery voltage is low (MBATTLOW = 1) OR

• Hardware reset input (RSI) event detected OR

• Manual reset event detected OR

• Watchdog timer expires OR

• SFT_RST = 1 OR

5

6

• PWR_OFF = 1

Immediate shutdown (see Figure 4).

• The battery voltage is undervoltage (V

< V

) OR

MBATT

MBATTUVLO

• The battery voltage is overvoltage (V

> V

MBATT

MBATTOVLO

• AVSD input is overvoltage (V

> V

) OR

AVSD

MBATTOVLO

• The junction temperature is too high (T > T

J

JSHDN

• SHDN pin is asserted (SHDN = 1)

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MBA TT

MBA TTLOW

MBLPD

MBA TT_OK

MBA TTLOW

MBLPD

MBA TT_OK

SDx ENABLE

LDOx ENABLE

GPIOx ENABLE

RSO

FPS0

FPS1

AVSD

GLOBAL

FLEXIBLE

POWER

SEQUENCER

RESOURCES

SHDN

RSO

RSI

WK_EN0

EN0

nRST_IO

GLBLSHDN

WK_ACOK

ACOK

EN2

EN1

EN2

EN1

WK_LID

LID

WK_ALRM0R

ALARM0_R

ENSD0

WK_ALRM1R

ALARM1_R

RTC

ON/OFF

CONTROLLER

MBA TT_OK

SMPL_EVENT

WAKEUP

1.5µs

DELAY

WAKEUP

INTERRUPT

LATCHES

ACOK

LID

ACOK

SLPEN

EN1

EN2

ACOK_R

ACOK_F

WDTE N

OTP_WDTE N

RSO

WDTT

RSI

MRO

INTERRUPT

LATCHES

LID

OTP_WDTT

WATCHDOG

TIMER

WATCHDOG

SFT_RST

PWR_OFF

GLBLSHDN

WATCHDOG

WDTC[1:0]

LID_F

FPS0

FPS1

WDTS LPC

DEBOUNCE OUTPUT

DURING POR IS LOW

MBA TT

EN0DLY

EN0

MRWRN

MRO

DEBOUNCE

RISING/FALLING

EN0

TIMER

t

DBNC

MRT[2:0]

R

PDEN0

10kΩ

EN0_R

EN0 IS SHOWN AS ACTIVE-HIGH. OTP_EN0AL = 0

ACOK IS SHOWN AS ACTIVE-HIGH. OTP_ACOKAL = 0

LID IS SHOWN AS ACTIVE-HIGH. OTP_LIDAL = 0

Figure 18. Simplified Block Diagram: ON/OFF Controller

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START

RESET

1

IMMEDIATE

SHUTDOWN

RESET

GLOBAL SHUTDOWN

OFF

FPS0 = 0

FPS1 = 0

STATE

ACTION

6

2B

2

NO

DECISION

OK?

2A

2C

YES

OFF PAGE

POWER DOWN

SEQUENCE

(FIGURE 24)

CONNECTION

POWER UP

SEQUENCE

ON

FPS0 = 1

FPS1 = 1

5

6

3

SLEEP EXIT

SEQUENCE

SLEEP ENTRY

SEQUENCE

SLEEP

FPS0 = 1

FPS1 = 0

5

4

6

Figure 19. State Diagram: ON/OFF Controller

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OTP OPTION FOR ACTIVE-LOW EN0 (OTP_EN0AL = 1)

OTP OPTION FOR ACTIVE-HIGH EN0 (OTP_EN0AL = 0)

MBA TT

R

PUEN0

10kΩ

EN0

PDEN0

R

10kΩ

Figure 20. EN0 Simplified Input Stage: Active-High or Low

OTP OPTION FOR ACTIVE LOW EN0 (OTP_EN1AL = 1)

OTP OPTION FOR ACTIVE HIGH EN0 (OTP_EN1AL = 0)

AP

V_IO

EN1

GPIO

EN1

Figure 21. EN1 Simplified Input Stage: Active-High or Low

AP

V_IO

EN2

GPIO

Figure 22. EN2 Simplified Input Stage: Active-High or Low

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OTP OPTION FOR ACTIVE-LOW ACOK (OTP_ACOKAL = 1)

OTP OPTION FOR ACTIVE-HIGH ACOK (OTP_ACOKAL = 0)

MBA TT

R

PUACOK

ACOK

100kΩ

ACOK

nACOK

R

PDACOK

FROM SYSTEM’S

100kΩ

BATTERY CHARGER

Figure 23. ACOK Simplified Input Stage: Active-High or Low

OTP OPTION FOR ACTIVE-LOW LID (OTP_LIDAL = 1)

OTP OPTION FOR ACTIVE-HIGH LID (OTP_LIDAL = 0)

MBATT

R

PULID

100kΩ

LID

nLID

R

PDLID

FROM SYSTEM LID OR

BATTERY DOOR SWITCH

100kΩ

Figure 24. LID Simplied Input Stage: Active-High or Low

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OTP OPTION FOR ACTIVE-LOW SHDN (OTP_SHDNAL = 1)

MBATT

VCC

MBATT

AP

R

PUSHDN

100kΩ

SHDN

ALERT

DXP

GND

DIODE TO

nSHDN

TEMPERATURE

CONVERSION +

COMPARATOR

MAX6642

OTP OPTION FOR ACTIVE-HIGH SHDN (OTP_SHDNAL = 0)

SHDN

R

PDSHDN

FROM SYSTEM’S THERMAL

OVERLOAD DETECTOR

100kΩ

Figure 25. SHDN Simplified Input Stage: Active-High or Low

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NOT DRAWN TO SCALE

Notes 1

POWER-UP

5

NORMAL OPERATION

8 9

POWER-DOWN

2

3

4

6 7

0V

3.6V

V

BATT

2.8V

V

BBATT

3.3V

V

RTC

32kHz OSC

t

OSU

V

EN0

t

DBNC

(OTP_EN0AL = 0)

nIRQ

(OPEN-DRAIN PULLED UP

TO SD2)

BIAS

t

BEN

FPS0

T

FPS0

= 1.28ms

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

V

(FPS0)

GPIO1

OUT_LDO4

OUT_LDO6

V

(FPS0)

OUT_SD2

32k_OUT0

nRST_IO

(OPEN-DRAIN PULLED UP

TO SD2)

FPS1

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

T

FPS1

= 1.28ms

V

(FPS1)

OUT_SD1

V

OUT_LDO1

OUT_LDO5

OUT_LDO3

OUT_LDO0

V

AP SOFTWARE

EN1 AND EN2

t

AP0

DON’T CARE

V

t

SUSD0

SD0

V

OTHER

(ENABLED BY SOFTWARE)

PWR_OFF

NOTES

1

2

3

4

5

6 7

8

9

10

11

12

1) THE AP AND ENTIRE SYSTEM IS OFF WITH NO BACKUP BATTERY AND NO MAIN BATTERY INSTALLED.

2) A HALF-CHARGED LITHIUM MANGANESE CELL IS INSTALLED FROM BBATT TO GND. V RISES TO ~V

2

. THE RTC RELATED PORTION OF THE I C REGISTER MAP

RTC

BBATT

POWERS UP TO ITS DEFAULT VALUE. THE OSCILLATOR STARTS TO FUNCTION AND THE RTC BLOCK BEGINS TO FUNCTION.

3) THE MAIN BATTERY IS CONNECTED. V

RISES UP TO ITS 3.3V REGULATION LEVEL. THE BACKUP-BATTERY CHARGER DEFAULTS TO “ON” WITH A 2.5V REGULATION

RTC

2

THRESHOLD. THE NON-RTC RELATED I C REGISTERS GO TO THEIR DEFAULT VALUES.

4) AN EXTERNAL EVENT PULLS EN0 HIGH. THE DEVICE DEBOUNCES EN0 AND STARTS THE BIAS FOLLOWED BY FPS0 AND FPS1.

5) FPS0 STARTS THE FUNDAMENTAL REGULATORS AT THE SAME TIME AS FPS1 STARTS THE SECONDARY REGULATORS.

6) FPS0 DEASSERTS nRST_IO ON ITS RISING EDGE #5. WITH nRST_IO HIGH, THE AP STARTS RUNNING SOFTWARE.

7) AP ASSERTS EN1 AND EN2. EN1 KEEPS THE FPS1 REGULATORS ENABLED. EN2 STARTS SD0.

8) WITH SD0 ENABLED, THE AP CONTINUES TO RUN SOFTWARE. IT CHECKS THE nIRQ INTERRUPT CAUSING nIRQ TO GO HIGH. IT POWERS UP THE “OTHER” RESOURCES OF

THE DEVICE AS REQUIRED.

9) THE AP AND ENTIRE SYSTEM ARE ON IN NORMAL OPERATING MODE.

10) THE AP DECIDES IT WANTS TO POWER DOWN AND IT POWERS DOWN THE OPTIONAL RESOURCES OF THE SYSTEM AND PMIC.

11) WITH ALL THE OPTIONAL RESOURCES POWERED DOWN, THE AP SETS TO “OFF” BIT AND PULLS EN1 AND EN2 LOW. EN2 LOW TURNS DISABLES SD0. THE OFF BIT STARTS

THE POWER DOWN SEQUENCE OF FPS0 AND EN1 LOW STARTS THE POWER DOWN SEQUENCE OF FPS1.

12) AFTER THE FPS0 AND FPS1 POWER DOWN SEQUENCES ARE FINISHED, THE BIAS TURNS OFF AND THE AP IS OFF.

Figure 26. Application Processor Power-Up and Power-Down Timing

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NORMAL

ENTERING-SLEEP

SLEEP

4

EXITING SLEEP

NOTES

1

2

3

5

6

V

BATT

V

BBATT

V

RTC

32kHz OSC

V

EN0

t

DBNC

(OTP_EN0AL = 0)

nIRQ

(OPEN-DRAIN PULLED UP TO SD2)

BIAS

FPS0

V

OUT_LDO4

(FPS0)

OUT_LDO6

(FPS0)

V

OUT_SD2

(FPS0)

32k_OUT0

GPIO1

nRST_IO

(OPEN-DRAIN PULLED UP TO SD2)

T

=

FPS0

1.28ms

FPS1

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

V

OUT_SD1

(FPS1)

V

OUT_LDO1

(FPS1)

V

OUT_LDO5

(FPS1)

OUT_LDO3

(FPS1)

OUT_LDO0

(FPS1)

AP SOFTWARE

t

AP0

EN1 AND EN2

V

SD0

t

SUSD0

V

OTHER

(ENABLED BY SOFTWARE)

PWR_OFF

NOTES

1

2

11

4

5

6

1) THE AP AND ENTIRE SYSTEM ARE ON AND IN NORMAL OPERATING MODE.

2) THE AP DECIDES IT WANTS TO POWER DOWN AND IT POWERS DOWN THE OPTIONAL RESOURCES OF THE SYSTEM AND PMIC.

3) WITH ALL THE OPTIONAL RESOURCES POWERED DOWN, THE AP AND PULLS EN1 AND EN2 LOW. EN2 LOW TURNS DISABLES SD0. EN1 LOW STARTS THE POWER DOWN

SEQUENCE OF FPS1.

4) AFTER THE FPS1 POWER DOWN SEQUENCES ARE FINISHED, THE AP IS IN SLEEP.

5) AN EN0 BUTTON PRESS GENERATES A WAKEUP EVENT THAT TURNS FPS1 ON.

6) WITH THE FPS1 POWER UP SEQUENCE FINISHED, THE AP IS IN ITS NORMAL OPERATING MODE.

Figure 27. Application Processor Entering and Exiting Sleep Timing

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is used to generate the eight combinations of the FPS

timing period TFPSx[2:0]. This oscillator is turned on once

a valid wakeup signal is received.

Nonvolatile Power-OFF Event Recorder

Several events within an IC based system can auton-

omously cause a power off (i.e., global shutdown).

The source of the power down event is recorded in

a non-volatile register such that when the system’s

microprocessor powers on again it can determine the

source of the previous power-off condition. Maxim recom-

mends that as part of the software’s initialization code, it

check the NVERC register. This power-off event recorder

register is non-volatile as long as the RTCs coin cell

(BBATT) remains within its valid voltage range. Unlike

most interrupt registers, the NVERC register does not

have a corresponding interrupt mask and status register.

Additionally, it does not affect the nIRQ pin. No status

register is provided since all NVERC events result in a

global shutdown which would subsequently reset any

related status.

Each regulator, GPIO1, GPIO2, GPIO3, and nRST_IO

has a flexible power sequence slave register (FPS_x)

which allows its enable source to be specified as a flex-

ible power sequencer timer or a software bit. When a

FPSSRCx specifies the enable source to be a flexible

power sequencer, the power up and power down delays

are configured by FPSPUx[2:0] and FPSPDx[2:0]. can

be specified in that regulators flexible power sequencer

configuration register.

If any of the FPS hardware inputs (EN0, EN1) are not

needed, connect them to ground. Grounding these inputs

when they are not needed ensures that they do not acci-

dentally turn on any voltage regulators—furthermore, it

improves the thermal impedance of the IC package.

Flexible Power Sequencer (FPS)

Table 11 shows one possible configuration of the flex-

ible power sequencer. Figure 26 and Figure 27 show the

timing diagrams for the default flexible power sequencer

settings.

The FPS allows each regulator to power up under hard-

ware or software control. Additionally, each regulator

can power on independently or among a group of other

regulators with an adjustable power-up and power-down

delays (sequencing). GPIO1, GPIO2, and GPIO3 can be

programmed to be part of a sequence allowing external

regulators to be sequenced along with internal regulators.

nRST_IO can be programmed to be part of a sequence.

Features

● Three Sequencers

● Power-Up and Power-Down Sequencing Control

● Eight Power-Up Sequence Time Slots

● Eight Power-Down Sequence Time Slots

Figure 26 shows LDO0, LDO1, LDO2, and LDO3 power-

ing up under the control of flexible power sequencer 2.

● Adjustable Time Period Between Time Slots from 40µs

The flexible sequencing structure consists of two hardware

enable inputs (EN0, EN1), and three master sequencing

timers. Each master sequencing timer is programmable

through its configuration register to have a hardware

enable source or a software enable source (CNFGFPSx).

When enabled/disabled the master sequencing timer

generates eight sequencing events. The time period

between each event is programmable within the

configuration register. An internal 800kHz silicon oscillator

to 5,120µs in Eight Binary Weighted Steps

● Sequence Enable/Disable can be Controlled by

Hardware and Software

● <10µs Sequencer Delay

● Capable of Controlling:

• All Regulators

• GPIO1, GPIO2, and GPIO3

• nRST_IO

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t

FPSCOFF

FPSCON

ENFPS2

t

FPSDOFF

FPSDON

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

INTERNAL

SEQUENCER

50% DUTY

EVENTS

t

FPST

V

LDO0

V

LDO1

V

LDO2

V

LDO3

NOTES

1

2

3

4

1) LDO0, LDO1, LDO2, AND LDO3 ARE OFF. EACH LDO’S ENABLE REGISTER SELECTS ACTIVE DISCHARGE ENABLED AND FPS2 AS THE ENABLE SOURCE. EACH LDO’S

FLEXIBLE SEQUENCER CONFIGURATION REGISTER IS PROGRAMMED WITH THE POWER-UP AND POWER-DOWN TIMING DELAYS AS SHOWN IN THE FIGURE. THE

CNFGFPS2 REGISTER SELECTS THE ENFPS2 BIT AS THE ENABLE SOURCE.

2) THE ENFPS2 BIT IS SET HIGH WHICH CAUSES EIGHT INTERNAL SEQUENCING EVENTS. EACH REGULATOR IS ENABLED AT THE SEQUENCING EVENT THAT

CORRESPONDS TO ITS FLEXIBLE SEQUENCER CONFIGURATION REGISTER.

3) THE ENFPS2 BIT IS CLEARED TO LOW WHICH CAUSES AND EIGHT INTERNAL SEQUENCING EVENTS. EACH REGULATOR IS DISABLED AT THE SEQUENCING EVENT

THAT CORRESPONDS TO ITS FLEXIBLE SEQUENCER CONFIGURATION REGISTER.

4) LDO0, LDO1, LDO2, AND LDO3 ARE OFF.

Figure 28. Example Timing Diagram: Flexible Power Sequencer

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Table 11. Example Configuration of the Flexible Power Sequencer

FPS MASTER

CONFIGURATION

TIMER PERIOD

(MS)

ENABLE

SOURCE

FPS SLAVE

CONFIGURATION

ENABLE

SOURCE

POWER UP

DELAYS

POWER DOWN

DELAYS

FPS0

FPS1

FPS2

1.28

N/A

EN0

EN1

N/A

SD0

SD1

Bit or EN2

FPS1

BIT

N/A

3

N/A

4

SD2

6

2

SD3

N/A

6

N/A

2

LDO0

FPS1

BIT

LDO1

3

4

LDO2

N/A

6

N/A

2

LDO3

FPS1

FPS0

FPS1

FPS0

BIT

LDO4

2

5

LDO5

3

LDO6

4

3

LDO7

N/A

4

N/A

3

LDO8

BIT

GPIO1

GPIO2

GPIO3

nRESET_OUT

FPS0

AME3 = 0

FPS0

0

7

N/A

7

N/A

1

Commitment Time

If the FPS begins a power-up sequence, it is committed

to completing that sequence (see t in Figure 28).

In other words, if the FPS begins a power-up sequence,

and then a power-down event (such as RSI) is initiated

before the power-up is complete, that power-down event

waits in a queue and executes after the FPS power-up

sequence is complete. Similarly, if the FPS begins a

power-down sequence, it is committed to completing that

Table 12. Changing Enable Sources

Behavior

FPSCON

EXISTING ENABLE NEW ENABLE

REGULATOR

SOURCE: STATE

BEHAVIOR

FPS or software:

enabled

FPS or software:

disabled

Turns oﬀ within

6.6µs

FPS or software:

disabled

FPS or software:

enabled

Turns on within

6.6µs

sequence (see t

in Figure 28). In other words,

FPSCOFF

FPS or software:

enabled

FPS: enabled

Remains on

Remains oﬀ

if the FPS begins a power-down sequence, and then a

power-up event (such as ACOK) is initiated before the

power-down is complete, that power-up event waits in a

queue and executes after the FPS power-up sequence is

complete. Note that the above comments are applicable

to all resources that can be assigned to the FPS (GPIO,

BUCK, LDO).

Software: enabled

FPS: enabled

FPS or software:

disabled

FPS or software:

disabled

Note an FPS enabled source is any of the seven flexible power

sequencers, a software enabled source is the dedicated enable

bit that is in location B0 of each regulator’s enabled register.

Changing Regulator Enable Source

The FPS allows the regulator enable sources to be

changed at any time. Table 12 illustrates what happens

when changing enable sources.

Ten regulators are assigned to FPS#1 and enabled in a

given sequence. No regulators are assigned to FPS#2

but FPS#2 is enabled. Then, three of the regulator enable

sources are changed from FPS#1 to FPS#2. Since both

FPS#1 and FPS#2 are enabled during the change, the

regulators remain on. Finally, the three regulators on

FPS#2 can then be enabled/disabled independently.

Example 14: Powering up ten regulators on sequencer 1

and then reassigning three of them to sequencer 2.

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2

I C Interface and Interrupt Output

Features

2

The IC features a revision 3 I C-compatible, 2-wire

serial interface consisting of a bidirectional serial data

line (SDA) and a serial clock line (SCL). The IC acts as a

slave-only device where it relies on the master to gener-

ate a clock signal. SCL clock rates from 0Hz to 3.4MHz

are supported.

● I C Revision 3 Compatible Serial Communications

Channel

• 0Hz to 100kHz (Standard Mode)

• 0Hz to 400kHz (Fast Mode)

• 0Hz to 1MHz (Fast-Mode Plus)

• 0Hz to 3.4MHz (High-Speed Mode)

2

I C is an open-drain bus and therefore SDA and SCL

2

● Does not Utilize I C Clock Stretching

require pullup resistors. Optional resistors (24Ω) in series

with SDA and SCL protect the device inputs from high-

voltage spikes on the bus lines. Series resistors also

minimize cross-talk and undershoot on bus signals.

2

● I C Watchdog Timer

2

I C System Conﬁguration

2

The I C bus is a multi-master bus. The maximum number

2

Figure 29 shows the functional diagram for the I C

based communications controller. For additional informa-

tion on I C, refer to the I C-bus specification and user

manual that is available from NXP (document title:

UM10204).

of devices that can attach to the bus is only limited by bus

capacitance.

2

Figure 30 shows an example of a typical I C system. A

device on the I C bus that sends data to the bus in called

2

a ”transmitter”. A device that receives data from the bus

is called a “receiver”. The device that initiates a data

transfer and generates the SCL clock signals to control

the data transfer is a “master.” Any device that is being

addressed by the master is considered a “slave.” The IC

2

is a slave on the I C bus and it can be both a transmitter

and a receiver.

COMMUNICATIONS CONTROLLER

INI2C

SCL

INTERFACE

DECODERS

SHIFT REGISTERS

BUFFERS

SDA

GND

PERIPHERAL

0

PERIPHERAL

1

PERIPHERAL

2

PERIPHERAL

N-1

PERIPHERAL

N

Figure 29. Functional Logic Diagram: Communications Controller

SDA

SCL

MASTER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

SLAVE

TRANSMITTER

TRANSMITTER/

RECEIVER

Figure 30. Functional Logic Diagram: Communications Controller

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2

transmission by issuing a not-acknowledge followed by

a STOP condition (see the I C Acknowledge Bit section

I C Interface Power

2

The I C interface derives its power from INI2C. Typically,

a power input such as INI2C would require a local 0.1µF

ceramic bypass capacitor to ground. However, in highly

integrated power distribution systems, a dedicated capac-

itor may not be necessary. If the impedance between

INI2C and the next closest capacitor (≥ 0.1µF) is less than

100mΩ in series with 10nH, then a local capacitor is not

needed. Otherwise, place a local 0.1µF ceramic bypass

capacitor from INI2C to ground.

for information on not-acknowledge). The STOP condi-

tion frees the bus. To issue a series of commands to the

slave, the master can issue repeated start (Sr) commands

instead of a STOP command in order to maintain control

of the bus. In general, a repeated start command is func-

tionally equivalent to a regular start command.

When a STOP condition or incorrect address is detected,

the IC internally disconnects SCL from the serial interface

until the next START condition, minimizing digital noise

and feed-through.

INI2C accepts voltages from 1.7V to 3.6V (V

2

).

INI2C

Cycling V

does not reset the I C registers.

INI2C

2

I C Acknowledge Bit

2

I C Data Transfer

2

Both the I C bus master and the IC (slave) generate

One data bit is transferred during each SCL clock cycle.

The data on SDA must remain stable during the high

period of the SCL clock pulse. Changes in SDA while

SCL is high are control signals (see the I C Interface and

Interrupt Output section).

acknowledge bits when receiving data. The acknowledge

bit is the last bit of each nine-bit data packet. To generate

an acknowledge (A), the receiving device must pull SDA

low before the rising edge of the acknowledge-related

clock pulse (ninth pulse) and keep it low during the high

period of the clock pulse (Figure 33). To generate a not-

acknowledge (nA), the receiving device allows SDA to be

pulled high before the rising edge of the acknowledge-

related clock pulse and leaves it high during the high

period of the clock pulse.

2

Each transmit sequence is framed by a START (S) condi-

tion and a STOP (P) condition. Each data packet is nine

bits long: eight bits of data followed by the acknowledge

bit. Data is transferred with the MSB first.

2

I C Start and Stop Conditions

Monitoring the acknowledge bits allows for detection

of unsuccessful data transfers. An unsuccessful data

transfer occurs if a receiving device is busy or if a system

fault has occurred. In the event of an unsuccessful data

transfer, the bus master should reattempt communication

at a later time.

When the serial interface is inactive, SDA and SCL idle

high. A master device initiates communication by issuing

a START condition. A START condition is a high-to-low

transition on SDA with SCL high. A STOP condition is a low-

to-high transition on SDA, while SCL is high (Figure 32).

A START condition from the master signals the begin-

ning of a transmission to the IC. The master terminates

S

Sr

P

SDA

t

SU;STO

SU;STA

SCL

t

HD;STA

Figure 31. START and STOP Conditions

NOT ACKNOWLEDGE (nA)

ACKNOWLEDGE (A)

S

SDA

t

SU;DAT

8

t

HD;DAT

SCL

1

2

9

Figure 32. Acknowledge Bits

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2

I C Slave Address

I C General Call Address

2

The IC implements 7-bit slave addressing. An I C bus

master initiates communication with a slave device

(MAX77863) by issuing a START condition followed

by the slave address. As shown in Table 13, the IC

slave addresses are factory programmable with OTP_

I2CADDR[1:0]. With any one programming option of

OTP_I2CADDR[1:0], the IC responds to only four slave

addresses; all other slave addresses are ignored.

The IC does not implement the I C specifications “gen-

eral call address.” If the IC sees the general call address

(0b0000_0000), it does not issue an acknowledge.

2

I C Watchdog Timer

2

The IC contains an I C watchdog timer to ensure reliable

operation of the I C bus. This I C watchdog timer helps

the system recover from I C bus hang-ups that can occur

when devices on an I C bus operate out of sync from

2

Figure 33 is an example of the slave address byte

format using the RTCs slave address. As shown, the

slave address byte consists of seven address bits and

a read/write bit (R/nW). After receiving any of the slave

addresses shown in Table 13, the IC issues an acknowl-

edge by pulling SDA low during the ninth clock cycle.

each other due to noise or poor system design.

2

In many cases, I C bus hang-ups can be cleared by the

master. The master can clear the I C bus by issuing nine

consecutive stop commands. In all known cases, the

device’s I C state machine is cleared whenever the mas-

ter issues nine consecutive stop commands. However, to

account for unforeseen system issues, the I C watchdog

timer serves as a backup protection method for I C bus

hang-ups.

2

I C Clock Stretching

2

In general, the clock signal generation for the I C bus is

the responsibility of the master device. The I C specifica-

2

tion allows slow slave devices to alter the clock signal by

holding down the clock line. The process in which a slave

device holds down the clock line is typically called clock

stretching. The IC does not use any form of clock stretch-

ing to hold down the clock line.

2

The I C watchdog timer is disabled by default. With the

2

I C watchdog timer disabled, the device meets the 0Hz

SCL frequency requirements in the I C specification

(UM10204). In many cases, this 0Hz capability is not

needed. Activating the I C watchdog timer defeats the

2

0Hz specification of I C.

2

Table 13. MAX77863 I C Slave Addresses

RTC SLAVE ADDRESS

WRITE

RTC SLAVE

PMIC/GPIO SLAVE

ADDRESS WRITE

PMIC/GPIO SLAVE

ADDRESS READ

OTP_ I2C ADDR[1:0]

ADDRESS READ

0x91, 0b1001_0001

0x95, 0b1001_0101

0xD1, 0b1101_0001

0xD5, 0b1101_0101

0b00

0b01

0b10

0b11

0x90, 0b1001_0000

0x94, 0b1001_0100

0xD0, 0b1101_0000

0xD4, 0b1101_0100

0x38, 0b0011_1000

0x3C, 0b0011_1100

0x78, 0b0111_1000

0x7C, 0b0111_1100

0x39, 0b0011_1001

0x3D, 0b0011_1101

0x79, 0b0111_1001

0x7D, 0b0111_1101

Slave Address is constructed with M, O, M, M, M, O, M, R/nW

where:

M = bit fixed in metal

O = factory programmable OTP bit

R/nW = user controlled Read/Write bit

ACKNOWLEDGE

A

S

SDA

SCL

1

2

0

3

1

4

0

5

0

6

0

7

R/nW

8

9

Figure 33. Slave Address Byte Example Using the Power Management Slave Address

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2

Enable the I C watchdog timer with the I2CTWD[1:0] bits.

pullup resistor is dissipating power, and lower value pullup

resistors dissipate more power (V /R).

2

With the I C watchdog timer enabled, the device monitors

the time between a START and STOP condition. If this

Operating in high-speed mode requires some special

considerations. For a full list of considerations, see the

I C specification. The major considerations with respect

2

time ever exceeds the programmed I C watchdog timer

2

period, the MAX77863 I C state machine is reset.

2

Note that the IC contains both a system watchdog timer

and an I C watchdog timer. See the System Watchdog

Timer section for more information.

to the MAX77863 are:

2

● The I C bus master uses current source pullups to

shorten the signal rise times.

2

I C Communication Speed

● The I C slave must use a different set of input filters

on its SDA and SCL lines to accommodate for the

higher bus speed.

The IC is compatible with all four communication speed

ranges as defined by the revision 3 I C specification:

2

● The communication protocols need to utilize the high-

● 0Hz to 100kHz (standard mode)

● 0Hz to 400kHz (fast mode)

speed master code.

At power-up and after each stop condition, the device

input filters are set for standard mode, fast mode, or fast-

mode plus (i.e., 0Hz to 1MHz). To switch the input filters

for high-speed mode, use the high-speed master code

protocols that are described in the I C Communication

Protocols section.

● 0Hz to 1MHz (fast-mode plus)

● 0Hz to 3.4MHz (high-speed mode)

Operating in standard mode, fast mode, and fast-mode

plus does not require any special protocols. The main

consideration when changing the bus speed through

this range is the combination of the bus capacitance and

pullup resistors. Higher time constants created by the

bus capacitance and pullup resistance (C x R) slow the

bus operation. Therefore, when increasing bus speeds,

the pullup resistance must be decreased to maintain a

reasonable time constant. Refer to the “Pullup Resistor

2

I C Communication Protocols

The IC supports both writing and reading from its regis-

2

ters. Table 13 shows the I C communication protocols

for each functional block. The power management and

GPIO functions use the same communications pro-

tocols. The Real-Time Clock (RTC) section does not

support the “writing multiple bytes using register-data

pairs” protocol—instead, the Real-Time Clock (RTC)

section supports the “writing to sequential registers”

protocol.

2

Sizing” section of the I C Revision 3 specification for

detailed guidance on the pullup resistor selection. In gen-

eral, for bus capacitances of 200pF, a 100kHz bus needs

5.6kΩ pullup resistors, a 400kHz bus needs about 1.5kΩ

pullup resistors, and a 1MHz bus needs 680Ω pullup

resistors. Note that when the open-drain bus is low, the

2

Table 14. I C Communication Protocols Supported by Different Functional Blocks

POWER MANAGEMENT AND GPIO

Writing to a single register

RTC

Writing to a single register

Writing multiple bytes using register-data pairs

Reading from a single register

Writing to sequential registers

Reading from a single register

Reading from sequential registers

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done writing it issues a stop or repeated start. This pro-

tocol is recommended when writing the RTC timekeeping

registers (RTC_SEC, RTC_MIN, RTC_HOURS, RTC_

WEEKDAY, RTC_DATE, RTC_MONTH, RTC_YEAR1,

RTC_YEAR2).

Writing to a Single Register

2

Figure 34 shows the protocol for the I C master device to

write one byte of data to the IC. This protocol is the same

as the SMBus specification’s “write byte” protocol.

The “write byte” protocol is as follows:

The “writing to sequential registers” protocol is as follows:

1) The master sends a start command (S).

2) The master sends the 7-bit slave address followed by

a write bit (R/nW = 0).

2) The master sends the 7-bit slave address followed by

a write bit (R/nW = 0).

3) The addressed slave asserts an acknowledge (A) by

pulling SDA low.

3) The addressed slave asserts an acknowledge (A) by

pulling SDA low.

4) The master sends an 8-bit register pointer.

5) The slave acknowledges the register pointer.

6) The master sends a data byte.

4) The master sends an 8-bit register pointer.

5) The slave acknowledges the register pointer.

6) The master sends a data byte.

7) The slave updates with the new data.

7) The slave acknowledges the data byte. The next

rising edge on SDA loads the data byte into its target

register and the data becomes active.

8) The slave acknowledges or not acknowledges the data

byte. The next rising edge on SDA loads the data byte

into its target register and the data becomes active.

8) Steps 6 to 7 are repeated as many times as the

master requires.

9) The master sends a stop condition (P) or a repeated

start condition (Sr). Issuing a P ensures that the bus in-

put ﬁlters are set for 1MHz or slower operation. Issuing

an Sr leaves the bus input ﬁlters in their current state.

9) During the last acknowledge related clock pulse, the

master can issue an acknowledge or a not-acknowl-

edge.

Writing to Sequential Registers

10) The master sends a stop condition (P) or a repeat-

ed start condition (Sr). Issuing a P ensures that the

bus input ﬁlters are set for 1MHz or slower operation.

Issuing an Sr leaves the bus input ﬁlters in their

current state.

Figure 35 shows the protocol for writing to sequential

registers. This protocol is similar to the “write byte”

protocol (Figure 34) except the master continues to write

after it receives the first byte of data. When the master is

LEGEND

MASTER TO SLAVE

SLAVE TO MASTER

1

7

1

0

1

8

1

8

1

NUMBER OF BITS

S

SLAVE ADDRESS

A

REGISTER POINTER

A

DATA

A or nA

P or Sr*

R/nW

THE DATA IS LOADED INTO

THE TARGET REGISTER AND

BECOMES ACTIVE DURING

THIS RISING EDGE

SDA

SCL

B1

7

B0

A

9

ACKNOWLEDGE

8

*P FORCES THE BUS FILTERS TO SWITCH

TO THEIR <= 1MHz MODE. Sr LEAVES THE

BUS FILTERS IN THEIR CURRENT STATE

Figure 34. Writing to a Single Register with the “Write Byte” Protocol

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LEGEND

MASTER TO SLAVE

SLAVE TO MASTER

1

7

1

0

1

8

1

8

1

NUMBER OF BITS

S

SLAVE ADDRESS

A

REGISTER POINTER X

A

DATA X

A

α

R/nW

8

1

8

1

DATA X+1

A

DATA X+2

A

α

8

1

8

1

NUMBER OF BITS

DATA n-1

A

DATA n

A or nA

P or Sr*

α

β

THE DATA IS LOADED INTO

THE TARGET REGISTER AND

BECOMES ACTIVE DURING

THIS RISING EDGE

SDA

B1

7

B0

A

9

B9

ACKNOWLEDGE

8

1

SCL

DETAIL: α

THE DATA IS LOADED INTO

THE TARGET REGISTER AND

BECOMES ACTIVE DURING

THIS RISING EDGE

SDA

SCL

B1

7

B0

A

9

ACKNOWLEDGE

*P FORCES THE BUS

8

FILTERS TO SWITCH TO

THEIR <=1MHz MODE. Sr

LEAVES THE BUS FILTERS IN

THEIR CURRENT STATE

DETAIL: β

Figure 35. Writing to Sequential Register “x” to “n”

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3) The addressed slave asserts an acknowledge by

pulling SDA low.

Writing Multiple Bytes

Using Register-Data Pairs

2

Figure 36 shows the protocol for the I C master device

to write multiple bytes to the IC using register-data pairs.

4) The master sends an 8-bit register pointer.

5) The slave acknowledges the register pointer.

6) The master sends a data byte.

2

This protocol allows the I C master device to address the

slave only once and then send data to multiple registers

in a random order. Registers can be written continuously

until the master issues a stop condition.

7) The slave acknowledges the data byte. The next

rising edge on SDA loads the data byte into its target

register and the data becomes active.

The “Writing Multiple Bytes using Register-

Data Pairs” protocol is not supported by the RTC

functional block.

8) Steps 4 to 7 are repeated as many times as the

master requires.

9) The master sends a stop condition. During the ris-

ing edge of the stop related SDA edge, the data byte

that was previously written is loaded into the target

register and becomes active.

The “multiple byte register-data pair” protocol is as follows:

1) The master sends a start command.

2) The master sends the 7-bit slave address followed by

a write bit.

LEGEND

MASTER TO SLAVE

SLAVE TO MASTER

1

7

1

0

1

8

1

8

1

NUMBER OF BITS

S

SLAVE ADDRESS

A

REGISTER POINTER X

A

DATA X

A

α

β

R/nW

8

1

8

1

REGISTER POINTER n

A

DATA n

A

8

1

8

1

REGISTER POINTER Z

A

DATA Z

A

P

THE DATA IS LOADED INTO

THE TARGET REGISTER AND

BECOMES ACTIVE DURING

THIS RISING EDGE.

B9

1

SDA

SCL

B1

7

B0

A

9

ACKNOWLEDGE

8

DETAIL: α

THE DATA IS LOADED INTO

THE TARGET REGISTER AND

BECOMES ACTIVE DURING

THIS RISING EDGE.

A

9

SDA

SCL

B1

7

B0

ACKNOWLEDGE

8

DETAIL: β

Figure 36. Writing to Multiple Registers with the “Multiple Byte Register-Data Pair” Protocol

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all the data it requires it issues a not-acknowledge (nA)

and a stop (P) to end the transmission. This continuous

Reading from a Single Register

2

Figure 37 shows the protocol for the I C master device

to read one byte of data to the MAX77863. This protocol

is the same as the SMBus specification’s “Read Byte”

protocol.

read protocol is recommended when reading from the

RTC timekeeping registers (RTC_SEC, RTC_MIN, RTC_

HOURS, RTC_WEEKDAY, RTC_DATE, RTC_MONTH,

RTC_YEAR1, RTC_YEAR2). When reading the RTC

timekeeping registers, secondary buffers are used to

prevent errors when the internal registers update. The

secondary buffers are loaded with the timekeeping regis-

ter data during an address read byte to the RTC (0xD1)

and when the register pointer rolls over to zero. The time

information is read from these secondary registers, while

the clock continues to run. This eliminates the need to

reread the registers in case the main registers update

during a read.

The “read byte” protocol is as follows:

1) The master sends a start command (S).

2) The master sends the 7-bit slave address followed by

a write bit (R/nW = 0).

3) The addressed slave asserts an acknowledge (A) by

pulling SDA low.

4) The master sends an 8-bit register pointer.

5) The slave acknowledges the register pointer.

6) The master sends a repeated start command (Sr).

The “Continuous Read from Sequential Registers” proto-

col is as follows:

7) The master sends the 7-bit slave address followed by

a read bit (R/nW = 1).

1) The master sends a start command (S).

2) The master sends the 7-bit slave address followed by

a write bit (R/nW = 0).

8) The addressed slave asserts an acknowledge by pull-

ing SDA low.

3) The addressed slave asserts an acknowledge (A) by

pulling SDA low.

9) The addressed slave places 8-bits of data on the bus

from the location speciﬁed by the register pointer.

4) The master sends an 8-bit register pointer.

5) The slave acknowledges the register pointer.

6) The master sends a repeated start command (Sr).

10) The master issues a not-acknowledge (nA).

11) The master sends a stop condition (P) or a repeat-

ed start condition (Sr). Issuing a P ensures that the

bus input ﬁlters are set for 1MHz or slower operation.

Issuing an Sr leaves the bus input ﬁlters in their

current state.

7) The master sends the 7-bit slave address followed by

a read bit (R/nW = 1). When reading the RTC time-

keeping registers, secondary buﬀers are loaded with

the timekeeping register data during this operation.

Note that when the IC receives a stop it does not modify

its register pointer.

8) The addressed slave asserts an acknowledge by pull-

ing SDA low.

Reading from Sequential Registers

Figure 35 shows the protocol for reading from sequential

registers. This protocol is similar to the “read byte” pro-

tocol except the master issues an acknowledge to signal

the slave that it wants more data—when the master has

9) The addressed slave places 8-bits of data on the bus

from the location speciﬁed by the register pointer.

10) The master issues an acknowledge (A) signaling the

slave that it wishes to receive more data.

*P FORCES THE BUS FILTERS TO SWITCH

TO THEIR <=1MHz MODE. Sr LEAVES THE

BUS FILTERS IN THEIR CURRENT STATE.

LEGEND

MASTER TO SLAVE

SLAVE TO MASTER

8

NUMBER

OF BITS

1

7

1

0

1

7

1

8

1

S

SLAVE ADDRESS

A

REGISTER POINTER X A Sr SLAVE ADDRESS

R/nW

A

DATA X

nA P or Sr*

R/nW

Figure 37. Reading from a Single Register with the “Read Byte” Protocol

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11) Steps 9 to 10 are repeated as many times as the

master requires. Following the last byte of data, the

master must issue a not acknowledge (nA) to signal

that it wishes to stop receiving data.

4) The addressed slave issues a not acknowledge (nA).

5) The master can now increase its bus speed up to

3.4MHz and issue any read/write operation.

6) The master can continue to issue high-speed read/

write operations until a stop (P) is issued. To continue

operations in high-speed mode, use repeated start

(Sr) commands instead of stop (P) comments. Issuing

a stop (P) sets the bus for 1MHz or slower operation.

12) The master sends a stop condition (P) or a repeated

start condition (Sr). Issuing a stop (P) ensures that

the bus input filters are set for 1MHz or slower opera-

tion. Issuing an Sr leaves the bus input filters in their

current state.

Factory OTP

Note that when the IC receives a stop it does not modify

its register pointer.

To optimize system flexibility, the IC offers many one-

time programmable (OTP) options. These OTP options

can only be programmed by Maxim during the end-of-

line production test. Many OTP options set the reset

value of registers; in this case, the default value is

listed by an “x” in the register table. Additional OTP

options that are not part of the basic register set are

summarized in Table 15. If non-standard OTP settings

are desired, contact Maxim; minimum order quantities

may apply.

Engaging HS-Mode for

Operation up to 3.4MHz

Figure 39 shows the protocol for engaging HS-mode

operation. HS-mode operation allows for a bus operating

speed up to 3.4MHz.

The “Engaging HS-Mode” protocol is as follows:

1) Begin the protocol while operating at a bus speed of

1MHz or lower.

2) The master sends a start command (S).

3) The master sends the 8-bit master code of 0b0000

1XXX where 0bXXX are don’t care bits.

LEGEND

*P FORCES THE BUS FILTERS TO SWITCH TO

THEIR <=1MHz MODE. Sr LEAVES THE BUS

FILTERS IN THEIR CURRENT STATE.

MASTER TO SLAVE

SLAVE TO MASTER

8

1

7

1

0

1

7

1

8

1

NUMBER OF BITS

S

SLAVE ADDRESS

A

REGISTER POINTER X A Sr SLAVE ADDRESS

A

DATA X

A

R/nW

8

1

8

1

8

1

NUMBER OF BITS

DATA X+1

A

DATA X+2

A

DATA X+3

A

8

1

8

1

8

1

NUMBER OF BITS

DATA n-2

A

DATA n-1

A

DATA n

nA P or Sr*

Figure 38. Reading Continuously from Sequential Registers “x” to “n”

LEGEND

MASTER TO SLAVE

SLAVE TO MASTER

1

8

1

ANY READ/WRITE PROTOCOL

FOLLOWED BY Sr

ANY READ/WRITE

PROTOCOL

S

HS-MASTER CODE

nA Sr

Sr

P

FOLLOWED BY Sr

FAST-MODE

HS-MODE

FAST-MODE

Figure 39. Engaging HS-Mode

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Table 15. OTP Bit Descriptions

FUNCTIONAL

BIT NAME

BLOCK

DESCRIPTION

32kHz

Buﬀered

Output

32K_OUT0 Output Driver Stage Conﬁguration

0 = The 32K_OUT0 output driver is a push-pull stage between ground and GPIO_INB.

1 = The 32K_OUT0 output driver is an open-drain stage.

OTP_32K

OTP_SD_SS

OTP_EN0AL

OTP_EN1AL

OTP_ACOKAL

OTP_LIDAL

Step-Down Regulator Soft-Start Rate

0 = 12.5mV/µs

1 = 25mV/µs

Step-Down

Regulators

Enable 0 Active Low (Figure 20)

0 = EN0 is active-high

1 = EN0 is active-low

On/Oﬀ

Controller

Enable 1 Active-Low (Figure 20)

0 = EN1 is active-high

1 = EN1 is active-low

On/Oﬀ

Controller

AC Okay Active-Low (Figure 23)

0 = ACOK is active-high

1 = ACOK is active-low

On/Oﬀ

Controller

LID Active-Low (Figure 24)

0 = LID is active-high

1 = LID is active-low

On/Oﬀ

Controller

SHDN Active-Low (Figure 25)

0 = SHDN is active-high

1 = SHDN is active-low

On/Oﬀ

Controller

OTP_SHDNAL

If OTP_WDTEN = 0, then WDTEN can be changed at any time.

System

Watchdog

Timer

If OTP_WDTEN = 1, then once WDTEN is set the watchdog timer cannot be disabled by

clearing WDTEN. Once enabled, the system watchdog timer runs until a global shutdown

occurs or the power oﬀ (PWR_OFF) functions is initiated.

OTP_WDTEN

OTP_WDTT

System

Watchdog

Timer

If OTP_WDTT = 0, then TWD[1:0] can be changed at any time.

If OTP_WDTT = 1, then TWD[1:0] can only be changed when WDTEN = 0.

Reset Output Deassert Delay Time

0b00 = 1.28ms

nRST_IO

OTP_TRSTO[1:0]

0b01 = 10.24ms

0b10 = 40.96ms

0b11 = 81.92ms

2

I C

OTP_I2CADDR[1:0]

I C Address Selection Bits. See Table 13.

Manual Reset Global Shutdown Control. See the Global Resources section for more

information on global shutdown.

Global

Resources

0 = The device shuts down due to a manual-reset event and stays oﬀ until a wakeup

event is generated.

OTP_MR

1 = The device shuts down due to a manual-reset event and automatically generates its

own wakeup.

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Register Descriptions

REGISTER NAME

CID0

0x3C

0x58

Read

Fixed

2

I C Slave Address

Register Address

Access Type

Reset Condition

BIT

NAME

SR[7:0]

DESCRIPTION

Serial number least-signiﬁcant byte

SR[23:16] + SR[15:8] + SR[7:0] form a 24-bit serial number

B[7:0]

Global Configuration Register 1

REGISTER NAME

CNFGGLBL1

0x3C

2

I C Slave Address

Register Address

Reset Value

0x00

0b xx01 xx1x

(“x” is an OTP bit)

Access Type

Read/write

Reset Condition

V

< V

RTC VRTC_UVLO

BIT

NAME

DESCRIPTION

B7

RSVD

Reserved - Write to 0b1

Main-Battery Low-Power Down

B6

MBLPD

0 = MBATTLOW does not cause a global shutdown.

1 = MBATTLOW rising forces a global shutdown.

0x00 = 100mV

0x01 = 200mV

0b000 = 2.7V

0b001 = 2.8V

0b010 = 2.9V

0b011 = 3.0V

0x02 = 300mV

0x03 = 400mV

0b100 = 3.1V

0b101 = 3.2V

0b110 = 3.3V

0b111 = 3.4V

Low-Battery Comparator

Hysteresis

B[5:4]

LBHYST

Low-Battery DAC Falling

B[3:1]

LBDAC[2:0]

LBRSTEN

Threshold (V

)

MONL

Low-Battery Monitor to nRST_IO Enable (Figure 1)

0 = The low-battery monitor only generates the MBATTLOW status bit and the

MBATTLOW_R interrupt bit.

B0

1 = In addition to the bits mentioned above, the low-battery monitor also pulls nRST_IO low

when V

is less than V

.

MON

MONL

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CNFGGLBL2: Global Configuration Register 2

REGISTER NAME

CNFGGLBL2

2

I C Slave Address

0x3C

0x01

Register Address

Reset Value

0b 0000 0x11

(“x” is an OTP bit)

Access Type

Read/write

Reset Condition

Global shutdown

BIT

NAME

DESCRIPTION

2

I C Watchdog Timer Period

2

0b00 = I C watchdog timer is disabled.

0b01 = 1.33ms

0b10 = 35.7ms

B[7:6]

I2CTWD[1:0]

GLBL_LPM

0b11 = 41.7ms

Global Low-Power Mode

0 = The global low-power mode signal is logic low. Devices that have been programmed to follow

the global low-power mode signal operates in their normal-power modes.

1 = The global low-power mode signal is logic high. Devices that have been programmed to follow

the global low-power mode signal operates in their low-power modes.

B5

Note that this bit is logically ORed with the alternative mode operation of GPIO0.

B4

B3

Reserved. Write to 1. Read is don’t care.

System Watchdog Timer Automatic Clear in the SLEEP Mode

0 = The system watchdog timer does not automatically clear in the sleep state.

1 = The system watchdog timer automatically clears in the sleep state.

WDTSLPC

WDTEN

System Watchdog Timer Enable

0 = System watchdog timer disabled.

1 = System watchdog timer enabled.

B2

If OTP_WDTEN = 0, then WDTEN can be changed at any time.

If OTP_WDTEN = 1, then once WDTEN is set the watchdog timer cannot be disabled by clearing

WDTEN. Once enabled, the system watchdog timer runs until a global shutdown occurs.

System Watchdog Timer Period

0b00 = 2s

0b01 = 16s

0b10 = 64s

0b11 = 128s

B[1:0]

TWD[1:0]

If OTP_WDTT = 0, then TWD can be changed at any time. If the value of TWD needs to be

changed, clear the system watchdog timer ﬁrst (WDTC[1:0] = 0b01), then change the value of

TWD.

If OTP_WDTT = 1, then TWD can only be changed when WDTEN = 0.

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CNFGGLBL3: Global Configuration Register 3

REGISTER NAME

GLBLCNFG3

2

I C Slave Address

0x3C

Register Address

Reset Value

0x02

0x00

Access Type

Read/write

Global shutdown

Reset Condition

BIT

B7

B6

B5

B4

B3

B2

NAME

DESCRIPTION

Reserved

DEFAULT

0

System Watchdog Timer Clear. Writing 0b01 to these bits clears the watchdog timer.

These bits automatically reset to 0b00 after they are written to 0b01.

0b00 = The system watchdog timer is not cleared.

B[1:0]

WDTC[1:0]

0b00

0b01 = The system watchdog timer is cleared.

0b10 = The system watchdog timer is not cleared.

0b11 = The system watchdog timer is not cleared.

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IRQTOP: Top Level Interrupt Register

REGISTER NAME

IRQTOP

2

I C Slave Address

0x3C

Register Address

Reset Value

0x05

0x00

Access Type

Read

Special Features

Reset Condition

IRQTOP is cleared when read.

Global shutdown

BIT

NAME

DESCRIPTION

DEFAULT

Top-Level Global Interrupt

B7

IRQ_GLBL

0 = No unmasked interrupts pending in the INTLBT register

0

1 = There are unmasked interrupts pending in the INTLBT register

Top-Level Step-Down Interrupt

B6

B5

IRQ_SD

0 = No unmasked interrupts pending in the IRQSD register

1 = There are unmasked interrupts pending in the IRQSD register

0

Top-Level LDO Interrupt

0 = No unmasked interrupts pending in the IRQ_LVL2_L0-7 or IRQ_LVL2_L8

registers.

IRQ_LDO

1 = There are unmasked interrupts pending in the IRQ_LVL2_L0-7 or

IRQ_LVL2_L8 registers.

Top-Level GPIO Interrupt

B4

B3

IRQ_GPIO

IRQ_RTC

0 = No unmasked interrupts pending in the IRQ_LVL2_GPI register.

1 = There are unmasked interrupts pending in the IRQ_LVL2_GPI register.

0

Top-Level RTC Interrupt

0 = No unmasked interrupts pending in the RTCINT register.

1 = There are unmasked interrupts pending in the RTCINT register.

Top-Level 32kHz Oscillator Interrupt

0 = The 32kHz crystal oscillator has not failed since the last time this bit was read.

1 = The 32kHz crystal oscillator has failed since the last time this bit was read.

See the 32K_OK bit for the oscillator status.

B2

IRQ_32K

0

Top-Level On/Oﬀ Controller Interrupt

B1

B0

IRQ_ONOFF

0 = No unmasked interrupts pending in the ONOFFIRQ register.

1 = There are unmasked interrupts pending in the ONOFFIRQ register.

0

Reserved

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IRQTOPM: Top Level Interrupt Mask Register

IRQTOPM masks interrupts generated by the top level IRQ register IRQTOP. See Figure 2 for a logic diagram showing

the IRQTOP and IRQTOPM bits.

REGISTER NAME

IRQTOPM

0x3C

2

I C Slave Address

Register Address

Reset Value

0x0D

0x75

Access Type

Read/write

Global shutdown

Reset Condition

BIT

NAME

DESCRIPTION

DEFAULT

Top-Level Global Interrupt Mask. IRQ_GLBLM blocks the interrupts from the global

resources (INTLBT register) from aﬀecting the nIRQ pin as shown in Figure 2.

Be careful not to confuse IRQ_GLBLM with GLBLM. GLBLM blocks all interrupts

from aﬀecting the nIRQ pin as shown in Figure 2.

0 = Unmasked

B7

IRQ_GLBLM

0

1 = Masked

Top-Level Step-Down Interrupt Mask

0 = Unmasked

1 = Masked

B6

B5

B4

B3

B2

IRQ_SDM

IRQ_LDOM

IRQ_GPIOM

IRQ_RTCM

IRQ_32KM

1

0

1

Top-Level LDO Interrupt Mask

0 = Unmasked

1 = Masked

Top-Level GPIO Interrupt Mask

0 = Unmasked

1 = Masked

Top-Level RTC Interrupt Mask

0 = Unmasked

1 = Masked

Top-Level 32kHz Oscillator Interrupt Mask

0 = Unmasked

1 = Masked

Top-Level On/Oﬀ Controller Interrupt Mask

0 = Unmasked

1 = Masked

B1

B0

IRQ_ONOFFM

0

1

Reserved

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INTENLBT

INTENLBT enables/disables interrupts generated by the low-battery monitor and the 120°C and 140°C thermal monitor

comparators.

REGISTER NAME

INTENLBT

0x3C

2

I C Slave Address

Register Address

Reset Value

0x0E

0x00

Access Type

Read/write

Global shutdown

Reset Condition

BIT

NAME

DESCRIPTION

DEFAULT

B[7:4]

Reserved

0b0000

Low-Battery Interrupt Mask

0 = Unmasked

1 = Masked

B3

B2

B1

LBM

0

120°C Thermal Alarm 1 Interrupt Mask

0 = Unmasked

1 = Masked

T

JALRM1M

JALRM2M

140°C Thermal Alarm 2 Interrupt Mask

0 = Unmasked

1 = Masked

Global Interrupt Mask. IRQ_GLBLM blocks the interrupts from the global

resources (INTLBT register) from aﬀecting the nIRQ pin as shown in

Figure 2. Be careful not to confuse IRQ_GLBLM with GLBLM. GLBLM blocks

all interrupts from aﬀecting the nIRQ pin as shown in Figure 2.

0 = Unmasked

B0

GLBLM

0

1 = Masked

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STATLBT: Low-Battery and Thermal Monitor Status

STATLBT shows the status of the low-battery monitor and thermal monitors.

REGISTER NAME

STATLBT

0x3C

2

I C Slave Address

Register Address

Reset Value

0x13

0x10

Access Type

Read

Reset Condition

Global shutdown

BIT

NAME

DESCRIPTION

DEFAULT

B[7:4]

Reserved. These bits can be written to any value. They always read 0b0001.

0b0001

Main-Battery Low Voltage. See Figure 1 for a simpliﬁed drawing.

B3

B2

B1

B0

MBATTLOW

0 = V

1 = V

> V

< V

0

MON

MONL

120°C Thermal Alarm Status Bit

T

0 = T < T

JALRM1

J 120

J

J120

1 = T > T

J

140°C Thermal Alarm Status Bit

0 = T < T

JALRM2

J

J140

1 = T > T

J

Software Version Of The Unmasked nIRQ MOSFET Gate Drive (Figure 1)

0 = Unmasked gate drive is logic-low.

IRQ

1 = Unmasked gate drive is logic-high.

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INTLBT: Low-Battery and Thermal Monitors Interrupt Register

INTLBT shows the interrupts for the status of the low-battery monitor and thermal monitors.

REGISTER NAME

INTLBT

0x3C

2

I C Slave Address

Register Address

Reset Value

0x06

0x00

Access Type

Read

Special Features

Reset Condition

Clear on read

Global shutdown

TRIGGER

TYPE

BIT

NAME

DESCRIPTION

DEFAULT

B[7:4]

Reserved

0b0000

N/A

Low-Main Battery Interrupt

0 = V

read.

1 = V

has not fallen below V

since the last time this bit was

MONL

Rising

edge

MON

B3

B2

MBATTLOW_R

0

has fallen below V

since the last time this bit was read.

MON

MONL

Interrupt 120C Thermal Flag Bit

0 = T has not risen above T since the list time this bit was read.

JALRM1

Rising

edge

T

JALRM1_R

JALRM2_R

J

1 = T has risen above T

since the list time this bit was read.

J

JALRM1

Interrupt 140C Thermal Flag Bit

0 = T has not risen above T

Rising

edge

B1

B0

since the list time this bit was read.

JALRM21

0

J

1 = T has risen above T

J

since the list time this bit was read.

JALRM2

Reserved

N/A

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Step-Down Regulator Output Voltage Setting Registers

REGISTER NAME

VSDx

2

I C Slave Address

0x3C

0x18: SD2

0x19: SD3

Register Address

Reset Value

SD2 0b 0xxx xx00 (“x” is an OTP bit)

SD3: 0b xxxx xx00 (“x” is an OTP bit)

Access Type

Read/write

Reset Condition

Global shutdown

BIT

BIT NAME DESCRIPTION

Target Voltage for SD2, SD3

B[7:0]

VSDx[7:0]

See the Step-Down Regulator 8-Bit Output Target Output Voltages (SD2, SD3) table.

Step-Down Regulator Output Voltage Setting Registers

REGISTER NAME

VSD0

2

I C Slave Address

0x3C.

Register Address

Reset Value

0x16

0b 0xxx xx00 (“x” is an OTP bit)

Read/write

Access Type

Reset Condition

Global shutdown

BIT

BIT NAME DESCRIPTION

Target Voltage for SD0

See the Step-Down Regulator 8-Bit Output Target Output Voltages (SD0) table.

B[7:0]

V[7:0]

Step-Down Regulator Output Voltage Setting Registers

REGISTER NAME

VSD1

2

I C Slave Address

0x3C

Register Address

Reset Value

0x17

0b 0xxx xx00 (“x” is an OTP bit)

Read/write

Access Type

Reset Condition

Global shutdown

BIT

BIT NAME DESCRIPTION

Target Voltage for SD1

See the Step-Down Regulator 8-bit Output Target Output Voltages (SD1) table.

B[7:0]

V[7:0]

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Step-Down Regulator Dynamic Voltage Scaling Output Setting Registers

REGISTER NAME

VDVSSD0

0x3C

2

I C Slave Address

Register Address

Reset Value

0x1B

0x20

Access Type

Read/write

Global shutdown

Reset Condition

BIT

BIT NAME

DESCRIPTION

DEFAULT

Dynamic Voltage Management Target Voltage for SD0. See the Step-Down

Regulator 8-Bit Output Target Output Voltages (SD0) table.

To control DVS for SD0 through GPIO5, set AME5 = 1. DIR5 sets whether GPIO5

is active-high or active-low. With the GPIO5 input active, the step-down regulator’s

target voltage is set by VDVSSD0. With the GPIO5 input inactive, the step-down

regulator’s target voltage is set by VSD0.

B[7:0]

VDVSSD0[7:0]

0x20

Step-Down Regulator Dynamic Voltage Scaling Output Setting Registers

REGISTER NAME

VDVSSD1

2

I C Slave Address

0x3C

Register Address

Reset Value

0x1C

0x10

Access Type

Read/write

Global shutdown

Reset Condition

BIT

BIT NAME

DESCRIPTION

DEFAULT

Dynamic Voltage Management Target Voltage for SD1. See the Step-Down

Regulator 8-bit Output Target Output Voltages (SD1) table.

To control DVS for SD1 through GPIO6, set AME6 = 1. DIR6 sets whether GPIO6

is active-high or active-low. With the GPIO6 input active, the step-down regulator’s

target voltage is set by VDVSSD1. With the GPIO6 input inactive, the step-down

regulator’s target voltage is set by VSD0.

B[7:0]

VDVSSD1[7:0]

0x10

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Step-Down Regulator 8-Bit Output Target Output Voltages (SD2, SD3)

0x00 =

0x20 =

0x40 =

0x60 =

0x80 =

0xA0 =

0xC0 =

0xE0 =

reserved

1.0000V

1.4000V

1.8000V

2.2000V

2.6000V

3.0000V

3.4000V

0x01 =

0x21 =

0x41 =

0x61 =

0x81 =

0xA1 =

0xC1 =

0xE1 =

reserved

1.0125V

1.4125V

1.8125V

2.2125V

2.6125V

3.0125V

3.4125V

0x02 =

0x22 =

0x42 =

0x62 =

0x82 =

0xA2 =

0xC2 =

0xE2 =

0.6250V

1.0250V

1.4250V

1.8250V

2.2250V

2.6250V

3.0250V

3.4250V

0x03 =

0x23 =

0x43 =

0x63 =

0x83 =

0xA3 =

0xC3 =

0xE3 =

0.6375V

1.0375V

1.4375V

1.8375V

2.2375V

2.6375V

3.0375V

3.4375V

0x04 =

0x24 =

0x44 =

0x64 =

0x84 =

0xA4 =

0xC4 =

0xE4 =

0.6500V

1.0500V

1.4500V

1.8500V

2.2500V

2.6500V

3.0500V

3.4500V

0x05 =

0x25 =

0x45 =

0x65 =

0x85 =

0xA5 =

0xC5 =

0xE5 =

0.6625V

1.0625V

1.4625V

1.8625V

2.2625V

2.6625V

3.0625V

3.4625V

0x06 =

0x26 =

0x46 =

0x66 =

0x86 =

0xA6 =

0xC6 =

0xE6 =

0.6750V

1.0750V

1.4750V

1.8750V

2.2750V

2.6750V

3.0750V

3.4750V

0x07 =

0x27 =

0x47 =

0x67 =

0x87 =

0xA7 =

0xC7 =

0xE7 =

0.6875V

1.0875V

1.4875V

1.8875V

2.2875V

2.6875V

3.0875V

3.4875V

0x08 =

0x28 =

0x48 =

0x68 =

0x88 =

0xA8 =

0xC8 =

0xE8 =

0.7000V

1.1000V

1.5000V

1.9000V

2.3000V

2.7000V

3.1000V

3.5000V

0x09 =

0x29 =

0x49 =

0x69 =

0x89 =

0xA9 =

0xC9 =

0xE9 =

0.7125V

1.1125V

1.5125V

1.9125V

2.3125V

2.7125V

3.1125V

3.5125V

0x0A =

0x2A =

0x4A =

0x6A =

0x8A =

0xAA =

0xCA =

0xEA =

0.7250V

1.1250V

1.5250V

1.9250V

2.3250V

2.7250V

3.1250V

3.5250V

0x0B =

0x2B =

0x4B =

0x6B =

0x8B =

0xAB =

0xCB =

0xEB =

0.7375V

1.1375V

1.5375V

1.9375V

2.3375V

2.7375V

3.1375V

3.5375V

0x0C =

0x2C =

0x4C =

0x6C =

0x8C =

0xAC =

0xCC =

0xEC =

0.7500V

1.1500V

1.5500V

1.9500V

2.3500V

2.7500V

3.1500V

3.5500V

0x0D =

0x2D =

0x4D =

0x6D =

0x8D =

0xAD =

0xCD =

0xED =

0.7625V

1.1625V

1.5625V

1.9625V

2.3625V

2.7625V

3.1625V

3.5625V

0x0E =

0x2E =

0x4E =

0x6E =

0x8E =

0xAE =

0xCE =

0xEE =

0.7750V

1.1750V

1.5750V

1.9750V

2.3750V

2.7750V

3.1750V

3.5750V

0x0F =

0x2F =

0x4F =

0x6F =

0x8F =

0xAF =

0xCF =

0xEF =

0.7875V

1.1875V

1.5875V

1.9875V

2.3875V

2.7875V

3.1875V

3.5875V

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Step-Down Regulator 8-Bit Output Target Output Voltages (SD2, SD3) (continued)

0x10 =

0x30 =

0x50 =

0x70 =

0x90 =

0xB0 =

0xD0 =

0xF0 =

0.8000V

1.2000V

1.6000V

2.0000V

2.4000V

2.8000V

3.2000V

3.6000V

0x11 =

0x31 =

0x51 =

0x71 =

0x91 =

0xB1 =

0xD1 =

0xF1 =

0.8125V

1.2125V

1.6125V

2.0125V

2.4125V

2.8125V

3.2125V

3.6125V

0x12 =

0x32 =

0x52 =

0x72 =

0x92 =

0xB2 =

0xD2 =

0xF2 =

0.8250V

1.2250V

1.6250V

2.0250V

2.4250V

2.8250V

3.2250V

3.6250V

0x13 =

0x33 =

0x53 =

0x73 =

0x93 =

0xB3 =

0xD3 =

0xF3 =

0.8375V

1.2375V

1.6375V

2.0375V

2.4375V

2.8375V

3.2375V

3.6375V

0x14 =

0x34 =

0x54 =

0x74 =

0x94 =

0xB4 =

0xD4 =

0xF4 =

0.8500V

1.2500V

1.6500V

2.0500V

2.4500V

2.8500V

3.2500V

3.6500V

0x15 =

0x35 =

0x55 =

0x75 =

0x95 =

0xB5 =

0xD5 =

0xF5 =

0.8625V

1.2625V

1.6625V

2.0625V

2.4625V

2.8625V

3.2625V

3.6625V

0x16 =

0x36 =

0x56 =

0x76 =

0x96 =

0xB6 =

0xD6 =

0xF6 =

0.8750V

1.2750V

1.6750V

2.0750V

2.4750V

2.8750V

3.2750V

3.6750V

0x17 =

0x37 =

0x57 =

0x77 =

0x97 =

0xB7 =

0xD7 =

0xF7 =

0.8875V

1.2875V

1.6875V

2.0875V

2.4875V

2.8875V

3.2875V

3.6875V

0x18 =

0x38 =

0x58 =

0x78 =

0x98 =

0xB8 =

0xD8 =

0xF8 =

0.9000V

1.3000V

1.7000V

2.1000V

2.5000V

2.9000V

3.3000V

3.7000V

0x19 =

0x39 =

0x59 =

0x79 =

0x99 =

0xB9 =

0xD9 =

0xF9 =

0.9125V

1.3125V

1.7125V

2.1125V

2.5125V

2.9125V

3.3125V

3.7125V

0x1A =

0x3A =

0x5A =

0x7A =

0x9A =

0xBA =

0xDA =

0xFA =

0.9250V

1.3250V

1.7250V

2.1250V

2.5250V

2.9250V

3.3250V

3.7250V

0x1B =

0x3B =

0x5B =

0x7B =

0x9B =

0xBB =

0xDB =

0xFB =

0.9375V

1.3375V

1.7375V

2.1375V

2.5375V

2.9375V

3.3375V

3.7375V

0x1C =

0x3C =

0x5C =

0x7C =

0x9C =

0xBC =

0xDC =

0xFC =

0.9500V

1.3500V

1.7500V

2.1500V

2.5500V

2.9500V

3.3500V

3.7500V

0x1D =

0x3D =

0x5D =

0x7D =

0x9D =

0xBD =

0xDD =

0xFD =

0.9625V

1.3625V

1.7625V

2.1625V

2.5625V

2.9625V

3.3625V

3.7625V

0x1E =

0x3E =

0x5E =

0x7E =

0x9E =

0xBE =

0xDE =

0xFE =

0.9750V

1.3750V

1.7750V

2.1750V

2.5750V

2.9750V

3.3750V

3.7750V

0x1F =

0x3F =

0x5F =

0x7F =

0x9F =

0xBF =

0xDF =

0xFF =

0.9875V

1.3875V

1.7875V

2.1875V

2.5875V

2.9875V

3.3875V

3.7875V

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MAX77863

Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Step-Down Regulator 8-Bit Output Target Output Voltages (SD0)

0x00 = Reserved

0x01 = Reserved

0x02 = 0.6250V

0x03 = 0.6375V

0x04 = 0.6500V

0x05 = 0.6625V

0x06 = 0.6750V

0x07 = 0.6875V

0x08 = 0.7000V

0x09 = 0.7125V

0x0A = 0.7250V

0x0B = 0.7375V

0x0C = 0.7500V

0x0D = 0.7625V

0x0E = 0.7750V

0x0F = 0.7875V

0x10 = 0.8000V

0x11 = 0.8125V

0x12 = 0.8250V

0x13 = 0.8375V

0x14 = 0.8500V

0x15 = 0.8625V

0x16 = 0.8750V

0x17 = 0.8875V

0x18 = 0.9000V

0x19 = 0.9125V

0x1A = 0.9250V

0x1B = 0.9375V

0x1C = 0.9500V

0x1D = 0.9625V

0x1E = 0.9750V

0x1F = 0.9875V

0x20 = 1.0000V

0x21 = 1.0125V

0x22 = 1.0250V

0x23 = 1.0375V

0x24 = 1.0500V

0x25 = 1.0625V

0x26 = 1.0750V

0x27 = 1.0875V

0x28 = 1.1000V

0x29 = 1.1125V

0x2A = 1.1250V

0x2B = 1.1375V

0x2C = 1.1500V

0x2D = 1.1625V

0x2E = 1.1750V

0x2F = 1.1875V

0x30 = 1.2000V

0x31 = 1.2125V

0x32 = 1.2250V

0x33 = 1.2375V

0x34 = 1.2500V

0x35 = 1.2625V

0x36 = 1.2750V

0x37 = 1.2875V

0x38 = 1.3000V

0x39 = 1.3125V

0x3A = 1.3250V

0x3B = 1.3375V

0x3C = 1.3500V

0x3D = 1.3625V

0x3E = 1.3750V

0x3F = 1.3875V

0x40 = 1.4000V

0x41 to 0xFF are reserved and

writes to this space are ignored.

Step-Down Regulator 8-bit Output Target Output Voltages (SD1)

0x00 = Reserved

0x01 = Reserved

0x02 = 0.6250V

0x03 = 0.6375V

0x04 = 0.6500V

0x05 = 0.6625V

0x06 = 0.6750V

0x07 = 0.6875V

0x08 = 0.7000V

0x09 = 0.7125V

0x0A = 0.7250V

0x0B = 0.7375V

0x0C = 0.7500V

0x0D = 0.7625V

0x0E = 0.7750V

0x0F = 0.7875V

0x10 = 0.8000V

0x11 = 0.8125V

0x12 = 0.8250V

0x13 = 0.8375V

0x14 = 0.8500V

0x15 = 0.8625V

0x16 = 0.8750V

0x17 = 0.8875V

0x18 = 0.9000V

0x19 = 0.9125V

0x1A = 0.9250V

0x1B = 0.9375V

0x1C = 0.9500V

0x1D = 0.9625V

0x1E = 0.9750V

0x1F = 0.9875V

0x20 = 1.0000V

0x21 = 1.0125V

0x22 = 1.0250V

0x23 = 1.0375V

0x24 = 1.0500V

0x25 = 1.0625V

0x26 = 1.0750V

0x27 = 1.0875V

0x28 = 1.1000V

0x29 = 1.1125V

0x2A = 1.1250V

0x2B = 1.1375V

0x2C = 1.1500V

0x2D = 1.1625V

0x2E = 1.1750V

0x2F = 1.1875V

0x30 = 1.2000V

0x31 = 1.2125V

0x32 = 1.2250V

0x33 = 1.2375V

0x34 = 1.2500V

0x35 = 1.2625V

0x36 = 1.2750V

0x37 = 1.2875V

0x38 = 1.3000V

0x39 = 1.3125V

0x3A = 1.3250V

0x3B = 1.3375V

0x3C = 1.3500V

0x3D = 1.3625V

0x3E = 1.3750V

0x3F = 1.3875V

0x40 = 1.4000V

0x41 = 1.4125V

0x42 = 1.4250V

0x43 = 1.4375V

0x44 = 1.4500V

0x45 = 1.4625V

0x46 = 1.4750V

0x47 = 1.4875V

0x48 = 1.5000V

0x49 = 1.5125V

0x4A = 1.5250V

0x4B = 1.5375V

0x4C = 1.5500V

0x4D to 0xFF are reserved and

writes to this space are ignored.

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Complete System PMIC, Featuring 13 Regulators,

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Step-Down Regulator Configuration—Register 1

REGISTER NAME

CNFG1SDx

2

I C Slave Address

0x3C

0x1D: SD0

0x1E: SD1

0x1F: SD2

0x20: SD3

Register Address

Reset Value

0b 01xx 00x0 (“x” is an OTP bit)

Read/write

Access Type

Reset Condition

Global shutdown

BIT

BIT NAME

DESCRIPTION

SDx Slew Rate During DVS

0x0 = 0b00 = 13.75mV/µs ramp rate

0x1 = 0b01 = 27.50mV/µs ramp rate

0x2 = 0b10 = 55.00mV/µs ramp rate

B[7:6]

SR_SDx[1:0]

0x3 = 0b11 = 100mV/µs ramp rate (Note 10)

The typical use case for SR_SDx is to set them to the desired value during system initialization and

then leave them that way during the normal operation of the system. The SR_SDx bits should not be

changed while its associated step-down regulator is in the middle of an output voltage slew rate event.

See the Dynamic Voltage Scaling section for more information.

SDx Power Mode Conﬁguration

When FPSSRC_SDx[1:0] = 0b11

0b00 = Disabled. SDx is oﬀ.

EN2 can override this setting and enable SD0 when it is high.

0b01 = Group low-power mode. SDx operates in normal mode when the global low-power mode

signal is low. When the global low-power mode signal is high, SDx operates in low-power mode.

0b10 = Low-power mode. SDx is forced into low-power mode. The maximum load current is 5mA

and the quiescent supply current is 5μA.

0b11 = Normal operation mode. SDx is forced into its normal operating mode.

When FPSSRC_SDx[1:0]≠0b11

PWR_MD_SDx_

[1:0]

0b00 = SDx is disabled when the ﬂexible power sequencer set by FPSSRC_SDx is disabled.

SDx is enabled in normal-power mode when the ﬂexible power sequencer is enabled.

EN2 can override this setting and enable SD0 when it is high.

B[5:4]

0b01 = SDx is disabled when the ﬂexible power sequencer set by FPSSRC_SDx is disabled.

SDx is enabled when the ﬂexible power sequencer is enabled. When SDx is enabled, it operates in

normal mode when the global low-power mode signal is low, and it operates in low-power mode

when the global low-power mode signal is logic high.

0b10 = SDx is disabled when the ﬂexible power sequencer set by FPSSRC_SDx is disabled.

SDx is enabled in low-power mode when the ﬂexible power sequencer is enabled.

0b11 = Same as 0b00.

Note that SD0 is also controlled with the EN2 hardware pin. See Table 9 for the ENSD0 and

PWR_MD_SD0[1:0] enable logic.

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Step-Down Regulator Configuration—Register 1 (continued)

BIT

BIT NAME

DESCRIPTION

Active-Low SDx Active Discharge Enable

0 = The active discharge function is enabled. When the step-down regulator is disabled, an internal

100Ω discharge resistor is connected to the output to discharge the energy stored in the output

capacitor. When the step-down regulator is enabled, the discharge resistor is disconnected from the

output.

B3

nADE_SDx

1 = The active discharge function is disabled. When the step-down regulator is disabled, the internal

100Ω discharge resistor is not connected to the output, and the discharge rate is dependent on the

output capacitance and the load present. When the step-down regulator is enabled, the discharge

resistor is disconnected from the output.

SDx Forced PWM Mode Enable

0 = SDx regulator skips pulses under light load conditions, and operates at a ﬁxed frequency with

medium to heavy load conditions. The regulator automatically transitions between pulse skipping and

ﬁxed frequency as needed.

B2

B1

FPWM_SDx

1 = SDx regulator operates with ﬁxed frequency under all load conditions.

Reserved. This bit must always be cleared to 0.

Active-Low SDx Falling Slew Rate Active-Discharge Enable

This bit is a don’t care when a given step-down converter is in low-power mode. In low-power mode,

the regulator behaves as if active discharge is always disabled.

0 = Active-discharge enabled. SDx operates in forced PWM mode during the time the output voltage

decreases. With forced PWM mode enabled, SDx can sink current from the output capacitor to ensure

that the output voltage falls at the rate programmed by SR_SDx[1:0]. To ensure a smooth output

voltage decrease, the PMW mode remains engaged for 50μs after the output voltage decreases to its

B0

nFSRADE_SDx target voltage.

1 = Active-discharge disabled. SDx is allowed to operate in skip mode during the time the output

voltage decreases (only if FPWM_SDx = 0). In skip mode, SDx cannot sink current from the output

capacitor. Since SDx cannot sink current in skip mode the output voltage falling slew rate is a function

of the external load on SDx. If the external load on SDx is heavy, then the output voltage falling slew

rate is the rate programmed by SR_SDx[1:0]. If the external load on SDx is light, then the output

voltage falling slew rate is a function of the output capacitance and the external load. Note that the

SDx internal feedback string always imposes a 2µA load on the output.

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Complete System PMIC, Featuring 13 Regulators,

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Step-Down Regulator Configuration—Register 2

REGISTER NAME

CNFG2SD

2

I C Slave Address

0x3C

Register Address

Reset Value

0x22

0x07

Access Type

Read/write

Global shutdown

Reset Condition

BIT

BIT NAME

DESCRIPTION

DEFAULT

0b00

B[7:6]

B[5:3]

Reserved. Write these bits to 0b00.

Reserved. Write these bits to 0b000.

0b000

SD0 Remote Output Voltage Sense Enable

0 = Disabled

1 = Enabled

B2

ROVS_EN_SD0

ROVS_EN_SD1

1

Note that when SD0 is operating in low-power mode, the ROVS function is automatically

disabled, however; this bit is not aﬀected. If this bit is set, then ROVS automatically

re-enables when SD0 enters its normal operating mode.

SD1 Remote Sense Enable

0 = Disabled

1 = Enabled

Note that when SD1 is operating in low-power mode, the ROVS function is automatically

disabled, however; this bit is not aﬀected. If this bit is set, then ROVS automatically

re-enables when SD1 enters its normal operating mode.

B1

B0

1

Reserved

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Complete System PMIC, Featuring 13 Regulators,

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Step-Down Regulator Interrupt Request Register

REGISTER NAME

IRQSD

2

I C Slave Address

0x3C

Register Address

Reset Value

0x07

0x00

Access Type

Read

Special Features

Reset Condition

Cleared upon read operation

Global shutdown

TRIGGER

TYPE

BIT

NAME

DESCRIPTION

DEFAULT

SD0 Power Fail Interrupt

PFI_SD0 0 = VSD0 has not fallen below VPOK_SDx since the last time this bit was read.

1 = VSD0 has fallen below VPOK_SDx since the last time this bit was read.

Falling

edge

B7

0

SD1 Power Fail Interrupt

PFI_SD1 0 = VSD1 has not fallen below its target voltage since the last time this bit was read.

1 = VSD1 has fallen below its target voltage since the last time this bit was read.

Falling

edge

B6

B5

0

SD2 Power Fail Interrupt

PFI_SD2 0 = VSD2 has not fallen below its target voltage since the last time this bit was read.

1 = VSD2 has fallen below its target voltage since the last time this bit was read.

Falling

edge

SD3 Power Fail Interrupt

PFI_SD3 0 = VSD3 has not fallen below its target voltage since the last time this bit was read.

1 = VSD3 has fallen below its target voltage since the last time this bit was read.

Falling

edge

B4

0

B[3:0]

Reserved

0b0000

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Complete System PMIC, Featuring 13 Regulators,

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Step-Down Regulator Interrupt Request Register Mask

REGISTER NAME

IRQMASKSD

0x3C

2

I C Slave Address

Register Address

Reset Value

0x0F

0xFF

Access Type

Read/write

N/A

Special Features

Reset Condition

Global shutdown

BIT

NAME

DESCRIPTION

DEFAULT

SD0 Power Fail Interrupt Mask

0 = Unmasked

B7

PFIM_SD0

1

1 = Masked

SD1 Power Fail Interrupt Mask

0 = Unmasked

1 = Masked

B6

B5

PFIM_SD1

PFIM_SD2

PFIM_SD3

1

SD2 Power Fail Interrupt Mask

0 = Unmasked

1 = Masked

SD3 Power Fail Interrupt Mask

0 = Unmasked

B4

1

1 = Masked

B[3:0]

Reserved. Write 0b1111. Read is don’t care.

0b1111

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Step-Down Regulator Status

REGISTER NAME

STATSD

0x3C

2

I C Slave Address

Register Address

Reset Value

0x14

0xFF

Access Type

Read

Special Features

Reset Condition

N/A

Global shutdown

BIT

NAME

DESCRIPTION

SD0 Power Okay Status

DEFAULT

B7

nPOK_SD0

0 = V

1 = V

above POK rising threshold–OK

below POK rising threshold–not OK

1

SD0

SD1 Power Okay Status

B6

B5

nPOK_SD1

nPOK_SD2

nPOK_SD3

0 = V

above POK rising threshold–OK

below POK rising threshold–not OK

SD1

1 = V

SD1

SD2 Power Okay Status

0 = V

above POK rising threshold–OK

below POK rising threshold–not OK

SD2

1 = V

SD2

SD3 Power Okay Status

B4

0 = V

above POK rising threshold–OK

1

SD3

1 = V

below POK rising threshold–not OK

SD3

B[3:0]

Reserved

0b1111

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Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

CNFG1_Lx: Linear Regulator Configuration Register (LDO0 to LDO8)

REGISTER NAME

CNFG1_Lx

2

I C Slave Address

0x3C

0x23: LDO0

0x25: LDO1

0x27: LDO2

0x29: LDO3

0x2B: LDO4

0x2D: LDO5

0x2F: LDO6

0x31: LDO7

Register Address

0x33: LDO8

Reset Value

0b 01xx 00x0 (“x” is an OTP bit)

Read/write

Access Type

Reset Condition

Global shutdown

ACCESS DESCRIPTION

BIT

NAME

TYPE

(DEFAULT VALUE IS SET WITH OTP)

LDOx Power Mode Conﬁguration

When FPSSRC_Lx[1:0] = 0b11

0b00: Output disabled. LDOx is oﬀ.

0b01: Group low-power mode. LDOx operates in normal mode when the global

low-power mode signal is low. When the global low-power mode signal is high,

LDOx operates in low-power mode.

0b10: Low-power mode. LDOx is forced into low-power mode. The maximum load

current is 5mA and the quiescent supply current is 1.5µA.

0b11: Normal mode. LDOx is forced into its normal operating mode.

When FPSSRC_Lx[1:0] ≠ 0b11

0b00 = LDOx is disabled when the ﬂexible power sequencer set by FPSSRC_Lx is

disabled. LDOx is enabled in normal-power mode when the ﬂexible power sequencer

is enabled.

7:6

PWR_MD_Lx[1:0]

R/W

0b01 = LDOx is disabled when the ﬂexible power sequencer set by FPSSRC_Lx

is disabled. LDOx is enabled when the ﬂexible power sequencer is enabled. When

LDOx is enabled, it operates in normal mode when the global low-power mode signal

is low, and it operates in low-power mode when the global low-power mode signal is

logic high.

0b10 = LDOx is disabled when the ﬂexible power sequencer set by FPSSRC_Lx is

disabled. LDOx is enabled in low-power mode when the ﬂexible power sequencer is

enabled.

0b11 = Same as 0b00.

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CNFG1_Lx: Linear Regulator Configuration Register (LDO0 to LDO8) (continued)

ACCESS DESCRIPTION

BIT

NAME

TYPE

(DEFAULT VALUE IS SET WITH OTP)

Target voltage for LDO0, LDO1

0x00 = 0.800V

0x01 = 0.825V

0x02 = 0.850V

0x03 = 0.875V

0x04 = 0.900V

0x05 = 0.925V

0x06 = 0.950V

0x07 = 0.975V

0x08 = 1.000V

0x09 = 1.025V

0x0A = 1.050V

0x0B = 1.075V

0x0C = 1.100V

0x0D = 1.125V

0x0E = 1.150V

0x0F = 1.175V

0x10 = 1.200V

0x11 = 1.225V

0x12 = 1.250V

0x13 = 1.275V

0x14 = 1.300V

0x15 = 1.325V

0x16 = 1.350V

0x17 = 1.375V

0x18 = 1.400V

0x19 = 1.425V

0x1A = 1.450V

0x1B = 1.475V

0x1C = 1.500V

0x1D = 1.525V

0x1E = 1.550V

0x1F = 1.575V

0x20 = 1.600V

0x21 = 1.625V

0x22 = 1.650V

0x23 = 1.675V

0x24 = 1.700V

0x25 = 1.725V

0x26 = 1.750V

0x27 = 1.775V

0x28 = 1.800V

0x29 = 1.825V

0x2A = 1.850V

0x2B = 1.875V

0x2C = 1.900V

0x2D = 1.925V

0x2E = 1.950V

0x2F = 1.975V

0x30 = 2.000V

0x31 = 2.025V

0x32 = 2.050V

0x33 = 2.075V

0x34 = 2.100V

0x35 = 2.125V

0x36 = 2.150V

0x37 = 2.175V

0x38 = 2.200V

0x39 = 2.225V

0x3A = 2.250V

0x3B = 2.275V

0x3C = 2.300V

0x3D = 2.325V

0x3E = 2.350V

0x3F = 2.375V

TV_Lx[5:0]

(Target Voltage for

FB String 1: LDO0,

LDO1)

5:0

R/W

Target voltage for LDO2, LDO3, LDO5, LDO6, LDO7, LDO8

0x00 = 0.80V

0x01 = 0.85V

0x02 = 0.90V

0x03 = 0.95V

0x04 = 1.00V

0x05 = 1.05V

0x06 = 1.10V

0x07 = 1.15V

0x08 = 1.20V

0x09 = 1.25V

0x0A = 1.30V

0x0B = 1.35V

0x0C = 1.40V

0x0D = 1.45V

0x0E = 1.50V

0x0F = 1.55V

0x10 = 1.60V

0x11 = 1.65V

0x12 = 1.70V

0x13 = 1.75V

0x14 = 1.80V

0x15 = 1.85V

0x16 = 1.90V

0x17 = 1.95V

0x18 = 2.00V

0x19 = 2.05V

0x1A = 2.10V

0x1B = 2.15V

0x1C = 2.20V

0x1D = 2.25V

0x1E = 2.30V

0x1F = 2.35V

0x20 = 2.40V

0x21 = 2.45V

0x22 = 2.50V

0x23 = 2.55V

0x24 = 2.60V

0x25 = 2.65V

0x26 = 2.70V

0x27 = 2.75V

0x28 = 2.80V

0x29 = 2.85V

0x2A = 2.90V

0x2B = 2.95V

0x2C = 3.00V

0x2D = 3.05V

0x2E = 3.10V

0x2F = 3.15V

0x30 = 3.20V

0x31 = 3.25V

0x32 = 3.30V

0x33 = 3.35V

0x34 = 3.40V

0x35 = 3.45V

0x36 = 3.50V

0x37 = 3.55V

0x38 = 3.60V

0x39 = 3.65V

0x3A = 3.70V

0x3B = 3.75V

0x3C = 3.80V

0x3D = 3.85V

0x3E = 3.90V

0x3F = 3.95V

TV_Lx[5:0]

(Target Voltage for

FB String 2: LDO2,

LDO3, LDO5, LDO6,

LDO7, LDO8)

R/W

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CNFG1_Lx: Linear Regulator Configuration Register (LDO0 to LDO8) (continued)

ACCESS DESCRIPTION

BIT

NAME

TYPE

(DEFAULT VALUE IS SET WITH OTP)

Target voltage for LDO4

0x00 = 0.8000V

0x01 = 0.8125V

0x02 = 0.8250V

0x03 = 0.8375V

0x04 = 0.8500V

0x05 = 0.8625V

0x06 = 0.8750V

0x07 = 0.8875V

0x08 = 0.9000V

0x09 = 0.9125V

0x0A = 0.9250V

0x0B = 0.9375V

0x0C = 0.9500V

0x0D = 0.9625V

0x0E = 0.9750V

0x0F = 0.9875V

0x10 = 1.0000V

0x11 = 1.0125V

0x12 = 1.0250V

0x13 = 1.0375V

0x14 = 1.0500V

0x15 = 1.0625V

0x16 = 1.0750V

0x17 = 1.0875V

0x18 = 1.1000V

0x19 = 1.1125V

0x1A = 1.1250V

0x1B = 1.1375V

0x1C = 1.1500V

0x1D = 1.1625V

0x1E = 1.1750V

0x1F = 1.1875V

0x20 = 1.2000V

0x21 = 1.2125V

0x22 = 1.2250V

0x23 = 1.2375V

0x24 = 1.2500V

0x25 = 1.2625V

0x26 = 1.2750V

0x27 = 1.2875V

0x28 = 1.3000V

0x29 = 1.3125V

0x2A = 1.3250V

0x2B = 1.3375V

0x2C = 1.3500V

0x2D = 1.3625V

0x2E = 1.3750V

0x2F = 1.3875V

0x30 = 1.4000V

0x31 = 1.4125V

0x32 = 1.4250V

0x33 = 1.4375V

0x34 = 1.4500V

0x35 = 1.4625V

0x36 = 1.4750V

0x37 = 1.4875V

0x38 = 1.5000V

0x39 = 1.5125V

0x3A = 1.5250V

0x3B = 1.5375V

0x3C = 1.5500V

0x3D = 1.5625V

0x3E = 1.5750V

0x3F = 1.5875V

TV_Lx[5:0]

(Target Voltage for FB

String 3: LDO4)

R/W

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CNFG2_Lx: Linear Regulator Configuration Register Details

REGISTER NAME

CNFG2_Lx

2

I C Slave Address

0x3C

0x24: LDO0

0x26: LDO1

0x28: LDO2

0x2A: LDO3

0x2C: LDO4

0x2E: LDO5

0x30: LDO6

0x32: LDO7

Register Address

0x34: LDO8

Reset Value

0b 01xx 00x0 (“x” is an OTP bit)

Read/write

Access Type

Reset Condition

Global shutdown

ACCESS

TYPE

BIT

NAME

DESCRIPTION (Default value is set with OTP)

Overvoltage Clamp Enable for LDOx

0 = Overvoltage clamp disabled

1 = Overvoltage clamp enabled (default)

OVCLMP_

EN_ Lx

7

R/W

Auto Low-Power Mode Enable Bit

0 = Auto low-power mode is disabled

1 = Auto low-power mode is enabled (default)

Reserved. This bit defaults to 1 and should be left at 1.

ALPM_EN_

Lx

Reserved

6

R/W

Adjustable compensation for PDRVx LDOs (LDO2 to LDO6). For LDO0, LDO01, LDO7, and LDO8

these bits must be 0b00.

LDO2 to LD06 support operation with a remote output capacitor. The optimum compensation for each

LDO is dependent on the series R-L-C impedance from the LDO output (LDO_OUTx) and its ground

(GND). The series resistance (R) is from parasitic resistance of the PCB and the ESR of the capacitor.

A good rule of thumb for parasitic “R” on a PCB is 0.5mΩ per square for 1oz copper and 1.0mΩ per

square for 0.5oz copper. The series inductance (L) is from the parasitic inductance of the PCB and the

ESL of the capacitor. A good rule of thumb for parasitic “L” on the PCB is 5nH/cm of electrical length.

The series C is the output capacitor itself.

5

Note that the COMP_Lx bits should only be changed when the LDO is disabled. If the compensation

bits are changed when the LDO is enabled, the output voltage glitches as the compensation changes.

0b00 = Fast transconductance setting for internal ampliﬁer. Use this setting when the LDOs output

capacitor loop has a series R-L-C output impedance of 50mΩ, 5nH, and ≥ C

(Table 1).

OUT_x

This output impedance corresponds to an output capacitor that is placed directly at the output pins

of the LDO (i.e., not remote). Load transient performance with this setting is 55mV typical between

OUTxx and GND (default).

COMP_Lx_

[1:0]

R/W

0b01 = Medium-fast transconductance setting for internal ampliﬁer. Use this setting when the LDOs

output capacitor loop has a series R-L-C output impedance of 150mΩ, 10nH, and ≥ C

OUT_x

(Table 1). This output impedance corresponds to an output capacitor that is relatively close to the

output pins of the LDO (2cm electrical length). Load transient performance with this setting is 66mV

typical between OUTxx and GND.

0b10 = Medium-slow transconductance setting for internal ampliﬁer. Use this setting when the LDOs

output capacitor loop has a series R-L-C output impedance of 500mΩ, 35nH, and ≥ C

OUT_x

(Table 1). This output impedance corresponds to an output capacitor that is placed at the point of

load which may be a few centimeters from the output pins of the LDO (7cm electrical length). Load

transient performance with this setting is 99mV typical between OUTxx and GND.

4

0b11 = Slow transconductance setting for internal ampliﬁer. Use this setting when the LDOs output

capacitor loop has a series R-L-C output impedance of 1000mΩ, 50nH, and ≥ C

(Table 1).

OUT_x

This output impedance corresponds to an output capacitor that is placed very far away from the

output pins of the LDO (10cm electrical length). Load transient performance with this setting is

125mV typical between OUTxx and GND.

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CNFG2_Lx: Linear Regulator Configuration Register Details (continued)

ACCESS

TYPE

BIT

NAME

DESCRIPTION (default value is set with OTP)

Voltage Okay Status Bit for LDOx

3

2

POK_Lxx

R

0 = The voltage is less than the POK threshold.

1 = The voltage is above the POK threshold.

R/W

Reserved. This bit must always be cleared to 0.

Active Discharge Enable for LDOx

0 = The active discharge function is disabled. When the regulator is disabled, the internal

active-discharge resistor is not connected to its output and the output voltage decays at a

rate that is determined by the output capacitance and the external load. When the regulator is

enabled, the internal active-discharge resistor is not connected to its output.

1 = The active discharge function is enabled. When the regulator is disabled, an internal

active-discharge resistor is connected to its output which discharges the energy stored in the

output capacitance. When this regulator is enabled, the internal active-discharge resistor is

disconnected from its output.

1

0

ADE_Lx

R/W

Soft-Start Slew Rate Conﬁguration for LDOx

(Applies to both start-up and output voltage setting changes)

0 = Fast startup and dynamic voltage change–100mV/µs

1 = Slow startup and dynamic voltage change–5mV/µs

SS_Lx

R/W

CNFG3_LDO: Linear Regulator Global Configuration Register

REGISTER NAME

CNFG3_LDO

0x3C

2

I C Slave Address

Register Address

Reset Value

0x35

0x00

Access Type

Read/write

Global shutdown

Reset Condition

ACCESS

TYPE

BIT

NAME

DESCRIPTION

7:1

R/W

Reserved. Write 0b0000000. Read is a don’t care.

LDO Bias Enable

0

L_B_EN

R/W

0 = Bias is disabled if all LDOs are disabled (default).

1 = Bias is enabled.

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IRQ_LVL2_Lx: Interrupt Registers

REGISTER NAME

IRQ_LVL2_Lx

2

I C Slave Address

0x3C

0x08: IRQ_LVL2_L0-7

0x09: IRQ_LVL2_L8

Register Address

Reset Value

0x00

Access Type

Reset Condition

Read/write

Global shutdown

ACCESS

TYPE

BIT

NAME

DESCRIPTION

IRQ Interrupt Bit

IRQ_LVL2_Lx

R

1: An interrupt has occurred. Cleared when read.

0: No interrupt has occurred since the last time this register was read.

IRQ_LVL2_L8, Register Address = 0x09, Default = 0x00

Bit 7: Reserved

Bit 6: Reserved

Bit 5: Reserved

Bit 4: Reserved

Bit 3: Reserved

Bit 2: Reserved

Bit 1: Reserved

Bit 0: IRQ_LVL2_L8

7:0

IRQ_LVL2_Lx

R

IRQ_LVL2_L0-7, Register Address = 0x08, Default = 0x00

Bit 7: IRQ_LVL2_L7

Bit 6: IRQ_LVL2_L6

Bit 5: IRQ_LVL2_L5

Bit 4: IRQ_LVL2_L4

Bit 3: IRQ_LVL2_L3

Bit 2: IRQ_LVL2_L2

Bit 1: IRQ_LVL2_L1

Bit 0: IRQ_LVL2_L0

7:0

IRQ_LVL2_Lx

R

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IRQ_MSK_Lx: Interrupt Mask Registers

REGISTER NAME

IRQ_MSK_Lx

2

I C Slave Address

0x3C

0x10: IRQ_MSK_L0-7

0x11: IRQ_MSK_L8

Register Address

Reset Value

0xFF

Access Type

Reset Condition

Read/write

Global shutdown

ACCESS

TYPE

BIT

NAME

DESCRIPTION

Interrupt Mask Bit

MSK_Lx

R/W

1: Interrupt is masked and nIRQ is not driven low due to an LDO event.

0: Interrupt is unmasked.

IRQ_MSK_L8, Register Address = 0x11, Default = 0xFF

Bit 7: Reserved

Bit 6: Reserved

Bit 5: Reserved

Bit 4: Reserved

Bit 3: Reserved

Bit 2: Reserved

Bit 1: Reserved

Bit 0: IRQ_MSK_L8

7:0

IRQ_MSK_L8

R/W

IRQ_MSK_L0-7, Register Address = 0x10, Default = 0xFF

Bit 7: IRQ_MSK_L7

Bit 6: IRQ_MSK_L6

Bit 5: IRQ_MSK_L5

Bit 4: IRQ_MSK_L4

Bit 3: IRQ_MSK_L3

Bit 2: IRQ_MSK_L2

Bit 1: IRQ_MSK_L1

Bit 0: IRQ_MSK_L0

7:0

IRQ_MSK_L0-7

R/W

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CNFG_GPIOx: GPIO Configuration Register

REGISTER NAME

CNFG1_GPIOx

2

I C Slave Address

0x3C

0x36 for GPIO0

0x37 for GPIO1

0x38 for GPIO2

0x39 for GPIO3

0x3A for GPIO4

0x3B for GPIO5

0x3C for GPIO6

0x3D for GPIO7

Register Address

Reset Value

When AMEx = 0  GPIO0/1/2/3/5/6/7 = 0x02, GPIO4 = 0x03

When AMEx = 1  GPIO0/5/6 = 0x02, GPIO1/2/3 = 0x00, GPIO4 = 0x01, GPIO7 = 0x00

Access Type

Read/write

Reset Condition

Global shutdown

BIT

NAME

DESCRIPTION

When set for GPO (DIRx = 0):

DBNCx are don’t care when GPO.

When set for GPI (DIRx = 1):

Debounce conﬁguration. GPIx has the following debounce times for both rising and falling edges.

0b00 = No debounce

0b01 = 8ms

B[7:6]

DBNCx[1:0]

0b10 = 16ms

0b11 = 32ms

When set for GPO (DIRx = 0):

REFE_IRQx are don’t care when GPO.

When set for GPI (DIRx = 1):

Rising edge and falling edge interrupt conﬁguration. GPIx has the interrupt behavior which is

programmed with REFE_IRQx.

B[5:4] REFE_IRQx[1:0]

0b00 = Mask interrupt

0b01 = Falling edge interrupt

0b10 = Rising edge interrupt

0b11 = Falling and rising edge interrupt

When set for GPO (DIRx = 0):

GPO output drive level is programmed with Dox.

0 = Logic low

1 = Logic high (DRVx = 1) and open-drain (DRVx = 0)

B3

DOx

When set for GPI (DIRx = 1):

0 = Clear DOx to 0 and set PUEx to 1 to enable the internal pullup.

1 = Set DOx to 1 and set PDEx to 1 to enable the internal pulldown.

See the GPIO programming matrix (Table 7. GPIO Programming Matrix) for more information.

When set for GPO (DIRx = 0):

DIx is a don’t care when GPO.

When set for GPI (DIRx = 1):

Input Drive Level. GPIOx input logic level is speciﬁed by DIx.

0 = Input logic low

B2

DIx

1 = Input logic high

When DIRx = 1, this bit is read only, writes to this bit are ignored.

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CNFG_GPIOx: GPIO Configuration Register (continued)

BIT

NAME

DESCRIPTION

When AMEx = 0:

GPIOx direction

0 = General purpose output (GPO)

1 = General purpose input (GPI)

When AMEx = 1:

B1

DIRx

When GPIO1/2/3/4 are set as an alternate mode output, write DIR1/2/3/4 (respectively) to 0 but note

that the output is internally set to be active-high. When GPIO0/5/6 is set as an alternate mode input,

DIR0/5/6 (respectively), determine if the signal is active-high or active-low.

0 = Active-low

1 = Active-high

When set for GPO (DIRx = 0):

Push-pull output drive. GPIO output conﬁguration is determined by PPDRVx.

0 = Open-drain

1 = Push-pull

B0

PPDRVx

When set for GPI (DIRx = 1):

PPDRVx is a don’t care when GPI.

PUE_GPIO: GPIO Pullup Enable Register

REGISTER NAME

PUE_GPIO

0x3C

2

I C Slave Address

Register Address

Reset Value

0x3E

0x00

Access Type

Read/write

Global shutdown

Reset Condition

BIT

B7

B6

B5

B4

B3

B2

B1

B0

NAME

PDE7

PDE6

PDE5

PDE4

PDE3

PDE2

PDE1

PDE0

DESCRIPTION

DEFAULT

0

GPOIx Pulldown Enable

0 = Pulldown disabled

1 = Pulldown enabled

See the GPIO programming matrix (Table 7) for more information.

It is recommended that users disable the pullup and pulldown resistors

for GPIO7 when it operates in alternate mode.

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PDE_GPIO: GPIO Pulldown Register

REGISTER NAME

PDE_GPIO

0x3C

2

I C Slave Address

Register Address

Reset Value

0x3F

0x00

Access Type

Read/write

Global shutdown

Reset Condition

BIT

B7

B6

B5

B4

B3

B2

B1

B0

NAME

PDE7

PDE6

PDE5

PDE4

PDE3

PDE2

PDE1

PDE0

DESCRIPTION

DEFAULT

0

GPOIx Pulldown Enable

0 = Pulldown disabled

1 = Pulldown enabled

See the GPIO programming matrix (Table 7) for more information.

It is recommended that the MAX77863 user disable the pullup and pulldown

resistors for GPIO7 when it operates in alternate mode.

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AME_GPIO: Alternate Mode Enable GPIO Configuration Register

REGISTER NAME

AME_GPIO

2

I C Slave Address

0x3C

Register Address

Reset Value

0x40

0b xxxx xxxx (“x” is an OTP bit)

Read/write

Access Type

Reset Condition

Global shutdown

BIT

NAME

DESCRIPTION

Alternate Mode Enable for GPIO7

0 = Standard GPI or GPO as programmed by DIR7

1 = 1.25V buﬀered reference output.

DBNC7 is a don’t care

REFE_IRQx is a don’t care

B7

AME7

DO7 is a don’t care

DI7 is a don’t care

DIR7 is internally cleared to 0

PPDRV7 is a don’t care

It is recommended that the MAX77863 user disable the pullup and pulldown resistors for GPIO7

when it operates in alternate mode.

Alternate Mode Enable for GPIO6

0 = Standard GPI or GPO as programmed by DIR5

1 = SD1 dynamic voltage scaling input

DBNC6 is valid

B6

AME6

REFE_IRQ6 is valid

DO6 is a don’t care

DI6 is valid

DIR6 sets active low or active high

PPDRV6 is a don’t care

Alternate Mode Enable for GPIO5

0 = Standard GPI or GPO as programmed by DIR5

1 = SD0 dynamic voltage scaling input

DBNC5 is valid

B5

AME5

REFE_IRQ5 is valid

DO5 is a don’t care

DI5 is valid

DIR5 sets active-low or active-high

PPDRV5 is a don’t care

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AME_GPIO: Alternate Mode Enable GPIO Configuration Register (continued)

BIT

NAME

DESCRIPTION

Alternate Mode Enable for GPIO4

0 = Standard GPI or GPO as programmed by DIR4

1 = 32kHz output (32k_OUT1)

DBNC4 is a don’t care

B4

AME4

REFE_IRQ4 is a don’t care

D04 is a don’t care and the output logic level is set by the 32kHz oscillator.

DI4 is a don’t care

DIR4 is internally cleared to 0

PPDRV4 is valid

Alternate Mode Enable for GPIO3

0 = Standard GPI or GPO as programmed by DIR3

1 = Flexible power sequencer active-high output

DBNC3 is a don’t care, write to 0b00

REFE_IRQ3 is a don’t care, write to 0b00

D03 is internally set by the ﬂexible power sequencer in accordance with the FPS_GPIO3 register

settings.

B3

AME3

DI3 is a don’t care, write to 0

DIR3 is a don’t care, write to 0

PPDRV3 is valid

Alternate Mode Enable for GPIO2

0 = Standard GPI or GPO as programmed by DIR2

1 = Flexible power sequencer active-high output

DBNC2 is a don’t care, write to 0b00

REFE_IRQ2 is a don’t care, write to 0b00

D02 is internally set by the ﬂexible power sequencer in accordance with the FPS_GPIO2

register settings.

B2

AME2

DI2 is a don’t care, write to 0

DIR2 is a don’t care, write to 0

PPDRV2 is valid

Alternate Mode Enable for GPIO1

0 = Standard GPI or GPO as programmed by DIR1

1 = Flexible power sequencer active-high output

DBNC1 is a don’t care, write to 0b00

REFE_IRQ1 is a don’t care, write to 0x00

D01 is internally set by the ﬂexible power sequencer in accordance with the FPS_GPIO1 register

settings.

B1

AME1

DI1 is a don’t care, write to 0

DIR1 is a don’t care, write to 0

PPDRV1 is valid

Alternate Mode Enable for GPIO0

0 = Standard GPI or GPO as programmed by DIR0

1 = Low-power mode control input

DBNC0 is valid

B0

AME0

REFE_IRQ0 is valid

DO0 is a don’t care

DI0 is valid

DIR0 sets active-low or active-high

PPDRV0 is a don’t care

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IRQ_LVL2_GPIO: GPIO Level 2 Interrupt Register

REGISTER NAME

IRQ_LVL2_GPIO

2

I C Slave Address

0x3C

Register Address

Reset Value

0x0A

0b00000000

Read

Access Type

Special Features

Reset Condition

Clear on read

Global shutdown

BIT

B7

B6

B5

B4

B3

B2

B1

B0

NAME

DESCRIPTION

DEFAULT

EDGE7

EDGE6

EDGE5

EDGE4

EDGE3

EDGE2

EDGE1

EDGE0

0

GPIOx Edge Detection Interrupt

0 = No edges have been detected on GPIOx since the last time this bit was

read.

1 = An edge corresponding to REFE_IRQx has been detected on GPIOx

since the last time this bit was read. Note that REFE_IRQx = 0b00 sets an

interrupt mask which forces EDGEx to 0.

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RTCINT: RTC Interrupt Register

REGISTER NAME

RTCINT

2

I C Slave Address

0x68

Register Address

Reset Value

0x00

0b00000000

Read Only

Clear on read

Access Type

Special Features

Reset Condition

V

< V

RTCUVLO

RTC

BIT

BIT NAME

DESCRIPTION

DEFAULT

RTC 60 Second Timer Expired Interrupt

0 = 60s timer did not expire

1 = 60s timer expired

0

RTC60S

0

RTC Alarm 1 Interrupt

0 = No interrupt

1 = Interrupt

1

2

3

4

RTCA1

RTCA2

SMPL

0

RTC Alarm 2 Interrupt

0 = No interrupt

1 = Interrupt

SMPL Event Interrupt

0 = No interrupt

1 = Interrupt

RTC Periodic 1 Second Timer Expired Interrupt

0 = 1s timer did not expire

RTC1S

1 = 1s timer expired

WTSR Interrupt

0 = No interrupt

1 = Interrupt

Reserved. This bit is internally set to 0.

5

WTSR

RSVD

0

7:6

Reserved

00

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RTCINTM: RTC Interrupt Register Mask

REGISTER NAME

RTCINTM

0x68

2

I C Slave Address

Register Address

Reset Value

0x01

0x3F

Access Type

Read/write

This is a double buﬀered register. Writes to this register are only uploaded to the RTC when UDR is

set. This register is only updated from the RTC when RDUDR is set.

Special Feature

Reset Condition

V

< V

RTCUVLO

RTC

BIT

BIT NAME

DESCRIPTION

DEFAULT

RTC 60 Second Timer Expired Interrupt Mask

0 = Not masked

1 = Masked

0

RTC60SM

RTCA1M

RTCA2M

SMPLINTM

RTC1SM

1

RTC Alarm 1 Interrupt Mask

0 = Not masked

1 = Masked

1

2

3

4

1

RTC Alarm 2 Interrupt Mask

0 = Not masked

1 = Masked

SMPL Event Interrupt Mask

0 = Not masked

1 = Masked

RTC Periodic 1 Second Timer Expired Interrupt Mask

0 = Not masked

1 = Masked

5

RVSD

Reserved. This bit is a don’t care.

Reserved

1

7:6

RSVDM

0b00

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RTCCNTLM: RTC Control Mode Register

REGISTER NAME

RTCCNTLM

0x68

2

I C Slave Address

Register Address

Reset Value

0x02

0x03

Access Type

Read/write

This is a double buﬀered register. Writes to this register are only uploaded to the RTC when UDR is set.

This register is only updated from the RTC when RDUDR is set.

Special Feature

Reset Condition

V

< V

RTCUVLO

RTC

BIT

BIT NAME

DESCRIPTION

DEFAULT

Access Control Of Bcd Bit In Register Rtccntl

0

BCDM

0 = Writes to Bit 0 (BCD) of register address 0x03 (RTCCNTL) not allowed

1 = Writes to Bit 0 (BCD) of register address 0x03 (RTCCNTL) allowed

1

Access Control of HRMODE Bit in Register RTCCNTL

1

HRMODEM

RSVD

0 = Writes to bit 0 (HRMODE) of register address 0x03 (RTCCNTL) not allowed

1 = Writes to bit 0 (HRMODE) of register address 0x03 (RTCCNTL) allowed

1

7:2

Reserved

000000

RTCCNTL: RTC Control Register

REGISTER NAME

RTCCNTL

0x68

2

I C Slave Address

Register Address

Reset Value

0x03

0x00

Access Type

Read/write

This is a double buﬀered register. Writes to this register are only uploaded to the RTC when UDR is

set. This register is only updated from the RTC when RDUDR is set.

Special Feature

Reset Condition

V

< V

RTCUVLO

RTC

BIT

BIT NAME

DESCRIPTION

DEFAULT

Data Mode For Time And Calendar Updates

0 = Binary

1 = Binary-coded decimal (BCD)

0

BCD

0

If BCDM = 0, writes to BCD are not allowed.

When switching between binary and BCD, the time contents are no longer valid

and must be reinitialized.

Hour Format Control

0 = 12-hour mode

1 = 24-hour mode

Note that the AMPM bit is deﬁned for the HOUR or HOURA register only which

makes sense for the 12-hr mode as the 24-hr mode already has AM/PM implied.

1

HRMODE

RSVD

0

If HRMODEM = 0, writes to HRMODE are not allowed.

When switching between 12-hour and 24-hour mode, the registers do not

automatically update. The user must reprogram all registers.

7:2

Reserved

000000

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RTCUPDATE0: RTC Update 0 Register

REGISTER NAME

RTCUPDATE0

0x68

2

I C Slave Address

Register Address

Reset Value

0x04

0x0A

Access Type

Read/write

Reset Condition

V

< V

RTC RTCUVLO

BIT

BIT NAME

DESCRIPTION

DEFAULT

Access control to update RTC registers by transferring data from the “write buﬀers” to

the actual registers.

0 = No action

0

UDR

1 = Update register

0

Typical transfer time from write buﬀers to the timekeeper counters is 15ms after UDR is

set.

UDR is internally cleared to after the registers data has been transferred.

Flags Cleared Upon Read Control Bit

1

FCUR

0 = User must write 0 to clear UDF and RBUDF.

1 = UDF and RBUDF cleared upon read.

1

This Bit Freezes The Sec Counter From Incrementing

0 = SEC counter increments normally.

1 = SEC counter stops incrementing which stops all subsequent registers in the timer

string (MIN, HOUR, DAY, etc). This setting eﬀectively stops the clock.

2

3

FREEZE_SEC

Reserved

0

1

Reserved

Access control to update RTC registers by transferring data from the actual registers to

the “read buﬀers.”

0 = No action

1 = Update “read buﬀers”

Typical transfer time from timekeeper counters to read is 15ms after RBUDR is set.

RBUDR is internally cleared to after the registers data has been transferred.

4

RBUDR

RSVD

0

7:5

Reserved

000

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RTCUPDATE1: RTC Update 1 Register

REGISTER NAME

RTCUPDATE1

2

I C Slave Address

0x68

Register Address

Reset Value

0x05

0x00

Access Type

Read only

Special Feature

Reset Condition

Clear on read when FCUR is set

V

< V

RTCUVLO

RTC

BIT

BIT NAME

DESCRIPTION

DEFAULT

This bit is an update ﬂag that indicates when an actual transfer of data from the “write Buﬀers”

to the corresponding register occurs. When this bit is 1, then the user can initiate a new write

operation, otherwise it is not safe to do so.

0 = Update not done

1 = Update done

0

UDF

0

Typical update time is 15ms after the UDR bit is set.

If FCUR bit (RTCUPDATE0 register) is 1, this bit is automatically cleared after a read

operation. If FCUR is 0, the user must write a 0 to clear it.

This bit is an update ﬂag that indicates when an actual transfer of data from the actual

registers to “Read Buﬀers” occurs. When this bit is 1, then the user can initiate a new read

operation, otherwise it is not safe to do so.

0 = Update not done

1 = Update done

1

RBUDF

RSVD

0

Typical update time is 15ms after the RBUDR bit is set.

If FCUR bit (RTCUPDATE0 register) is 1, this bit is automatically cleared after a read

operation. If FCUR is 0, the user must write a 0 to clear it.

7:2

Reserved

000000

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RTCSMPL: RTC Sudden Momentary Power Loss Register

REGISTER NAME

RTCSMPL

0x68

2

I C Slave Address

Register Address

Reset Value

0x06

0x00

Access Type

Read/write

Reset Condition

V

< V

RTC RTCUVLO

BIT

BIT NAME

DESCRIPTION

DEFAULT

1:0

RVSD

Reserved

0b00

Sets the SMPL Timer Threshold

0b00 = 0.5s

3:2

SMPLT[1:0]

0b01 = 1.0s

0b00

0b10 = 1.5s

0b11 = 2.0s

5:4

6

RSVD

RVSD

Reserved

00

0

Reserved. This bit is a don’t care.

SMPL Feature Enable Control

0 = SMPL disabled

7

SMPL_EN

0

1 = SMPL enabled

RTCSEC: RTC Seconds Register

REGISTER NAME

RTCSEC

0x68

2

I C Slave Address

Register Address

Reset Value

0x07

0x00

Access Type

Read/write

This is a double buﬀered register. Writes to this register are only uploaded to the RTC when UDR is set.

This register is only updated from the RTC when RDUDR is set.

Special Feature

Reset Condition

V

< V

RTCUVLO

RTC

BIT

6:0

7

BIT NAME

DESCRIPTION

DEFAULT

0000000

0

RTC Seconds Counter Register

In binary format (BCD = 0), valid values for B6 through B0 are 0 through 59.

In BCD format, valid data for B6 through B4 are 0 through 5, and valid data for B3

through B0 are 0 through 9.

SEC[6:0]

RSVD

Reserved

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RTCMIN: RTC Minutes Register

REGISTER NAME

RTCMIN

0x68

2

I C Slave Address

Register Address

Reset Value

0x08

0x00

Access Type

Read/write

This is a double buﬀered register. Writes to this register are only uploaded to the RTC when UDR is set.

This register is only updated from the RTC when RDUDR is set.

Special Feature

Reset Condition

V

< V

RTCUVLO

RTC

BIT

6:0

7

BIT NAME

DESCRIPTION

DEFAULT

0b0000000

0

RTC Minutes Counter Register

In binary format (BCD = 0), valid values for B6 through B0 are 0 through 59. In BCD

format (BCD = 1), valid data for B6 through B4 are 0 through 5, and valid data for B3

through B0 are 0 through 9.

MIN[6:0]

RSVD

Reserved

RTCHOUR: RTC Hours Register

REGISTER NAME

RTCHOUR

0x68

2

I C Slave Address

Register Address

Access Type

Reset Value

0x09

Read/write

0x01

This is a double buﬀered register. Writes to this register are only uploaded to the RTC when UDR is set.

This register is only updated from the RTC when RDUDR is set.

Special Feature

Reset Condition

V

< V

RTCUVLO

RTC

BIT

BIT NAME

DESCRIPTION

Default

RTC Hours Counter Register

Note that there would be two possibilities for values chosen for B5 through B0

depending on the current status of the HRMODE Bit:

If HRMODE = 1 (24Hr Mode)

Binary Mode (BCD = 0): B5 is zero, and B4 through B0 valid values are 0 through 23.

BCD Mode (BCD = 1): Valid values for B5 through B4 are 0 through 2, and valid values

for B3 through B0 are 0 through 9 (the full number does not exceed 23).

If HRMODE = 0 (12 Hr Mode)

5:0

HOUR[5:0]

0b000001

Binary Mode (BCD = 0): B5 and B4 are 0, and valid values for B3 through B0 are 1

through 12.

BCD Mode (BCD = 1): Valid values for B5 through B4 are 0 through 1, and valid values

for B3 through B0 are 0 through 9 (the full number does not exceed 12).

AM/PM Selection. AMPM is only valid when the clock is set for 12-hour mode

(HRMODE = 0). When the clock is set for 24-hour mode, this bit is a don’t care.

0 = AM

1 = PM

6

7

AMPM

RSVD

0

Reserved

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RTCDOW: RTC Day-of-Week Register

REGISTER NAME

RTCDOW

0x68

2

I C Slave Address

Register Address

Reset Value

0x0A

0x01

Access Type

Read/write

This is a double buﬀered register. Writes to this register are only uploaded to the RTC when UDR is set.

This register is only updated from the RTC when RDUDR is set.

Special Feature

Reset Condition

V

< V

RTCUVLO

RTC

BIT

0

BIT NAME

DESCRIPTION

DEFAULT

SUN

MON

TUE

WED

THU

FRI

1

0

Bits B6 through B0 each represent one day of the week. As such, only one bit is set

at a time.

1

B[6:0] = 000_0001 represents Sunday

B[6:0] = 000_0010 represents Monday

B[6:0] = 000_0100 represents Tuesday

B[6:0] = 000_1000 represents Wednesday

B[6:0] = 001_0000 represents Thursday

B[6:0] = 010_0000 represents Friday

B[6:0] = 100_0000 represents Saturday

2

3

4

5

6

SAT

7

RSVD

Reserved

RTCMONTH: RTC Month Register

REGISTER NAME

RTCMONTH

0x68

2

I C Slave Address

Register Address

Reset Value

0x0B

0x01

Access Type

Read/write

This is a double buﬀered register. Writes to this register are only uploaded to the RTC when UDR is

set. This register is only updated from the RTC when RDUDR is set.

Special Feature

Reset Condition

V

< V

RTCUVLO

RTC

BIT

4:0

7:5

BIT NAME

DESCRIPTION

Default

0b00001

0b000

RTC Months Counter Register

In Binary format (BCD = 0), valid values for B4 through B0 are 1 through 12. In BCD

format (BCD = 1), valid data for B4 is either 0 or 1, and valid data for B3 through B0 are

0 through 9 (the full value in BCD format does not exceed 12 and must be greater than

zero).

MONTH[4:0]

RSVD

Reserved

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RTCYEAR: RTC Year Register

REGISTER NAME

RTCYEAR

0x68

2

I C Slave Address

Register Address

Reset Value

0x0C

0x00

Access Type

Read/write

This is a double buﬀered register. Writes to this register are only uploaded to the RTC when UDR is set.

This register is only updated from the RTC when RDUDR is set.

Special Features

Reset Condition

V

< V

RTCUVLO

RTC

BIT

BIT NAME

DESCRIPTION

DEFAULT

RTC Years Counter Register

In Binary format (BDC = 0), valid values for B7 through B0 are 0 through 99.

In BCD format (BCD = 1), valid data for B7 through B4 are 0 through 9,

and similarly valid data for B3 through B0 are 0 through 9.

7:0

YEAR[7:0]

0b00000000

RTCDOM: RTC Day-of-Month Register

REGISTER NAME

RTCDOM

0x68

2

I C Slave Address

Register Address

Reset Value

0x0D

0x01

Access Type

Read/Write

This is a double buﬀered register. Writes to this register are only uploaded to the RTC when UDR is set.

This register is only updated from the RTC when RDUDR is set.

Special Features

Reset Condition

V

< V

RTCUVLO

RTC

BIT

5:0

7:6

BIT NAME

DESCRIPTION

DEFAULT

0b000001

0b000

RTC Days in a Month Register

In Binary format (BCD = 0), valid values for B5 through B0 are 1 through 31. In BCD

format (BCD = 1), valid data for B4 through B5 are 0 through 3, and valid data for B3

through B0 are 0 through 9 (the full value should be greater than 0 but not exceed

31).

Furthermore, there is a restriction on choosing the number of days in a month

according to the selected month and year as shown below:

For months 1, 3, 5, 7, 8, 10, and 12 the selected value for B5 through B0 must be 1

through 31.

For months 4, 6, 9, and 11 the selected value for B5 through B0 must be 1 through 30.

For month 2, or month of Feb., the selected value for B5 through B0 must be 1

through 28 for normal years, or must be 1 through 29 for leap years. Does not

account for solar years. Leap years are those that are evenly divisible by 4. 0, 4, 8, .

. . 24, 28, . . .72, 76 . . . 92, 96

DAY[5:0]

RSVD

Reserved

Note: It is the responsibility of the user to make sure that days selected for the month actually matches the intended

number of days in the month. For example, a user should not select 31 days for the months of February, April, June,

September, or November.

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RTCSECAx: RTC ALARMx Seconds Register

REGISTER NAME

RTCSECAx

2

I C Slave Address

0x68

0x0E for RTCSECA1

0x15 for RTCSECA2

Register Address

Reset Value

Access Type

0x00

Read/write

This is a double buﬀered register. Writes to this register are only uploaded to the RTC when UDR is

set. This register is only updated from the RTC when RDUDR is set.

Special Feature

Reset Condition

V

< V

RTCUVLO

RTC

BIT

BIT NAME

DESCRIPTION

Default

RTC Seconds Alarm Register

6:0

SECAx[6:0]

AESECAx

If the value of SECAx is equal to the value of SEC and AESECAx = 1, an RTCAx

alarm interrupt is generated.

0b0000000

Alarm Enable Control

0 = Alarm disable

1 = Alarm enable

7

0

RTCMINAx: RTC ALARMx Minutes Register

REGISTER NAME

RTCMINAx

2

I C Slave Address

0x68

0x0F for RTCMINA1

0x16 for RTCMINA2

Register Address

Reset Value

Access Type

0x00

Read/write

This is a double buﬀered register. Writes to this register are only uploaded to the RTC when UDR is

set. This register is only updated from the RTC when RDUDR is set.

Special Feature

Reset Condition

V

< V

RTCUVLO

RTC

BIT

BIT NAME

DESCRIPTION

DEFAULT

RTC Minutes Alarm Register

6:0

MINAx[6:0]

AEMINAx

If the value of MINAx is equal to the value of MIN and AEMINAx is 1, an RTCAx alarm

interrupt is generated.

0b0000000

Alarm Enable Control

0 = Alarm disable

1 = Alarm enable

7

0

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RTCHOURAx: RTC ALARMx Hours Register

REGISTER NAME

RTCHOURAx

2

I C Slave Address

0x68

0x10 for RTCHOURA1

0x17 for RTCHOURA2

Register Address

Reset Value

Access Type

0x00

Read/write

This is a double buﬀered register. Writes to this register are only uploaded to the RTC when UDR is set.

This register is only updated from the RTC when RDUDR is set.

Special Feature

Reset Condition

V

< V

RTCUVLO

RTC

BIT

BIT NAME

DESCRIPTION

DEFAULT

RTC Hours Alarm Register

If the value of HOURAx is equal to the value of HOUR and AEHOURAx is 1, an

RTCAx alarm interrupt is generated.

If HRMODE = 1 (24-hr mode)

Binary mode: B5 is zero, and B4 through B0 valid values are 0 through 23.

BCD mode: Valid values for B5 through B4 are 0 through 2, and valid values for B3

through B0 are 0 through 9 (the full number should not exceed 23).

If HRMODE = 0 (12-hr mode)

5:0

HOURAx[5:0]

0b000000

Binary mode: B5 and B4 are 0, and valid values for B3 through B0 are 1 through 12.

BCD mode: Valid values for B5 through B4 are 0 through 1, and valid values for B3

through B0 are 0 through 9 (the full number should not exceed 12).

AM/PM selection, only valid during 12-hr mode.

6

7

AMPMAx

0 = AM

1 = PM

0

Alarm Enable Control

0 = Alarm disable

1 = Alarm enable

AEHOURAx

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RTCDOWA1: RTC ALARMx Day-of-Week Register

REGISTER NAME

RTCDOWAx

2

I C Slave Address

0x68

0x11 for RTCDOWA1

0x18 for RTCDOWA2

Register Address

Reset Value

Access Type

0x01

Read/write

This is a double buﬀered register. Writes to this register are only uploaded to the RTC when UDR is set.

This register is only updated from the RTC when RDUDR is set.

Special Feature

Reset Condition

V

< V

RTCUVLO

RTC

BIT

0

BIT NAME

DESCRIPTION

DEFAULT

SUNAx

MONAx

TUEAx

WEDAx

THUAx

FRIAx

1

0

RTC Day Of Week Alarm Register

If the value of RTCDOWAx is equal to the value of DOW and AEDOWAx is 1, an

RTCAx alarm interrupt is generated.

1

2

3

Bits B6 through B0 each represents one day of the week. This would dictate that only

one bit at a time is allowed to be set as shown below:

B[6:0] = 0b000_0001 represents Sunday

4

5

B[6:0] = 0b000_0010 represents Monday

B[6:0] = 0b000_0100 represents Tuesday

B[6:0] = 0b000_1000 represents Wednesday

B[6:0] = 0b001_0000 represents Thursday

B[6:0] = 0b010_0000 represents Friday

6

7

SATAx

0

B[6:0] = 0b100_0000 represents Saturday

Alarm Enable Control

0 = Alarm disable

1 = Alarm enable

AEDOWAx

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RTCMONTHAx: RTC ALARMx Month Register

REGISTER NAME

RTCMONTHAx

2

I C Slave Address

0x68

0x12 for RTCMONTHA1

0x19 for RTCMONTHA2

Register Address

Reset Value

Access Type

0x01

Read/write

This is a double buﬀered register. Writes to this register are only uploaded to the RTC when UDR is

set. This register is only updated from the RTC when RDUDR is set.

Special Feature

Reset Condition

V

< V

RTCUVLO

RTC

BIT

4:0

6:5

7

BIT NAME

DESCRIPTION

DEFAULT

0b00001

0b00

RTC Month Alarm Register

If the value of MONTHAx is equal to the value of MONTH and AEMONTHAx is 1, an

RTCAx alarm interrupt is generated.

MONTHAx[4:0]

RSVD

Reserved

Alarm Enable Control

0 = Alarm disable

1 = Alarm enable

AEMONTHAx

0

RTCYEARAx: RTC ALARMx Year Register

REGISTER NAME

RTCYEARAx

2

I C Slave Address

0x68

0x13 for RTCYEARA1

0x1A for RTCYEARA2

Register Address

Reset Value

Access Type

0x00

Read/write

This is a double buﬀered register. Writes to this register are only uploaded to the RTC when UDR is

set. This register is only updated from the RTC when RDUDR is set.

Special Features

Reset Condition

V

< V

RTCUVLO

RTC

BIT

BIT NAME

DESCRIPTION

DEFAULT

RTC Year Alarm Register

6:0

YEARAx[6:0]

AEYEARAx

If the value of YEARAx is equal to the value of YEAR and AEYEARAx is 1, an

RTCAx alarm interrupt is generated.

0b0000000

Alarm Enable Control

0 = Alarm disable

1 = Alarm enable

7

0

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RTCDOMAx: RTC ALARMx Day-of-Month Register

REGISTER NAME

RTCDOMAx

2

I C Slave Address

0x68

0x14 for RTCDOMA1

0x1B for RTCDOMA2

Register Address

Reset Value

Access Type

0x01

Read/write

This is a double buﬀered register. Writes to this register are only uploaded to the RTC when UDR is

set. This register is only updated from the RTC when RDUDR is set.

Special Feature

Reset Condition

V

< V

RTCUVLO

RTC

BIT

5:0

6

BIT NAME

DESCRIPTION

DEFAULT

RTC Day Of Month Alarm 1 Register

If the value of DAYAx is equal to the value of DAY and AEDAYAx is 1, an

RTCAx alarm interrupt is generated.

DAYAx[5:0]

RSVD

0b000001

Reserved

0

Alarm Enable Control

0 = Alarm disable

1 = Alarm enable

7

AEDAYAx

Note: It is the responsibility of the user to make sure that days selected for the month actually matches the intended

number of days in the month. For example, a user should not select 31 days for the months of February, April, June,

September, or November.

RTC Block Issues

Issue 1: Does not account for solar year which induces a calendar error on Feb 29, 2100.

Issue 2: Does not allow alarms in BCD to be set past year 2079.

Issue 3: Does not have ability to set the century. This is not necessarily a problem but it means that the host has to

control the century.

Pedigree

The RTC is shared between the PR83, PR80, and PQ63. PR61 and PR77 use a very similar RTC.

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CNFG1_32K: 32kHz Oscillator Configuration 1

REGISTER NAME

CNFG1_32K

2

I C Slave Address

0x3C

Register Address

Reset Value

0x03

0b x1xx 11xx (“x” is an OTP bit)

Read/write

Access Type

B[7:4] are reset by V

B[3:0] are reset by V

< V

RTC

RTCUVLO

Reset Condition

or global shutdown

BIT

B7

BIT NAME

DESCRIPTION

DEFAULT

Status of Crystal Driver Output

0 = Output frequency is not OK.

1 = Output frequency is OK.

This is read only.

32K_OK

0

1

B6

Reserved

Crystal Driver Load Capacitance

0b00 = 12pF per node

B[5:4]

32KLOAD[1:0]

0b01 = 22pF per node

xx

0b10 = No internal load cap selected

0b11 = 10pF per node

B3

B2

Reserved

1

32kHz Oscillator Output Enable

0 = Disabled

32K_OUT0_EN

1 = Enabled

32kHz Oscillator Mode of Operation

0b00 = Low-power mode

0b01 = Global low-power mode. The oscillator operates in low-jitter mode when

the global low-power mode signal is low. When the global low-power mode

signal is high, the oscillator operates in low-power mode.

0b10 = Same as 0b00

B[1:0]

PWR_MD_32K[1:0]

xx

0b11 = Low-jitter mode

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CNFGBBC: Backup Battery Configuration Register

REGISTER NAME

CNFGBBC

0x3C

2

I C Slave Address

Register Address

Reset Value

0x04

0x41

Access Type

Read/write

Reset Condition

V

< V

RTC RTCUVLO

BIT

BIT NAME

DESCRIPTION

Default

Output Resistor

0x00 = 0.1kΩ0x01 = 1kΩ

0x02 = 3kΩ

7:6

BBCRS[1:0]

0b01

0x03 = 6kΩ

Low Charging Current Enable

0 = Enable

5

BBCLOWIEN

0

1 = Disable

Charging Voltage Limit Setting

0x00 = 2.5V

4:3

BBCVS[1:0]

0x01 = 3.0V

0b00

0x02 = 3.3V

0x03 = 3.5V

Charging Current Setting

BBCLOWIEN = 0

0x00 = 50ΜA

0x01 = 50μA

0x02 = 50μA

2:1

BBCCS[1:0]

0x03 = 100μA

BBCLOWIEN = 1

0x00 = 200μA

0x01 = 600μA

0x10 = 800μA

0x11 = 400μA

0b00

Backup Battery Charger Enable

0 = Backup battery charger oﬀ

1 = Backup battery charger on

0

BBCEN

1

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ONOFFCNFG1: On/Off Controller Configuration Register 1

REGISTER NAME

ONOFFCNFG1

0x3C

2

I C Slave Address

Register Address

Reset Value

0x41

0b 0xxx x00x (“x” is an OTP bit)

Read/write

Access Type

Reset Condition

Global shutdown

BIT

NAME

DESCRIPTION

Software Reset. See Figure 4 for a ﬂow diagram.

0 = No action

1 = Generates a global shutdown event that initiates the FPS0 and FPS1 power-down event

and generates a reset.

B7

SFT_RST

If both SFT_RST and PWR_OFF are set, the resulting action is SFT_RST. See the SFT_RST

and PWR_OFF Logic table.

B6

RSVD

Reserved. Write 1. Read is don’t care.

Manual Reset Time

0b000 = 2s

0b001 = 3s

0b010 = 4s

0b011 = 5s

0b100 = 6s

0b101 = 8s

0b110 = 10s

0b111 = 12s

B[5:3]

MRT[2:0]

Sleep Enable

0 = Pulling EN1 low does not place the AP into sleep mode

1 = Clears the latch that enables FPS1 from a wakeup event (“WAKE”). With this latch clear,

the AP can be placed into sleep mode by pulling EN1 low.

B2

SLPEN

SLPEN is automatically cleared when the MAX77863 “OFF” signal rises or when a wakeup

event occurs.

Power Oﬀ. See Figure 4

0 = No action

1 = Generates a global shutdown event that initiates the FPS0 and FPS1 power-down event

but does not generate a reset. Note that PWR_OFF is cleared at the end of any global

shutdown event that it generates.

If both SFT_RST and PWR_OFF are set, the resulting action is SFT_RST. See the SFT_RST

and PWR_OFF Logic table.

B1

B0

PWR_OFF

EN0DLY

EN0 Delay

0 = The only delay for EN0 is the debounce circuit.

1 = In addition to the debounce circuit, there is an addition 1 second delay for EN0.

SFT_RST and PWR_OFF Logic

SFT_RST

PWR_OFF

BEHAVIOR

0

1

0

1

0

1

No action

Power oﬀ function

Software reset function

Reserved

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ONOFFCNFG2: On/Off Controller Configuration Register 2

REGISTER NAME

ONOFFCNFG2

0x3C

2

I C Slave Address

Register Address

Reset Value

0x42

0b 000x x111

Read/write

Global shutdown

Access Type

Reset Condition

BIT

NAME

DESCRIPTION

Automatic Wakeup Due To Software Reset (Figure 4)

0 = Setting SFT_RST results in a power down and default oﬀ state where the device waits

for a wakeup event.

B7

B6

SFT_RST_WK

WD_RST_WK

1 = Setting SFT_RST results in a power cycle and the default on state.

Automatic Wakeup Due To System Watchdog Reset (Figure 4)

0 = A system watchdog timer expiring results in a power down and default-oﬀ state where the

device waits for a wakeup event.

1 = a system watchdog time expiring results in a power cycle and the default on state

Active-Low, Low-Power Mode During Sleep Mask Bit

0 = Masked. EN1 cannot aﬀect EN1_LPM and LPM_BUS.

1 = Unmasked. If the IC is not asserting RSO the EN1 signal can aﬀect

EN1_LPM and LPM_BUS. See Figure 8 for the simpliﬁed logic.

B5

nSLP_LPM_MSK

nSLP_LPM_MSK is automatically cleared when the MAX77863 “OFF” signal rises.

Wakeup on ACOK

B4

B3

B2

B1

B0

WK_ACOK

WK_LID

0 = An ACOK event does not generate a wakeup signal.

1 = An ACOK event generates a wakeup signal.

Wakeup on LID

0 = A LID event does not generate a wakeup signal.

1 = A LID event generates a wakeup signal.

Wakeup on ALARM1_R

0 = An ALARM1_R event does not generate a wakeup signal.

1 = An ALARM1_R event generates a wakeup signal.

WK_ALARM1R

WK_ALARM2R

WK_EN0

Wakeup on ALARM2_R

0 = An ALARM2_R event does not generate a wakeup signal.

1 = An ALARM2_R event generates a wakeup signal.

Wakeup on EN0

0 = An EN0 event does not generate a wakeup signal.

1 = An EN0 event generates a wakeup signal.

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ONOFFIRQ: On/Off Controller Interrupt Register

REGISTER NAME

ONOFFIRQ

0x3C

2

I C Slave Address

Register Address

Reset Value

0x0B

0x00

Access Type

Read

Special Features

Reset Condition

Clear on read

Global shutdown

BIT

NAME

DESCRIPTION

DEFAULT

ACOK Rising Interrupt

B7

ACOK_R

0 = No ACOK rising edges have occurred since the last time this bit was read.

1 = An ACOK rising edge as occurred since the last time this bit was read.

0

ACOK Falling Interrupt

B6

B5

B4

B3

B2

B1

ACOK_F

LID_R

0 = No ACOK falling edges have occurred since the last time this bit was read.

1 = An ACOK falling edge as occurred since the last time this bit was read.

0

LID Rising Interrupt

0 = No LID rising edges have occurred since the last time this bit was read.

1 = An LID rising edge as occurred since the last time this bit was read.

LID Falling Interrupt

0 = No LID falling edges have occurred since the last time this bit was read.

1 = An LID falling edge as occurred since the last time this bit was read.

LID_F

EN0 Rising Interrupt

0 = No EN0 rising edges have occurred since the last time this bit was read.

1 = An EN0 rising edge as occurred since the last time this bit was read.

EN0_R

EN0 Falling Interrupt

0 = No EN0 falling edges have occurred since the last time this bit was read.

1 = An EN0 falling edge as occurred since the last time this bit was read.

EN0_F

EN0 Active for 1s Interrupt

0 = EN0 has not been active for 1 second since the last time this bit was read.

1 = EN0 has been active for 1 second since the last time this bit was read.

EN0_1SEC

Manual Reset Warning Interrupt

The time for the hard power oﬀ warning is one setting shorter than what is programmed

by MRT[2:0] (i.e., HRDPOW[2:0]-1). When MRT[2:0] = 0b000, MRWRN is essentially a

don’t care.

B0

MRWRN

0

0 = EN0 has not been active for MRT[2:0]-1 since the last time this bit was read.

1 = EN0 has been active for MRT[2:0]-1 since the last time this bit was read.

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Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

ONOFFIRQM: On/Off Controller Interrupt Mask Register

REGISTER NAME

ONOFFIRQM

0x3C

2

I C Slave Address

Register Address

Reset Value

0x12

0x00

Access Type

Read/write

Global shutdown

Reset Condition

BIT

NAME

DESCRIPTION

DEFAULT

ACOK Rising Interrupt Mask

0 = Unmasked

1 = Masked

B7

B6

B5

B4

B3

B2

B1

B0

ACOK_RM

ACOK_FM

LID_RM

0

ACOK Falling Interrupt Mask

0 = Unmasked

1 = Masked

0

LID Rising Interrupt Mask

0 = Unmasked

1 = Masked

LID Falling Interrupt Mask

0 = Unmasked

1 = Masked

LID_FM

EN0 Rising Interrupt Mask

0 = Unmasked

1 = Masked

EN0_RM

EN0 Falling Interrupt Mask

0 = Unmasked

1 = Masked

EN0_FM

EN0 Active for 1s Interrupt Mask

0 = Unmasked

1 = Masked

EN0_1SECM

MRWRNM

Manual Reset Warning Interrupt Mask

0 = Unmasked

1 = Masked

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8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

ONOFFSTAT: On/Off Controller Status Register

REGISTER NAME

ONOFFSTAT

0x3C

2

I C Slave Address

Register Address

Reset Value

0x15

0x00

Access Type

Read

Reset Condition

Global shutdown

BIT

NAME

DESCRIPTION

Reserved

DEFAULT

B[7:3]

0b00000

EN0 Input Status

For OTP_EN0AL = 0

0 = EN0 is not active (logic low).

1 = EN0 is active (logic high).

B2

B1

B0

EN0

0

For OTP_EN0AL = 1

0 = EN0 is not active (logic high).

1 = EN0 is active (logic low).

ACOK Input Status

For OTP_ACOKAL = 0

0 = ACOK is not active (logic low).

1 = ACOK is active (logic high).

ACOK

For OTP_ACOKAL = 1

0 = ACOK is not active (logic high).

1 = ACOK is active (logic low).

LID Input Status

For OTP_LIDAL = 0

0 = LID is not active (logic low).

1 = LID is active (logic high).

LID

For OTP_LIDAL = 1

0 = LID is not active (logic high).

1 = LID is active (logic low).

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Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

NVERC: Non-Volatile Event Recorder

REGISTER NAME

NVERC

0x3C

2

I C Slave Address

Register Address

Reset Value

0x0C

0x40

Access Type

Read only

Clear on read

Special Features

Reset Condition

V

< V

RTCUVLO

RTC

BIT

BIT NAME

DESCRIPTION

Shutdown Due to Reset Input

DEFAULT

B7

RSTIN

0 = The reset input signal (RSI) did not cause a global shutdown.

1 = The reset input signal (RSI) caused a global shutdown.

0

Shutdown Due to Main-Battery Undervoltage Lockout

0 = Main-battery did not cause a global shutdown.

1 = The main-battery caused a global shutdown by falling below its UVLO threshold

B6

B5

MBU

MBO

1

0

(V

< V

). If the sudden momentary power loss (SMPL) function is

MBATT

MBATTUVLO

enabled, the PMIC can automatically recover from a momentary power loss.

See the Voltage Monitors section for more information.

Shutdown Due to Main-Battery Overvoltage Lockout

0 = Main-battery did not cause a global shutdown.

1 = The main-battery caused a global shutdown by rising above its OVLO threshold

(V

< V

).

MBATT

MBATTOVLO

Shutdown Due to Main-Battery Low

B4

B3

B2

B1

B0

MBLSD

TOVLD

HDRST

WTCHDG

SHDN

0 = Main-battery low did not cause a global shutdown.

1 = Main-battery low caused a global shutdown because MBLPD is set and V

0

< V

.

MON

MONL

Shutdown Due to Junction Temperature Overload

0 = the junction temperature did not cause a global shutdown

1 = the junction temperature caused a global shutdown by rising above T

JSHDN.

Shutdown Due to Hard-Reset (a.k.a. Manual Reset)

0 = The hard-reset function did not cause a global shutdown.

1 = The hard-reset function caused a global shutdown.

Shutdown Due to System Watchdog Timer

0 = The system watchdog timer did not cause a global shutdown.

1 = The system watchdog timer caused a global shutdown.

Shutdown Due to Shutdown Pin (SHDN)

0 = The shutdown pin did not cause a global shutdown.

1 = The shutdown pin caused a global shutdown.

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Multicore Applications

NVERC: Non-Volatile Event Recorder (continued)

REGISTER

ADDRESS

B0

NAME

B7

B6

B5

B4

B3

B2

B1

(HEX)

0x43

0x44

0x45

0x4F

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

CNFGFPS0

CNFGFPS1

CNFGFPS2

FPS_SD0

RSVD

TFPS0[2:0]

TFPS1[2:0]

SRCFPS0[1:0]

SRCFPS1[1:0]

SRCFPS2[1:0]

ENFPS0

ENFPS1

ENFPS2

TFPS2[2:0]

FPSSRC_SD0[1:0]

FPSSRC_SD1[1:0]

FPSSRC_SD2[1:0]

FPSSRC_SD3[1:0]

FPSPU_SD0[2:0]

FPSPU_SD1[2:0]

FPSPU_SD2[2:0]

FPSPU_SD3[2:0]

RSVD

FPSPD_SD0[2:0]

FPS_SD1

FPSPD_SD1[2:0]

FPSPD_SD2[2:0]

FPSPD_SD3[2:0]

RSVD RSVD

FPS_SD2

FPS_SD3

FPS_SD4

RSVD

FPS_GPIO1

FPS_GPIO2

FPS_GPIO3

FPS_RSO

FPSSRC_GPIO1[1:0]

FPSSRC_GPIO2[1:0]

FPSSRC_GPIO3[1:0]

FPSSRC_RSO[1:0]

FPSPU_GPIO1[2:0]

FPSPU_GPIO2[2:0]

FPSPU_GPIO3[2:0]

FPSPU RSO[2:0]

FPSPD_GPIO1[2:0]

FPSPD_GPIO2[2:0]

FPSPD_GPIO3[2:0]

FPSPD_RSO[2:0]

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Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

CNFGFPSx : Flexible Power Sequencing x Master Configuration Register

This register contains the configuration information for the flexible power sequencing master timer x configuration.

REGISTER NAME

CNFGFPS0/1

2

I C Slave Address

0x3C

0x43: CNFGFPS0

0x44: CNFGFPS1

Register Address

Reset Value

0b 00xx xxxx (“x” is an OTP bit)

Read/write

Access Type

Special Features

Reset Condition

Global shutdown

BIT

NAME

DESCRIPTION

MSB

B7

Reserved for future use.

B6

B5

Timer Period. Speciﬁes the time period between each sequencer event.

0x00 = 0b000 = 40µs

0x04 = 0b100 = 640µs

B4

0x01 = 0b001 = 80µs

0x05 = 0b101 = 1,280µs

TFPSx[2:0]

0x02 = 0b010 = 160µs

0x06 = 0b110 = 2,560µs

B3

0x03 = 0b011 = 320µs

0x07 = 0b111 = 5,120µs

Enable Source. Speciﬁes the enable source for the sequencer.

0b00 = EN0 hardware input

0b01 = EN1 hardware input

0b10 = ENFPSx software bit

0b11 = Reserved

B2

B1

SRCFPSx[1:0]

ENFPSx

Software Enable

0 = Disable FPS0/1

1 = Enable FPS0/1

LSB

B0

X = ENFPSx is a don’t care if SRCFPS0/1[1:0]≠0b10

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CNFGFPSx : Flexible Power Sequencing x Master Configuration Register (continued)

REGISTER NAME

CNFGFPS2

2

I C Slave Address

0x3C

Register Address

Reset Value

0x45: CNFGFPS2

0b 00xx xxxx (“x” is an OTP bit)

Read/Write

Access Type

Special Features

Reset Condition

Global Shutdown

BIT

NAME

DESCRIPTION

MSB

B7

Reserved for future use.

B6

Reserved for future use.

Timer Period.

B5

Speciﬁes the time period between each sequencer event.

0x00 = 0b000 = 40µs

0x01 = 0b001 = 80µs

0x02 = 0b010 = 160µs

0x03 = 0b011 = 320µs

0x04 = 0b100 = 640µs

0x05 = 0b101 = 1,280µs

0x06 = 0b110 = 2,560µs

0x07 = 0b111 = 5,120µs

B4

B3

B2

B1

TFPS2[2:0]

Enable Source. Speciﬁes the enable source for the sequencer.

0b00 = FPS2 enable follows FPS0

0b01 = FPS2 enable follows FPS1

0b10 = ENFPS2 software bit

SRCFPS2[1:0]

ENFPS2

0b11 = Reserved

Software Enable

0 = Disable FPS2

1 = Enable FPS2

LSB

B0

X = ENFPS2 is a don’t care if SRCFPS2[1:0]≠0b10

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Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

FPS_x: Flexible Power Sequencing Slave Configuration Register (FPSx)

This register contains the configuration information for the flexible power sequencing slave configuration register x.

REGISTER NAME

FPS_x

2

I C Slave Address

0x3C

Register Address

Reset Value

18 total FPSx registers–0x46 to 0x57

0b xxxx xxxx (“x” is an OTP bit)

Read/write

Access Type

Special Features

Reset Condition

Global shutdown

BIT

NAME

DESCRIPTION

Regulator Flexible Power Sequencer Source

0b00 = FPS0

0b01 = FPS1

0b10 = FPS2

B[7:6]

FPSSRCx[1:0]

0b11 = Not conﬁgured as part of a ﬂexible power sequence:

The LDO enables are controlled by PWR_MD_Lx.

The step-down regulator enables are controlled by PWR_MD_SDx.

nRST_IO is transparent with respect to the ﬂexible power sequencers.

Regulator Flexible Power Sequencer Power Up Period. Speciﬁes the power up time

slots.

0x0 = 0b000 = 0

0x1 = 0b001 = 1

0x2 = 0b010 = 2

0x3 = 0b011 = 3

0x4 = 0b100 = 4

0x5 = 0b101 = 5

0x6 = 0b110 = 6

0x7 = 0b111 = 7

B[5:3]

FPSPUx[2:0]

Regulator Flexible Power Sequencer Power Up Period. Speciﬁes the power up time

slots.

0x0 = 0b000 = 0

0x1 = 0b001 = 1

0x2 = 0b010 = 2

0x3 = 0b011 = 3

0x4 = 0b100 = 4

0x5 = 0b101 = 5

0x6 = 0b110 = 6

0x7 = 0b111 = 7

B[2:0]

FPSPDx[2:0]

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Complete System PMIC, Featuring 13 Regulators,

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Multicore Applications

Typical Application Circuit

AVSD

INA_SD0

V_{MBA TT}

V_SD2

1µF

IN_LDO0-1

IN_LDO2

4.7µF

6.3V

0402

0603

1µH > 4A

PGND

GND

LXA_SD0

PGA_SD0

V_SD0

22µF

6.3V

0805

V_{MBA TT}

IN_LDO3-5

IN_LDO4-6

0.6V TO 1.4V

6A CONTINUOUS

8A PEAK

1µF

6.3V

0402

PGND

INB_SD0

V_{MBA TT}

GND

4.7µF

6.3V

0603

V_SD3

IN_LDO7-8

1µF

6.3V

0402

1µH > 4A

PGND

LXB_SD0

PGB_SD0

MAX77863

22µF

6.3V

0805

0.8 TO 2.35V AT 150mA

0.8 TO 3.95V AT 150mA

0.8 TO 3.95V AT 300mA

0.8 TO 1.58V AT 150mA

0.8 TO 3.95V AT 150mA

0.8 TO 2.35V AT 450mA

0.8 TO 2.35V AT 300mA

V_LDO0

OUT_LDO0

OUT_LDO1

OUT_LDO2

OUT_LDO3

OUT_LDO4

OUT_LDO5

OUT_LDO6

OUT_LDO7

OUT_LDO8

FB_SD0

SNSP_SD0

SNSN_SD0

PGND

22µF

4V

V_LDO1

V_LDO2

V_LDO3

V_LDO4

V_LDO5

V_LDO6

V_LDO7

V_LDO8

ALL LDOs

UTIL IZE THE

POINT-OF-

LOAD

CAPACITOR

FOR

LOAD

0603

IN_SD1

V_{MBA TT}

2.2µF

6.3V

0603

PGND

1µH > 3A

PGND

STABILITY

LX_SD1

PG_SD1

V_SD1

22µF

6.3V

0805

0.6V TO 1.55V AT 3A

MON

MBA TT

FB_SD1

SNSP_SD1

SNSN_SD1

PGND

22µF

V_{MBA TT}

LOAD

4V

0.1µF

0603

6.3V

0402

1S2P

Li+ OR

Li-POLY

GND

IN_SD2

V_{MBA TT}

2.2µF

6.3V

GND

PGND

0603

PGND

BBATT

XOUT

1µH > 2.5A

PGND

0.1µF

6.3V

0402

LX_SD2

PG_SD2

V_SD2

LITHIUM

MANGANESE

22µF

6.3V

0603

0.6V TO 3.38V AT 2A

10µF

6.3V

0603

FB_SD2

IN_SD3

PGND

LOAD

GND

XIN

XGND

V_{MBA TT}

2.2µF

6.3V

0603

PGND

GND

1µH > 2.5A

PGND

32kHz_OUT

V_SD2

32k_OUT0

INI2C

LX_SD3

PG_SD3

V_SD3

22µF

6.3V

0603

0.6V TO 3.38V AT 2A

0.1µF

6.3V

0402

10µF

6.3V

0603

FB_SD3

PGND

LOAD

GND

SDA

SCL

nIRQ

SDA

SCL

nIRQ

GPIO_INA

GPIO0

GPIO1

GPIO2

GPIO3

V_{MBA TT}

0.1µF

PGND

GPIO0

GPIO1

GPIO2

GPIO3

6.3V

0402

GND

EN0

EN1

EN2

GPIO_INB

GPIO4

GPIO5

GPIO6

GPIO7

V_SD2

0.1µF

6.3V

0402

GPIO4

GPIO5

GPIO6

GPIO7

D_SD3

GND

FROM UP THERMAL SENSOR

FROM SYSTEM’S BATTERY CHARGER

FROM SYSTEM’S BATTERY DOOR

SHDN

ACOK

LID

V_SD2

100k

nRST_IO

nRESET_OUT

RESET

BUTTON

NICx

GND

XGND PGND

GND

Figure 40. MAX77863 Typical Application Circuit for 1s Battery Configuration

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Typical Application Circuit (continued)

AC-TO-DC ADAPTER

BATTERY

EN_5V0

STEP-D OW N

REGULATOR

CHARGER

MBA TT

LOW-I_QLDO

2S1P

Li+ OR

Li-POLY

V_SD2

IN_LDO0-1

IN_LDO2

AVSD

INA_SD0

SD5V0

1µF

6.3V

0402

4.7µF

6.3V

SD5V0

0603

1µF

6.3V

0402

PGND

V_SD3

GND

1µH > 4A

IN_LDO3-5

IN_LDO4-6

1µF

6.3V

0402

LXA_SD0

PGA_SD0

V_SD0

GND

22µF

6.3V

0805

0.6V TO 1.4V

6A CONTINUOUS

8A PEAK

GND

IN_LDO7-8

PGND

0.8 to 2.35V at 150mA

0.8 to 3.95V at 150mA

0.8 to 3.95V at 300mA

0.8 to 1.58V at 150mA

0.8 to 3.95V at 150mA

0.8 to 2.35V at 450mA

0.8 to 2.35V at 300mA

VLDO0

VLDO1

VLDO2

VLDO3

VLDO4

VLDO5

VLDO6

VLDO7

VLDO8

OUT_LDO0

OUT_LDO1

OUT_LDO2

OUT_LDO3

OUT_LDO4

OUT_LDO5

OUT_LDO6

OUT_LDO7

OUT_LDO8

INB_SD0

SD5V0

4.7µF

6.3V

0603

ALL LDOs

UTIL IZE THE

POINT-OF-

LOAD

CAPACITOR

FOR

MAX77863

1µH > 4A

PGND

LXB_SD0

PGB_SD0

22µF

6.3V

0805

PGND

FB_SD0

SNSP_SD0

SNSN_SD0

PGND

STABILITY

22µF

4V

0603

LOAD

MON

MBA TT

IN_SD1

SD5V0

0.1µF

PGND

2.2µF

6.3V

0603

GND

6.3V

0402

GND

1µH > 3A

GND

PGND

LITHIUM

MANGANESE

0.1µF

6.3V

0402

BBATT

XOUT

XIN

LX_SD1

PG_SD1

V_SD1

22µF

6.3V

0805

0.6V TO 1.55V AT 3A

PGND

XGND

FB_SD1

SNSP_SD1

SNSN_SD1

GND

PGND

22µF

GND

32KHZ_OUT

LOAD

4V

0603

32k_OUT0

INI2C

VSD2

0.1µF

6.3V

0402

IN_SD2

SD5V0

PGND

2.2µF

6.3V

0603

GND

1µH > 2.5A

PGND

SDA

SCL

nIRQ

SDA

SCL

nIRQ

LX_SD2

PG_SD2

V_SD2

22µF

6.3V

0603

0.6V TO 3.38V AT 2A

10µF

6.3V

0603

EN0

EN1

EN2

FB_SD2

IN_SD3

LOAD

PGND

SD5V0

D_SD3

2.2µF

6.3V

0603

GND

PGND

FROM UP THERMAL SENSOR THERM

FROM SYSTEM’S BATTERY CHARGER

FROM SYSTEM’S BATTERY DOOR

SHDN

ACOK

LID

1µH > 2.5A

PGND

ACOK

LID

LX_SD3

PG_SD3

V_SD3

22µF

6.3V

0603

0.6V TO 3.38V AT 2A

GPIO_INA

GPIO0

GPIO1

GPIO2

GPIO3

10µF

6.3V

0603

FB_SD3

NICx

0.1µF

6.3V

0402

GPIO0

GPIO1

EN_5V0

GPIO3

LOAD

PGND

GND

100k

PGND

V_SD2

GPIO_INB

GPIO4

GPIO5

GPIO6

GPIO7

0.1µF

6.3V

0402

GPIO4

GPIO5

GPIO6

GPIO7

nRST_IO

nRESET_OUT

RESET

BUTTON

GND

XGND PGND

GND

Figure 41. MAX77863 Typical Application Circuit for 2s Battery Configurations

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Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Ordering Information

PART

PIN-PACKAGE

OPTIONS

90-WLP, 0.4mm Pitch,

10 x 9 Array, 4.1mm x 3.8mm x 0.7mm

4 DC-to-DC

OTP Version CID4 = 0x01

MAX77863AEWJ+T

All devices are specified over the -40°C to +85°C ambient operating temperature range.

+Denotes a lead(Pb)-free/RoHS-compliant package.

T = Table and reel.

Package Information

For the latest package outline information and land patterns

(footprints), go to www.maximintegrated.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status

only. Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

PACKAGE

TYPE

PACKAGE OUTLINE

LAND

PATTERN NO.

CODE

NO.

90 Bump,

WLP

0.4mm Pitch,

10 x 9 Array

4.1 x 3.8 x

0.7mm

Maxim’s

Application

Note 1891:

Wafer-Level

Package (WLP)

W903A4+1

21-0573

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Complete System PMIC, Featuring 13 Regulators,

8 GPIOs, RTC, and Flexible Power Sequencing for

Multicore Applications

Revision History

REVISION REVISION

PAGES

CHANGED

DESCRIPTION

NUMBER

DATE

0

1

9/19

Initial release

—

2/20

Fixed typo in title

1–183

For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and speciﬁcations without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

©

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

2020 Maxim Integrated Products, Inc.

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型号：	MAX77863AEWT
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Complete System PMIC, Featuring 13 Regulators, 8 GPIOs, RTC, and Flexible Power Sequencing for Multicore Applications 集成电源管理电路
文件：	总183页 (文件大小：3022K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX77863AEWT [MAXIM]

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