MAX8566_11 [MAXIM]
High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator 32-Lead TQFN Package; 高效率， 10A ， PWM内置开关降压稳压器的32引脚TQFN封装
| 型号： | MAX8566_11 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator 32-Lead TQFN Package |
| 文件： | 总20页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3690; Rev 3; 3/11
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
MAX856
General Description
Features
o Internal 8mΩ On-Resistance MOSFETs
The MAX8566 high-efficiency switching regulator deliv-
ers up to 10A load current at output voltages from 0.6V
o 10A Output PWM Step-Down Regulator
to (0.87 x V ). The IC operates from 2.3V to 3.6V input
IN
o
1% Output Accuracy over Load, Line, and
supplies, making it ideal for point-of-load applications.
The total output-voltage set error is less than 1ꢀ over
load, line, and temperature.
Temperature
o Operates from 2.3V to 3.6V Input Supply
o Adjustable Output from 0.6V to (0.87 x V )
IN
The MAX8566 operates in pulse-width-modulation
(PWM) mode with a 250kHz to 2.4MHz switching fre-
quency range that is programmable by an external
resistor. The IC can be synchronized to an external
clock in the same frequency range using the SYNC
input. The high operating frequency minimizes the size
o 250kHz to 2.4MHz Adjustable Frequency or SYNC
Input
o Allows All-Ceramic-Capacitor Design
o SYNCOUT Drives 2nd Regulator 180° Out-of-Phase
o Prebiased or Monotonic Soft-Start
o Programmable Soft-Start Time
of external components. Using low-R
n-channel
DS(ON)
MOSFETs for both high- and low-side switches main-
tains high efficiency at both heavy-load and high-
switching frequencies.
o Output Tracking or Sequencing
o Sourcing and Sinking Output Current
o Power-Good Output
The MAX8566 employs a voltage-mode control archi-
tecture with a high-bandwidth (> 10MHz) error amplifi-
er. The voltage-mode control architecture makes
switching frequencies greater than 1MHz possible,
achieving all-ceramic-capacitor designs to minimize PC
board space. The error amplifier works with Type 3
compensation to fully utilize the bandwidth of the high-
frequency switching to obtain fast transient response.
Adjustable soft-start time provides flexibility to minimize
input startup inrush current. An open-drain, power-
good (PWRGD) signal goes high when the output
reaches 90ꢀ of its regulation point.
o 32-Lead TQFN Package
o REFIN for DDR-Termination Application
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX8566ETJ+
-40°C to +85°C
32 TQFN-EP*
+Denotes lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Typical Operating Circuit
The MAX8566 provides a SYNCOUT output to synchro-
nize a second MAX8566 or a second regulator switch-
ing 180° out-of-phase with the first to reduce the input
ripple current, which consequently reduces the input-
capacitance requirements. The MAX8566 also pro-
vides an external reference input (REFIN) for
output-tracking applications.
INPUT
2.25V TO 3.6V
REFIN FOR
TRACKING
REFIN
SS
PGND
PGND
PGND
PGND
LX
SYSTEM
ENABLE
EN
The MAX8566 is available in a 32-pin, 5mm x 5mm TQFN
package. The MAX8566 and all the required external
components fit into a footprint of less than 0.80in2.
SYNC
FREQ
SYNCOUT
GND
FB
SYNC INPUT
MAX8566ETJ+
PROGRAMMABLE
FREQUENCY
STEP-DOWN REGULATOR
TQFN 5mm x 5mm
L1
SYNC OUTPUT 180°
LX
OUTPUT
UP TO 10A
330nH/10A
LX
Applications
ASIC/CPU/DSP Core Voltages
POL Power Supplies
C5
2 x 22µF
6.3V
LX
MONOTONIC SS
SELECTION
POWER-GOOD
OUTPUT
DDR Power Supplies
Base-Station Power Supplies
Fiber Power Supplies
Telecom Power Supplies
COMPENSATION
Network Power Supplies
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
ABSOLUTE MAXIMUM RATINGS
EN/SS, EN, IN, SYNC, V
,
Continuous Power Dissipation (T = +85°C)
A
DD
LSS, PWRGD to GND ..........-0.3V to +4V (4.5V nonswitching)
SYNCOUT, SS, COMP, FB, REFIN,
FREQ to GND .........................................-0.3V to (V + 0.3V)
DD
LX Current (Note 1).................................................-12A to +12A
BST to LX.................................-0.3V to +4V (4.5V nonswitching)
PGND to GND .......................................................-0.3V to +0.3V
TQFN (derate 33.3mW/°C above +70°C) ..................2666.7W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Note 1: LX has internal clamp diodes to PGND and IN. Applications that forward bias these diodes should take care not to exceed
MAX856
the IC’s package power-dissipation limits.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = V
= V = 3.3V, V = 0.5V, V
= 0V, T = 0°C to +85°C, typical values are at T = +25°C, unless otherwise noted.)
A
IN
DD
EN
FB
SYNC
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IN/V
DD
IN and V Voltage Range
DD
2.3
2.3
3.6
3.6
2.2
V
V
LSS Voltage Range
Quiescent current, V = 0.7V
0.7
14
FB
IN Supply Current
mA
mA
µA
V
f
S
= 1MHz, no load
Quiescent current, V = 0.7V
1.8
16
4
FB
V
Supply Current
DD
f
= 1MHz, V
= V
LSS DD
S
T
- V ) =
BST LX
= +25°C
50
2.2
A
Total Shutdown Current into IN
and V
V
= V
= V
= (V
IN
DD
LSS
3.6V, V = 0V
DD
EN
T = 0°C to +85°C
3
A
V
V
rising
falling
2.0
1.90
DD
DD
V
Undervoltage-Lockout
LX starts/stops switching, 2µs
deglitch
DD
Threshold
1.72
BST
T = +25°C
10
V
= V
= V
= 3.6V, V =
LX
A
IN
DD
BST
Shutdown Supply Current
µA
ns
3.6V or 0V, V = 0V
EN
T = 0°C to +85°C
A
0.05
20
PWM COMPARATOR
Comparator Propagation Delay
COMP
10mV overdrive
Clamp Voltage, High
Slew Rate
V
= 2.3V to 3.6V, V = 0.7V
1.80
0.75
2.0
1.4
30
2.15
100
V
V/µs
Ω
IN
FB
Shutdown Resistance
ERROR AMPLIFIER
FB Regulation Voltage
From COMP to GND, V = 0V
EN
V
V
= 1V to 2V, V
= 2.5V and 3.3V
DD
0.594
0
0.6
0.606
V
V
COMP
V
-
DD
= 2.3V to 2.6V
= 2.6V to 3.6V
DD
DD
1.65
Error-Amplifier Common-Mode
Input Range
V
-
DD
V
0
1.7
Error-Amplifier Maximum Output
Current
0.8
mA
2
_______________________________________________________________________________________
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
MAX856
ELECTRICAL CHARACTERISTICS (continued)
(V = V
IN
= V = 3.3V, V = 0.5V, V
= 0V, T = 0°C to +85°C, typical values are at T = +25°C, unless otherwise noted.)
A
DD
EN
FB
SYNC
A
PARAMETER
CONDITIONS
= 0.7V, T = +25°C
MIN
TYP
40
MAX
200
UNITS
nA
FB Input Bias Current
V
V
FB
A
REFIN Input Bias Current
= 0.6V, T = +25°C
70
250
nA
REFIN
A
V
1.65
-
DD
V
V
= 2.3V to 2.6V
= 2.6V to 3.6V
0
0
DD
DD
REFIN Common-Mode Range
V
V
1.7
-
DD
LX (ALL PINS COMBINED)
V
V
V
V
= V
= V
= V
= V
- V = 3.3V
8
12
8
16
20
IN
IN
IN
IN
BST
BST
LSS
LSS
LX
On-Resistance, High Side
I
I
= -2A
= 2A
mΩ
LX
LX
- V = 2.5V
LX
= 3.3V
= 2.5V
16
On-Resistance, Low Side
Current-Limit Threshold
mΩ
12
15
5
20
V
V
= 2.5V or 3.3V, high side
12
20
A
IN
IN
V
= 3.6V
= 0V
200
LX
= 3.6V, V = 0V,
= +25°C
EN
Leakage Current
µA
T
A
V
-200
+5
LX
R
R
= 50kΩ
0.8
1.7
1
1.2
2.3
75
FREQ
Switching Frequency
V
V
= 2.5V or 3.3V
= 2.5V or 3.3V
MHz
IN
IN
= 23.3kΩ
2
FREQ
Minimum Off-Time
50
95
10
ns
ꢀ
ꢀ
A
Maximum Duty Cycle
R
R
= 50kΩ, V = 2.5V or 3.3V
87
FREQ
FREQ
IN
Minimum Duty Cycle
= 50kΩ, V = 2.5V or 3.3V
IN
RMS LX Output Current
ENABLE/SOFT-START
EN Input Logic-Low Threshold
EN Input Logic-High Threshold
10
0.4
0.7
V
V
1.65
30
1.90
Monotonic start
No monotonic start
= 0V or 3.6V, V = 3.6V, T = +25°C
45
20
1
ꢀ of
MODE Input Threshold
V
= 2.3V to 3.6V
DD
V
DD
EN, MODE Input Current
Soft-Start Charging Current
SS Discharge Resistance
V
V
= V
0.01
8
µA
µA
kΩ
EN
SS
MODE
DD
A
= 0.3V
5
11
8
_______________________________________________________________________________________
3
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
ELECTRICAL CHARACTERISTICS (continued)
(V = V
IN
= V = 3.3V, V = 0.5V, V
= 0V, T = 0°C to +85°C, typical values are at T = +25°C, unless otherwise noted.)
A
DD
EN
FB
SYNC
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SYNC
Capture Range
V
V
= 2.3V to 3.6V
= 2.3V to 3.6V
0.25
100
100
0.4
2.40
MHz
ns
DD
DD
t
t
LO
Pulse Width
HI
MAX856
V
V
0.95
1
IH
IL
Input Threshold
Input Current
V
V
= 2.3V to 3.6V
V
DD
1.6
+10
+1
I
I
-1
-1
IH
= 0V or 3.6V, V
= 3.6V
DD
µA
SYNC
T
A
= +25°C
+0.01
IL,
SYNCOUT
Frequency Range
V
= 2.3V to 3.6V
0.25
160
2.40
230
MHz
DD
Phase Shift from SYNC or
Internal Oscillator
Frequency = 1MHz
180
Degrees
V
0.4
-
V
0.05
-
DD
DD
V
V
OH
OL
I
V
=
1mA,
SYNCOUT
Output Voltage
V
= 2.3V to 3.6V
DD
0.05
0.4
THERMAL SHUTDOWN
Thermal-Shutdown Threshold
Thermal-Shutdown Hysteresis
POWER GOOD
When LX stops switching
+165
20
°C
°C
ꢀ of
V
Threshold Voltage
V
falling, 3mV hysteresis
86
30
90
93
REFIN
FB
or 0.6V
Falling-Edge Deglitch
Output Low Voltage
Leakage Current
50
80
0.3
1
µs
V
I
= 4mA
0.15
0.01
PWRGD
V
= 3.6V, V = 0.9V, T = +25°C
µA
PWRGD
FB
A
4
_______________________________________________________________________________________
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
MAX856
ELECTRICAL CHARACTERISTICS
(V = V
IN
= V = 3.3V, V = 0.5V, V
= 0V, T = -40°C to +85°C, unless otherwise noted. Note 2)
A
DD
EN
FB
SYNC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IN/V
DD
IN and V Voltage Range
DD
2.325
2.325
3.600
3.600
2.2
V
LSS Voltage Range
IN Supply Current
V
Quiescent current, V = 0.7V
mA
mA
FB
V
Supply Current
Quiescent current, V = 0.7V
FB
4
DD
V
V
rising
falling
2.2
DD
DD
V
Undervoltage-Lockout
LX starts/stops switching,
2µs rising/falling-edge delay
DD
V
Threshold
1.72
COMP
Clamp Voltage, High
Slew Rate
V
= 2.3V to 3.6V, V = 0.7V
1.80
0.75
2.18
100
V
V/µs
Ω
IN
FB
Shutdown Resistance
ERROR AMPLIFIER
FB Regulation Voltage
From COMP to GND, V = 0V
EN
V
V
= 1V to 2V, V = 2.3V or 3.6V
0.591
0
0.609
V
V
COMP
IN
V
-
DD
= 2.325V to 2.6V
= 2.6V to 3.6V
DD
DD
1.65
Error-Amplifier Common-Mode
Input Range
V
-
DD
V
0
0.8
0
1.7
Error-Amplifier Maximum Output
Current
mA
V
V
-
DD
V
V
= 2.325V to 2.5V
= 2.6V to 3.6V
DD
DD
1.65
REFIN Common-Mode Range
V
-
DD
0
1.7
LX (ALL PINS COMBINED)
V
V
V
V
= V
= V
= V
= V
- V = 3.3V
16
20
15
20
20
IN
IN
IN
IN
BST
BST
LSS
LSS
LX
On-Resistance, High Side
I
I
= -2A
mΩ
LX
LX
- V = 2.5V
LX
= 3.3V
= 2.5V
On-Resistance, Low Side
Current-Limit Threshold
= 2A
mΩ
V
= 2.5V or 3.3V
12
A
IN
_______________________________________________________________________________________
5
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
ELECTRICAL CHARACTERISTICS (continued)
(V = V
IN
= V = 3.3V, V = 0.5V, V
= 0V, T = -40°C to +85°C, unless otherwise noted. Note 2)
A
DD
EN
FB
SYNC
PARAMETER
CONDITIONS
MIN
0.8
TYP
MAX
1.2
2.3
90
UNITS
R
FREQ
R
FREQ
= 50kΩ
Switching Frequency
V
V
= 2.5V or 3.3V
= 2.5V or 3.3V
MHz
IN
IN
= 23.3kΩ
1.7
Minimum Off-Time
ns
ꢀ
A
Maximum Duty Cycle
RMS Output Current
ENABLE/SOFT-START
R
= 50kΩ, V = 2.5V or 3.3V
87
FREQ
IN
MAX856
10
EN Input Logic-Low Threshold
EN Input Logic-High Threshold
0.7
V
V
1.65
30
Monotonic start
45
20
1
ꢀ of
DD
MODE Input Threshold
V
= 2.3V to 3.6V
IN
V
No monotonic start
EN, MODE Input Current
Soft-Start Charging Current
SYNC
V
V
or V
= 0V or 3.6V, V
= 3.6V
µA
µA
EN
SS
MODE
DD
= 0.3V
5
12
Capture Range
V
V
= 2.3V to 3.6V
= 2.3V to 3.6V
0.25
100
100
0.4
2.40
1.6
MHz
ns
IN
IN
t
t
LO
Pulse Width
HI
V
IH
IL
Input Threshold
V
= 2.3V to 3.6V
V
IN
V
6
_______________________________________________________________________________________
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
MAX856
ELECTRICAL CHARACTERISTICS (continued)
(V = V
IN
= V = 3.3V, V = 0.5V, V
= 0V, T = -40°C to +85°C, unless otherwise noted. Note 2)
A
DD
EN
FB
SYNC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SYNCOUT
Frequency Range
V
= 2.3V to 3.6V
0.25
160
2.40
MHz
DD
Phase Shift from SYNC or
Internal Oscillator
Frequency = 1MHz
230 Degrees
V
0.4
-
DD
V
V
OH
OL
I
V
= 1mA,
= 2.3V to 3.6V
SYNCOUT
Output Voltage
V
DD
0.4
POWER-GOOD
ꢀ of
93
Threshold Voltage
V
falling, 3mV hysteresis
85
30
FB
V
REF
µs
V
Falling-Edge Deglitch
80
PWRGD Output Voltage
I
= 4mA
0.3
PWRGD
Note 2: Specifications to -40°C are guaranteed by design and not production tested.
Typical Operating Characteristics
(Typical values are at V = V
= 3.3V, V
= 1.8V, R
= 50kΩ, I
= 10A, and T = +25°C.)
OUT A
IN
DD
OUT
FREQ
EFFICIENCY vs. LOAD CURRENT
EFFICIENCY vs. LOAD CURRENT
= 2.5V, V = 3.3V
EFFICIENCY vs. LOAD CURRENT
V
IN
= V = 2.5V
V
IN
V
IN
= V = 3.3V
LSS
LSS
LSS
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
V
= 2.5V
= 1.8V
OUT
OUT
V
= 1.8V
OUT
V
= 1.8V
= 1.5V
OUT
V
V
= 1.5V
OUT
V
OUT
V
= 0.8V
OUT
0.1
1
10
100
0.1
1
10
100
0.1
1
10
100
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
_______________________________________________________________________________________
7
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
Typical Operating Characteristics (continued)
(Typical values are at V = V
= 3.3V, V
= 1.8V, R
= 50kΩ, I
= 10A, and T = +25°C.)
OUT A
IN
DD
OUT
FREQ
LOAD REGULATION
FREQUENCY vs. TEMPERATURE
REFERENCE VOLTAGE vs. TEMPERATURE
0.10
0.05
0.65
0.64
0.63
0.62
0.61
0.60
0.59
0.58
0.57
0.56
0.55
2.5
2.0
1.5
1.0
0.5
0
R
= 23.3kΩ
FREQ
0
MAX856
V
= 2.5V
OUT
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
-0.35
-0.40
V
= 1.8V
OUT
R
R
= 50kΩ
FREQ
V
= 0.8V
OUT
= 100kΩ
FREQ
0
1
2
3
4
5
6
7
8
9
10
-40
0
40
80
120
-40
-15
10
35
60
85
LOAD CURRENT (A)
TEMPERATURE (°C)
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE
MAXIMUM OUTPUT CURRENT
vs. OUTPUT VOLTAGE
EXPOSED PADDLE TEMPERATURE
vs. LOAD CURRENT
10
9
8
7
6
5
4
3
2
1
0
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
V
= 0V
EN
120
70
T
= +85°C
= +25°C
A
T
A
20
T
= -40°C
A
-30
-80
MAX8566 EV KIT PCB
200LFM
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
INPUT VOLTAGE (V)
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5
OUTPUT VOLTAGE (V)
0
2
4
6
8
10
LOAD CURRENT (A)
OUTPUT SHORT-CIRCUIT CURRENT
vs. INPUT VOLTAGE
LINE REGULATION
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
0.5
0.4
0.3
0.2
0.1
I
= 0A
LOAD
0
-0.1
-0.2
-0.3
-0.4
-0.5
I
= 4.5A
LOAD
I
= 10A
LOAD
2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00
2.25 2.45 2.65 2.85 3.05 3.25 3.45 3.65 3.85
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
8
_______________________________________________________________________________________
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
MAX856
Typical Operating Characteristics (continued)
(Typical values are at V = V
= 3.3V, V
= 1.8V, R
= 50kΩ, I
= 10A, and T = +25°C.)
OUT A
IN
DD
OUT
FREQ
GAIN/PHASE OF THE VOLTAGE LOOP
LOAD TRANSIENT (0 TO 5A)
MAX8566 toc13
MAX8566 toc12
147 kHz
V
OUT
0dB
AC-COUPLED
(50mV/div)
GAIN
(10dB/div)
5A
0
56°
0°
I
OUT
PHASE
(45°/div)
(2A/div)
1
10
100
1000
t = 10µs/div
FREQUENCY (kHz)
STARTUP INTO 0.18Ω LOAD
(R = 0.18Ω)
FULL-LOAD SWITCHING WAVEFORMS
LOAD
MAX8566 toc14
MAX8566 toc15
7A
(PEAK)
IN
12A
10A
I
L
I
(2A/div)
(5A/div)
0A
3.3V
V
EN
V
OUT
(2V/div)
0V
1.8V
(10mV/div)
V
OUT
3V
3V
(1V/div)
V
0V
LX
(2V/div)
0V
V
PWRGD
0V(2V/div)
0A
t = 400ns/div
t = 400µs/div
_______________________________________________________________________________________
9
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
Typical Operating Characteristics (continued)
(Typical values are at V = V
= 3.3V, V
= 1.8V, R
= 50kΩ, I
= 10A, and T = +25°C.)
OUT A
IN
DD
OUT
FREQ
SOFT-START WITH REFIN
SYNCHRONIZED OPERATION (NO LOAD)
MAX8566 toc16
MAX8566 toc17
6.5A
I
IN
I
IN
(AC-COUPLED)
(20mA/div)
(5A/div)
MAX856
0A
0A
0A
I
L1
V
0.6V
(2A/div)
REFIN
(500mV/div)
I
L2
0V
1.8V
(2A/div)
V
OUT
V
3.3V
0V
3.3V
LX1
3V
(1V/div)
(5V/div)
V
(5V/div)
V
0V
PWRGD
LX2
(2V/div)
0V
0V
t = 400µs/div
t = 400ns/div
SOFT-START TIME
vs. SOFT-START CAPACITANCE
STARTUP INTO PREBIASED OUTPUT
(R
= 0.18Ω)
LOAD
MAX8566 toc19
800
700
600
500
400
300
200
100
0
7.5A
(PEAK)
I
IN
(5A/div)
0A
3.3V
V
EN
(12V/div)
0V
1.8V
0.9V
V
OUT
(1V/div)
3V
V
0V
PWRGD
(2V/div)
0V
0
1
2
3
4
5
6
7
8
9
10
t = 400µs/div
C
(µF)
SS
10 ______________________________________________________________________________________
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
MAX856
Pin Description
PIN
NAME
FUNCTION
Monotonic Startup Enable/Disable. Connect MODE to GND or to the center tap of an external
resistor-divider to enable/disable monotonic startup mode.
1
MODE
Error-Amplifier Output. Connect the necessary compensation network from COMP to FB. COMP is
internally pulled to GND when the IC is in shutdown mode.
2
3
COMP
Power-Good Output. Open-drain output that is high impedance when V ꢀ 90% of 0.6V. Otherwise,
FB
PWRGD is internally pulled low. PWRGD is internally pulled low when the IC is in shutdown mode,
PWRGD
V
DD
is below the UVLO threshold, or the IC is in thermal shutdown.
High-Side MOSFET Driver Supply. Bypass BST to LX with a 0.1µF capacitor. BST is connected to
LSS through an internal pMOS switch.
4
BST
LX
Inductor Connection. All LX pins are internally connected together. Connect all LX pins to the
switched side of the inductor. LX is high impedance when the IC is in shutdown mode.
5–12
13–17
Power Ground. All PGND pins are internally connected. Connect all PGND pins externally to the
power ground plane.
PGND
Input Power Supply. All IN pins are internally connected. Connect all IN pins externally to an input
supply from 2.3V to 3.6V. Bypass IN to PGND with 20µF of ceramic capacitance.
18–22
23
IN
LSS
Low-Side MOSFET-Driver Supply Voltage. Connect LSS to a 2.3V to 3.6V supply voltage.
IC Supply Voltage Input. Connect V to IN through an external 2ꢁ resistor. Bypass V to GND
with a 4.7µF capacitor.
DD
DD
24
V
DD
External Reference Input. Connect to an external reference. FB regulates to the voltage at REFIN.
Connect REFIN to SS to use the internal reference.
25
26
27
28
29
REFIN
SS
Soft-Start Input. Connect a capacitor from SS to GND to set the soft-start time. See the Soft-Start and
REFIN section.
Enable Input. Active-high logic input to enable/disable the MAX8566. Connect EN to IN to enable
the IC. Connect EN to GND to disable the IC.
EN
Synchronization Input. Synchronize to an external clock with a frequency of 250kHz to 2.4MHz.
Leave SYNC unconnected to disable the synchronization function.
SYNC
FREQ
Oscillator Frequency Selection. Connect a resistor from FREQ to GND to select the switching
frequency. See the Frequency Select (FREQ) section.
Oscillator Output. The SYNCOUT output is 180° out-of-phase from the internal oscillator or the
30
SYNCOUT SYNC signal to facilitate running a second regulator 180° out-of-phase with the first to reduce input
ripple current.
31
32
GND
Analog Circuit Ground
Feedback Input. Connect FB to the center tap of an external resistor-divider from the output to GND
to set the output voltage.
FB
Exposed Pad. Internally connected to GND. Connect to a large ground plane to maximize thermal
performance. Not indented as an electrical connection point.
—
EP
______________________________________________________________________________________ 11
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
V
DD
SHUTDOWN
CONTROL
UVLO
CIRCUITRY
MAX856
EN
CURRENT-LIMIT
COMPARATOR
BST
ILIM THRESHOLD
LX
BIAS
GENERATOR
IN
P
VOLTAGE
REFERENCE
L
SS
N
LX
CONTROL
LOGIC
SS
SOFT-START
THERMAL
SHUTDOWN
N
ERROR
AMPLIFIER
PWM
COMPARATOR
-
PGND
LSS
REFIN
FB
+
-
MODE
+
FREQ
COMP
SYNC
OSCILLATOR
SYNCOUT
COMP LOW
DETECTOR
SHDN
PWRGD
FB
MAX8566
N
0.54V
GND
Figure 1. Functional Diagram
12 ______________________________________________________________________________________
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
MAX856
low-side MOSFETs. The break-before-make logic and
Detailed Description
the timing for charging the bootstrap capacitors are
The MAX8566 high-efficiency, voltage-mode switching
calculated by the controller logic block. The error signal
from the voltage error amplifier is compared with the
ramp signal generated by the oscillator at the PWM
comparator and thus the required PWM signal is pro-
duced. The high-side switch is turned on at the begin-
ning of the oscillator cycle and turns off when the ramp
regulator is capable of delivering up to 10A of output
current. The MAX8566 provides output voltages from
0.6V to (0.87 x V ) from 2.3V to 3.6V input supplies,
IN
making it ideal for on-board point-of-load applications.
The output voltage accuracy is better than 1ꢀ over
load, line, and temperature.
voltage exceeds the V
signal or the current-limit
COMP
The MAX8566 features a wide switching frequency
range, allowing the user to achieve all-ceramic-capaci-
tor designs and faster transient responses. The high
operating frequency minimizes the size of external
components. The MAX8566 also features a wide 2.3V
to 3.6V input voltage range, making it ideal for point-of-
load applications with both 3.3V and 2.5V input volt-
ages. The MAX8566 is available in a small (5mm x
5mm), 32-pin TQFN package. The SYNCOUT function
allows end users to operate two MAX8566s at the same
switching frequency with 180° out-of-phase operation
to minimize the input ripple current, consequently
reducing the input capacitance requirements. The
REFIN function makes the MAX8566 an ideal candidate
for DDR and tracking power supplies. Using internal
threshold is exceeded. The low-side switch is then
turned on for the remainder of the oscillator cycle.
Current Limit
The internal, high-side MOSFET has a typical 15A peak
current-limit threshold. When current flowing out of LX
exceeds this limit, the high-side MOSFET turns off and
the synchronous rectifier turns on. The synchronous
rectifier remains on until the inductor current falls below
the low-side current limit. This lowers the duty cycle
and causes the output voltage to droop until the current
limit is no longer exceeded.
The MAX8566 uses a hiccup mode to prevent over-
heating during short-circuit output conditions. The
device enters hiccup mode when V
drops below
FB
low-R
(8mΩ) n-channel MOSFETs for both high-
DS(ON)
420mV and the current limit is reached. The IC turns off
for 3.4ms and then enters soft-start. If the short-circuit
condition remains after the soft-start time, the IC shuts
down for another 3.4ms. The IC repeats this behavior
until the short-circuit condition is removed.
and low-side switches maintains high efficiency at both
heavy-load and high-switching frequencies. In addition,
the MAX8566 features a low-side-driver supply input
(LSS) to boost the efficiency with a higher driver volt-
age (3.3V) for 2.5V input applications.
Soft-Start and REFIN
The MAX8566 utilizes an adjustable soft-start function
to limit inrush current during startup. An 8µA (typ) cur-
rent source charges an external capacitor connected to
SS to increase the capacitor voltage in a controlled
manner. The soft-start time is adjusted by the value of
the external capacitor from SS to GND. The required
capacitance value is determined as:
The MAX8566 employs the voltage-mode control archi-
tecture with a high bandwith (> 10MHz) error amplifier.
The voltage-mode control architecture allows above
2MHz switching, reducing board area. The op-amp
voltage error amplifier works with Type 3 compensation
to fully utilize the bandwidth of the high-frequency
switching to obtain fast transient response. Adjustable
soft-start time provides flexibilities to minimize input
startup inrush current. An open-drain power-good
8µA × t
(PWRGD) output goes high when V reaches 0.54V.
FB
SS
C =
0.6V
Principle of Operation
The controller logic block is the central processor that
determines the duty cycle of the high-side MOSFET
under different line, load, and temperature conditions.
Under normal operation, where the current limit and
temperature protection are not triggered, the controller
logic block takes the output from the PWM comparator
and generates the driver signals for both high-side and
where t is the required soft-start time in seconds.
SS
The MAX8566 also features an external reference input
(REFIN). The IC regulates FB to the voltage applied to
REFIN. The internal soft-start is not available when
using an external reference. A method of soft-start
when using an external reference is shown in Figure 2.
Connect REFIN to SS to use the internal 0.6V reference.
______________________________________________________________________________________ 13
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
High-Side MOSFET Driver Supply (BST)
The gate-drive voltage for the high-side, n-channel
switch is generated by a flying-capacitor boost circuit.
The capacitor between BST and LX is charged from the
R1
REFIN
V
supply while the low-side MOSFET is on. When
C
R2
LSS
MAX8566
the low-side MOSFET is switched off, the stored voltage
of the capacitor is stacked above LX to provide the
necessary turn-on voltage for the high-side internal
MOSFET.
MAX856
Frequency Select (FREQ)
The switching frequency is resistor programmable from
250kHz to 2.4MHz. Set the switching frequency of the
Figure 2. Soft-Start Implementation with External Reference
Undervoltage Lockout (UVLO)
IC with a resistor from FREQ to GND (R
calculated as:
). R
is
FREQ
FREQ
The UVLO circuitry inhibits switching when V
is
DD
below 2V. Once V
rises above 2V, UVLO clears and
DD
⎛
⎞
the soft-start function activates. A 100mV hysteresis is
built in for glitch immunity.
50kΩ
0.95µs
1
f
s
R
=
×
− 0.05µs
FREQ
⎜
⎟
⎝
⎠
Monotonic Startup Modes (MODE)
When starting up into a precharged output, the MAX8566
does not discharge the output prior to entering soft-start
where f is the desired switching frequency in Hz.
S
SYNC Function (SYNC, SYNCOUT)
The MAX8566 features a SYNC function that allows the
switching frequency to be synchronized to any frequen-
cy between 250kHz to 2.4MHz. Drive SYNC with a
(known as monotonic startup). Drive MODE to 1/3 of V
DD
to enable monotonic startup mode. Connect MODE to
GND to disable monotonic startup mode.
C5
0.047µF
C24
OPEN
L1
0.47µH
23
4
V
OUT
BST
LSS
IN
1.8V AT 10A
18
5
V
IN
LX
LX
2.3V TO 3.6V
19
20
21
22
6
7
8
9
C7
22µF
C3
0.22µF
C6
IN
22µF
2kΩ
C1
10µF
C2
10µF
IN
IN
IN
LX
LX
LX
R4
100Ω
3300pF
10
11
12
17
16
R1
10Ω
LX
LX
C8
MAX8566
24
120pF
R5
V
DD
LX
24.9kΩ
C4
1µF
PGND
PGND
R2
20kΩ
15
POWER-GOOD
OUTPUT
PGND
3
14
13
R6
12.4kΩ
PWRGD
EN
PGND
PGND
27
32
2
R17
20kΩ
FB
R7
16.9kΩ
C9
330pF
1
MODE
REFIN
SYNC
FREQ
COMP
25
R18
10kΩ
28
29
30
26
SYNCOUT
SS
C10
22pF
GND
31
R3
50kΩ
C11
0.022µF
Figure 3. Typical Application Circuit
14 ______________________________________________________________________________________
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
MAX856
square wave at the desired synchronization frequency.
Inductor Design
A rising edge on SYNC triggers the internal SYNC cir-
cuitry. The frequency of the input into SYNC must be
higher than the internal oscillator frequency set by
Choose an inductor with the following equation:
V
× V − V
(
)
OUT
IN
OUT
L =
R
. Leave SYNC disconnected to disable the func-
FREQ
f × V × LIR × I
s
IN
OUT(MAX)
tion and operate on the internal oscillator.
The MAX8566 has a SYNCOUT output that generates a
clock signal that is 180° out-of-phase with its internal
oscillator, or the signal applied to SYNC. This allows for
another regulator to be synchronized 180° out-of-phase
to reduce the input ripple current.
where LIR is the ratio of the inductor ripple current to
average continuous current at the minimum duty cycle.
Choose the LIR between 20ꢀ to 40ꢀ for best perfor-
mance and stability.
Use a low-loss inductor with the lowest possible DC
resistance that fits in the allotted dimensions. Powered
iron ferrite core types are often the best choice for per-
formance. With any core material the core must be
large enough not to saturate at the peak inductor cur-
Power-Good Output (PWRGD)
PWRGD is an open-drain output that goes high imped-
ance once the soft-start ramp has concluded, provided
V
is above 0.54V. PWRGD pulls low when V
is
FB
FB
rent (I
). Calculate I
as follows:
PEAK
PEAK
below 0.54V for at least 50µs. PWRGD is low during
shutdown.
LIR
2
⎛
⎝
⎞
⎠
I
= 1+
× I
OUT(MAX)
⎟
PEAK
⎜
Low-Side MOSFET Driver Supply (LSS)
The MAX8566 provides an external input for the low-
side MOSFET driver supply (LSS). This allows for high-
er gate-drive voltages to maximize converter efficiency
at low input voltages.
Output Capacitor Selection
The key selection parameters for the output capacitor
are capacitance, ESR, ESL, and voltage rating require-
ments. These affect the overall stability, output ripple
voltage, and transient response of the DC-DC convert-
er. The output ripple occurs due to variations in the
charge stored in the output capacitor, the voltage drop
due to the capacitor’s ESR, and the voltage drop due to
the capacitor’s ESL. Calculate the output voltage ripple
due to the output capacitance, ESR, and ESL as:
Shutdown Mode
Drive EN to GND to shut down the IC and reduce qui-
escent current to 4µA. During shutdown, the output is
high impedance. Drive EN high to enable the
MAX8566.
Thermal Protection
Thermal-overload protection limits total power dissipa-
tion in the device. When the junction temperature
V
= V
+ V
+ V
RIPPLE
RIPPLE(C)
RIPPLE(ESR) RIPPLE(ESL)
where the output ripple due to output capacitance,
ESR, and ESL are:
exceeds T = +165°C a thermal sensor forces the
J
device into shutdown, allowing the die to cool. The ther-
mal sensor turns the device on again after the junction
temperature cools by 20°C, causing a pulsed output
during continuous overload conditions. The soft-start
sequence begins after a thermal-shutdown condition.
I
P−P
V
=
RIPPLE(C)
8 × C
× f
s
OUT
V
= I
× ESR
RIPPLE(ESR)
RIPPLE(ESL)
P−P
Applications Information
I
P−P
V
=
× ESL
t
V
DD
Decoupling
ON
To decrease the noise effects due to the high switching
frequency and maximize the output accuracy of the
I
t
P−P
or V
=
× ESL, whichever isgreater.
RIPPLE(ESL)
OFF
MAX8566, decouple V
DD
the capacitor as close to V
with a 4.7µF capacitor from
DD
V
to GND and a 2Ω resistor from V
to V . Place
DD IN
as possible.
DD
______________________________________________________________________________________ 15
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
The peak inductor current (I ) is:
determines the zero. The double pole and zero fre-
quencies are given as follows:
P-P
V
− V
OUT
V
OUT
IN
I
=
×
1
P−P
f × L
V
f
= f
=
s
IN
P1_LC
P2_LC
⎛
⎞
R
R
+ ESR
O
2π × L × C
×
O
⎜
⎟
Use these equations for initial capacitor selection.
Determine final values by testing a prototype or an
evaluation circuit. A smaller ripple current results in less
output voltage ripple. Since the inductor ripple current
is a factor of the inductor value, the output voltage rip-
ple decreases with larger inductance. Use ceramic
capacitors for low ESR and low ESL at the switching
frequency of the converter. The low ESL of ceramic
capacitors makes ripple voltages negligible.
+ R
⎝
⎠
O
L
1
f
=
Z_ESR
2π × ESR × C
O
MAX856
where R is equal to the sum of the output inductor’s
L
DCR and the internal switch resistance, R
typical value for R
. A
DS(ON)
is 8mΩ. R is the output load
DS(ON)
O
resistance, which is equal to the rated output voltage
divided by the rated output current. ESR is the total
equivalent series resistance of the output filtering
capacitor. If there is more than one output capacitor of
the same type in parallel, the value of the ESR in the
above equation is equal to that of the ESR of a single
output capacitor divided by the total number of output
capacitors.
Load-transient response depends on the selected out-
put capacitance. During a load transient, the output
instantly changes by ESR x I
. Before the controller
LOAD
can respond, the output deviates further, depending on
the inductor and output capacitor values. After a short
time (see the Typical Operating Characteristics), the
controller responds by regulating the output voltage
back to its predetermined value. The controller
response time depends on the closed-loop bandwidth.
A higher bandwidth yields a faster response time, pre-
venting the output from deviating further from its regu-
lating value. See the Compensation Design section for
more details.
The high switching frequency range of the MAX8566
allows the use of ceramic output capacitors. Since the
ESR of ceramic capacitors is typically very low, the fre-
quency of the associated transfer-function zero is high-
er than the unity-gain crossover frequency, f , and the
C
zero cannot be used to compensate for the double pole
created by the output filtering inductor and capacitor.
The double pole produces a gain drop of 40dB and a
phase shift of 90 degrees per decade. The error ampli-
fier must compensate for this gain drop and phase shift
to achieve a stable high-bandwidth closed-loop sys-
tem. Therefore, use Type 3 compensation as shown in
Figure 4. Type 3 compensation possesses three poles
Input Capacitor Selection
The input capacitor reduces the current peaks drawn
from the input power supply and reduces switching
noise in the IC. The impedance of the input capacitor at
the switching frequency should be less than that of the
input source so high-frequency switching currents do
not pass through the input source but are instead
shunted through the input capacitor. High source
impedance requires high input capacitance. The input
capacitor must meet the ripple-current requirement
imposed by the switching currents. The RMS input rip-
ple current is given by:
and two zeros with the first pole, f , located at zero
P1_EA
frequency (DC). Locations of other poles and zeros of
the Type 3 compensation are given by:
1
f
=
Z1_EA
Z2_EA
2π × R1 × C1
1
f
=
V
× V − V
(
)
OUT
IN
OUT
2π × R3 × C3
1
2π × R1 × C2
1
I
= I
×
RIPPLE
LOAD
V
IN
f
=
=
P2_EA
where I
is the input RMS ripple current.
Compensation Design
RIPPLE
f
P3_EA
2π × R2 × C3
The power transfer function consists of one double pole
and one zero. The double pole is introduced by the out-
put filtering inductor, L, and the output filtering capaci-
The above equations are based on the assumptions
that C1>>C2, and R3>>R2, which are true in most
applications. Placement of these poles and zeros is
tor, C . The ESR of the output filtering capacitor
O
16 ______________________________________________________________________________________
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
MAX856
Due to the underdamped nature of the output LC dou-
ble pole, set the two zero frequencies of the Type 3
compensation less than the LC double-pole frequency
to provide adequate phase boost. Set the two zero fre-
L
quencies to 80ꢀ of the LC double-pole frequency.
LX
Hence:
R2
L × C × R + ESR
(
)
1
O
O
MAX8566
R1 =
×
R3
0.8 × C1
R
+ R
C3
L
O
FB
L × C × R + ESR
(
)
1
O
O
C1
C2
R1
C3 =
×
COMP
0.8 × R3
R
+ R
R4
L
O
Set the second compensation pole, f
yields:
, at f
P2_EA
Z_ESR
C
× C1 × ESR
O
C2 =
R1 × C1− C × ESR
O
Figure 4. Type 3 Compensation Network
Set the third compensation pole at 1/2 of the switching
frequency to gain some phase margin. Calculate R2 as
follows:
determined by the frequencies of the double pole and
ESR zero of the power transfer function. It is also a func-
tion of the desired closed-loop bandwidth. The following
section outlines the step-by-step design procedure to
calculate the required compensation components.
1
R2 =
π × C3 × f
S
Begin by setting the desired output voltage. The output
voltage is set using a resistor-divider from the output to
GND with FB at the center tap (R3 and R4 in Figure 4).
Use 20kΩ for R4 and calculate R3 as:
The above equations provide accurate compensation
when the zero-cross frequency is significantly higher
than the double-pole frequency. When the zero-cross
frequency is near the double-pole frequency, the actual
zero-cross frequency is higher than the calculated fre-
quency. In this case, lowering the value of R1 reduces
the zero-cross frequency. Also, set the third pole of the
Type 3 compensation close to the switching frequency
if the zero-cross frequency is above 200kHz to boost
the phase margin. Note that the value of R4 can be
altered to make the values of the compensation compo-
nents practical. The recommended range for R4 is
10kΩ to 50kΩ.
V
0.6V
⎛
⎞
⎠
OUT
R3 = R4 ×
− 1
⎜
⎝
⎟
The zero-cross frequency of the closed-loop, f , should
C
be less than 20ꢀ of the switching frequency, f .
S
Higher zero-cross frequency results in faster transient
response. It is recommended that the zero-cross fre-
quency of the closed loop should be chosen between
10ꢀ and 20ꢀ of the switching frequency. Once f is
C
chosen, C1 is calculated from the following equation:
PCB Layout Considerations
and Thermal Performance
V
IN
1.5625 ×
The MAX8566EVKIT provides an optimal layout and
should be followed closely. For custom design, follow
these guidelines:
V
P-P
C1 =
⎛
⎞
R
R
L
f
× 2 × π × R3 × 1+
C
⎜
⎟
⎝
⎠
O
1) Place decoupling capacitors (V
and SS) as close
DD
to the IC as possible. Keep the power ground plane
(connected to PGND) and signal ground plane (con-
nected to GND) separate.
where V
is the ramp peak-to-peak voltage (1V typ).
P-P
______________________________________________________________________________________ 17
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
OPEN-LOOP
GAIN
COMPENSATION
TRANSFER
FUNCTION
THE THIRD
POLE
DOUBLE POLE
MAX856
GAIN
(dB)
THE SECOND
POLE
POWER-STAGE
TRANSFER FUNCTION
THE FIRST AND
SECOND ZEROS
FREQUENCY
Figure 5. Transfer Function for Type 3 Compensation
2) Connect input and output capacitors to the power
ground plane; connect all other capacitors to the sig-
nal ground plane.
4) Connect IN, LX, and PGND separately to a large
copper area to help cool the IC to further improve
efficiency and long-term reliability.
3) Keep the high-current paths as short and wide as
possible. Keep the path of switching current short
and minimize the loop area formed by LX, the output
capacitors, and the input capacitors.
5) Ensure all feedback connections are short and
direct. Place the feedback resistors and compensa-
tion components as close to the IC as possible.
6) Route high-speed switching nodes away from sensi-
tive analog areas (FB, COMP).
18 ______________________________________________________________________________________
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
MAX856
Chip Information
Pin Configuration
PROCESS: BiCMOS
TOP VIEW
Package Information
24
23
22 21 20 19
18
17
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
REFIN 25
16 PGND
SS 26
EN 27
15
14
PGND
PGND
PACKAGE
TYPE
32 TQFN-EP
PACKAGE
CODE
T3255+4
OUTLINE
NO.
21-0140
LAND
SYNC 28
13 PGND
PATTERN NO.
MAX8566
29
30
12
11
FREQ
LX
LX
90-0012
SYNCOUT
GND 31
10 LX
*EP
7
32
9
FB
LX
+
1
2
3
4
5
6
8
THIN QFN
*CONNECT EP TO GND.
______________________________________________________________________________________ 19
High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
Revision History
REVISION REVISION
DESCRIPTION
PAGES
CHANGED
NUMBER
DATE
0
6/05
Initial release
—
Made corrections to Ordering Information, Pin Description, Compensation Design section,
Pin Configuration, and Package Information
1, 11, 17,
19, 20, 21
1
2/09
2
3
12/10
3/11
Modified the Typical Application Circuit (Figure 3) to change the 2.4kΩ resistor to 2kΩ
14
17
MAX856
Corrected error in C1 equation and added descriptive verbiage
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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