MAX8650 [MAXIM]
4.5V to 28V Input Current-Mode Step-Down Controller with Adjustable Frequency; 4.5V至28V输入，电流模式降压型控制器，可调节开关频率
| 型号： | MAX8650 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 4.5V to 28V Input Current-Mode Step-Down Controller with Adjustable Frequency |
| 文件： | 总25页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3973; Rev 0; 1/06
4.5V to 28V Input Current-Mode Step-
Down Controller with Adjustable Frequency
General Description
Features
The MAX8650 synchronous PWM buck controller oper-
ates from a 4.5V to 28V input and generates an
adjustable 0.7V to 5.5V output voltage at loads up to 25A.
♦ Operates from 4.5V to 28V Supply
♦ 1% FB Voltage Accuracy Over Temperature
♦ Adjustable Output Voltage Down to 0.7V or REFIN
The MAX8650 uses a peak current-mode control archi-
tecture with an adjustable (200kHz to 1.2MHz) constant
switching frequency and is externally synchronizable. The
IC’s current limit uses the inductor’s DC resistance to
improve efficiency or an external sense resistor for high
accuracy. The current-limit threshold is adjusted with an
external resistor. Foldback-type current limit can be
implemented to reduce the power dissipation in overload
or short-circuit conditions. Short-circuit protection is
provided based on sensing the current in the low-side
MOSFET. A reference input is provided for use with a
high-accuracy external reference or for double-data-rate
(DDR)-tracking applications.
♦ Adjustable Switching Frequency or External
Synchronization from 200kHz to 1.2MHz
♦ 180° Phase-Shifted Clock Output
♦ Adjustable Overcurrent Limit
♦ Adjustable Foldback Current Limit
♦ Adjustable Slope Compensation
♦ Selectable Current-Limit Mode: Latch-Off or
Automatic Recovery
♦ Monotonic Output-Voltage Rise at Startup
♦ Output Sources and Sinks Current
♦ Enable Input
Monotonic prebiased startup is available for a safe-start
in applications where the output capacitor may have an
initial charge. This feature prevents the output from
pulling low during startup, which is a common charac-
teristic of conventional buck regulators.
♦ Power-OK (POK) Output
A 180° out-of–phase synchronization output is available
♦ Adjustable Soft-Start
for synchronizing with another converter.
♦ Independently Adjustable Overvoltage Protection
Applications
Ordering Information
Base Stations
DDR
PKG
CODE
Network and Telecom Power Modules
PART
TEMP RANGE PIN-PACKAGE
Storage
Servers
IBA Applications
24 QSOP
MAX8650EEG+ -40°C to +85°C
E24-1
+Denotes lead-free package.
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
R2
R1
V
IN
7V TO 28V
SYNC
1
2
FSYNC
MODE
BST
C1
D2
EN
4
5
ON
OFF
11
24
3
EN
POK
V
OUT
0.7V TO 5.5V
POK
DH
L1
SYNCO
C2
6
7
Q1
SYNCO
SCOMP
LX
DL
MAX8650EEG
23
C5
R8
R3
C3
C6
22
21
Q2
8
ILIM2
REFIN
PGND
VL
C7
9
20
16
SS
10
C8
IN
R4
C10
C9
R9
ILIM1
12
14
AVL
C4
R6
R5
19
18
COMP
FB
CS+
15 C11
13
R7
CS-
17
OVP
GND
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
ABSOLUTE MAXIMUM RATINGS
IN, EN to GND ........................................................-0.3V to +30V
BST to LX...............................................................-0.3V to +7.5V
AVL, FB, POK, COMP, SS, MODE, REFIN to GND .....-0.3V to +6V
CS+, CS- to GND .....................................................-0.3V to +6V
PGND to GND .......................................................-0.3V to +0.3V
DH to LX....................................................-0.3V to (V
+ 0.3V)
BST
LX to GND .................... -1V (-2.5V for < 50ns transient) to +30V
Continuous Power Dissipation (T = +70°C)
A
DL to PGND.................................................-0.3V to (V + 0.3V)
24-Pin QSOP (derate 9.5mW/°C above +70°C)..........762mW
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
VL
ILIM2, ILIM1, SYNCO, FSYNC, OVP,
SCOMP to GND .....................................-0.3V to (V
+ 0.3V)
AVL
VL to PGND ...........................................................-0.3V to +7.5V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = 12V, V
IN
- V = 6.5V, T = -40°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.) (Note 1)
LX A A
BST
PARAMETER
CONDITIONS
MIN
TYP
MAX
28.0
3
UNITS
V
Operating Input Voltage Range
Quiescent Supply Current
VL = IN for V < 7V
4.5
IN
V
= 0.75V, no switching
2
mA
FB
EN = GND, V ≤ 28V
10
IN
Shutdown Supply Current
µA
V
I
IN
+ I + I
VL AVL
EN = GND, V
= V = V = 5V
32
AVL
VL
IN
AVL Undervoltage-Lockout Trip
Level
V
rising, 3% typ hysteresis
3.90
0.7
4.15
4.40
AVL
Minimum output voltage is limited by minimum duty cycle
and external components
Output Voltage Adjust Range
5.5
7.0
V
VL Regulation Voltage
VL Output Current
AVL Regulation Voltage
AVL Output Current
SOFT-START
7V < V < 28V, 1mA < I
< 40mA
6.0
40
6.5
V
IN
LOAD
mA
V
5.5V < V < 7V, 1mA < I
< 10mA
4.900
10
4.975
5.050
VL
LOAD
mA
SS Shutdown Resistance
SS Soft-Start Current
REFIN INPUT
From SS to GND, V = 0V
20
23
100
28
Ω
EN
V
V
= 0.625V
18
µA
SS
V
-
AVL
1.0V
REFIN Dual Mode™ Threshold
V
V
AVL
REFIN Input Bias Current
REFIN Input Voltage Range
= 0.7V to 1.5V
-250
0
+250
1.5
nA
V
REFIN
Dual Mode is a trademark of Maxim Integrated Products, Inc.
2
_______________________________________________________________________________________
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
ELECTRICAL CHARACTERISTICS (continued)
(V = 12V, V
IN
- V = 6.5V, T = -40°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.) (Note 1)
LX A A
BST
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ERROR AMPLIFIER
REFIN = AVL
0.693
0.7
0.707
V
V
REFIN
-
REFIN
+
FB Regulation Voltage
V
V
= 0.7V to 1.5V
V
REFIN
REFIN
0.00375
0.00375
Transconductance
70
110
20
5
160
100
50
µS
Ω
COMP Shutdown Resistance
FB Input Leakage Current
From COMP to GND, V = 0V
EN
V
= 0.7V
nA
V
FB
FB Input Common-Mode Range
CURRENT-SENSE AMPLIFIER
Voltage Gain
-0.1
+1.5
V
= 0 to 5.5V, V
- V = 30mV
CS-
12
V/V
OUT
CS+
CURRENT LIMIT
R
= 24kΩ
27.2
68.0
-42.5
-170
-90
32.0
80.0
36.8
92.0
-57.5
-230
-150
+25
ILIM1
Peak Current-Limit
mV
mV
Threshold (V
- V
)
CS+
CS-
ILIM1 = AVL
R
ILIM2
R
ILIM2
= 50kΩ
-50.0
-200
-120
Valley Current-Limit Threshold
(V - V
)
LX
PGND
= 200kΩ
Negative Current-Limit Threshold % of (typ) positive direction current limit (V - V
)
%
LX
PGND
CS+, CS- Input Current
V
= V
= 0V or 5.5V
CS-
-25
µA
CS+
CS+, CS- Input Common-Mode
Range
0
5.5
V
SLOPE COMPENSATION
V
V
= 2.5V
231.25 250.00 268.75
113.77 123.00 132.23
231.25 250.00 268.75
113.77 123.00 132.23
110.70 123.00 132.23
SCOMP
SCOMP
= 1.25V
Slope Compensation at Maximum
Duty Cycle
SCOMP = AVL
SCOMP = GND, T = 0°C to +85°C
mV
A
T
A
= -40°C to +85°C
SCOMP High Threshold
SCOMP Low Threshold
SCOMP Adjustment Range
SCOMP Input Leakage Current
OSCILLATOR
V
- 0.5
V
V
AVL
0.5
1.25
2.5
V
V
= 1.25V to 2.5V
5
200
nA
SCOMP
R
R
= 21.0kΩ
= 143kΩ
800
160
1000
200
235
75
1200
240
FSYNC
Switching Frequency
kHz
FSYNC
Minimum Off-Time
Minimum On-Time
Measured at DH
Measured at DH
ns
ns
100
_______________________________________________________________________________________
3
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
ELECTRICAL CHARACTERISTICS (continued)
(V = 12V, V
IN
- V = 6.5V, T = -40°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.) (Note 1)
LX A A
BST
PARAMETER
FSYNC Synchronization Range
FSYNC Input-High Pulse Width
FSYNC Input-Low Pulse Width
FSYNC Rise/Fall Time
CONDITIONS
MIN
160
100
100
TYP
MAX
UNITS
kHz
ns
1200
ns
100
0.4
ns
SYNCO Phase Shift
180
Degrees
V
SYNCO Output Low Level
I
I
= 5mA
= 5mA
SYNCO
V
-
AVL
1V
SYNCO Output High Level
V
V
SYNCO
FSYNC Pin Threshold
for SYNC Mode
1.7
2.5
0.4
FSYNC Input Low
FSYNC Input High
FET DRIVERS
V
V
2.5
V
V
V
V
V
V
V
V
- V = 6.5V
1.13
1.4
1.0
1.3
1.6
1.7
0.8
0.85
20
1.8
2.2
2
BST
BST
BST
BST
LX
DH On-Resistance, High State
DH On-Resistance, Low State
DL On-Resistance, High State
DL On-Resistance, Low State
Ω
Ω
Ω
Ω
- V = 5V
LX
- V = 6.5V
LX
- V = 5V
2.2
2.5
2.8
1.5
1.5
30
5
LX
= 6.5V
= 5V
VL
VL
VL
VL
= 6.5V
= 5V
Break-Before-Make Dead Time
LX, BST Leakage Current
THERMAL PROTECTION
Thermal Shutdown
Low side off to high side on, high side off to low side on
= 35V, V = 28V, V = 28V
ns
V
µA
BST
LX
IN
Rising temperature
+160
15
°C
°C
Thermal-Shutdown Hysteresis
4
_______________________________________________________________________________________
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
ELECTRICAL CHARACTERISTICS (continued)
(V = 12V, V
IN
- V = 6.5V, T = -40°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.) (Note 1)
LX A A
BST
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
POK
REFIN = AVL, V rising, typical hysteresis is 3%
629.0
88.7
650.0
91.7
25
671.0
94.7
200
1
mV
FB
Power-OK Threshold
% of
V
V
V
= 0.7V to 1.5V, V rising, typical hysteresis is 3%
FB
REFIN
POK Output Voltage, Low
POK Leakage Current, High
OVP
= 0.6V, I
= 2mA
mV
µA
FB
POK
= 5.5V
POK
REFIN = AVL
770
110
800
115
840
120
500
mV
OVP Threshold Voltage
% of
REFIN
V
V
= 0.7V to 1.5V
REFIN
V
OVP Leakage Current, High
MODE CONTROL
= 0.8V
nA
OVP
MODE Logic-Level Low
MODE Logic-Level High
MODE Input Current
4.5V ≤ V
4.5V ≤ V
≤ 5.5V
≤ 5.5V
0.4
+1
V
V
AVL
AVL
1.8
-1
V
= 0 to V
µA
MODE
AVL
SHUTDOWN CONTROL
EN Logic-Level Low
4.5V ≤ V
4.5V ≤ V
≤ 5.5V
≤ 5.5V
0.45
V
V
AVL
AVL
EN Logic-Level High
2
V
V
= 0V
-1
+1
EN
EN
EN Input Current
µA
= 28V
1.5
6.0
Note 1: Specifications are 100% production tested at T = +85°C. Limits over the operating temperature range are guaranteed
A
by design.
_______________________________________________________________________________________
5
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
Typical Operating Characteristics
(Circuit of Figure 3, 500kHz switching, V = 17V, V
IN
= 3.3V, T = +25°C, unless otherwise noted.)
A
OUT
EFFICIENCY vs. LOAD CURRENT
(CIRCUIT OF FIGURE 4)
3.310
EFFICIENCY vs. LOAD CURRENT
LOAD REGULATION
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
12V INPUT, 1.25V OUTPUT
3.305
3.300
3.295
3.290
3.285
3.280
3.275
3.270
12V INPUT, 3.3V OUTPUT
12V INPUT, 2.5V OUTPUT
12V INPUT, 1.8V OUTPUT
24V INPUT, 3.3V OUTPUT
12V INPUT, 0.9V OUTPUT
1
10
100
0
5
10
15
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
OSCILLATOR FREQUENCY
vs. INPUT VOLTAGE
LINE REGULATION
R
ILIM1
vs. PEAK CURRENT LIMIT
530
520
510
500
490
480
470
3.310
3.305
3.300
3.295
3.290
3.285
3.280
3.275
3.270
60
55
50
45
40
35
30
25
20
NO LOAD
T
= +25°C
T
= -40°C
A
A
15A LOAD
T
= +85°C
A
6
10
14
18
22
26
30
6
10
14
18
22
26
30
0.03
0.04
0.05
0.06
0.07
0.08
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
PEAK CURRENT LIMIT V - V (V)
CS+
CS-
STEP-LOAD RESPONSE
7.5A TO 15A TO 7.5A
STEP-LOAD RESPONSE
-8A TO 8A TO -8A (CIRCUIT OF FIGURE 4)
MAX8650 toc07
MAX8650 toc08
50mV/div
(AC-COUPLED)
V
OUT
OUT
V
I
OUT
OUT
100mV/div
(AC-COUPLED)
I
5A/div
0V
0V
5A/div
40µs/div
100µs/div
6
_______________________________________________________________________________________
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
Typical Operating Characteristics (continued)
(Circuit of Figure 3, 500kHz switching, V = 17V, V
IN
= 3.3V, T = +25°C, unless otherwise noted.)
A
OUT
POWER-DOWN WAVEFORMS
POWER-UP WAVEFORMS
ENABLE/SHUTDOWN WAVEFORMS
MAX8650 toc11
MAX8650 toc10
MAX8650 toc09
V
POK
5V/div
5V/div
5V/div
5V/div
V
POK
V
POK
V
IN
5V/div
1V/div
5V/div
0V
V
EN
V
OUT
V
IN
2V/div
V
OUT
I
L
5A/div
0V
V
OUT
1V/div
0V
5A/div
0V
I
L
10A/div
0V
I
L
200µs/div
2ms/div
2ms/div
SYNCHRONIZATION WAVEFORMS
SHORT CIRCUIT AND RECOVERY
OVERVOLTAGE PROTECTION
MAX8650 toc12
MAX8650 toc13
MAX8650 toc14
7.5A LOAD
V
OUT
V
FSYNC
5V/div
5V/div
2V/div
1V/div
V
OUT
V
0V
SYNCO
10A/div
0V
10V/div
0V
V
DH
I
L
10V/div
I
0V
10A/div
0V
5V/div
0V
IN
V
V
DL
DH
1µs/div
200µs/div
40µs/div
CLOSED-LOOP BODE PLOT WITH NO LOAD
CLOSED-LOOP BODE PLOT WITH 15A LOAD
MAX8650 toc16
MAX8650 toc15
GAIN
GAIN
0dB
0dB
10dB/div
10dB/div
PHASE
PHASE
0°
30°/div
0°
30°/div
1k
10k
100k
1M
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
_______________________________________________________________________________________
7
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
Pin Description
PIN
NAME
FUNCTION
Frequency Set and Synchronization. Connect a resistor from FSYNC to GND to set the switching
frequency, or drive with an external clock signal between 160kHz and 1.2MHz. See the Switching
Frequency and Synchronization section.
1
FSYNC
Current-Limit Operating-Mode Selection. Connect MODE to AVL for latch-off current limit or connect
MODE to GND for automatic-recovery current limit.
2
MODE
Synchronization Output. Provides a clock output that is 180° out-of-phase with the internal oscillator
for synchronizing another MAX8650.
3
4
5
6
7
SYNCO
BST
DH
Boost Capacitor Connection. Connect a 0.1µF ceramic capacitor from BST to LX.
High-Side n-Channel MOSFET Gate-Driver Output. Connect DH to the gate of the high-side MOSFET.
DH is internally pulled low in shutdown.
LX
External Inductor Connection
Low-Side n-Channel MOSFET Gate-Driver Output. Connect DL to the gate of the low-side MOSFET
(synchronous rectifier). DL is internally pulled low in shutdown.
DL
Power Ground. Connect PGND to the power ground plane and to the source of the low-side external
MOSFET. The return path for both gate drivers is through PGND.
8
PGND
Internal 6.5V Linear-Regulator Output. Connect a 1µF to 10µF ceramic capacitor from VL to ground. For
9
VL
IN
V
IN
< 7V, connect VL directly to IN. VL powers both gate drivers. VL is the input to the AVL linear regulator.
10
11
Input Supply Voltage. IN is the input to the VL linear regulator. Connect VL to IN for V < 7V.
IN
Enable. Apply logic-high to enable the output, or logic-low to put the controller in low-power shutdown
mode. Connect EN to IN for always-on operation.
EN
Internal 5V Linear-Regulator Output. Connect a 1µF ceramic capacitor from AVL to ground. AVL
powers the MAX8650’s internal circuits.
12
13
AVL
Ground. Connect GND to the analog ground plane. Connect the analog ground and power ground
planes at a single point near the IC. Low-current signals return to GND.
GND
14
15
CS+
CS-
Positive Differential Current-Sense Input
Negative Differential Current-Sense Input
Programmable Current-Limit Input for Inductor Current. Connect a resistor from ILIM1 to GND to set
the peak current-limit threshold. ILIM1 sources 10µA through the resistor, and the voltage at ILIM1 is
attenuated 7.5:1 to set the final current limit. For example, a 60kΩ resistor results in 600mV at ILIM1.
16
ILIM1
This results in a current-limit threshold (V
- V ) of 80mV. The ILIM1 resistor range is 24kΩ to
CS+
CS-
60kΩ. Connect ILIM1 to AVL to set the default current-limit threshold of 80mV.
8
_______________________________________________________________________________________
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
Pin Description (continued)
PIN
NAME
FUNCTION
Output Voltage Sensing for Overvoltage Protection. Connect OVP to the center of a resistor-divider
from OUT to GND to set the FB independent output overvoltage trip point. Connect OVP to FB if this
independence is not desired. The OVP threshold is 115% of the nominal FB regulation voltage.
17
OVP
Feedback Input. Connect FB to the center of a resistor voltage-divider between the output and GND
18
19
20
21
FB
COMP
SS
to set the output voltage. The FB threshold regulates at 0.7V or V
.
REFIN
Loop Compensation. Connect COMP to an external RC network to compensate the loop. COMP is
internally pulled to GND through 20Ω during shutdown.
Soft-Start. Connect a 0.1µF to 1µF ceramic capacitor from SS to GND. This capacitor sets the soft-
start period during startup. SS is internally pulled to GND through 20Ω during shutdown.
External Reference Input. Connect REFIN to AVL to use the internal 0.7V reference for the feedback
threshold.
REFIN
Programmable Current-Limit Input for the Low-Side MOSFET (LX-PGND). Connect a resistor from ILIM2
to GND to set the valley current-limit threshold. ILIM2 sources 5µA through the resistor, and the voltage
at ILIM2 is attenuated 5:1 to set the final current limit. For example, a 50kΩ resistor results in 250mV at
22
ILIM2
ILIM2. This results in a current-limit threshold (V - V
) of 50mV. V
PGND
must not exceed 1V.
LX
ILIM2
Programmable Slope-Compensation Input. The slope-compensation voltage rate is the voltage at
SCOMP times 0.1 divided by the oscillator period (T). Connect SCOMP to AVL or GND to set to the
default of 250mV/T or 125mV/T, respectively.
23
24
SCOMP
POK
Open-Drain Output that Is High Impedance when the Output Voltage Rises Above 92% of the
Nominal Regulation Value. POK pulls low during shutdown and when the output drops below 88% of
the nominal regulation value.
_______________________________________________________________________________________
9
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
IN
MAX8650
BST
6.5V LDO
REGULATOR
EN
VL
UVLO
LEVEL
SHIFT
DH
LX
THERMAL
SHDN
VL
5V AVL
LDO
AVL
PWM
DL
CONTROL
LOGIC
VOLTAGE
REFERENCE
PGND
REF
SELECT
LOGIC
SYNCO
FSYNC
REF
SOFT-START
CIRCUITRY
REFIN
SS
OVP
OSCILLATOR
1.15V REF
COMP
CLAMP
ERROR
AMP
GM
SLOPE
COMP
SCOMP
FB
PWM
COMPARATOR
COMP
OVP
CSA
CS+
12
CURRENT-
LIMIT
CONTROL LOGIC
MODE
ILIM2
5µA
LEVEL
SHIFT
VL
CURRENT-
LIMIT COMP
X1
DIVIDE BY 5
CS-
10µA
VL
POK
ILIM1
GND
DIVIDE BY 7.5
FB
0.92V
REF
Figure 1. Functional Diagram
10 ______________________________________________________________________________________
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
Undervoltage Lockout
When AVL drops below 4.03V, the MAX8650 assumes
Detailed Description
DC-DC Converter Control Architecture
The MAX8650 step-down controller uses a PWM, cur-
rent-mode control scheme. An internal transconduc-
tance amplifier establishes an integrated error voltage.
The heart of the PWM controller is an open-loop com-
parator that compares the integrated voltage-feedback
signal against the amplified current-sense signal plus
the adjustable slope-compensation ramp, which are
summed into the main PWM comparator to preserve
inner-loop stability. At each rising edge of the internal
clock, the high-side MOSFET turns on until the PWM
comparator trips or the maximum duty cycle is
reached. During this on-time, current ramps up through
the inductor, storing energy in a magnetic field and
sourcing current to the output. The current-mode feed-
back system regulates the peak inductor current as a
function of the output-voltage error signal. The circuit
acts as a switch-mode transconductance amplifier and
pushes the output LC filter pole normally found in a
voltage-mode PWM to a higher frequency.
that the supply voltage is too low for proper operation,
so the undervoltage-lockout (UVLO) circuitry inhibits
switching and forces the DL and DH gate drivers low.
When AVL rises above 4.15V, the controller enters the
startup sequence and then resumes normal operation.
Startup and Soft-Start
The internal soft-start circuitry gradually ramps up the
reference voltage to control the rate of rise of the step-
down controller’s output and reduce input surge cur-
rents during startup. The soft-start period is determined
by the value of the capacitor from SS to GND. The soft-
start time is approximately (30.4ms/µF) x C . The
SS
MAX8650 also features monotonic output-voltage rise;
therefore, both external power MOSFETs are kept off if
the voltage at FB is higher than the voltage at SS. This
allows the MAX8650 to start up into a prebiased output
without pulling the output voltage down.
Before the MAX8650 can begin the soft-start and power-
up sequence, the following conditions must be met:
During the second half of the cycle, the high-side
MOSFET turns off and the low-side MOSFET turns on.
The inductor releases the stored energy as the current
ramps down, providing current to the output. The output
capacitor stores charge when the inductor current
exceeds the required load current and discharges when
the inductor current is lower, smoothing the voltage
across the load. Under soft-overload conditions, when
the peak inductor current exceeds the selected current
limit (see the Current-Limit Circuit section), the high-side
MOSFET is turned off immediately and the low-side
MOSFET is turned on and remains on to let the inductor
current ramp down until the next clock cycle. Under
heavy-overload or short-circuit conditions, the valley
foldback current limit is enabled to reduce power dissi-
pation of external components.
• V
AVL
exceeds the 4.15V UVLO threshold.
• EN is at logic-high.
• The thermal limit is not exceeded.
Enable (EN)
The MAX8650 features a low-power shutdown mode. A
logic-low at EN shuts down the controller. During shut-
down, the output is high impedance, and both DH and
DL are low. Shutdown reduces the quiescent current
(I ) to less than 10µA. A logic-high at EN enables the
Q
controller.
Synchronous-Rectifier Driver (DL)
Synchronous rectification reduces conduction losses in
the rectifier by replacing the normal Schottky catch
diode with a low-resistance MOSFET switch. The
MAX8650 also uses the synchronous rectifier to ensure
proper startup of the boost gate-driver circuit and to
provide the current-limit signal. The low-side gate driver
(DL) swings from 0 to the 6.5V provided from VL. The
DL waveform is always the complement of the DH high-
side gate-drive waveform (with controlled dead time to
prevent cross-conduction or shoot-through). An adap-
tive dead-time circuit monitors the DL voltage and pre-
vents the high-side MOSFET from turning on until DL is
fully off. For the dead-time circuit to work properly,
there must be a low-resistance, low-inductance path
from the DL driver to the MOSFET gate. Otherwise,
the sense circuitry in the MAX8650 can interpret the
MOSFET gate as off when gate charge actually
remains. Use very short, wide traces, approximately 10
The MAX8650 operates in a forced-PWM mode. As a
result, the controller maintains a constant switching fre-
quency, regardless of load, to allow for easier filtering
of the switching noise.
Internal Linear Regulators
The MAX8650 contains two internal LDO regulators. The
AVL regulator provides 5V for the IC’s internal circuitry,
and the VL regulator provides 6.5V for the MOSFET gate
drivers. Connect a 4.7µF ceramic capacitor from VL to
PGND, and connect a 1µF ceramic capacitor from AVL
to GND. For applications where the input voltage is
between 4.5V and 7V, connect VL directly to IN and con-
nect a 10Ω resistor from VL to AVL.
______________________________________________________________________________________ 11
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
nents, mainly inductor and power MOSFETs, and
upstream power source, when output is severely over-
loaded or short circuited and POK is low. Thus, the cir-
cuit can withstand short-circuit conditions continuously
VL
BST
without causing overheating of any component. The
peak constant-current limit sets the current-limit point
more accurately since it does not have to suffer the wide
variation of the low-side power MOSFET’s on-resistance
due to tolerance and temperature.
DH
N
N
MAX8650
LX
The valley current is sensed across the on-resistance of
DL
the low-side MOSFET (V
- V ). The valley current
LX
PGND
limit trips when the sensed voltage exceeds the valley
current-limit threshold. The valley current limit recovers
when the sensed voltage drops below the valley current-
limit threshold (except when using the latch-off option).
Figure 2. DH Boost Circuit
Set the minimum valley current-limit threshold, when the
output voltage is at the nominal regulated value, higher
than the maximum peak current-limit setting. With this
method, the current-limit point accuracy is controlled by
the peak current limit and is not interfered with by the
wide variation of MOSFET on-resistance. See the Setting
the Current Limit section for how to set these limits.
to 20 squares (50 mils to 100 mils wide if the MOSFET
is 1in from the device) for the gate drive. The dead time
at the other edge (DH turning off) also has an adaptive
dead-time circuit operating in a similar manner. For
both edges, there is an additional 20ns fixed dead time
after the adaptive dead time expires.
High-Side Gate-Drive Supply (BST)
A flying capacitor boost circuit (Figure 2) generates the
gate-drive voltage for the high-side n-channel MOSFET.
The capacitor between BST and LX is charged from VL
to 6.5V minus the diode forward-voltage drop while the
low-side MOSFET is on. When the low-side MOSFET is
switched off, the stored voltage of the capacitor is
stacked above LX to provide the necessary turn-on
The MAX8650 can be configured for either an
adjustable valley current-limit threshold with adjustable
foldback ratio, or a fixed valley current limit that latches
the converter off. When latch-off is used (MODE is con-
nected to AVL), set the current-limit threshold by only
one resistor from ILIM2 to GND and make sure this
threshold is higher than the maximum output current
required by at least a 20% margin. Cycle EN or input
power to reset the current-limit latch.
voltage (V ) for the high-side MOSFET. The controller
GS
then closes an internal switch between BST and DH to
turn the high-side MOSFET on.
The peak current limit is used to sense the inductor cur-
rent, and is more accurate than the valley current limit
since it does not depend upon the on-resistance of the
low-side MOSFET. The peak current can be measured
across the resistance of the inductor for the highest effi-
ciency, or alternatively, a current-sense resistor can be
used for more accurate current sensing. A resistor con-
nected from ILIM1 to GND sets the peak current-limit
threshold.
Current-Sense Amplifier
The current-sense circuit amplifies the differential cur-
rent-sense voltage (V
- V
). This amplified cur-
CS-
CS+
rent-sense signal and the internal slope-compensation
signal are summed (V ) together and fed into the
SUM
PWM comparator’s inverting input. The PWM compara-
tor shuts off the high-side MOSFET when V
SUM
exceeds the integrated feedback voltage (V
).
For more information on the current limit, see the
Setting the Current Limit section.
COMP
The differential current sense is also used to provide
peak inductor current limiting. This current limit is more
accurate than the valley current limit, which is mea-
sured across the low-side MOSFET’s on-resistance.
Switching Frequency and Synchronization
The MAX8650 has an adjustable internal oscillator that
can be set to any frequency from 200kHz to 1.2MHz.
To set the switching frequency, connect a resistor from
FSYNC to GND. Calculate the resistor value from the
following equation:
Current-Limit Circuit
The MAX8650 uses both foldback and peak current
limiting (Figure 5). The valley foldback current limit is
used to reduce power dissipation of external compo-
12 ______________________________________________________________________________________
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
of its nominal regulation voltage, POK is high imped-
⎛
⎞
⎛
⎞
1
1kΩ
ance. When the output drops below 89% of its nominal
regulation voltage, POK is internally pulled low. POK is
also internally pulled low when the MAX8650 is shut
down. To use POK as a logic-level signal, connect a
pullup resistor from POK to the logic supply rail.
R
=
−162ns
⎜
⎟
FSYNC
⎜
⎟
2f
16.34ns
⎝
⎠
⎝
⎠
S
The MAX8650 can also be synchronized to an external
clock by connecting the clock signal to FSYNC. In
addition, SYNCO is provided to synchronize a second
MAX8650 controller 180° out-of-phase with the first by
connecting SYNCO of the first controller to FSYNC of
the second. When the first controller is synchronized to
an external clock, the external clock is inverted to gen-
erate SYNCO. Therefore, to get 180° out-of-phase oper-
ation, the clock input to the first controller should have
a 50% duty cycle.
Thermal-Overload Protection
Thermal-overload protection limits total power dissipa-
tion in the MAX8650. When the junction temperature
exceeds +160°C, an internal thermal sensor shuts
down the device, allowing the IC to cool. The thermal
sensor turns the IC on again after the junction tempera-
ture cools by 15°C, resulting in a pulsed output during
continuous thermal-overload conditions.
Power-Good Signal (POK)
POK is an open-drain output on the MAX8650 that mon-
itors the output voltage. When the output is above 92%
V
IN
10V TO 24V
R1
D1
C1
R2
C2
C3
SYNC
EN
1
11
24
3
2
FSYNC
EN
MODE
BST
D2
4
5
ON
OFF
POK
V
OUT
POK
DH
L1
3.3V/15A
C6
6
7
Q1
Q2
SYNCO
C9A
SYNCO
LX
DL
MAX8650EEG
23
R14
SCOMP
C9B
C10
R5
22
21
8
ILIM2
REFIN
PGND
VL
C11
R6
9
C5
C13
C15
20
16
10
SS
IN
R13
C14
R15
12
14
15
ILIM1
AVL
C7
R8
19
18
COMP
FB
CS+
CS-
C8
C12
R9
R10
R11
R12
13
GND
17
OVP
Figure 3. Applications Circuit with 500kHz Switching, 10V to 24V Input, and 3.3V/15A Output
______________________________________________________________________________________ 13
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
Table 1. Component List for Figure 3
COMPONENT
C1, C2, C3
C5, C6
DESCRIPTION
10µF, 25V X5R ceramic capacitors
0.1µF, 10V X7R ceramic capacitors
220pF, 50V X7R ceramic capacitor
Not installed
VENDOR/PART
TDK C3225X5R1E106M (1210)
Kemet C0603C104M9RAC (0603)
TDK C1608X7R1H271K
—
QUANTITY
3
2
1
0
C7
C8
150µF 20%, 4V, 7mΩ ESR polymer
aluminum electrolytic capacitors
C9A, C9B
Panasonic EEFSDOG151R
2
C10, C14
C11
0.47µF 10%, 10V X5R ceramic capacitors
4.7µF, 10V X5R ceramic capacitor
100pF, 25V C0G ceramic capacitor
1µF, 16V X5R ceramic capacitors
100V, 200mA switching diode
Taiyo Yuden LMK107BJ474KA (0603)
TDK C2012X5R1A475M (0805)
Kemet C603C101K3GAC (0603)
TDK C1608X7R1C105M (0603)
Central CMPD914 (SOT23)
2
1
1
2
1
1
C12
C13, C15
D1
D2
30V, 100mA Schottky diode
Central CMPSH-3 (SOT23)
1.2µH, 18.2A, 2.6mΩ max, 2.16mΩ typ
inductor
L1
TOKO FDA1254-1R2M
1
Q1
Q2
30V n-channel MOSFET
30V n-channel MOSFET
51.1kΩ 1% resistor (0603)
100kΩ 5% resistor (0603)
0Ω resistor
Fairchild FDS7296N3
1
1
1
1
1
0
1
1
1
2
2
1
1
1
Fairchild FDS7088SN3
R1
—
—
—
—
—
—
—
—
—
—
—
—
R2
R3
R4
Not installed
R5
17.4kΩ 1% resistor (0603)
130kΩ 1% resistor (0603)
220kΩ 5% resistor (0603)
7.5kΩ 1% resistors (0603)
28.0kΩ 1% resistors (0603)
39.2Ω 1% resistor (0603)
2.4kΩ 5% resistor (0603)
39.2kΩ 5% resistor (0603)
R6
R8
R9, R11
R10, R12
R13
R14
R15
14 ______________________________________________________________________________________
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
V
IN
10.8V TO 13.2V
R2
D1
R1
C1
C2
SYNC
EN
1
11
24
3
2
FSYNC
EN
MODE
BST
D2
OPTIONAL
4
5
ON
OFF
POK
V
OUT
POK
DH
L1
0.9V 8A
C5
6
7
Q1
Q2
SYNCO
C8A C8B C8C C8D C8E
SYNCO
LX
DL
MAX8650
23
22
R11
SCOMP
ILIM2
R5
C9
8
PGND
VL
R6
C10
9
21
C3
REFIN
C12
C14
10
V
REFIN
IN
0.9V
DC
C4
20
16
19
C13
R12
SS
12
14
15
AVL
R7
ILIM1
COMP
CS+
CS-
C6
R8
C11
C7
R9
18
17
FB
13
GND
R10
OVP
Figure 4. Applications Circuit with 400kHz Switching, 12V Input, and 0.9V ±±A Output
______________________________________________________________________________________ 15
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
Table 2. Component List for Figure 4
COMPONENT
DESCRIPTION
VENDOR / PART
Taiyo Yuden EMK325BJ106MN
Kemet C0603C103M9RAC
Kemet C0603C104M9RAC
TDK C1608X7R1H182K
QUANTITY
C1, C2
C3
10µF, 16V X5R ceramic capacitors (1210)
0.01µF, 10V X7R ceramic capacitor (0603)
0.1µF, 10V X7R ceramic capacitors
1800pF, 50V X7R ceramic capacitor
X7% 22pF, 50V ceramic capacitor
2
1
2
1
1
C4, C5
C6
C7
TDK C1608C0G1H220K
680µF/20%, 2.5V, 6mΩ ESR capacitors, POS
Al Lytic
C8A–C8E
C9, C13
Sanyo 2R5TPD680M6
5
2
10V 10%, 0.47µF X5R ceramic capacitors
(0603)
Taiyo Yuden LMK107BJ474KA
C10
C11
C12, C14
D1
4.7µF, 10V X5R ceramic capacitor (0805)
100pF, 25V ceramic capacitor (C0G)
1µF, 16V X5R ceramic capacitors (0603)
Diode, switching, 100V, 200mA
30V, 100mA diode Schottky
0.56µH, 15A, 1.7mΩ inductor
30V n-MOSFET, 8-pin SO
30V n-MOSFET, 8-pin SO
100kΩ 5% resistor (0603)
66.5kΩ 1% resistor (0603)
0Ω resistor
TDK C2012X5R1A475M
1
1
2
1
1
1
1
1
1
1
1
0
1
1
1
1
2
1
1
Kemet C0402C101K3GAC
TDK C1608X7R1C105M
Central/CMPD914
D2
Central/CMPSH-3
L1
Panasonic ETQPLR56WFC
Q1
Vishay Si4346DY
Q2
Vishay Si4362DY
R1
—
—
—
—
—
—
—
—
—
—
—
R2
R3
R4
Resistor, open
R5
16.2kΩ 1% resistor (0603)
35.7 kΩ 1% resistor (0603)
15.8kΩ 1% resistor (0603)
160kΩ 5% resistor (0603)
10kΩ 5% resistors (0603)
1.5kΩ 5% resistor (0603)
1.1kΩ 5% resistor (0603)
R6
R7
R8
R9, R10
R11
R12
Table 3. Suggested Components Manufacturers
MANUFACTURER
Central Semiconductor
Fairchild Semiconductor
Panasonic
COMPONENTS
PHONE
WEBSITE
Diodes
631-435-1110
972-910-8000
714-373-7939
847-545-6700
408-573-4150
847-803-6100
402-564-3131
www.centralsemi.com
www.fairchildsemi.com
www.panasonic.com
www.sumida.com
MOSFETs
Capacitors
Inductors
Sumida
Taiyo Yuden
Capacitors
Capacitors
MOSFETs
www.t-yuden.com
TDK
www.component.tdk.com
www.vishay.com
Vishay
16 ______________________________________________________________________________________
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
I
I
I
PEAK
AVL
LOAD
MAX8650
R4
R3
VALLEY
SCOMP
TIME
Figure 5. Inductor-Current Waveform
Figure 6. Resistor-Divider for Setting the Slope Compensation
For a slope compensation of 250mV/T, connect
SCOMP to AVL.
Design Procedure
Setting the Output Voltage
To set the output voltage for the MAX8650, connect FB
to the center of an external resistor-divider from the out-
put to GND (R9 and R10 of Figure 3). Select R9
between 8kΩ and 24kΩ, and then calculate R10 with
the following equation:
For applications with a duty cycle greater than 50%, set
the SCOMP voltage with a resistor voltage-divider from
AVL to GND (R3 and R4 in Figure 6). First, use the fol-
lowing equation to find the SCOMP voltage:
V
× 60 × R
L
OUT
V
=
SCOMP
⎛
⎞
V
OUT
f × L
S
R10 = R9 ×
−1
⎜
⎟
V
⎝
⎠
FB
where R is the DC resistance of the inductor, and f is
L
S
the switching frequency.
where V = 0.7V. R9 and R10 should be placed as
FB
Next, select a value for R3, typically 10kΩ, and solve
for R4 as follows:
close to the IC as possible.
Setting the Output Overvoltage
Protection Threshold
To set the overvoltage threshold voltage for the
MAX8650, connect OVP to the center of an external
resistor-divider from the output to GND (R11 and R12 of
Figure 3). Select R11 between 8kΩ and 24kΩ, then cal-
culate R12 with the following equation:
5V − V
× R3
(
SCOMP
)
R4 =
V
SCOMP
This sets the slope-compensation voltage rate to
/ (10 x T).
V
SCOMP
Inductor Selection
⎛
⎞
There are several parameters that must be examined
when determining which inductor is to be used. Input
voltage, output voltage, load current, switching fre-
quency, and LIR. LIR is the ratio of inductor-current rip-
ple to maximum DC load current. A higher LIR value
allows for a smaller inductor, but results in higher loss-
es and higher output ripple. A good compromise
between size and efficiency is an LIR of 0.3. Once all
the parameters are chosen, the inductor value is deter-
mined as follows:
V
OUT
R12 = R11×
−1
⎜
⎟
V
⎝
⎠
OVP
where V
= 0.8V when using the internal reference.
When using an external reference, V
OVP
is 115% of
OVP
V
.
REFIN
Setting the Slope Compensation
For most applications where the duty cycle is less than
50%, connect SCOMP to GND to set the slope com-
pensation to the default of 125mV/T, where T is the
V
× (V − V
)
OUT
IN
OUT
L =
oscillator period (T = 1 / f ).
S
V
× f ×I
× LIR
IN
S
LOAD(MAX)
______________________________________________________________________________________ 17
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
where f is the switching frequency. Choose a standard-
S
value inductor close to the calculated value. The exact
inductor value is not critical and can be adjusted to
make trade-offs between size, cost, and efficiency.
Lower inductor values minimize size and cost, but they
also increase the output ripple and reduce the efficiency
due to higher peak currents. On the other hand, higher
inductor values increase efficiency, but eventually resis-
tive losses due to extra turns of wire exceed the benefit
gained from lower AC current levels. This is especially
true if the inductance is increased without also increas-
ing the physical size of the inductor. Find a low-loss
inductor with the lowest possible DC resistance that fits
the allotted dimensions. Ferrite cores are often the best
choice, although powdered iron is inexpensive and can
work well at 300kHz. The chosen inductor’s saturation
current rating must exceed the peak inductor current
determined as:
OUT
LX
R
FOBK
MAX8650
ILIM2
R
ILIM2
Figure 7. ILIM2 Resistor Connections
2) If the resulting value of R
is negative, either
ILIM2
increase P or choose a low-side MOSFET with a
FB
lower R
. The latter is preferred as it increases
DS(ON)
the efficiency and results in a lower short-cir-
cuit current.
LIR
I
=I
+
×I
LOAD(MAX)
PEAK LOAD(MAX)
2
To set the constant-current limit for the latchup
mode, only R
is used. The equation for R
ILIM2
ILIM2
Setting the Current Limit
below sets the current-limit threshold at 1.2 times the
maximum rated output current:
Valley Current Limit
The MAX8650 has an adjustable valley current limit,
configurable for foldback with automatic recovery, or a
constant-current limit with latchup. To set the current
limit for foldback mode, connect a resistor from ILIM2
1.2 ×I
× R
DS(ON)
VALLEY
R
=
ILIM2
1µA
to the output (R
to GND (R
), and another resistor from ILIM2
). See Figure 7. The values of R
are calculated as follows:
FOBK
Similarly, I
is the value of the inductor valley
VALLEY
ILIM2
FOBK
current at maximum load and R
is the maxi-
DS(ON)
and R
ILIM2
mum on-resistance of the low-side MOSFET at the
highest operating junction temperature.
1) First, select the percentage of foldback (P ). This
FB
percentage corresponds to the current limit when
Peak Current Limit
V
V
P
P
equals zero, divided by the current limit when
equals its nominal voltage. A typical value of
OUT
OUT
The peak current-limit threshold (V ) is set by a resis-
TH
tor connected from ILIM1 to GND. V corresponds to
TH
is in the 15% to 40% range. A lower value of
yields lower short-circuit current. The following
equations are used to calculate R
FB
FB
the peak voltage across the sensing element (inductor
or current-sense resistor), R
as follows:
. R
is calculated
LIM1
LIM1
and R
:
FOBK
ILIM2
8 × V
P
× V
OUT
TH
FB
R
=
R
=
ILIM1
FOBK
10µA
This allows a maximum DC output current (I ) of:
5µA × 1− P
(
FB
)
LIM
5 × R
×I
× 1− P
× R
FOBK
DS(ON) VALLEY
(
FB
)
V
I
PK−PK
TH
R
=
ILIM2
I
=
−
LIM
⎡
⎤
V
− 5 × R
×I
× 1− P
R
2
OUT
DS(ON) VALLEY
(
FB
)
DC
⎢
⎥
⎦
⎣
where R
is either the DC resistance of the inductor or
the value of the optional current-sense resistor.
DC
where I
is the value of the inductor valley current
VALLEY
at maximum load (I
is the maximum on-resistance of the low-side
MOSFET at the highest operating junction temperature.
- 1/2 x I
), and
P-P
LOAD(MAX)
To ensure maximum output current, use the minimum
value of V from each setting, and the maximum R
values at the highest expected operating temperature.
R
DS(ON)
TH
DC
18 ______________________________________________________________________________________
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
R3
L1
L1
V
MAX8650
OUT
MAX8650
V
OUT
LX
LX
R4
R4
C9
C9
R5
C13
R5
C13
CS+
CS-
CS+
CS-
Figure ±. Current Sense Using the Inductor’s DC Resistance
Figure 9. Using a Current-Sense Resistor for Improved Current-
Sense Accuracy
The DC resistance of the inductor’s copper wire has a
+0.22%/°C temperature coefficient.
2) Maximum drain-to-source voltage (V
): should
DSS
be at least 20% higher than the input supply rail at
the high-side MOSFET’s drain.
To use the DC resistance of the output inductor for cur-
rent sensing, an RC circuit is added (see Figure 8). The
3) Gate charges (Q , Q , Q ): the lower, the better.
G
GD GS
RC time constant is set at twice the inductor (L/R ) time
DC
For a 5V input application, choose the MOSFETs with
rated R at V
constant. Pick the value of C9 (typically 0.47µF), then cal-
≤ 4.5V. With higher input volt-
GS
DS(ON)
culate the resistor value from R4 = 2L / (R x C9).
DC
ages, the internal VL regulator provides 6.5V for gate
drive to minimize the on-resistance for a wide range of
MOSFETs.
Add a resistor (R5 in Figure 8) to the CS- connection to
minimize input offset error. Calculate the value of R5 as
follows:
For a good compromise between efficiency and cost,
choose the high-side MOSFET (N1, N2) that has con-
duction losses equal to switching losses at nominal
input voltage and output current. The selected low-side
1) When V
≥ 2.4V:
OUT
⎛
⎞
R
×10µA
ILIM1
20µA +
× R4
⎜
⎟
MOSFET (N3, N4) must have an R
that satisfies
DS(ON)
32kΩ
20mA
⎝
⎠
R5 =
2) When V
the current-limit-setting condition above. Make sure that
the low-side MOSFET does not spuriously turn on due
to dV/dt caused by the high-side MOSFET turning on,
as this would result in shoot-through current and
degrade the efficiency. MOSFETs with a lower
< 2.4V:
OUT
15µAx R4
×10µA
R5 =
Q
/Q ratio have higher immunity to dV/dt. For high-
GD GS
⎛
⎞
R
ILIM1
current applications, it is often preferable to parallel two
MOSFETs rather than to use a single large MOSFET.
15µA +
⎜
⎟
32kΩ
⎝
⎠
For proper thermal-management design, the power dis-
sipation must be calculated at the desired maximum
operating junction temperature, maximum output cur-
rent, and worst-case input voltage (for the low-side
Capacitor C13 is connected in parallel with R5 and is
equal in value to C9.
The equivalent current-sense resistance when using an
inductor for current sensing is equal to the DC resis-
MOSFET, worst case is at V
; for the high-side
IN(MAX)
tance of the inductor (R ).
MOSFET, it could be either at V
or V
).
IN(MIN)
DC
IN(MAX)
The high-side and low-side MOSFETs have different
loss components due to the circuit operation. The low-
side MOSFET operates as a zero voltage switch; there-
fore, major losses are the channel-conduction loss
MOSFET Selection
The MAX8650 drives two or four external, logic-level, n-
channel MOSFETs as the circuit switch elements. The
key selection parameters are:
(P
) and the body-diode conduction loss (P
).
LSCC
LSDC
1) On-resistance (R
): the lower, the better.
DS(ON)
______________________________________________________________________________________ 19
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
ing junction temperature with the above calculated
⎛
⎞
V
2
OUT
power dissipations.
P
= 1−
×I
× R
DS(ON)
LSCC
⎜
⎟
LOAD
V
⎝
⎠
IN
To reduce EMI caused by switching noise, add a 0.1µF
ceramic capacitor from the high-side switch drain to
the low-side switch source or add resistors in series
with DH and DL to slow down the switching transitions.
However, adding series resistors increases the power
dissipation of the MOSFET, so ensure this does not
overheat the MOSFET.
Use R
at T
:
J(MAX)
DS(ON)
P
= 2×I
× V × t × f
LSDC
LOAD F DT S
where V is the body-diode forward-voltage drop, t is
F
DT
the dead time between high-side and low-side switching
transitions (30ns typ), and f is the switching frequency.
S
Input Capacitor
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching.
The input capacitor must meet the ripple-current
The high-side MOSFET operates as a duty-cycle con-
trol switch and has the following major losses: the
channel-conduction loss (P
), the VL overlapping
HSCC
switching loss (P
), and the drive loss (P
).
HSDR
HSSW
requirement (I
) imposed by the switching currents
RMS
The high-side MOSFET does not have body-diode con-
duction loss, unless the converter is sinking current,
when the loss due to body-diode conduction is calcu-
defined by the following equation:
I
V
× V − V
lated as P
= 2 x I
x V x t x f :
LOAD OUT
(
IN
OUT
)
HSDC
LOAD
F
DT
S
I
=
RMS
V
IN
V
2
OUT
P
=
×I
× R
DS(ON)
LOAD
HSCC
I
has a maximum value when the input voltage
RMS
V
IN
equals twice the output voltage (V = 2 x V
), so
OUT
IN
I
= I
/ 2. Ceramic capacitors are recom-
RMS(MAX)
LOAD
Use R
at T
:
J(MAX)
DS(ON)
P
mended due to their low ESR and ESL at high frequen-
cy with relatively low cost. Choose a capacitor that
exhibits less than 10°C temperature rise at the maxi-
mum operating RMS current for optimum long-term reli-
ability. Ceramic capacitors with X5R or better
temperature characteristics are recommended.
Q
+ Q
GD
GS
= V ×I
×
× f
S
HSSW
IN LOAD
I
GATE
where I
is the average DH driver output-current
capability determined by:
GATE
Output Capacitor
The key selection parameters for the output capacitor
are the actual capacitance value, the equivalent series
resistance (ESR), the equivalent series inductance
(ESL), and the voltage-rating requirements. These
parameters affect the overall stability, output voltage
ripple, and transient response. The output ripple has
three components: variations in the charge stored in
the output capacitor, the voltage drop across the
capacitor’s ESR and ESL caused by the current into
and out of the capacitor. The maximum output voltage
ripple is estimated as follows:
0.5 × V
VL
I
≅
GATE
R
+ R
GATE
DS(ON)(DR)
where R
is the high-side MOSFET driver’s
DS(ON)(DR)
on-resistance (1.5Ω typ) and R
is the internal gate
GATE
resistance of the MOSFET (~2Ω):
R
GATE
P
= Q × V × f ×
HSDR
G
GS
S
R
+ R
DS(ON)(DR)
GATE
where V ≈ V
GS
VL.
V
= V
+ V
+ V
RIPPLE
RIPPLE(ESR)
RIPPLE(C) RIPPLE(ESL)
In addition to the losses above, allow approximately
20% more for additional losses due to MOSFET output
capacitances and low-side MOSFET body-diode
reverse-recovery charge dissipated in the high-side
MOSFET, but is not well defined in the MOSFET data
sheet. Refer to the MOSFET data sheet for thermal-
resistance specifications to calculate the PC board
area needed to maintain the desired maximum operat-
The output voltage ripple as a consequence of the
ESR, ESL, and output capacitance is:
V
=I
× ESR
RIPPLE(ESR) P−P
V
IN
V
=
× ESL
RIPPLE(ESL)
L + ESL
20 ______________________________________________________________________________________
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
tor or the alternate series current-sense resistor to mea-
I
P−P
sure the inductor current. Current-mode control elimi-
nates the double pole in the feedback loop caused by
the inductor and output capacitor resulting in a smaller
phase shift and requiring a less elaborate error-amplifier
compensation than voltage-mode control. A simple sin-
gle-series R and C is all that is needed to have a sta-
V
=
RIPPLE(C)
8 × C
× f
S
OUT
where I
is the peak-to-peak inductor current:
P-P
V
− V
V
OUT
IN
OUT
C
C
I
=
×
P−P
ble, high-bandwidth loop in applications where ceramic
capacitors are used for output filtering. For other types
of capacitors, due to the higher capacitance and ESR,
the frequency of the zero created by the capacitance
and ESR is lower than the desired closed-loop
crossover frequency. To stabilize a nonceramic output
capacitor loop, add another compensation capacitor
from COMP to GND to cancel this ESR zero.
f × L
V
IN
S
These equations are suitable for initial capacitor selec-
tion, but final values should be chosen based on a proto-
type or evaluation circuit. As a general rule, a smaller
current ripple results in less output-voltage ripple. Since
the inductor ripple current is a factor of the inductor
value and input voltage, the output-voltage ripple
decreases with larger inductance, and increases with
higher input voltages. Ceramic, tantalum, or aluminum
polymer electrolytic capacitors are recommended. The
aluminum electrolytic capacitor is the least expensive;
however, it has higher ESR. To compensate for this, use
a ceramic capacitor in parallel to reduce the switching
ripple and noise. For reliable and safe operation, ensure
that the capacitor’s voltage and ripple-current ratings
exceed the calculated values.
The basic regulator loop is modeled as a power modu-
lator, an output feedback-divider, and an error amplifi-
er. The power modulator has DC gain set by g
x
mc
, the out-
R
, with a pole and zero pair set by R
LOAD
LOAD
put capacitor (C
), and its ESR. Below are equations
OUT
that define the power modulator:
R
R
× f × L
S
LOAD
LOAD
G
= g
×
mc
MOD(dc)
+ f × L
S
The response to a load transient depends on the
selected output capacitors. After a load transient, the
output voltage instantly changes by ESR x ∆I
where R
= V
/ I
, f is the switching
OUT(MAX) S
LOAD
OUT
.
LOAD
frequency, L is the output inductance, and g
= 1 /
mc
Before the controller can respond, the output voltage
deviates further, depending on the inductor and output-
capacitor values. After a short period (see the Typical
Operating Characteristics), the controller responds by
regulating the output voltage back to its nominal state.
The controller response time depends on its closed-
loop bandwidth. With a higher bandwidth, the response
time is faster, thus preventing the output voltage from
further deviation from its regulating value.
(A
x R ), where A
is the gain of the current-
VCS
DC
VCS
sense amplifier (12 typ), and R
of the inductor.
is the DC resistance
DC
Find the pole and zero frequencies created by the
power modulator as follows:
1
f
=
pMOD
⎛
⎞
R
R
× f × L
LOAD
LOAD
S
2π × C
×
+ ESR
⎜
⎟
OUT
+ f × L
Compensation Design
The MAX8650 uses an internal transconductance error
amplifier whose output compensates the control loop.
The external inductor, output capacitor, compensation
resistor, and compensation capacitors determine the
loop stability. The inductor and output capacitor are
chosen based on performance, size, and cost.
Additionally, the compensation resistor and capacitors
are selected to optimize control-loop stability. The com-
ponent values, shown in the circuits of Figures 3 and 4,
yield stable operation over the given range of input-to-
output voltages.
⎝
⎠
S
1
f
=
zMOD
2π × C
× ESR
OUT
When C
comprises “n” identical capacitors in paral-
OUT
lel, the resulting C
= n x C
, and ESR =
OUT
OUT(EACH)
ESR
/ n. Note that the capacitor zero for a paral-
(EACH)
lel combination of like capacitors is the same as for an
individual capacitor. See Figures 10 and 11 for illustra-
tions of the pole and zero locations.
The feedback voltage-divider has a gain of G = V
OUT
/
FB
FB
The controller uses a current-mode control scheme that
regulates the output voltage by forcing the required cur-
rent through the external inductor, so the MAX8650 uses
the voltage drop across the DC resistance of the induc-
V
, where V is equal to 0.75V.
FB
______________________________________________________________________________________ 21
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
CLOSE LOOP
CLOSE LOOP
GAIN
(dB)
GAIN
(dB)
POWER
MODULATOR
POWER
MODULATOR
ERROR
AMP
ERROR
AMP
f
C
0dB
0dB
FREQUENCY
f
pMOD
FREQUENCY
f
pMOD
FB
DIVIDER
FB
DIVIDER
f
f
C
zMOD
f
zMOD
Figure 10. Simplified Gain Plot for the f
> f Case
Figure 11. Simplified Gain Plot for the f < f Case
zMOD C
zMOD
C
The transconductance error amplifier has a DC gain,
For the case where f
is greater than f :
zMOD C
G
= g
x R , where g
is the error-amplifi-
mEA
EA(DC)
mEA
O
G
= g
× R
C
er transconductance, which is equal to 110µS, R is
O
EA(fc)
mEA
the output resistance of the error amplifier, which is
30MΩ. A dominant pole is set by the compensation
f
pMOD
capacitor (C ), the amplifier output resistance (R ),
C
O
G
= G
×
MOD(fc)
MOD(dc)
and the compensation resistor (R ), and a zero is set
f
C
C
by the compensation resistor (R ) and the compensa-
C
Then R can be calculated as:
C
tion capacitor (C ). There is an optional pole set by C
C
F
and R to cancel the output-capacitor ESR zero if it
C
V
occurs near the crossover frequency (f ). Thus:
C
OUT
R
=
C
g
× V × G
FB MOD(fc)
mEA
1
f
=
where g
= 110µS.
pdEA
mEA
2π × C × (R + R )
C
O
C
The error-amplifier compensation zero formed by R
C
and C should be set at the modulator pole fp
.
C
MOD
1
Calculate the value of C as follows:
C
f
=
=
zEA
2π × C × R
C
C
R
× f × L × C
S OUT
LOAD
C
=
C
R
+ f × L × R
LOAD
S
C
1
f
pEA
2π × C × R
If f
is less than 5 x f , add a second capacitor,
zMOD
C
F
C
C , from COMP to GND. The value of C is:
F
F
The crossover frequency, f , should be much higher
C
than the power-modulator pole fp
. Also, f should
C
MOD
1
be less than or equal to 1/5 the switching frequency.
Select a value for f in the range:
C =
F
2π × R × f
C
C
zMOD
f
S
As the load current decreases, the modulator pole also
decreases; however, the modulator gain increases
accordingly and the crossover frequency remains the
same.
f
<< f ≤
C
pMOD
At the crossover frequency, the total loop gain must
equal 1, and is expressed as:
V
FB
G
× G
×
=1
EA(fc)
MOD(fc)
V
OUT
22 ______________________________________________________________________________________
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
For the case where f
is less than f :
C
zMOD
1
f
=
pMOD
The power modulator gain at f is:
C
⎛
⎞
R
R
× f × L
LOAD
S
2π × C
×
+ ESR
⎜
⎟
OUT
+ f × L
⎝
⎠
f
LOAD
1
S
pMOD
G
= G
×
×
MOD(fc)
MOD(dc)
f
=
zMOD
⎛
⎜
⎞
⎟
⎛
⎝
⎞
⎟
⎠
3
−6
−6
0.22 × (500 ×10 )× 1.2 ×10
⎜
The error-amplifier gain at f is:
C
−6
2π × (300 ×10 )× ⎜
+ 0.0035⎟
⎛
⎝
⎞
⎟
⎠
⎜
⎜
⎝
3
⎟
⎟
⎠
0.22 + (500 ×10 )× 1.2 ×10
⎜
f
zMOD
G
= g
× R
mEA C
EA(fc)
= 3.23kHz
f
C
f
S
R is calculated as:
C
f
<< f ≤
C
pMOD
5
V
f
C
OUT
3.23kHz << f ≤ 100kHz, select f = 100kHz:
C
C
R
=
×
C
V
g
× G × f
MOD(fc) zMOD
FB
mEA
1
1
f
=
=
=152kHz
= 0.201
zMOD
where g
= 110µS.
mEA
−6
2π × C
× ESR
OUT
2π × (300 ×10 )× 0.0035
C is calculated from:
C
Since f
> f :
C
zMOD
R
× f × L × C
S OUT
LOAD
C
=
C
f
3230
pMOD
R
+ f × L × R
(
LOAD
S
)
C
G
= G
×
= 6.22 ×
MOD(fc)
MOD(dc)
3
f
C
100 ×10
C is calculated from:
F
V
OUT
R
=
C
g
× V × G
MOD(fc)
mEA
FB
1
C =
F
3.3
2π × R × f
=
=199kΩ
C
zMOD
⎛
⎜
⎝
⎞
⎟
⎠
−6
110 ×10
× 0.7 × 0.201
Below is a numerical example to calculate R and C
C
values of the typical operating circuit of Figure 3:
C
Select the nearest standard value: R = 200kΩ:
C
A
= 12
VCS
R
× f × L × C
S OUT
LOAD
C
=
L = 1.2µH
= 2.16mΩ
C
R
+ f × L × R
(
LOAD
S
)
C
R
DC
3
−6
−6
0.22(500 ×10 )× (1.2 ×10 )× (300 ×10
)
f = 500kHz
S
=
= 241p
= 5.2pF
⎛
⎜
⎝
⎞
⎠
3
−6
3
g
V
= 1 / (A
x R ) = 1 / (12 x 0.00216) = 38.6S
VCS DC
mc
0.22 + (500 ×10 )× (1.2 ×10 ) × (200 ×10 )
⎟
= 3.3V
OUT
Select the nearest standard value: C = 270pF:
C
I
= 15A
OUT(MAX)
R
= V
/ I
= 3.3 / 15 = 0.22Ω
LOAD
OUT OUT(MAX)
1
1
3
C
=
=
F
C
= 300µF
OUT
3
2π × R × f
C
zMOD
2π × (200 ×10 )× (152 ×10 )
ESR = 3.5mΩ
= g
Since the calculated value for C is very small (close to
F
the parasitic capacitance present at COMP), it is not
necessary:
R
R
× f × L
S
LOAD
LOAD
G
×
mc
MOD(dc)
+ f × L
S
⎛
⎝
⎞
⎟
⎠
⎞
⎟
3
−6
−6
0.22 × (500 ×10 )× 1.2 ×10
⎜
R8 = R = 200kΩ
C
= 38.6 ×
= 6.22
C7 = C = 270pF
C
⎛
3
0.22 + (500 ×10 )× 1.2 ×10
⎜
C8 = C = Not installed
F
______________________________________________________________________________________ 23
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
the power MOSFET data sheet for recommended
Applications Information
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switch-
copper area.
7) Place the feedback and compensation components
as close to the IC pins as possible. Connect the
ing losses and clean, stable operation. The switching
feedback resistor-divider from FB to the output as
power stage requires particular attention. Follow these
close as possible to the farthest output capacitor.
guidelines for good PC board layout:
8) Refer to the MAX8650 evaluation kit for an example
1) Place IC decoupling capacitors as close to IC pins
layout.
as possible. Keep the power ground plane and sig-
nal ground plane separate. Place the input ceramic
Chip Information
decoupling capacitor directly across and as close as
PROCESS: BiCMOS
possible to the high-side MOSFET’s drain and the
low-side MOSFET’s source. This is to help contain
the high switching current within this small loop.
2) For output current greater than 10A, a multilayer PC
Pin Configuration
board is recommended. Pour a signal ground plane
in the second layer underneath the IC to minimize
noise coupling.
TOP VIEW
3) Connect input, output, and VL capacitors to the
power ground plane; connect all other capacitors to
the signal ground plane.
FSYNC
1
2
24 POK
23 SCOMP
22 ILIM2
21 REFIN
20 SS
MODE
SYNCO
BST
DH
3
4) Place the inductor current-sense resistor and capac-
itor as close to the inductor as possible. Make a
Kelvin connection to minimize the effect of PC board
trace resistance. Place the input-bias balance resis-
tor (R5 in Figures 8 and 9) near CS-. Run two closely
parallel traces from across the capacitor (C9 in
Figures 8 and 9) to CS+ and CS-.
4
MAX8650
5
LX
6
19 COMP
18 FB
DL
7
PGND
VL
8
17 OVP
16 ILIM1
15 CS-
5) Place the MOSFET as close as possible to the IC to
minimize trace inductance of the gate-drive loop. If
parallel MOSFETs are used, keep the trace lengths
to both gates equal.
9
IN
10
11
12
EN
14 CS+
13 GND
6) Connect the drain leads of the power MOSFET to a
large copper area to help cool the device. Refer to
AVL
QSOP
24 ______________________________________________________________________________________
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
1
21-0055
E
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
© 2006 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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