MAX8753ETI_技术文档

19-3919; Rev 0; 1/06

TFT LCD DC-DC Converter with

Integrated Charge Pumps

General Description

Features

The MAX8753 quadruple-output DC-DC converter pro-

vides the regulated voltages required by active-matrix,

thin-film transistor (TFT), liquid-crystal displays (LCDs).

ꢀ 3 Integrated DC-DC Converters, 1 LDO

ꢀ 1MHz Current-Mode PWM Boost Regulator

Up to +13V Main High-Power Output

1ꢀ ꢁAAuraAc

It includes a high-power step-up regulator (V

), two

MAIN

), and a low-

low-power charge pumps (V

and V

POS

NEG

).

voltage 300mA linear regulator (V

High EffiAienAc (90ꢀ)

LOGIC

The step-up DC-DC converter is a high-frequency

(1MHz) current-mode regulator with a built-in power

MOSFET that allows the use of ultra-small inductors and

ceramic capacitors. It provides fast transient response

to pulsed loads and includes an automatic pulse-skip-

ping mode that increases efficiency over a wide-load

current range. The 1.5A current limit allows a +10V out-

put at more than 300mA from a +3.3V input.

ꢀ Dual Charge-Pump Outputs

No External Diodes for Positive Charge Pump

Up to +28V Positive Charge-Pump Output

Negative Charge-Pump Output

ꢀ 300mꢁ LogiA Linear Regulator

ꢀ +2.6V to +5.5V Input Operating Range

ꢀ 0.8mꢁ QuiesAent Current

The two charge pumps independently regulate one

positive and one negative output voltage. The positive

charge pump is a voltage tripler that accepts an input

voltage up to +13V and delivers a 20mA output up to

+28V without external switches or diodes. The negative

charge pump inverts an input voltage up to +24V and

delivers a 20mA negative output using external diodes.

ꢀ Internal Supplc SequenAing and Soft-Start

ꢀ Thermal ProteAtion

ꢀ Ultra-Thin, 28-Pin TQFN PaAkage (0.8mm max)

Ordering Information

The logic linear regulator converts the IC’s +2.6V-to-

+5.5V input to a regulated +2.5V or adjustable output.

The MAX8753 is available in a 28-pin thin QFN pack-

age with a maximum thickness of 0.8mm for ultra-thin

LCD panel design.

PꢁRT

TEMP RꢁNGE

PIN-PꢁCKꢁGE

28 Thin QFN

(5mm x 5mm)

MAX8753ETI+

-40°C to 85°C

+Denotes lead-free package.

Applications

Minimal Operating Circuit

Notebook Computers, PDAs

Car Navigation Displays

LCD Monitors

V

IN

+2.6V TO +5.5V

MAIN

PGND

IN

Pin Configuration

TOP VIEW

V

MAIN

GND

FB

SUPN

SHDN

21 20 19 18 17 16 15

14

13

PGND 22

N.C. 23

REF

C3P

FBN

V

NEG

GND

MAX8753

12 N.C.

24

25

26

27

28

DLP

SHDN

LCDON

C1N

LCDON

OUTL

V

LOGIC

IN

11

10

9

MAX8753

REF

V

POS

OUTL

FBL

FBP

FBL

DLP

OUTP

8

C1P

FBP

1

2

3

4

5

6

7

TQFN

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

TFT LCD DC-DC Converter with

Integrated Charge Pumps

ꢁBSOLUTE MꢁXIMUM RꢁTINGS

SUPN to PGND.......................................................-0.3V to +30V

IN, SHDN, LCDON to GND ......................................-0.3V to +6V

C3P to PGND.........................................-0.3V to (V

+ 0.3V)

DLP, OUTL, FBL, FBP, FBN, INTG, FB,

SUPN

Continuous Power Dissipation (T = +70°C)

REF to GND ............................................-0.3V to (V + 0.3V)

A

IN

28-Pin 5mm x 5mm TQFN (derated 21.3mW/°C

PGND to GND .......................................................-0.3V to +0.3V

LX to PGND ............................................................-0.3V to +14V

SUPP to PGND .......................................................-0.3V to +14V

above +70°C)............................................................1702mW

Operating Temperature Range .......................... -40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

C1N, C2N to PGND ................................-0.3V to (V

+ 0.3V)

SUPP

OUTP to PGND ........................................(V

- 0.3V) to +30V

SUPP

C1P to C1N, C2P to C2N, OUTP to C2P ................-0.3V to +14V

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICꢁL CHꢁRꢁCTERISTICS

(Circuit of Figure 1, V = 3.0V, SHDN = LCDON = IN, V

= V

= 10V, PGND = GND, C

= 0.22µF, C

= 470pF, T =

INTG ꢁ

IN

SUPP

SUPN

REF

0°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.)

A

PARAMETER

INPUT SUPPLIES

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input Supply Range

V

2.6

2.1

5.5

2.5

1.5

10

V

IN

Input Undervoltage Threshold

IN Quiescent Supply Current

IN Shutdown Current

V

rising, 100mV hysteresis (typ)

2.3

0.8

0.1

UVLO

IN

I

= V

= 1.5V, V = -0.2V

FBN

mA

µA

V

IN

FB

FBP

= 0, V = 5V

SHDN

IN

SUPP Supply Range

7

13

SUPP

SUPP Quiescent Current

SUPP Shutdown Current

SUPN Supply Range

I

V

= 1.5V

0.4

0.1

0.8

10

mA

µA

V

FBP

= 0, V

= 14V, OUTP floating

= 24V

SHDN

SUPP

V

24

SUPN

SUPN Quiescent Current

SUPN Shutdown Current

MAIN BOOST CONVERTER

Output Voltage Range

FB Regulation Voltage

FB Input Bias Current

I

V

= -0.2V

0.4

0.1

0.8

10

mA

µA

SUPN

FBN

= 0, V

SHDN

SUPN

V

13

V

MAIN

IN

V

1.232

1.245

125

1.258

275

FB

I

V

= 1.25V, INTG = GND

nA

FB

FB Undervoltage Shutdown

Threshold

FB falling

75

125

200

mV

Operating Frequency

Oscillator Maximum Duty Cycle

Load Regulation

f

0.85

78

1.00

85

1.15

90

MHz

%

OSC

I

= 0 to 100mA, V

= 10V

0.2

%

MAIN

Line Regulation

0.1

%/V

µS

Ω

INTG Transconductance

LX Switch On-Resistance

LX Leakage Current

320

0.35

0.01

R

= 100mA

LX

0.7

20

LX(ON)

I

LX

V

= 13V, V = 0

SHDN

µA

LX

2

_______________________________________________________________________________________

TFT LCD DC-DC Converter with

Integrated Charge Pumps

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V = 3.0V, SHDN = LCDON = IN, V

= V

= 10V, PGND = GND, C

= 0.22µF, C

= 470pF, T =

INTG A

IN

SUPP

SUPN

REF

0°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

0.38

0.75

1.13

1.45

MAX

UNITS

Phase I = soft-start (1.0ms)

Phase II = soft-start (1.0ms)

Phase III = soft-start (1.0ms)

Phase IV = fully on (> 3.0ms)

LX Current Limit

I

A

LX(MAX)

1.08

1.80

3072 /

Soft-Start Period

t

SS

Power-up to the end of phase III

s

f

OSC

POSITIVE CHARGE PUMP

V

Input Supply Range

V

7

13

14.0

28

V

SUPP

Overvoltage Threshold

V

= rising, hysteresis (typ) = 200mV

13.2

13.6

SUPP

OUTP Operating Range

Operating Frequency

FBP Regulation Voltage

FBP Line Regulation

FBP Input Bias Current

Soft-Start Period

V

SUPP

1.213

-50

0.25 x

Hz

V

f

OSC

V

1.250

10

1.287

+50

FBP

V

5mA

= 8V to 12V, V

= 1.5V

= 20V, I

=

SUPP

OUTP

mV

nA

s

I

V

FBP

1024 /

V

SSP

f

OSC

C1N, C2N High-Side On-

Resistance

I

= 50mA

15

5

Ω

SOURCE

C1N, C2N Low-Side On-

Resistance

= 50mA

SINK

C1P Switch On-Resistance

C2P Switch On-Resistance

OUTP Switch On-Resistance

NEGATIVE CHARGE PUMP

I

= 50mA

8

Ω

SOURCE

V

Input Supply Range

V

7

24

V

SUPN

0.25 x

Operating Frequency

FBN Regulation Voltage

FBN Line Regulation

FBN Input Bias Current

Soft-Start Period

Hz

mV

nA

s

f

OSC

V

213

-50

250

287

+50

FBN

V

5mA

= 8V to 24V, V

= -0.05V

= -10V, I

=

OUTN

SUPN

OUTN

10

I

V

FBN

1024 /

fosc

V

SSN

C3P High-Side On-Resistance

C3P Low-Side On-Resistance

I

= 50mA

15

10

Ω

SINK

_______________________________________________________________________________________

3

TFT LCD DC-DC Converter with

Integrated Charge Pumps

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V = 3.0V, SHDN = LCDON = IN, V

= V

= 10V, PGND = GND, C

= 0.22µF, C

= 470pF, T =

INTG A

IN

SUPP

SUPN

REF

0°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.)

A

PARAMETER

REGULATOR

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V

LOGIC

FBL Regulation Voltage

FBL Input Bias Current

V

I

= 0 to 300mA

1.225

-50

1.250

1.275

+50

V

nA

V

FBL

OUTL

I

V

= 1.3V

FBL

FBL Undervoltage Lockout

FBL Dual-Mode™ Threshold

V

rising, hysteresis (typ) = 125mV

= rising

1.100

220

1.125

250

1.150

280

FBL_UV

mV

OUTL Voltage Accuracy

(Preset Mode)

V

= GND, I

= 0 to 300mA

OUTL

2.425

2.500

2.575

-2

V

FBL

OUTL Load Regulation

OUTL Line Regulation

OUTL On-Resistance

OUTL Short-Circuit Current

REFERENCE

I

= 0 to 300mA

= 2.6V to 5.5V

%

OUTL

V

0.1

0.7

500

IN

= 3.3V, I

= 100mA

1.5

Ω

IN

OUTL

= GND, V

= 1V

mA

OUTL

FBL

Reference Voltage

V

-2µA < I

< +50µA

1.231

0.9

1.250

1.05

1.269

1.2

V

REF

Reference Undervoltage

Threshold

V

rising

REF

LOGIC SIGNALS

LCDON, SHDN Input Low Voltage

LCDON, SHDN Input High

Voltage

Hysteresis = 0.15 x V (typ)

0.9

V

IN

2.1

SHDN Input Current

I

V

= 0 to IN

0.01

1

µA

SHDN

LCDON Input Current

SEQUENCING

I

= 0 to IN

LCDON

DLP Capacitor Charge Current

V

= 0.5V

4

5

6

µA

V

DLP

DLP Turn-On Threshold

DLP Discharge Switch

On-Resistance

= rising

1.20

1.25

1.30

V

= 0

40

Ω

SHDN

FAULT PROTECTION

Duration to Trigger Fault

FBL Fault-Trip Level

t

50

ms

V

FAULT

Falling edge

0.95

1.07

450

1.01

1.10

500

1.08

1.14

550

FB, FBP Fault-Trip Level

FBN Fault-Trip Level

Falling edge

V

Rising edge

mV

°C

Thermal-Shutdown Threshold

Typical hysteresis = 15°C

+160

Dual-Mode is a trademark of Maxim Integrated Products, Inc.

4

_______________________________________________________________________________________

TFT LCD DC-DC Converter with

Integrated Charge Pumps

ELECTRICAL CHARACTERISTICS

(Circuit of Figure 1, V = 3.0V, SHDN = LCDON = IN, V

= V

= 10V, PGND = GND, C

= 0.22µF, C

= 470pF, T =

INTG A

IN

SUPP

SUPN

REF

-40°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.) (Note 1)

A

PARAMETER

INPUT SUPPLIES

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input Supply Range

V

2.6

2.1

5.5

2.5

1.5

13

V

IN

Input Undervoltage Threshold

IN Quiescent Supply Current

SUPP Supply Range

V

rising, 100mV hysteresis (typ)

UVLO

IN

I

= V

= 1.5V, V = -0.2V

FBN

mA

V

IN

FB

FBP

7

SUPP

SUPP Quiescent Current

SUPN Supply Range

I

V

= 1.5V

0.8

24

mA

V

FBP

FBN

V

SUPN

SUPN Quiescent Current

MAIN BOOST CONVERTER

Output Voltage Range

FB Regulation Voltage

I

= -0.2V

0.8

mA

V

13

V

MAIN

IN

V

1.225

1.258

FB

FB Undervoltage Shutdown

Threshold

FB falling

75

200

mV

Operating Frequency

LX Switch On-Resistance

LX Current Limit

f

0.75

1.25

0.7

MHz

Ω

OSC

R

I

= 100mA

LX(ON)

LX(MAX)

LX

I

Phase IV = fully on (> 3.0ms)

1.08

1.8

A

POSITIVE CHARGE PUMP

V

Input Supply Range

V

7

13

V

SUPP

Overvoltage Threshold

V

= rising, hysteresis (typ) = 200mV

13.2

1.213

14.0

1.287

SUPP

FBP Regulation Voltage

V

FBP

NEGATIVE CHARGE PUMP

V

Input Supply Range

V

7

24

V

SUPN

FBN Regulation Voltage

REGULATOR

V

213

287

mV

FBN

V

LOGIC

FBL Regulation Voltage

OUTL On-Resistance

REFERENCE

V

I

= 0 to 300mA

1.220

1.275

1.5

V

FBL

REF

OUTL

V

= 3.3V, I

= 100mA

Ω

IN

OUTL

Reference Voltage

V

-2µA < I

< +50µA

1.225

0.9

1.269

1.2

V

REF

Reference Undervoltage

Threshold

V

rising

REF

LOGIC SIGNALS

LCDON, SHDN Input Low

Voltage

Hysteresis = 0.15 x V (typ)

0.9

V

IN

LCDON, SHDN Input High

Voltage

2.1

_______________________________________________________________________________________

5

TFT LCD DC-DC Converter with

Integrated Charge Pumps

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V = 3.0V, SHDN = LCDON = IN, V

= V

= 10V, PGND = GND, C

= 0.22µF, C

= 470pF, T =

INTG A

IN

SUPP

SUPN

REF

-40°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.) (Note 1)

A

PARAMETER

SEQUENCING

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DLP Turn-On Threshold

FBL Fault-Trip Level

V

= rising

1.2

1.3

V

DLP

Falling edge

0.95

1.07

1.08

1.14

FB, FBL, FBP Fault-Trip Level

Note 1: Specifications to -40°C are guaranteed by design, not production tested.

Typical Operating Characteristics

(Circuit of Figure 1, V = 3V, V

= 9V, T = +25°C, unless otherwise noted.)

A

IN

MAIN

STEP-UP EFFICIENCY

vs. LOAD CURRENT

STEP-UP MAXIMUM OUTPUT CURRENT

vs. INPUT VOLTAGE

NORMALIZED V

vs. LOAD CURRENT

MAIN

9.06

9.04

100

90

80

70

60

50

700

600

500

400

300

200

V

= 5.0V

IN

9.02

9.00

8.98

V

= 5.0V

IN

V

= 3.0V

IN

V

IN

= 3.0V

8.96

8.94

0

100

200

300

400

500

600

0

50

100

LOAD CURRENT (mA)

150

200

2

3

4

5

6

LOAD CURRENT (mA)

INPUT VOLTAGE (V)

NORMALIZED OUTL VOLTAGE

vs. OUTL LOAD CURRENT

OUTL DROPOUT VOLTAGE

vs. OUTL LOAD CURRENT

OUTN VOLTAGE

vs. OUTN LOAD CURRENT

2.52

2.51

2.50

2.49

2.48

2.47

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

-10.4

-10.6

-10.8

-11.0

-11.2

-11.4

V

= 9V

SUPN

V

= 5.0V

IN

V

= 10V

SUPN

V

= 3.0V

150

IN

0

50

100

200

250

300

0

50

100

150

200

250

300

0

5

10

15

20

OUTL LOAD CURRENT (mA)

OUTN LOAD CURRENT (mA)

6

_______________________________________________________________________________________

TFT LCD DC-DC Converter with

Integrated Charge Pumps

Typical Operating Characteristics (continued)

(Circuit of Figure 1, V = 3V, V

IN

= 9V, T = +25°C, unless otherwise noted.)

MAIN

A

OUTP VOLTAGE

vs. OUTP LOAD CURRENT

SWITCHING FREQUENCY

vs. INPUT VOLTAGE

REFERENCE VOLTAGE

vs. REFERENCE CURRENT

24.2

24.1

24.0

23.9

23.8

1.20

1.15

1.10

1.05

1.00

0.95

0.90

1.252

1.251

V

= 10V

SUPP

1.250

1.249

1.248

V

= 9V

SUPP

I

= 100mA

5.0

MAIN

0

5

10

15

20

2.5

3.0

3.5

4.0

4.5

5.5

0

10

20

30

40

50

OUTP LOAD CURRENT (mA)

INPUT VOLTAGE (V)

REFERENCE CURRENT (µA)

V

TRANSIENT RESPONSE

V

SWITCHING WAVEFORMS

MAIN

V

3-PULSE TRANSIENT RESPONSE

MAIN

0

A

B

0

A

B

A

B

0

9V

0

C

9V

C

0

40µs/div

A. LOAD FET GATE, 5V/div

400ns/div

10µs/div

C. I , 500mA/div

LX

A. V , 5V/div

LX

C. V

MAIN

, 50mV/div

MAIN

A. LOAD FET GATE, 5V/div

C. I , 500mA/div

LX

B. V

, 200mV/div

MAIN

I

= 20mA TO

160mA

MAIN

B. I , 500mA/div

I

= 160mA

B. V , 200mV/div

MAIN

I

= 20mA TO 1A,

MAIN

2µs PULSE

OUTP SOFT-START

V

MAIN

SOFT-START

V

SOFT-START (NO LOAD)

MAIN

A

B

A

0

B

A

B

OUTN

STARTUP

OUTN

STARTUP

0

V

MAIN

STARTUP

C

400µs/div

1ms/div

A. OUTP, 10V/div

B. I , 500mA/div

I

= 20mA

OUTP

A. SHDN, 5V/div

B. V , 5V/div

C. I , 500mA/div

MAIN

A. SHDN, 5V/div

B. V , 5V/div

C. I , 500mA/div

LX

I

= 160mA

SUPP

MAIN

_______________________________________________________________________________________

7

TFT LCD DC-DC Converter with

Integrated Charge Pumps

Typical Operating Characteristics (continued)

(Circuit of Figure 1, V = 3V, V

= 9V, T = +25°C, unless otherwise noted.)

A

IN

MAIN

OUTN SWITCHING WAVEFORMS

OUTP SWITCHING WAVEFORMS

OUTN SOFT-START

A

B

0

A

B

A

B

0

-11V

C

24V

C

0

10µs/div

4µs/div

1ms/div

A. V , 5V/div

OUTN

I

= 10mA

OUTN

A. V , 5V/div

C2N

C. V

OUTP

, 200mV/div

A. SHDN, 5V/div

B. OUTN, 5V/div

C. I , 200mA/div

SUPN

OUTN

C3P

CIN

OUTP

= 20mA

B. V , 100mV/div

B. V , 5V/div

I

I = 20mA

OUTL TRANSIENT RESPONSE

OUTL SOFT-START

A

B

0

2.5V

A

B

0

C

0

100µs/div

400µs/div

A. V

OUTL

, 50V/div

I

= 10mA TO 300mA

OUTL

A. SHDN, 5V/div

B. OUTL, 1V/div

C. V , 1V/div

OUTL

REF

= 10Ω

B. I , 100mA/div

R

FAULT TIMER

POWER-UP SEQUENCING

POWER-DOWN SEQUENCING

9V

A

B

0

A

24V

B

C

D

0

9V

B

C

D

C

0

-11V

24V

-11V

24V

E

F

E

F

D

E

0

2.5V

0

10ms/div

4ms/div

A. V

B. V

C. V

, 5V/div

D. V , 10V/div

LX

A. SHDN, 5V/div

D. V

E. V

DLP

, 10V/div

A. SHDN, 5V/div

D. V

OUTP

F. V , 1V/div

REF

, 10V/div

OUTN

MAIN

OUTP

OUTN

, 20V/div

, 10V/div

E. V

R

, 2V/div

B. V

OUTL

C. V

MAIN

, 5V/div

, 10V/div

B. V

OUTL

C. V

MAIN

, 5V/div

E. V

, 10V/div

OUTL

= OPEN TO 18Ω

OUTP

, 10V/div

F. V , 2V/div

, 10V/div

OUTN

MAIN

8

_______________________________________________________________________________________

TFT LCD DC-DC Converter with

Integrated Charge Pumps

Pin Description

NAME

FUNCTION

1

SUPP

Positive Charge-Pump Supply Voltage. Bypass to PGND with a 0.1µF capacitor.

2, 12, 20,

23

N.C.

No connection. Not internally connected.

3

4

5

6

C2N

C2P

Negative Terminal of Flying Capacitor C2

Positive Terminal of Flying Capacitor C2

OUTP

INTG

Positive Charge-Pump Output

Step-Up Regulator Integrator Output. Connect a 470pF capacitor from INTG to GND.

Step-Up Converter Feedback Input. Regulates to 1.245V (nominal). Connect a resistor-divider from the

7

8

FB

output (V ) to FB to analog ground (GND). Place the resistor-divider within 5mm of FB.

MAIN

Positive Charge-Pump Feedback Input. Regulates to 1.25V (nominal). Connect a resistor-divider from the

output (OUTP) to FBP to analog ground (GND). Place the resistor-divider within 5mm of FBP.

FBP

Logic Linear Regulator Dual-Mode Feedback Input. Connect FBL to GND to select the 2.5V preset linear

regulator output voltage (OUTL). Connect FBL to the center tap of a resistive voltage-divider between

OUTL and GND to set an adjustable output voltage. In adjustable mode, FBL is regulated at 1.25V nominal.

Place the resistive divider within 5mm of FBL.

9

FBL

Logic Linear Regulator Output. Output of the 2.5V or adjustable linear regulator. Bypass to GND with a

10µF (min) capacitor.

10

OUTL

Supply Input. +2.6V to +5.5V input range. Supply input for the IC and input for the internal logic linear

regulator. Bypass to GND with a 0.1µF capacitor within 5mm of the IC pins.

11

13

14

IN

GND

REF

Analog Ground. Connect to power ground (PGND) underneath the IC.

Internal Reference Output. Bypass REF to GND with a 0.22µF (min) capacitor. REF can supply up to 50µA

to an external load.

Negative Charge-Pump Feedback Input. Connect a resistor-divider from the output (OUTN) to FBN to the

reference output (REF). Place the resistor-divider within 5mm of FBN.

15

FBN

16, 17

18

I.C.

C3P

Internally Connected. Make no connection to this pin.

Positive Terminal of Flying Capacitor C3

19

SUPN

Negative Charge-Pump Supply Voltage. Bypass to PGND with a 0.1µF capacitor.

Power MOSFET n-Channel Drain and Switching Node. Connect the inductor and catch diode to LX and

minimize the trace area for lowest EMI.

21

22

24

25

26

LX

Power Ground. PGND is the source of the main boost/n-channel power MOSFET. Connect PGND to the

output capacitor ground terminals through a short, wide PC board trace.

PGND

DLP

Positive Charge-Pump Startup Delay Input. Connect a capacitor from DLP to GND to set the delay time. A

5µA current source charges C

. DLP is pulled to GND by a 20Ω switch when shut down.

DLP

Active-Low Shutdown Control Input. All outputs are disabled when SHDN is low. When SHDN is high, REF

and OUTL are enabled and the LCD supplies can be enabled if LCDON is high.

SHDN

LCDON

LCD Supply Enable Input. All LCD supply outputs (MAIN, OUTN, and OUTP) are disabled when LCDON is

low. REF and OUTL are unaffected by LCDON.

27

28

C1N

C1P

Negative Terminal of Flying Capacitor C1

Positive Terminal of Flying Capacitor C1

_______________________________________________________________________________________

9

TFT LCD DC-DC Converter with

Integrated Charge Pumps

L1

6.8µH

V

MAIN

IN

+2.6V TO +5.5V

D1

+9V, 140mA

C

IN

C

MAIN1

10µF

R1

174kΩ

0.1µF

10µF

C

INTG

470pF

1

6

21

22

13

7

11

R

C

COMP

1nF

IN

PGND

GND

FB

R2

20kΩ

28kΩ

0.1µF

16

17

I.C.

D2

D3

V

MAIN

C3

0.1µF

19

SUPN

0.1µF

C5

0.1µF

18

C3P

FBN

V

NEG

25

SHDN

-11V, 10mA

MAX8753

C4

0.1µF

V

LOGIC

26

10

9

R3

215kΩ

C

15

NEG

+2.5V, 300mA

LCDON

1µF

OUTL

FBL

DLP

C

LOGIC

R4

19.1kΩ

24

14

5

10µF

REF

C

REF

DLP

V

POS

0.1µF

0.22µF

OUTP

+24V, 10mA

2

R5

46.4kΩ

C

N.C.

POS

1µF

8

12

FBP

4

R6

25.5kΩ

28

3

27

C1

0.1µF

C2

0.1µF

Figure 1. Typical Operating Circuit

Table 1. Critical Component List

Typical Operating Circuit

The MAX8753 typical application circuit (Figure 1) gen-

erates a +2.5V logic supply, a +9V source driver sup-

ply, and +24V and -11V gate-driver supplies for TFT

displays. The input voltage range for the IC is from

+2.6V to +5.5V.

DESIGNATION

DESCRIPTION

10µF, 6.3V X5R ceramic capacitors (0603)

TDK C1608X5R0J106M

C

, C

IN LOGIC

10µF 20%, 16V X5R ceramic capacitor

(1210)

Taiyo Yuden EMK325 BJ106KD

Table 1 lists the recommended components and Table 2

lists the contact information for component suppliers.

C

MAIN

D1

3A, 30V Schottky diode (M-flat)

Toshiba CMS02

200mA, 100V, dual ultra-fast diodes

(SOT23)

Fairchild MMBD4148SE

D2, D3

L1

6.8µH, 1.0A inductor

Sumida CDH38D09HP

10 ______________________________________________________________________________________

TFT LCD DC-DC Converter with

Integrated Charge Pumps

Table 2. Component Suppliers

SUPPLIER

Fairchild

PHONE

FAX

WEBSITE

www.fairchildsemi.com

408-822-2000

847-545-6700

408-573-4150

847-803-6100

949-455-2000

408-822-2102

847-545-6720

408-573-4159

847-390-4405

949-859-3963

Sumida

Taiyo Yuden

TDK

www.sumida.com

www.t-yuden.com

www.component.tdk.com

www.toshiba.com/taec

Toshiba

Detailed Description

The MAX8753 quadruple-output DC-DC converter pro-

vides the regulated voltages required by active-matrix,

TFT LCDs. Figure 1 shows the typical operating circuit.

INTG

LX

IN

It includes a high-power step-up regulator (V

), two

MAIN

), and a low-

low-power charge pumps (V

and V

POS

NEG

STEP-UP

REGULATOR

voltage, 300mA linear regulator (V

). The primary

LOGIC

DLP

boost converter uses an internal n-channel MOSFET to

provide maximum efficiency and to minimize the num-

ber of external components. The output voltage of the

PGND

FB

SHDN

ONLCD

SEQ

main boost converter (V

) can be set from V to

IN

MAIN

13V with external resistors. The positive charge pump

regulates a positive output (V ) without external

POS

OUTL

FBL

REF

switches or diodes. The negative charge pump regu-

lates a negative output (V ) with external diodes. A

LDO

REF

NEG

GND

proprietary regulation algorithm minimizes output rip-

ple, as well as capacitor sizes for both charge pumps.

Also included in the MAX8753 is a precision 1.25V ref-

erence that sources up to 50µA, logic shutdown, soft-

start, power-up sequencing, and fault detection. Figure

2 is the MAX8753 functional diagram.

SUPN

FBP

OUTP

C1N

C1P

C3P

FBN

POSITIVE

CHARGE-

PUMP

NEGATIVE

CHARGE-

PUMP

Main Step-Up Regulator

The main step-up regulator employs a current-mode,

fixed-frequency PWM architecture to maximize loop

bandwidth and provide fast transient response to

pulsed loads and TFT LCD panel source driver applica-

tions. The high switching frequency (1MHz) allows the

use of low-profile inductors and ceramic capacitors to

minimize the thickness of LCD panel designs. The inte-

grated high-efficiency MOSFET and the IC’s built-in,

digital, soft-start function reduces the number of exter-

nal components required while controlling inrush cur-

C2N

C2P

REGULATOR

MAX8753

SUPP

Figure 2. Functional Diagram

rent. The output voltage can be set from V to 13V with

IN

an external resistive voltage-divider.

Figure 3 shows the block diagram of the step-up regu-

lator. A transconductance error amplifier compares the

signal at FB to 1.24V and changes the COMP output.

The voltage at COMP determines the current trip point

each time the internal MOSFET turns on. As the load

varies, the transconductance error amplifier sources or

sinks current to the COMP output accordingly to pro-

duce the inductor peak current necessary to service

the load. To maintain stability at high duty cycles, a

The regulator controls the output voltage and the power

delivered to the output by modulating the duty cycle (D)

of the internal power MOSFET in each switching cycle.

The duty cycle of the MOSFET is approximated by:

V

− V

IN

MAIN

V

D ≈

MAIN

______________________________________________________________________________________ 11

TFT LCD DC-DC Converter with

Integrated Charge Pumps

L1

V

IN

= 2.6V TO 5.5V

IN

D1

V

MAIN

(UP TO 13V)

LX

DC-DC

LOGIC

DRV

R1

C

MAIN1

REF-OK

REF

C

REF

1.1V

CS

CSN

CSP

GND

PGND

OSC

EA

SC

EAN

EAP

R

COMP

FB

SLOPE

COMP

Gm

C

COMP

R2

REF

BUFFER

INTG

MAX8753

C

INTG

Figure 3. Step-Up Regulator Block Diagram

slope compensation signal is summed with the current-

sense and feedback signals.

Positive Charge-Pump Regulator

The positive charge-pump regulator is typically used to

generate the positive supply rail for the TFT LCD gate-

driver ICs (Figure 4). The output voltage is set with an

external resistive voltage-divider from its output to GND

with the midpoint connected to FBP. The positive

charge pump is a voltage tripler that accepts an input

voltage up to +13V and delivers a 20mA output up to

+28V without external switches or diodes.

On the rising edge of the internal clock, the controller

sets a flip-flop, turning on the n-channel MOSFET and

applying the input voltage across the inductor. The cur-

rent through the inductor ramps up linearly, storing

energy in its magnetic field. Once the sum of the cur-

rent-feedback signal and the slope compensation

exceed the COMP voltage, the controller resets the flip-

flop, and turns off the MOSFET. Since the inductor cur-

rent is continuous, a transverse potential develops

across the inductor (L1) that turns on the diode (D1).

The voltage across the inductor then becomes the dif-

ference between the output voltage and the input volt-

age. This discharge condition forces the current

through the inductor to ramp back down, transferring

the energy stored in the magnetic field to the output

capacitor and the load. The MOSFET remains off for the

rest of the clock cycle.

During the first half-cycle (CLK is low), C1N pin is con-

nected to the ground, which allows V

to charge up

SUPP

the first flying capacitor C1 through diode D1. The

amount of charge transferred from V to C1 is

SUPP

determined by the on-resistance of N1, which varies

according to the output of the feedback error amplifier.

During the second half-cycle (CLK is high), C1N is con-

nected to V

through P1, level shifting C1 by V

SUPP

volts. The on-resistance of P1 is also controlled by the

output of the feedback error amplifier. Meanwhile,

CLKB becomes low, pulling C2N to the ground. This

connects C1 in parallel with the second flying capacitor

12 ______________________________________________________________________________________

TFT LCD DC-DC Converter with

Integrated Charge Pumps

V

SUPP

D1

D2

CLK

P1

P2

D3

C1N

C2N

R

ON

R

ON

CONTROL

CTRL

N2

N1

EA

V

POS

OUTP

C1N

C1P

C

C1

C2

R1

C2P

C2N

SUPP OV

THRESHOLD

R2

R5

REF

CHARGE-

PUMP

LOGIC

OSC

FBP

EA

REF

R6

MAX8753

Figure 4. Positive Charge-Pump Regulator Block Diagram

C2. If the voltage across C2 plus a diode drop (V

+

p-channel MOSFET (P3) and a low-side n-channel

MOSFET (N3) to control the power transfer as shown in

Figure 5. The negative charge pump can also be con-

figured as a multiple-stage charge pump. The required

C2

V

) is smaller than the first level-shifted flying

DIODE

capacitor voltage (V + V

), charge flows from C1

SUPP

C1

to C2 until diode D2 turns off. Similarly, when CLKB

becomes high, C2 is also level shifted by V volts.

number of stages (n ) is determined by V

and

SUPN

SUPP

neg

This connects C2 in parallel with the reservoir capacitor

. If the voltage across C plus a diode drop

the desired negative output voltage. Figure 1 gives an

example with a two-stage negative charge pump.

C

POS

(V

POS

+ V

) is smaller than the second level-shift-

POS

DIODE

In Figure 5, during the first half-cycle, the p-channel

MOSFET turns on and flying capacitor C3 charges to

ed flying capacitor voltage (V + V

), charge flows

C2

SUPP

from C2 to C

until diode D3 turns off.

POS

V

minus a diode drop. During the second half-

SUPN

cycle, the p-channel MOSFET turns off, and the n-chan-

nel MOSFET turns on, level shifting C3. This connects

Negative Charge-Pump Regulator

The negative charge-pump regulator is typically used

to generate the negative supply rail for the TFT LCD

gate-driver ICs. The output voltage is set with an exter-

nal resistive voltage-divider from its output to REF with

the midpoint connected to FBN. The number of charge-

pump stages and the setting of the feedback divider

determine the output of the negative charge-pump reg-

ulator. The charge-pump controller includes a high-side

C3 in parallel with the reservoir capacitor C

. If the

NEG

voltage across C3 minus a diode drop is lower than the

voltage across C , charge flows from C3 to C

NEG

until the diode turns off. The amount of charge trans-

ferred to the output is controlled by the variable n-chan-

nel on-resistance.

______________________________________________________________________________________ 13

TFT LCD DC-DC Converter with

Integrated Charge Pumps

V

SUPN

P3

D4

D5

C3

C3P

R

ON

V

NEG

CONTROL

C

NEG

N3

OSC

R3

FBN

CHARGE-

PUMP

LOGIC

EA

250mV

R4

1.25V

REF

MAX8753

C

REF

GND

PGND

Figure 5. Negative Charge-Pump Regulator Block Diagram

The linear regulator is enabled whenever REF is in reg-

Linear Regulator

The MAX8753 contains a linear regulator that uses an

internal pMOS transistor to supply load currents up to

300mA. Connect FBL to GND to set the linear regulator

output to 2.5V. Connect an external resistive voltage-

divider between the regulator output and GND with the

midpoint connected to FBL to adjust the linear-regulator

output. An error amplifier compares the FBL voltage with

the 1.25V internal reference voltage and amplifies the

difference. If the feedback voltage is higher than the ref-

erence voltage, the controller lowers the gate voltage of

the pMOS transistor, which reduces the amount of cur-

rent delivered to the output. If the feedback voltage is

too low, the device increases the pMOS transistor’s gate

voltage, which allows more current to pass to the output

and raises the output voltage. The linear regulator also

includes an output current limit that protects the internal

pass transistor against short circuits.

ulation and SHDN is logic-high.

The linear regulator current-limit circuitry monitors the

current flowing through the internal pass transistor. The

internal current limit is approximately 500mA. The linear

regulator output declines when it is not able to supply

the load current. If the FBL voltage drops below 0.75V,

the current limit folds back to approximately 100mA.

Reference Voltage (REF)

The reference output is nominally 1.25V and can

source up to 50µA. Bypass REF with a 0.22µF ceramic

capacitor connected between REF and GND. The refer-

ence remains disabled in shutdown.

Power-Up Sequence and Shutdown Control

When the MAX8753 is powered up, all outputs are dis-

abled as long as SHDN is low. After SHDN is logic-

high, the reference and the linear regulator power up

first. The main DC-DC step-up converter, the negative

14 ______________________________________________________________________________________

TFT LCD DC-DC Converter with

Integrated Charge Pumps

charge pump, and the positive charge pump remain

Design Procedure

Main Step-Up Regulator

Inductor Selection

The minimum inductance value, peak current rating, and

series resistance are factors to consider when selecting

the inductor. These factors influence the converter’s effi-

ciency, maximum output load capability, transient

response time, and output voltage ripple. Physical size

and cost are also important factors to be considered.

disabled until LCDON is high. When LCDON is logic-

high, the main DC-DC step-up converter powers up with

soft-start enabled. Once the main step-up converter

reaches regulation, the negative charge pump turns on.

When the main step-up converter reaches regulation,

the positive charge-pump regulator delay block is

enabled. An internal current source starts charging the

DLP capacitor. The voltage on DLP linearly rises

because of the constant-charging current. When V

DLP

goes above V

, the switch control block is enabled,

REF

The maximum output current, input voltage, output volt-

age, and switching frequency determine the inductor

value. Very high inductance values minimize the cur-

rent ripple and therefore reduce the peak current,

which decreases core losses in the inductor and I²R

losses in the entire power path. However, large induc-

tor values also require more energy storage and more

turns of wire, which increase physical size and can

increase I²R losses in the inductor. Low inductance val-

ues decrease the physical size but increase the current

ripple and peak current. Finding the best inductor

involves choosing the best compromise between circuit

efficiency, inductor size, and cost.

and the positive charge-pump regulator begins its soft-

start. After the positive charge-pump regulator’s soft-

start is completed, the fault protection of the positive

charge-pump regulator is also enabled.

A logic-low level on LCDON disables the main BOOST

converter, the negative charge pump, and the positive

charge pump. The output capacitance and load current

determine the rate at which each output voltage

decays. The linear regulator and the reference remain

enabled unless SHDN drops below its logic-low thresh-

old. When shut down, the reference turns off and the IC

supply current drops to 0.1µA to maximize battery life

in portable applications. Do not leave SHDN floating. If

unused, connect SHDN to IN.

The equations used here include a constant LIR, which

is the ratio of the inductor peak-to-peak ripple current

to the average DC inductor current at the full-load cur-

rent. The best trade-off between inductor size and cir-

cuit efficiency for step-up regulators generally has an

LIR between 0.3 and 0.5. However, depending on the

AC characteristics of the inductor core material and

ratio of inductor resistance to other power-path resis-

tances, the best LIR can shift up or down. If the induc-

tor resistance is relatively high, more ripple can be

accepted to reduce the number of turns required and

increase the wire diameter. If the inductor resistance is

relatively low, increasing inductance to lower the peak

current can decrease losses throughout the power

path. If extremely thin high-resistance inductors are

used, as is common for LCD panel applications, the

best LIR can increase to between 0.5 and 1.0.

Output Fault Protection

During steady-state operation if the output of the linear

regulator, the step-up regulator, or either of the charge-

pump regulator outputs, does not exceed its respective

fault-detection threshold, the MAX8753 activates an

internal fault timer. If any condition or combination of

conditions indicates a continuous fault for the fault timer

duration (50ms typ), the MAX8753 sets the fault latch,

shutting down all the outputs except the reference. Once

the fault condition is removed, cycle the input voltage or

toggle SHDN to clear the fault latch and reactivate the

device. Each regulator’s fault-detection circuit is dis-

abled during the regulator’s soft-start time.

Thermal-Overload Protection

The thermal-overload protection prevents excessive

power dissipation from overheating the IC. If the junc-

tion temperature exceeds +160°C, a thermal sensor

immediately activates the thermal fault protection,

which shuts down all the outputs, allowing the device to

cool down. Once the device cools down, cycle the

input voltage to clear the thermal fault latch and reacti-

vate the device.

Once a physical inductor is chosen, higher and lower

values of the inductor should be evaluated for efficien-

cy improvements in typical operating regions.

In Figure 1’s typical operating circuit, the LCD’s gate-

on and gate-off voltages are generated from two

charge pumps powered by the step-up regulator. The

additional load on V

must therefore be considered

MAIN

in the inductance calculation. The effective maximum

output current I becomes the sum of the maxi-

MAIN(EFF)

mum load current on the step-up regulator’s output

______________________________________________________________________________________ 15

TFT LCD DC-DC Converter with

Integrated Charge Pumps

plus the contributions from the positive and negative

2







charge pumps:

3.3V

9V

9V − 3.3V

0.19A ×1MHz 0.45

0.80











L =

≈ 6.8µH



















I

=I

+n

×I

+ 3×I

MAIN(EFF) MAIN(MAX)

NEG NEG POS

Using the circuit’s minimum input voltage (2.6V) and

estimating efficiency of 70% at that operating point:

where I

is the maximum output current, n

MAIN(MAX)

NEG

is the number of negative charge-pump stages, I

the negative charge-pump output current, and I

the positive charge-pump output current.

is

NEG

POS

0.19A × 9V

2.6V × 0.7

I

=

≈ 0.94A

IN(DC,MAX)

Calculate the approximate inductor value using the typ-

ical input voltage (V ), the maximum output current

The ripple current and the peak current are:

IN

(I

), the expected efficiency (η

) taken from

MAIN(MAX)

TYP

an appropriate curve in the Typical Operating

Characteristics, and an estimate of LIR based on the

above discussion:

2.6V × 9V − 2.6V

(

)

= 0.27A

I

=

RIPPLE

6.8µH× 9V ×1MHz

2

0.27A















V

− V

× f

η

TYP

LIR





IN

MAIN

IN

I

= 0.94A +

=1.08A

L =

PEAK











2

V

I





MAIN  MAIN(EFF) OSC 

Choose an available inductor value from an appropriate

inductor family. Calculate the maximum DC input cur-

Output Capacitor Selection

The total output-voltage ripple has two components: the

capacitive ripple caused by the charging and discharg-

ing of the output capacitance, and the ohmic ripple due

to the capacitor’s equivalent series resistance (ESR):

rent at the minimum input voltage V

using con-

IN(MIN)

servation of energy and the expected efficiency at that

operating point (η ) taken from an appropriate curve

MIN

in the Typical Operating Characteristics:

V

= V

+ V

RIPPLE

RIPPLE(C) RIPPLE(ESR)

I

× V

MAIN(EFF)

MAIN

I

=

IN(DC,MAX)





I

C

V

− V

V

× η

MIN

MAIN

MAIN IN

IN(MIN)

V

≈

and

RIPPLE(C)





f





OUT

MAIN OSC

Calculate the ripple current at that operating point and

the peak current required for the inductor:

V

≈I

R

RIPPLE(ESR) PEAK ESR(COUT)

V

× V

− V

(

)

IN(MIN)

MAIN IN(MIN)

where I is the peak inductor current (see the

PEAK

I

=

RIPPLE

L × V

× f

Inductor Selection section). For ceramic capacitors,

MAIN OSC

the output voltage ripple is typically dominated by

I

V

. The voltage rating and temperature charac-

RIPPLE(C)

RIPPLE

I

=I

+

PEAK IN(DC,MAX)

teristics of the output capacitor must also be considered.

2

Input Capacitor Selection

The input capacitor (C ) (see Figure 1) reduces the

IN

The inductor’s saturation current rating and the

MAX8753’s LX current limit (I ) should exceed

current peaks drawn from the input supply and reduces

noise injection into the IC. A 10µF ceramic capacitor is

used in the typical operating circuit (Figure 1) because

of the high source impedance seen in typical lab

setups. Actual applications usually have much lower

source impedance since the step-up regulator often

runs directly from the output of another regulated sup-

LX(MAX)

I

and the inductor’s DC current rating should

PEAK

exceed I

. For good efficiency, choose an

IN(DC,MAX)

inductor with less than 0.1Ω series resistance.

Considering the typical operating circuit, the maximum

load current (I

) is 140mA with a 9V output

MAIN(MAX)

and a typical input voltage of 3.3V:

ply. Typically, C can be reduced below the values

IN

used in the typical operating circuit. Ensure a low noise

I

=140mA + 2 ×10mA + 3 ×10mA =190mA

MAIN(EFF)

supply at IN by using adequate C .

IN

Choosing an LIR of 0.45 and estimating efficiency of

80% at this operating point:

16 ______________________________________________________________________________________

TFT LCD DC-DC Converter with

Integrated Charge Pumps

Rectifier Diode

The MAX8753’s high switching frequency demands a

high-speed rectifier. Schottky diodes are recommend-

ed for most applications because of their fast recovery

time and low forward voltage. In general, a 2A Schottky

diode complements the internal MOSFET well.

where V

= 1.25V, and V

= 250mV is the regula-

FBN

REF

tion point of the negative charge-pump regulator.

Flying Capacitor

Increasing the flying capacitor (C ) value lowers the

X

effective source impedance and increases the output-

current capability of the charge pump. Increasing the

capacitance indefinitely has a negligible effect on out-

put-current capability because the internal switch resis-

tance and the diode impedance place a lower limit on

the source impedance. A 0.1µF ceramic capacitor

works well in most low-current applications. The flying

capacitor’s voltage rating must exceed the following:

Output-Voltage Selection

The output voltage of the main step-up regulator can be

adjusted by connecting a resistive voltage-divider from

the output (V

) to GND with the center tap connected

MAIN

to FB (see Figure 1). Select R2 in the 10kΩ to 50kΩ

range. Calculate R1 with the following equation:





V

> V

SUPP

> 2V

SUPP

MAIN

C1

R1=R2×

−1









V

FB

C2

V

> V

SUPN

C3

where V , the step-up regulator’s feedback set point,

FB

V

> 2V

, if used

is 1.245V. Place R1 and R2 close to the IC.

C4

SUPN

Loop Compensation

Charge-Pump Input Capacitor

For stability, add a pole-zero pair from FB to GND in the

Use an input capacitor on SUPP and SUPN with a value

equal to or greater than the flying capacitors on that

charge pump. Place the capacitors as close to SUPP

and SUPN as possible. Connect the capacitors directly

to PGND.

form of a series resistor (R

) and capacitor

COMP

(C

). R

should be approximately half the

COMP

value of the R2 feedback resistor. To further optimize

transient response, vary R in 20% steps and

COMP

C

in 50% steps while observing transient

COMP

response waveforms.

Charge-Pump Output Capacitor

Increasing the output capacitance or decreasing the

ESR reduces the output ripple voltage and the peak-to-

peak transient voltage. With ceramic capacitors, the

output-voltage ripple is dominated by the capacitance

value. Use the following equation to approximate the

required capacitor value:

Charge-Pump Regulators

Output Voltage Selection

Adjust the positive charge-pump regulator output volt-

age by connecting a resistive voltage-divider from the

regulator output V

to GND with the center tap con-

POS

nected to FBP (Figure 1). Select the lower resistor of

the divider R6 in the 10kΩ to 50kΩ range. Calculate

upper resistor R5 with the following equation:

I

LOAD_CP

C

≥

OUT_CP

2f

V

OSC RIPPLE_CP





V

POS

where C

pump, I

is the output capacitor of the charge

is the load current of the charge

RIPPLE_CP

OUT_CP

LOAD_CP

pump, and V

R5 =R6×

−1





V





FBP

is the desired peak-to-peak

value of the output ripple.

where V

= 1.25V (typ) is the regulation point of the

FBP

positive charge-pump regulator.

Charge-Pump Rectifier Diode

Adjust the negative charge-pump regulator output volt-

age by connecting a resistive voltage-divider from the

negative charge-pump output V

center tap connected to FBN (Figure 1). Select R4 in

the 20kΩ to 100kΩ range. Calculate R3 with the follow-

ing equation:

Use low-cost silicon switching diodes for D2 and D3

with a current rating equal to or greater than two times

the average charge-pump input current. If it helps

avoid an extra stage, some or all of the diodes can be

replaced with Schottky diodes with an equivalent cur-

rent rating.

to REF with the

NEG

V

− V

NEG

FBN

R3 =R4×

V

− V

REF

FBN

______________________________________________________________________________________ 17

TFT LCD DC-DC Converter with

Integrated Charge Pumps

PC Board Layout and Grounding

Applications Information

Careful PC board layout is important for proper opera-

tion. Use the following guidelines for good PC board

layout:

Power Dissipation

An IC’s maximum power dissipation depends on the

thermal resistance from the die to the ambient environ-

ment and the ambient temperature. The thermal resis-

tance depends on the IC package, PC board copper

area, other thermal mass, and airflow.

1) Minimize the area of the step-up regulator’s high-

current loops by placing the inductor (L1), output

diode (D1), and output capacitor (C

) near the

MAIN

input capacitor (C ) and near the LX and PGND

IN

The MAX8753, with its exposed backside paddle sol-

dered to 1in²of PC board copper, can dissipate about

1.7W into +70°C still air. More PC board copper, cooler

ambient air, and more airflow increase the possible dissi-

pation while less copper or warmer air decreases the

IC’s dissipation capability. The major components of

power dissipation are the power dissipated in the step-

up regulator, the linear regulator, and the charge pumps.

pins. The high-current input loop goes from the posi-

tive terminal of C to L , to the IC’s LX pin, out of

IN

1

PGND, and to C ’s negative terminal. The high-cur-

IN

rent output loop is from the positive terminal of C

IN

to L1, to the output diode (D1), to the positive termi-

nal of C , reconnecting between the output

MAIN

capacitor and input capacitor ground terminals.

Connect these loop components with short, wide

connections. Avoid using vias in the high-current

paths. If vias are unavoidable, use many vias in par-

allel to reduce resistance and inductance.

Step-Up Regulator

The largest portions of power dissipation in the step-up

regulator are the internal MOSFET, inductor, and the

output diode. If the step-up regulator has 90% efficien-

cy, approximately 3% to 5% of the power is lost in the

internal MOSFET, approximately 3% to 4% in the induc-

tor, and approximately 1% in the output diode. The

remaining 1% to 3% is distributed among the input and

output capacitors and the PC board traces. If the input

power is approximately 5W, the power lost in the inter-

nal MOSFET is approximately 150mW to 250mW.

2) Create a power-ground island (PGND) consisting of

the input and output capacitor grounds, PGND pin,

the charge-pump input capacitors, output capaci-

tors, and diodes. Connect these together with short,

wide traces or a small ground plane. Maximizing the

width of the power-ground traces improves efficien-

cy and reduces output-voltage ripple and noise

spikes. Create an analog-ground plane (AGND)

consisting of the GND pin, all the feedback-divider

ground connections, the INTG and DEL capacitor

ground connections, and the device’s exposed

backside pad. Connect the AGND and PGND

islands by connecting the PGND pin directly to the

exposed backside pad. Make no other connections

between these separate ground planes.

Linear Regulator

The power dissipation in the linear regulator is:

P

= (V − V

)×I

D(LOGIC)

IN

LOGIC LOGIC

Positive Charge-Pump Regulator

The power dissipation in the positive charge-pump reg-

ulator is:

3) Place the feedback voltage-divider resistors as close

to the feedback pin as possible. The divider’s center

trace should be kept short. Placing the resistors far

away causes the FB traces to become antennas that

can pick up switching noise. Care should be taken to

avoid running any feedback trace near LX or the

switching nodes in the charge pumps.

P

= (3 × V

− V

)×I

D(POS)

MAIN

POS POS

Negative Charge-Pump Regulator

The power dissipation in the negative charge-pump

regulator is:

4) Place the IN and OUTL bypass capacitors as close

to the device as possible. The ground connections

of the IN and OUTL bypass capacitors should be

connected directly to the PGND plane near the

PGND pin with a wide trace.

P

= (n

xV

+ V

)×I

D(NEG)

NEG

SUPN

NEG NEG

18 ______________________________________________________________________________________

TFT LCD DC-DC Converter with

Integrated Charge Pumps

5) Minimize the length and maximize the width of the

Chip Information

traces between the output capacitors and the load

for best transient response.

TRANSISTOR COUNT: 6922

PROCESS: BiCMOS

6) Minimize the size of the LX node while keeping it

wide and short. Keep the LX node away from the

feedback node and analog ground. Use DC traces

as shield if necessary.

Refer to the MAX8753 evaluation kit for an example of

proper board layout.

______________________________________________________________________________________ 19

TFT LCD DC-DC Converter with

Integrated Charge Pumps

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)

D2

D

b

0.10 M

C A B

C

L

D2/2

D/2

k

L

MARKING

AAAAA

E/2

E2/2

C

(NE-1) X

e

L

E2

E

PIN # 1 I.D.

0.35x45¡

DETAIL A

e/2

PIN # 1

I.D.

e

(ND-1) X

e

DETAIL B

e

L

C

L

C

L

L1

L

e

0.10

C

A

0.08

C

A3

A1

PACKAGE OUTLINE,

16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm

1

-DRAWING NOT TO SCALE-

I

21-0140

2

COMMON DIMENSIONS

20L 5x5 28L 5x5

EXPOSED PAD VARIATIONS

D2 E2

MIN. NOM. MAX. MIN. NOM. MAX.

3.00 3.10 3.20 3.00 3.10 3.20

PKG.

SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.

16L 5x5

32L 5x5

40L 5x5

L

DOWN

BONDS

ALLOWED

YES

NO

YES

exceptions

PKG.

CODES

–0.15

A

0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80

0.02 0.05 0.02 0.05 0.02 0.05 0.02 0.05 0.02 0.05

0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF.

T1655-2

T1655-3

**

A1

0

A3

b

T1655N-1 3.00 3.10 3.20 3.00 3.10 3.20

0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25

4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10

T2055-3

T2055-4

T2055-5

T2855-3

3.00 3.10 3.20 3.00 3.10 3.20

D

E

NO

**

YES

3.15 3.25 3.35 3.15 3.25 3.35 0.40

3.15 3.25 3.35 3.15 3.25 3.35

e

0.80 BSC.

0.25

0.65 BSC.

0.25

0.50 BSC.

0.25

0.50 BSC.

0.25

0.40 BSC.

YES

NO

YES

**

k

-

0.25 0.35 0.45

T2855-4

T2855-5

2.60 2.70 2.80 2.60 2.70 2.80

3.15 3.25 3.35 3.15 3.25 3.35

2.60 2.70 2.80 2.60 2.70 2.80

L

0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60

L1

-

0.30 0.40 0.50

T2855-6

T2855-7

**

N

ND

16

4

20

5

28

7

32

8

40

10

5

7

NE

T2855-8

3.15 3.25 3.35 3.15 3.25 3.35 0.40

JEDEC

NOTES:

WHHB

WHHC

WHHD-1

WHHD-2

-----

T2855N-1 3.15 3.25 3.35 3.15 3.25 3.35

NO

YES

NO

YES

NO

**

T3255-3

T3255-4

T3255-5

3.00 3.10 3.20 3.00 3.10 3.20

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

3. N IS THE TOTAL NUMBER OF TERMINALS.

T3255N-1 3.00 3.10 3.20 3.00 3.10 3.20

T4055-1 3.20 3.30 3.40 3.20 3.30 3.40

YES

**^{SEE COMMON DIMENSIONS TABLE}

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL

CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE

OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1

IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN

0.25 mm AND 0.30 mm FROM TERMINAL TIP.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR

T2855-3 AND T2855-6.

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.

12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.

13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", –0.05.

PACKAGE OUTLINE,

16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm

2

-DRAWING NOT TO SCALE-

21-0140

I

2

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Printed USA

is a registered trademark of Maxim Integrated Products, Inc.

Boblet


型号：	MAX8753ETI
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	TFT LCD DC-DC Converter with Integrated Charge Pumps TFT LCD DC -DC转换器，内置电荷泵转换器稳压器开关式稳压器或控制器电源电路开关式控制器输出元件信息通信管理泵 CD
文件：	总20页 (文件大小：596K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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