MAX9172ESA+T [MAXIM]
Line Receiver, 2 Func, 2 Rcvr, CMOS, PDSO8, MS-012AA, SOIC-8;
| 型号： | MAX9172ESA+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Line Receiver, 2 Func, 2 Rcvr, CMOS, PDSO8, MS-012AA, SOIC-8 光电二极管 接口集成电路 |
| 文件： | 总11页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2578; Rev 0; 10/02
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
General Description
Features
The MAX9171/MAX9172 single/dual low-voltage differential
signaling (LVDS) receivers are designed for high-speed
applications requiring minimum power consumption,
space, and noise. Both devices support switching rates
exceeding 500Mbps while operating from a single 3.3V
supply.
ꢀ Input Accepts LVDS and LVPECL
ꢀ In-Path Fail-Safe Circuit
ꢀ Space-Saving 8-Pin QFN and SOT23 Packages
ꢀ Fail-Safe Circuitry Sets Output High for Open,
Undriven Shorted, or Undriven Terminated Output
The MAX9171 is a single LVDS receiver and the
MAX9172 is a dual LVDS receiver. Both devices con-
form to the ANSI TIA/EIA-644 LVDS standard and con-
vert LVDS to LVTTL/LVCMOS-compatible outputs. A
fail-safe feature sets the outputs high when the inputs
are undriven and open, terminated, or shorted. The
MAX9171/MAX9172 are available in 8-pin SO packages
and space-saving thin QFN and SOT23 packages.
ꢀ Flow-Through Pinout Simplifies PC Board Layout
ꢀ Guaranteed 500Mbps Data Rate
ꢀ Second Source to DS90LV018A and DS90LV028A
(SO Packages Only)
ꢀ Conforms to ANSI TIA/EIA-644 Standard
ꢀ 3.3V Supply Voltage
For lower skew devices, refer to the MAX9111/ MAX9113
data sheet.
ꢀ -40°C to +85°C Operating Temperature Range
ꢀ Low Power Dissipation
Applications
Multipoint Backplane Interconnect
Ordering Information
Laser Printers
PIN-
PACKAGE
TOP
MARK
Digital Copiers
PART
TEMP RANGE
Cellular Phone Base Stations
LCD Displays
MAX9171EKA-T
MAX9171ESA
MAX9171ETA*
MAX9172EKA-T
MAX9172ESA
MAX9172ETA*
-40°C to +85°C 8 SOT23-8
-40°C to +85°C 8 SO
AALX
—
Network Switches/Routers
Clock Distribution
-40°C to +85°C 8 Thin QFN
-40°C to +85°C 8 SOT23-8
-40°C to +85°C 8 SO
—
AALY
—
-40°C to +85°C 8 Thin QFN
—
*Future product—contact factory for availability.
Pin Configurations
MAX9171
MAX9171
MAX9172
MAX9172
V
V
IN-
IN+
1
2
3
4
CC
1
2
3
4
8
7
6
5
1
2
3
4
1
2
3
4
V
IN1-
IN1+
IN2+
IN2-
8
7
6
5
IN-
IN1-
IN1+
IN2+
IN2-
8
7
6
5
V
8
7
6
5
CC
CC
CC
OUT
N.C.
GND
GND
OUT
N.C.
IN+
GND
OUT1
OUT2
OUT1
OUT2
GND
N.C.
N.C.
N.C.
N.C.
SOT23
SO/QFN*
SO/QFN*
SOT23
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
ABSOLUTE MAXIMUM RATINGS
CC
IN_+, IN_- to GND .................................................-0.3V to +4.0V
OUT_ to GND ............................................-0.3V to (V + 0.3V)
V
to GND...........................................................-0.3V to +4.0V
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
ESD Protection
CC
Continuous Power Dissipation (T = +70°C)
A
8-Pin SOT23 (derate 8.9mW/°C above +70°C) ...........714mW
8-Pin SO (derate 5.9mW/°C above +70°C) .................471mW
8-Pin QFN (derate 24.4mW/°C above +70°C) ..........1951mW
Human Body Model (IN_+, IN_-) ................................... 13kV
Lead Temperature (soldering, 10s) ................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 3.0V to 3.6V, differential input voltage |V | = 0.1V to 1.2V, receiver input voltage = 0 to V , common-mode voltage V
=
CC
ID
CC
CM
|V /2| to (V
ID
- |V /2|), T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= 3.3V, |V | = 0.2V, V
= 1.2V,
CC
ID
A
CC
ID
CM
T
A
= +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVDS INPUTS (IN_+, IN_-)
Differential Input High Threshold
Differential Input Low Threshold
Input Current (Noninverting Input)
V
Figure 1
Figure 1
Figure 1
-40
-40
-2.1
0
mV
mV
µA
TH
V
-100
+0.5
TL
I
-5.0
+0.5
+10.0
+0.5
IN+
Power-Off Input Current
(Noninverting Input)
V
= 0 to 3.6V, V = 0 to 3.6V, V
= 0
= 0
IN+
IN-
CC
I
-0.5
-0.5
-0.5
0
+4.4
0
µA
µA
µA
IN+OFF
or open (Figure 1)
Input Current (Inverting Input)
I
IN-
Figure 1
Power-Off Input Current
(Inverting Input)
V
= 0 to 3.6V, V = 0 to 3.6V, V
IN+ IN-
CC
I
IN-OFF
or open (Figure 1)
LVCMOS/LVTTL OUTPUTS (OUT_)
Open, undriven short, or
undriven parallel termination
2.7
2.7
3.2
Output High Voltage
V
I
I
= -4.0mA
V
OH
OH
OL
V
= 0V
3.2
0.1
ID
Output Low Voltage
Output Short-Circuit Current
POWER SUPPLY
V
= 4.0mA, V = -100mV
0.4
V
OL
ID
I
V
= 0 (Note 3)
-45
-77
-120
mA
OS
OUT_
MAX9171
MAX9172
3.6
7.0
6
9
Supply Current
I
Inputs open
mA
CC
2
_______________________________________________________________________________________
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
SWITCHING CHARACTERISTICS
(V
= 3.0V to 3.6V, C = 15pF, |V | = 0.2V, V
= 1.2V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
=
CC
L
ID
CM
A
3.3V, T = +25°C.) (Notes 4, 5, 6)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Propagation Delay
High to Low
t
t
t
t
Figures 2, 3
1.0
1.65
2.5
ns
PHLD
PLHD
SKD1
SKD2
Differential Propagation Delay
Low to High
Figures 2, 3
1.0
1.62
30
2.5
400
500
ns
ps
ps
ns
Differential Pulse Skew
Figures 2, 3 (Note 7)
Figures 2, 3 (Note 8)
|t
- t
|
PHLD PLHD
Differential Channel-to-Channel
Skew (MAX9172)
40
t
t
Figures 2, 3 (Note 9)
Figures 2, 3 (Note 10)
Figures 2, 3
1
SKD3
SKD4
Differential Part-to-Part Skew
1.5
0.8
0.8
Rise Time
Fall Time
t
t
0.55
0.51
ns
ps
TLH
THL
Figures 2, 3
All channels switching, V
= 0.4V,
OL(MAX)
Maximum Operating Frequency
f
250
300
MHz
MAX
V
= 2.7V, 40% < duty cycle < 60%
OH(MIN)
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to GND
except V , V , and V
.
ID
TH TL
Note 2: All devices are 100% production tested at T = +25°C and are guaranteed by design for T = -40°C to +85°C, as specified.
A
A
Note 3: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
Note 4: AC parameters are guaranteed by design and not production tested.
Note 5: C includes scope probe and test jig capacitance.
L
Note 6: Pulse generator output conditions: t = t < 1ns (0% to 100%), frequency = 250MHz, 50% duty cycle, V
= 1.3V, V = 1.1V.
OL
R
F
OH
Note 7: t
Note 8: t
is the magnitude of the difference of differential propagation delays in a channel. t
= |t
- t
|.
SKD1
SKD2
SKD1
PHLD PLHD
is the magnitude of the difference of the t
or t
of one channel and the t
or t
of the other channel
PLHD
PHLD
PLHD
PHLD
on the same part.
Note 9: t is the magnitude of the difference of any differential propagation delays between parts at the same V
and within
CC
SKD3
5°C of each other.
Note 10: t is the magnitude of the difference of any differential propagation delays between parts operating over the rated
SKD4
supply and temperature ranges.
_______________________________________________________________________________________
3
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
Typical Operating Characteristics
(V
= 3.3V, V
= 1.2V, |V | = 0.2V, f = 200MHz, C = 15pF, T = +25°C, unless otherwise specified.)
CM ID IN L A
CC
OUTPUT HIGH VOLTAGE
vs. SUPPLY VOLTAGE
OUTPUT LOW VOLTAGE
vs. SUPPLY VOLTAGE
OUTPUT SHORT-CIRCUIT CURRENT
vs. SUPPLY VOLTAGE
3.6
3.5
100
95
90
85
80
-65
-70
-75
-80
-85
I
= -4mA
I
= +4mA
V = +200mV, OUTPUT
ID
SHORTED TO GROUND
OH
OL
3.4
3.3
3.2
3.1
3.0
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
DIFFERENTIAL THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
MAX9172 SUPPLY CURRENT
vs. FREQUENCY
MAX9172 SUPPLY CURRENT
vs. TEMPERATURE
-35
-40
-45
-50
-55
40
30
20
10
0
9
8
7
6
f = 1MHz
BOTH CHANNELS SWITCHING
HIGH-LOW
LOW-HIGH
BOTH CHANNELS
SWITCHING
ONE CHANNEL
SWITCHING
3.0
3.1
3.2
3.3
3.4
3.5
3.6
0.1
1
10
100
1000
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
FREQUENCY (MHz)
TEMPERATURE (°C)
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
2.0
1.9
1.8
1.7
1.6
1.5
2.5
2.0
1.5
1.0
t
PHLD
t
PHLD
t
PLHD
t
PLHD
-40
-15
10
35
60
85
3.0
3.1
3.2
3.3
3.4
3.5
3.6
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
4
_______________________________________________________________________________________
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
Typical Operating Characteristics (continued)
(V
= 3.3V, V
= 1.2V, |V | = 0.2V, f = 200MHz, C = 15pF, T = +25°C, unless otherwise specified.)
CC
CM
ID
IN
L
A
DIFFERENTIAL PULSE SKEW
vs. SUPPLY VOLTAGE
DIFFERENTIAL PULSE SKEW
vs. TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY
vs. DIFFERENTIAL INPUT VOLTAGE
120
200
160
120
80
3.0
2.5
2.0
1.5
1.0
f
IN
= 20MHz
90
60
30
0
t
PHLD
t
PLHD
40
0
3.0
3.1
3.2
3.3
3.4
3.5
3.6
-40
-15
10
35
60
85
100
600
1100
1600
2100
2600
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
DIFFERENTIAL INPUT VOLTAGE (mV)
DIFFERENTIAL PROPAGATION DELAY
vs. LOAD
DIFFERENTIAL PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
TRANSITION TIME vs. TEMPERATURE
2.5
2.2
1.9
1.6
1.3
1.0
2.4
2.2
2.0
1.8
1.6
1.4
700
600
500
400
300
f
= 20MHz
f
IN
= 20MHz
IN
t
TLH
t
PHLD
t
PHLD
t
PLHD
t
PLHD
t
THL
0.1
0.6
1.1
1.6
2.1
2.6
3.1
10
20
30
LOAD (pF)
40
50
-40
-15
10
35
60
85
COMMON-MODE VOLTAGE (V)
TEMPERATURE (°C)
DIFFERENTIAL PULSE SKEW
vs. INPUT TRANSITION TIME
TRANSITION TIME vs. LOAD
2100
1700
1300
900
300
250
200
150
100
50
t
TLH
t
THL
500
100
0
10
20
30
LOAD (pF)
40
50
1.0
1.5
2.0
2.5
3.0
INPUT TRANSITION TIME (ns)
_______________________________________________________________________________________
5
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
MAX9171 Pin Description
PIN
NAME
FUNCTION
SOT23
SO/QFN
Positive Power-Supply Input. Bypass with a 0.1µF and a 0.001µF capacitor to GND with the
smallest capacitor closest to the pin.
1
8
V
CC
2
5
GND
OUT
N.C.
IN+
IN-
Ground
3
4, 5, 6
7
7
Receiver Output
3, 4, 6
No Connection. Not internally connected.
Noninverting Differential Receiver Input
Inverting Differential Receiver Input
Exposed Paddle. Solder to PC board ground.
2
1
8
—
(QFN only)
EP
MAX9172 Pin Description
PIN
NAME
FUNCTION
SOT23
SO/QFN
Positive Power-Supply Input. Bypass with a 0.1µF and a 0.001µF capacitor to GND with the
smallest capacitor closest to the pin.
1
8
V
CC
2
3
5
GND
OUT1
OUT2
IN2-
Ground
7
Receiver Output 1
4
6
Receiver Output 2
5
4
Inverting Differential Receiver Input 2
Noninverting Differential Receiver Input 2
Noninverting Differential Receiver Input 1
Inverting Differential Receiver Input 1
Exposed Paddle. Solder to PC board ground.
6
3
IN2+
IN1+
IN1-
7
2
1
8
—
(QFN only)
EP
signals to LVCMOS/LVTTL signals at rates in excess of
500Mbps. These devices are capable of detecting dif-
ferential signals as low as 100mV and as high as 1.2V
Detailed Description
LVDS Inputs
The MAX9171/MAX9172 feature LVDS inputs for inter-
facing high-speed digital circuitry. The LVDS interface
standard is a signaling method intended for point-to-
point communication over controlled-impedance
media, as defined by the ANSI TIA/EIA-644 standards.
The technology uses low-voltage signals to achieve fast
transition times and minimize power dissipation and
noise immunity. The MAX9171/MAX9172 convert LVDS
within a 0 to V
input voltage range. Table 1 is the
CC
input-output function table.
Fail-Safe
The MAX9171/MAX9172 fail-safe drives the receiver
output high when the differential input is:
• Open
• Undriven and shorted
• Undriven and terminated
Table 1. Input-Output Function Table
INPUTS
(IN_+) - (IN_-)
≥ 0mV
OUTPUT
OUT_
High
Without fail-safe, differential noise at the input may
switch the receiver and appear as data to the receiving
system. An open input occurs when a cable and termi-
nation are disconnected. An undriven, terminated input
occurs when a cable is disconnected with the termina-
tion still connected across the receiver inputs or when
the driver of a receiver is in high impedance. An undriv-
en, shorted input can occur due to a shorted cable.
≤ -100mV
Low
Open
High
Undriven short
Undriven parallel termination
High
High
6
_______________________________________________________________________________________
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
In-Path vs. Parallel Fail-Safe
The MAX9171/MAX9172 have in-path fail-safe that is
compatible with in-path fail-safe receivers, such as the
V
CC
DS90LV018A and DS90LV028A. Refer to the MAX9111/
MAX9113 data sheet for pin-compatible receivers with
parallel fail-safe and lower jitter. Refer to the MAX9130
data sheet for a single LVDS receiver with parallel fail-
safe in an SC70 package.
2.5µA
IN_+
IN_-
OUT_
The MAX9171/MAX9172 with in-path fail-safe are
designed with a +40mV input offset voltage, a 2.5µA
40mV
current source between V
and the noninverting
CC
input, and a 5µA current sink between the inverting
input and ground (Figure 1). If the differential input is
5µA
open, the 2.5µA current source pulls the input to V
-
CC
0.7V and the 5µA source sink pulls the inverting input to
ground, which drives the receiver output high. If the dif-
ferential input is shorted or terminated with a typical
value termination resistor, the +40mV offset drives the
receiver output high. If the input is terminated and float-
ing, the receiver output is driven high by the +40mV off-
set, and the 2:1 current sink to current source ratio
(5µA:2.5µA) pulls the inputs to ground. This can be an
advantage when switching between drivers on a multi-
point bus because the change in common-mode volt-
age from ground to the typical driver offset voltage of
Figure 1. Input with In-Path Fail-Safe Network Equivalent Circuit
IN_+
OUT_
PULSE
GENERATOR
IN_-
15pF
50Ω
50Ω
1.2V is not as much as the change from V
to 1.2V
CC
(parallel fail-safe pulls the bus to V ). Figure 2 shows
CC
the propagation delay and transition test time circuit
and Figure 3 shows the propagation delay and transi-
tion test time waveforms.
Figure 2. Propagation Delay and Transition Test Time Circuit
1.3V
IN_-
1.2V (0V DIFFERENTIAL)
IN_+
V = 0.2V
ID
1.1V
t
t
PHLD
PLHD
V
OH
80%
80%
1.5V
1.5V
20%
20%
OUT_
V
OL
t
t
THL
TLH
Figure 3. Propagation Delay and Transition Time Waveforms
_______________________________________________________________________________________
7
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
ESD Protection
Termination
ESD protection structures are incorporated on all pins
to protect against electrostatic discharges encountered
during handling and assembly. The receiver inputs of
the MAX9171/MAX9172 have extra protection against
static electricity. These pins are protected to 13kV
without damage. The structures withstand ESD during
normal operation and when powered down.
The MAX9171/MAX9172 require an external termination
resistor. The termination resistor should match the differ-
ential impedance of the transmission line. Termination
resistance values may range between 90Ω to 132Ω,
depending on the characteristic impedance of the
transmission medium.
When using the MAX9171/MAX9172, minimize the dis-
tance between the input termination resistors and the
MAX9171/MAX9172 receiver inputs. Use a single 1%
surface-mount resistor.
The receiver inputs of these devices are characterized
for protection to the limit of 13kV using the Human
Body Model.
Human Body Model
Figure 4a shows the Human Body Model, and Figure
4b shows the current waveform it generates when dis-
charged into a low-impedance load. This model con-
sists of a 100pF capacitor charged to the ESD test
voltage, which is then discharged into the test device
through a 1.5kΩ resistor.
Board Layout
For LVDS applications, a four-layer PC board that pro-
vides separate power, ground, LVDS signals, and out-
put signals is recommended. Separate the input LVDS
signals from the output signals to prevent crosstalk.
Solder the exposed pad on the QFN package to a pad
connected to the PC board ground plane by a matrix of
vias. Connecting the exposed pad is not a substitute
for connecting the ground pin. Always connect pin 5 on
the QFN package to ground.
Applications Information
Supply Bypassing
with high-frequency surface-mount ceram-
Bypass V
CC
ic 0.1µF and 0.001µF capacitors in parallel, as close to
the device as possible, with the 0.001µF capacitor clos-
est to the device. For additional supply bypassing,
place a 10µF tantalum or ceramic capacitor at the point
where power enters the circuit board.
R
C
1MΩ
R 1500Ω
D
DISCHARGE
RESISTANCE
CHARGE-CURRENT
LIMIT RESISTOR
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
STORAGE
CAPACITOR
s
100pF
SOURCE
Differential Traces
Input trace characteristics affect the performance of the
MAX9171/MAX9172. Use controlled-impedance PC board
traces to match the cable characteristic impedance.
Figure 4a. Human Body ESD Test Modules
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of traces.
I
100%
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
P
r
AMPERES
Each channel’s differential signals should be routed
close to each other to cancel their external magnetic
field. Maintain a constant distance between the differ-
ential traces to avoid discontinuities in differential
impedance. Avoid 90° turns and minimize the number
of vias to further prevent impedance discontinuities.
36.8%
10%
0
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Cables and Connectors
Transmission media typically have a controlled differen-
tial impedance of about 100Ω. Use cables and connec-
tors that have matched differential impedance to
minimize impedance discontinuities. Balanced cables
tend to pick up noise as common mode, which is
rejected by the LVDS receiver.
Figure 4b. Human Body Current Waveform
Chip Information
TRANSISTOR COUNT: 624
PROCESS: CMOS
8
_______________________________________________________________________________________
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
_______________________________________________________________________________________
9
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
10 ______________________________________________________________________________________
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 6, 8 & 10L,
QFN THIN (DUAL), EXPOSED PAD, 3x3x0.80 mm
21-0137
C
COMMON DIMENSIONS
SYMBOL
MIN.
0.70
2.90
2.90
0.00
0.20
MAX.
A
D
E
A1
L
0.80
3.10
3.10
0.05
0.40
k
0.25 MIN
0
A20.2 REF.
PACKAGE VARIATIONS
PKG. CODE
T633-1
N
6
D2
E2
e
JEDEC SPEC
MO229 / WEEA
MO229 / WEEC
b
[(N/2)-1] x e
1.90 REF
1.95 REF
1.50–0.10 2.30–0.10 0.95 BSC
1.50–0.10 2.30–0.10 0.65 BSC
0.40–0.05
0.30–0.05
T833-1
8
T1033-1
10
1.50–0.10 2.30–0.10 0.50 BSC MO229 / WEED-3 0.25–0.05 2.00 REF
PACKAGE OUTLINE, 6, 8 & 10L,
QFN THIN (DUAL), EXPOSED PAD, 3x3x0.80 mm
21-0137
C
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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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Printed USA
is a registered trademark of Maxim Integrated Products.
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