MAX9173ESE-T [MAXIM]
Line Receiver, 4 Func, 4 Rcvr, CMOS, PDSO16, 0.150 INCH, MS-012AC, SOIC-16;
| 型号： | MAX9173ESE-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Line Receiver, 4 Func, 4 Rcvr, CMOS, PDSO16, 0.150 INCH, MS-012AC, SOIC-16 光电二极管 接口集成电路 |
| 文件： | 总14页 (文件大小：335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2595; Rev 0; 10/02
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
General Description
Features
The MAX9173 quad low-voltage differential signaling
(LVDS) line receiver is ideal for applications requiring
high data rates, low power, and low noise. The
MAX9173 is guaranteed to receive data at speeds up
to 500Mbps (250MHz) over controlled-impedance
media of approximately 100Ω. The transmission media
can be printed circuit (PC) board traces or cables.
ꢀ Accepts LVDS and LVPECL Inputs
ꢀ Fully Compatible with DS90LV048A
ꢀ Low 1.0mA (max) Disable Supply Current
ꢀ In-Path Fail-Safe Circuitry
ꢀ Flow-Through Pinout
Simplifies PC Board Layout
Reduces Crosstalk
The MAX9173 accepts four LVDS differential inputs and
translates them to LVCMOS/LVTTL outputs. The
MAX9173 inputs are high impedance and require an
external termination resistor when used in a point-to-
point connection.
ꢀ Guaranteed 500Mbps Data Rate
ꢀ 400ps Pulse Skew (max)
ꢀ Conforms to ANSI TIA/EIA-644 LVDS Standard
ꢀ High-Impedance LVDS Inputs when Powered-Off
ꢀ Available in Tiny 3mm x 3mm QFN Package
The device supports a wide common-mode input range
of 0.05V to V
- 0.05V, allowing for ground potential
CC
differences and common-mode noise between the dri-
ver and the receiver. A fail-safe feature sets the output
high when the inputs are open, or when the inputs are
undriven and shorted or undriven and parallel terminat-
ed. The EN and EN inputs control the high-impedance
outputs. The enables are common to all four receivers.
Inputs conform to the ANSI TIA/EIA-644 LVDS stan-
dard. The flow-through pinout simplifies board layout
and reduces crosstalk by separating the LVDS inputs
and LVCMOS/LVTTL outputs. The MAX9173 operates
from a single 3.3V supply, and is specified for opera-
tion from -40°C to +85°C. Refer to the MAX9121/
MAX9122 data sheet for lower jitter quad LVDS
receivers with parallel fail-safe. Refer to the MAX9123
data sheet for a quad LVDS line driver with flow-
through pinout.
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
16 TSSOP
MAX9173EUE
MAX9173ESE
MAX9173ETE*
16 SO
16 Thin QFN-EP**
*Future product. Contact factory for availability.
**EP = Exposed pad.
Typical Operating Circuit
LVDS SIGNALS
MAX9173
MAX9123
The device is available in 16-pin TSSOP, SO, and
space-saving thin QFN packages.
Tx
100Ω
Rx
Applications
Digital Copiers
Tx
Tx
Tx
100Ω
100Ω
100Ω
Rx
Rx
Rx
Laser Printers
Cellular Phone Base Stations
Network Switches/Routers
Backplane Interconnect
Clock Distribution
LVTTL/LVCMOS
DATA INPUTS
LVTTL/LVCMOS
DATA OUTPUTS
LCD Displays
Telecom Switching Equipment
Pin Configurations and Functional Diagram appear at end of
data sheet.
100Ω SHIELDED TWISTED CABLE OR MICROSTRIP BOARD TRACES
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
ABSOLUTE MAXIMUM RATINGS
CC
IN_+, IN_- to GND .................................................-0.3V to +4.0V
OUT_, EN, EN to GND................................-0.3V to (V + 0.3V)
V
to GND ..........................................................-0.3V to +4.0V
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection (Human Body Model, IN_+, IN_-) ............ 7.0kV
Lead Temperature (soldering, 10s) .................................+300°C
CC
Continuous Power Dissipation (T = +70°C)
A
16-Pin TSSOP (derate 9.4mW/°C above T = +70°C)..755mW
A
16-Pin SO (derate 8.7mW/°C above T = +70°C) ........696mW
A
16-Pin QFN (derate 14.7mW/°C above T = +70°C)..1177mW
A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= 3.0V to 3.6V, differential input voltage |V | = 0.1V to 1.2V, common-mode input voltage V
= |V /2| to V
- |V /2|, outputs
CC ID
CC
ID
CM
ID
enabled, and T = -40°C to +85°C. Typical values are at V
= 3.3V, V
= 1.2V, |V | = 0.2V, and T = +25°C, unless otherwise
CM ID A
A
CC
noted.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVDS INPUTS (IN_+, IN_-)
Differential Input High Threshold
Differential Input Low Threshold
Input Current (Noninverting Input)
V
-45
-45
-2.5
0
mV
mV
µA
TH
V
-100
+0.5
TL
I
Figure 1
-5
IN_+
Power-Off Input Current
(Noninverting Input)
V
V
= 0 to 3.6V, V
= 0 or open (Figure 1)
= 0 to 3.6V,
IN_+
IN_-
I
-0.5
-0.5
-0.5
0
+5.0
0
+0.5
+10
+0.5
µA
µA
µA
IN_+OFF
CC
Input Current (Inverting Input)
I
Figure 1
IN_-
Power-Off Input Current
(Inverting Input)
V
V
= 0 to 3.6V, V
= 0 to 3.6V,
IN_+
IN_-
I
IN_-OFF
= 0 or open, Figure 1
CC
OH
LVCMOS/LVTTL OUTPUTS (OUT_)
Open, undriven short, or
2.7
2.7
3.2
undriven parallel termination
Output High Voltage (Table 1)
V
I
I
= -4.0mA
V
OH
V
= 0
3.2
0.1
-77
ID
Output Low Voltage
Output Short-Circuit Current
Output High-Impedance Current
LOGIC INPUTS (EN, EN)
Input High Voltage
V
= +4.0mA, V = -100mV
0.25
-120
+1
V
OL
OS
OZ
OL
ID
I
I
V
= 0 (Note 3)
-45
-1
mA
µA
OUT_
Disabled, V
= 0 or V
CC
OUT_
V
2.0
0
V
V
V
IH
CC
Input Low Voltage
V
0.8
+15
-1.5
IL
IN
Input Current
I
V
= high or low
= -18mA
-15
µA
V
IN
Input Clamp Voltage
POWER SUPPLY
V
I
-0.88
CL
CL
Supply Current
I
Inputs open
Disabled, inputs open
12
15
mA
mA
CC
Disabled Supply Current
I
0.56
1.0
CCZ
2
_______________________________________________________________________________________
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
AC ELECTRICAL CHARACTERISTICS
(V
= 3.0V to 3.6V, C = 15pF, |V | = 0.2V, V
= 1.2V, and T = -40°C to +85°C. Typical values are at V
= 3.3V and T =
CC A
CC
L
ID
CM
A
+25°C, unless otherwise noted.) (Notes 4–7)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Propagation Delay
High to Low
t
t
t
t
Figures 2 and 3
Figures 2 and 3
1.2
2.01
2.7
ns
PHLD
PLHD
SKD1
SKD2
Differential Propagation Delay
Low to High
1.2
2.07
60
2.7
400
500
ns
ps
ps
ns
Differential Pulse Skew
Figures 2 and 3 (Note 8)
Figures 2 and 3 (Note 9)
|t
- t
|
PHLD PLHD
Differential Channel-to-Channel
Skew
100
t
t
Figures 2 and 3 (Note 10)
Figures 2 and 3 (Note 11)
Figures 2 and 3
1
SKD3
SKD4
Differential Part-to-Part Skew
1.5
1.0
1.0
14
14
14
14
Rise Time
t
t
0.66
0.62
9.5
9.5
3
ns
ns
TLH
THL
PHZ
Fall Time
Figures 2 and 3
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
Maximum Operating Frequency
t
R
R
R
R
= 2kΩ, Figures 4 and 5
= 2kΩ, Figures 4 and 5
= 2kΩ, Figures 4 and 5
= 2kΩ, Figures 4 and 5
ns
L
L
L
L
t
ns
PLZ
PZH
t
ns
t
3
ns
PZL
f
All channels switching (Note 12)
250
MHz
MAX
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V , V , and V
.
ID
TH TL
Note 2: Devices are 100% production tested at T = +25°C and are guaranteed by design for T = -40°C to +85°C as specified.
A
A
Note 3: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
Note 4: AC parameters are guaranteed by design and characterization.
Note 5: C includes scope probe and test jig capacitance.
L
Note 6: Pulse generator output conditions: t = t < 1ns (0% to 100%), frequency = 250MHz, 50% duty cycle, V
= 1.3V, V
=
OL
R
F
OH
1.1V. High-impedance delay pulse generator output conditions: t = t < 3ns (0% to 100%), frequency = 1MHz, 50% duty
R
F
cycle, V
= 3V and V = 0.
OH
OL
Note 7: Propagation delay and differential pulse skew decrease when |V | is increased from 200mV to 400mV. Skew specifications
ID
apply for 200mV ≤ |V | ≤ 1.2V over the common-mode range V
= |V |/2 to V
- |V |/2.
CC ID
ID
CM
ID
Note 8:
Note 9:
t
t
is the magnitude of the difference of differential propagation delays in a channel. t
= |t
PHLD
- t
|.
SKD1
SKD2
SKD1
PLHD
PHLD PLHD
is the magnitude of the difference of the t
or t
of one channel and the t
or t
of any other channel
PLHD
PHLD
on the same part.
Note 10: t is the magnitude of the difference of any differential propagation delays between parts operating over rated conditions
SKD3
at the same V and within 5°C of each other.
CC
Note 11: t
is the magnitude of the difference of any differential propagation delays between parts operating over rated conditions.
SKD4
Note 12: 60% to 40% duty cycle, V = 0.4V (max), V
= 2.7V (min), load = 15pF.
OL
OH
_______________________________________________________________________________________
3
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
Typical Operating Characteristics
(V
= 3.3V, V
= 1.2V, |V | = 0.2V, f = 100MHz, input rise and fall time = 1ns (0% to 100%), C = 15pF, and T = +25°C, unless
CC
CM
ID
L
A
otherwise noted.) (Figures 2 and 3)
DIFFERENTIAL THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. FREQUENCY
SUPPLY CURRENT vs. TEMPERATURE
100
16
15
14
13
12
11
10
9
-35
-39
-43
-47
-51
-55
C = 15pF
L
ALL INPUTS OPEN
90
80
70
60
50
40
30
20
10
0
ALL CHANNELS
SWITCHING
V
TH
ONE CHANNEL
SWITCHING
V
TL
8
0.01
0.1
1
10
100
1000
-40
-15
10
35
60
85
3.0
3.1
3.2
3.3
3.4
3.5
3.6
FREQUENCY (MHz)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
OUTPUT SHORT-CIRCUIT CURRENT
vs. SUPPLY VOLTAGE
OUTPUT HIGH-IMPEDANCE CURRENT
vs. SUPPLY VOLTAGE
OUTPUT HIGH VOLTAGE
vs. SUPPLY VOLTAGE
-60
-65
-70
-75
-80
-85
-90
-95
-100
-0.010
-0.015
-0.020
-0.025
-0.030
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
I
= -4mA
ALL INPUTS OPEN
OH
EN = LOW, EN = HIGH, V
= 0
OUT
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
OUTPUT LOW VOLTAGE
vs. SUPPLY VOLTAGE
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
98
97
96
95
94
93
92
91
90
89
88
2.20
2.15
2.10
2.05
2.00
1.95
1.90
2.30
2.25
2.20
2.15
2.10
2.05
2.00
1.95
1.90
1.85
1.80
I
= 4mA
OL
t
PLHD
t
PLHD
t
PHLD
t
PHLD
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
Typical Operating Characteristics (continued)
(V
= 3.3V, V
= 1.2V, |V | = 0.2V, f = 100MHz, input rise and fall time = 1ns (0% to 100%), C = 15pF, and T = +25°C, unless
CC
CM
ID
L
A
otherwise noted.) (Figures 2 and 3)
DIFFERENTIAL PROPAGATION DELAY
DIFFERENTIAL PROPAGATION DELAY
vs. DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL PROPAGATION DELAY
vs. LOAD
vs. COMMON-MODE VOLTAGE
2.7
2.40
2.35
2.30
2.25
2.20
2.15
2.10
2.05
2.00
1.95
1.90
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
2.6
2.5
2.4
2.3
t
PLHD
t
t
PLHD
PLHD
t
PHLD
2.2
2.1
2.0
1.9
1.8
t
PHLD
t
PHLD
0.1
0.6
1.1
1.6
2.1
2.6
3.1
0.1
0.3
0.5
0.7
0.9
1.1
10
20
30
LOAD (pF)
40
50
COMMON-MODE VOLTAGE (V)
DIFFERENTIAL INPUT VOLTAGE (V)
TRANSITION TIME vs. SUPPLY VOLTAGE
TRANSITION TIME vs. TEMPERATURE
TRANSITION TIME vs. LOAD
720
680
640
600
560
800
750
700
650
600
550
500
450
400
2000
1800
1600
1400
1200
1000
800
t
TLH
t
t
TLH
TLH
t
THL
t
THL
t
THL
600
400
3.0
3.1
3.2
3.3
3.4
3.5
3.6
-40
-15
10
35
60
85
10
20
30
40
50
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
LOAD (pF)
DIFFERENTIAL PULSE SKEW
vs. INPUT TRANSITION TIME
DIFFERENTIAL PULSE SKEW
vs. SUPPLY VOLTAGE
400
350
300
250
200
150
100
50
120
110
100
90
80
70
60
50
40
30
20
10
0
f = 50MHz
0
1.0
1.5
2.0
2.5
3.0
3.0
3.1
3.2
3.3
3.4
3.5
3.6
INPUT TRANSITION TIME (ns)
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
5
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
Pin Description
PIN
NAME
FUNCTION
TSSOP/SO
QFN
15
16
1
1
2
3
4
5
6
7
8
IN1-
IN1+
IN2+
IN2-
IN3-
IN3+
IN4+
IN4-
Inverting Differential Receiver Input for Receiver 1
Noninverting Differential Receiver Input for Receiver 1
Noninverting Differential Receiver Input for Receiver 2
Inverting Differential Receiver Input for Receiver 2
Inverting Differential Receiver Input for Receiver 3
Noninverting Differential Receiver Input for Receiver 3
Noninverting Differential Receiver Input for Receiver 4
Inverting Differential Receiver Input for Receiver 4
2
3
4
5
6
Receiver Enable Inputs. When EN = high and EN = low or open, the outputs are active.
For other combinations of EN and EN, the outputs are disabled and in high
impedance.
9, 16
7, 14
EN, EN
10
11
12
8
9
OUT4
OUT3
GND
LVCMOS/LVTTL Receiver Output for Receiver 4
LVCMOS/LVTTL Receiver Output for Receiver 3
Ground
10
Power-Supply Input. Bypass V
Place the smaller value cap as close to the pin as possible.
to GND with 0.1µF and 0.001µF ceramic capacitors.
CC
13
11
V
CC
14
15
—
12
13
OUT2
OUT1
EP
LVCMOS/LVTTL Receiver Output for Receiver 2
LVCMOS/LVTTL Receiver Output for Receiver 1
Exposed Pad
Exposed Pad. Solder to ground plane for proper heat dissipation.
Table 1. Input/Output Function Table
ENABLES
INPUTS
OUTPUT
EN
EN
(IN_+) - (IN_-)
OUT_
V
≥ 0
H
L
ID
H
L or open
V
≤ -100mV
ID
Open, undriven short, or undriven parallel termination
H
Z
All other combinations of ENABLE pins
Don’t care
translates it to an LVTTL/LVCMOS output. The receiver
is specified to detect differential signals as low as
100mV and as high as 1.2V within an input voltage
Detailed Description
LVDS is a signaling method intended for point-to-point
communication over a controlled-impedance medium
as defined by the ANSI TIA/EIA-644 and IEEE 1596.3
standards. LVDS uses a lower voltage swing than other
common communication standards, achieving higher
data rates with reduced power consumption while
reducing EMI and system susceptibility to noise.
range of 0 to V . The 250mV to 400mV differential out-
CC
put of an LVDS driver is nominally centered around a
1.2V offset. This offset, coupled with the receiver’s 0 to
V
input voltage range, allows more than 1V shift in
CC
the signal (as seen by the receiver). This allows for a
difference in ground references of the transmitter and
the receiver, the common-mode effects of coupled
noise, or both.
The MAX9173 is a 500Mbps, four-channel LVDS receiv-
er intended for high-speed, point-to-point, low-power
applications. Each channel accepts an LVDS input and
6
_______________________________________________________________________________________
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
Fail-Safe
V
CC
The MAX9173 fail-safe drives the receiver output high
when the differential input is:
2.5µA
•
•
•
Open
IN_+
IN_-
Undriven and shorted
Undriven and terminated
OUT_
Without fail-safe, differential noise at the input may
switch the receiver and appear as data to the receiving
system. An open input occurs when a cable and termi-
nation are disconnected. An undriven, terminated input
occurs when a cable is disconnected with the termina-
tion still connected across the receiver inputs or when
the driver of a receiver is in high impedance. An undriv-
en, shorted input can occur due to a shorted cable.
45mV
5µA
“In-Path” vs. “Parallel” Fail-Safe
The MAX9173 has in-path fail-safe that is compatible
with in-path fail-safe receivers, such as the
DS90LV048A. Refer to the MAX9121/MAX9122 data
sheet for pin-compatible receivers with parallel fail-safe
and lower jitter. Refer to the MAX9130 data sheet for a
single LVDS receiver with parallel fail-safe in an SC70
package.
Figure 1. Input with Fail-Safe Network
sists of a 100pF capacitor charged to the ESD test volt-
age, which is then discharged into the test device
through a 1.5kΩ resistor.
Applications Information
Differential Traces
Input trace characteristics affect the performance of the
MAX9173. Use controlled-impedance board traces. For
point-to-point connections, match the receiver input ter-
mination resistor to the differential characteristic imped-
ance of the board traces.
The MAX9173 with in-path fail-safe is designed with a
+45mV input offset voltage, a 2.5µA current source
between V
and the noninverting input, and a 5µA
CC
current sink between the inverting input and ground
(Figure 1). If the differential input is open, the 2.5µA
current source pulls the input to approximately V
-
CC
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
0.8V and the 5µA current sink pulls the inverting input
to ground, which drives the receiver output high. If the
differential input is shorted or terminated with a typical
value termination resistor, the +45mV offset drives the
receiver output high. If the input is terminated and float-
ing, the receiver output is driven high by the +45mV off-
set, and the 2:1 current sink to current source ratio
(5µA:2.5µA) pulls the inputs to ground. This can be an
advantage when switching between drivers on a multi-
point bus because the change in common-mode volt-
age from ground to the typical driver offset voltage of
Each channel’s differential signals should be routed
close to each other to cancel their external magnetic
field. Maintain a constant distance between the differ-
ential traces to avoid discontinuities in differential
impedance. Minimize the number of vias to further pre-
vent impedance discontinuities.
1.2V is not as much as the change from V
to 1.2V
CC
Cables and Connectors
LVDS transmission media typically have controlled dif-
ferential impedance of 100Ω. Use cables and connec-
tors that have matched differential impedance to
minimize impedance discontinuities.
(parallel fail-safe pulls the bus to V ).
CC
ESD Protection
ESD-protection structures are incorporated on all pins
to protect against electrostatic discharges encountered
during handling and assembly. The receiver inputs of
the MAX9173 have 7.0kV of protection against static
electricity (per Human Body Model).
Avoid the use of unbalanced cables such as coaxial
cable. Balanced cables such as twisted pair offer
superior signal quality and tend to generate less EMI
due to magnetic field canceling effects. Balanced
cables pick up noise as common mode, which is reject-
ed by the LVDS receiver.
Figure 6a shows the Human Body Model, and Figure
6b shows the current waveform it generates when dis-
charged into a low-impedance load. This model con-
_______________________________________________________________________________________
7
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
inputs should be separated by 180° from the
Termination
The MAX9173 requires an external termination resistor.
The termination resistor should match the differential
impedance of the transmission line. Termination resis-
tance values may range between 90Ω to 132Ω,
depending on the characteristic impedance of the
transmission medium.
LVTTL/LVCMOS outputs to reduce crosstalk.
For LVDS applications, a four-layer PC board that pro-
vides separate layers of power, ground, LVDS inputs, and
output signals is recommended. When using the QFN
package, solder the exposed pad (EP) to the ground
plane using an array of vias for proper heat dissipation.
When using the MAX9173, minimize the distance be-
tween the input termination resistors and the MAX9173
receiver inputs. Use 1% surface-mount resistors.
Chip Information
Board Layout
In general, separate the LVDS inputs from single-ended
outputs to reduce crosstalk. Take special care when
routing traces with the QFN package. Ideally, the LVDS
TRANSISTOR COUNT: 1462
PROCESS: CMOS
IN_+
PULSE
GENERATOR
OUT_
C
L
IN_-
50Ω*
50Ω*
*50Ω REQUIRED FOR PULSE GENERATOR.
Figure 2. Propagation Delay and Transition Time Test Circuit
IN_-
1.3V
1.1V
V
ID
= 0.2V
1.2V (0V DIFFERENTIAL)
IN_+
t
t
PHLD
PLHD
V
OH
80%
80%
1.5V
1.5V
20%
20%
V
OL
OUT_
t
t
THL
TLH
Figure 3. Propagation Delay and Transition Time Test Waveforms
_______________________________________________________________________________________
8
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
V
CC
S
1
R
L
IN_+
IN_-
DEVICE
UNDER
TEST
OUT_
GENERATOR
EN
EN
C
L
50Ω
1/4 MAX9173
C INCLUDES LOAD AND TEST JIG CAPACITANCE.
L
S = V FOR t AND t MEASUREMENTS.
1
CC
PZL
PLZ
S = GND FOR t AND t MEASUREMENTS.
1
PZH
PHZ
Figure 4. High-Impedance Delay Test Circuit
EN WHEN EN = GND OR OPEN
1.5V
3V
0
1.5V
1.5V
3V
0
1.5V
EN WHEN EN = V
CC
t
PZL
V
CC
t
t
PLZ
50%
OUTPUT WHEN
= -100mV
0.5V
V
V
OL
V
ID
t
PZH
PHZ
OUTPUT WHEN
= 0
OH
0.5V
V
ID
50%
GND
Figure 5. High-Impedance Delay Waveforms
R
C
1M
R 1500Ω
D
I
P
100%
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
r
DISCHARGE
RESISTANCE
CHARGE-CURRENT
LIMIT RESISTOR
AMPERES
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
STORAGE
CAPACITOR
s
36.8%
100pF
SOURCE
10%
0
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Figure 6a. Human Body ESD Test Modules
Figure 6b. Human Body Current Waveform
_______________________________________________________________________________________
9
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
Pin Configurations
TOP VIEW
IN1-
1
2
3
4
5
6
7
8
16 EN
IN1+
IN2+
IN2-
IN3-
IN3+
IN4+
IN4-
15 OUT1
14 OUT2
IN2+
IN2-
IN3-
IN3+
1
2
3
4
12 OUT2
11
10 GND
OUT3
V
CC
MAX9173
13 V
CC
MAX9173
12 GND
11 OUT3
10 OUT4
9
9
EN
TSSOP/SO
THIN QFN-EP
Functional Diagram
V
CC
IN1+
OUT1
OUT2
OUT3
OUT4
IN1-
IN2+
IN2-
IN3+
IN3-
IN4+
IN4-
EN
EN
MAX9173
GND
10 ______________________________________________________________________________________
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
______________________________________________________________________________________ 11
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
b
0.10 M
C
A
B
D
D2/2
D/2
E/2
E2/2
- A -
(NE - 1)
X e
C
E2
E
L
L
- B -
k
e
C
L
(ND - 1)
X e
C
L
C
L
0.10
C
0.08
C
A
A2
A1
L
L
e
e
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
12 & 16L, QFN THIN, 3x3x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0136
C
2
12 ______________________________________________________________________________________
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
EXPOSED PAD VARIATIONS
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
12 & 16L, QFN THIN, 3x3x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
2
21-0136
C
2
______________________________________________________________________________________ 13
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
INCHES
MILLIMETERS
DIM
A
MIN
MAX
0.069
0.010
0.019
0.010
MIN
1.35
0.10
0.35
0.19
MAX
1.75
0.25
0.49
0.25
0.053
0.004
0.014
0.007
N
A1
B
C
e
0.050 BSC
1.27 BSC
E
0.150
0.228
0.016
0.157
0.244
0.050
3.80
5.80
0.40
4.00
6.20
1.27
E
H
H
L
VARIATIONS:
INCHES
1
MILLIMETERS
DIM
D
MIN
MAX
0.197
0.344
0.394
MIN
4.80
8.55
9.80
MAX
5.00
N
8
MS012
AA
TOP VIEW
0.189
0.337
0.386
D
8.75 14
10.00 16
AB
D
AC
D
C
A
B
0 -8
e
A1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0041
B
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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