MAX9174EUB [MAXIM]
670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters; 670MHz的LVDS至LVDS和任何对LVDS 1 ： 2分配器
| 型号： | MAX9174EUB |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters |
| 文件： | 总14页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2827; Rev 0; 4/03
670MHz LVDS-to-LVDS and Anything-to-LVDS
1:2 Splitters
General Description
Features
The MAX9174/MAX9175 are 670MHz, low-jitter, low-
skew 1:2 splitters ideal for protection switching, loop-
back, and clock and signal distribution. The devices
ꢀ 1.0ps
Jitter (max) at 670MHz
(RMS)
ꢀ 80ps
Jitter (max) at 800Mbps Data Rate
(P-P)
feature ultra-low 1.0ps
random jitter (max) that
(RMS)
ꢀ +3.3V Supply
ensures reliable operation in high-speed links that are
highly sensitive to timing errors.
ꢀ LVDS Fail-Safe Inputs (MAX9174)
ꢀ Anything Input (MAX9175) Accepts Differential
The MAX9174 has a fail-safe LVDS input and LVDS out-
puts. The MAX9175 has an anything differential input
(CML/LVDS/LVPECL) and LVDS outputs. The outputs
can be put into high impedance using the power-down
inputs. The MAX9174 features a fail-safe circuit that dri-
ves the outputs high when the input is open, undriven
and shorted, or undriven and terminated. The MAX9175
has a bias circuit that forces the outputs high when the
input is open. The power-down inputs are compatible
with standard LVTTL/LVCMOS logic. The power-down
CML/LVDS/LVPECL
ꢀ Power-Down Inputs Tolerate -1.0V and V
+ 1.0V
CC
ꢀ Low-Power CMOS Design
ꢀ 10-Lead µMAX and Thin QFN Packages
ꢀ -40°C to +85°C Operating Temperature Range
ꢀ Conform to ANSI TIA/EIA-644 LVDS Standard
ꢀ IEC 61000-4-2 Level 4 ESD Rating
inputs tolerate undershoot of -1V and overshoot of V
CC
+ 1V. The MAX9174/MAX9175 are available in 10-pin
µMAX and 10-lead thin QFN with exposed pad pack-
ages, and operate from a single +3.3V supply over the
-40°C to +85°C temperature range.
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
10 µMAX
MAX9174EUB
MAX9174ETB*
MAX9175EUB
MAX9175ETB*
Applications
10 Thin QFN-EP**
10 µMAX
Protection Switching
Loopback
10 Thin QFN-EP**
Clock Distribution
*Future product—contact factory for availability.
**EP = Exposed paddle.
Functional Diagram and Pin Configurations appear at end
of data sheet.
Typical Application Circuit
CLOCK DISTRIBUTION
ASIC
MAX9176
MAX9174
CLK IN
CLK1
ASIC
MAX9176
MAX9174
CLK IN
CLK2
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
670MHz LVDS-to-LVDS and Anything-to-LVDS
1:2 Splitters
ABSOLUTE MAXIMUM RATINGS
CC
IN+, IN- to GND...........................................……...-0.3V to +4.0V
OUT_+, OUT_- to GND..........................................-0.3V to +4.0V
PD0, PD1 to GND.......................................-1.4V to (V
V
to GND..………………………………………...-0.3V to +4.0V
Storage Temperature Range.............................-65°C to +150°C
ESD Protection
Human Body Model (R = 1.5kΩ, C = 100pF)
D
S
+ 1.4V)
IN+, IN-, OUT_+, OUT_-...............................................… 2kV
CC
Single-Ended and Differential Output
Short-Circuit Duration (OUT_+, OUT_-) .....................Continuous
Other Pins (V , PD0, PD1)...............................................2kV
CC
IEC 61000-4-2 Level 4 (R = 330Ω, C = 150pF)
D S
Continuous Power Dissipation (T = +70°C)
Contact Discharge IN+, IN-, OUT_+, OUT_- ................... 8kV
Air-Gap Discharge IN+, IN-, OUT_+, OUT_- ................. 15kV
Lead Temperature (soldering, 10s) .................................+300°C
A
10-Pin µMAX (derate 5.6mW/°C above +70°C)...........444mW
10-Lead QFN (derate 24.4mW/°C above +70°C)......1951mW
Maximum Junction Temperature .....................................+150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, R = 100Ω 1ꢀ, PD_ = high, differential input voltage |V | = 0.05V to 1.2V, MAX9174 input common-mode
CC
L ID
= |V /2| to (2.4V - |V /2|), MAX9175 input common-mode voltage V
voltage V
= |V /2| to (V
- | V /2|), T = -40°C to
CC ID A
CM
ID
ID
CM
ID
+85°C, unless otherwise noted. Typical values are at V
= +3.3V, |V | = 0.2V, V
= +1.25V, T = +25°C.) (Notes 1, 2, 3)
CM A
CC
ID
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
+50
+20
UNITS
DIFFERENTIAL INPUT (IN+, IN-)
Differential Input High Threshold
Differential Input Low Threshold
Input Current
V
mV
mV
µA
TH
V
-50
-20
TL
I
I
Figure 1
IN+, IN-
MAX9174
V
V
= 0V or open, Figure 1
CC
I
IN+,
= 3.6V or 0V, V = 3.6V
IN-
IN+
Power-Off Input Current
-20
+20
µA
I
IN-
MAX9175
or 0V, V
= 0V or open,
CC
Figure 1
R
R
60
108
394
IN1
IN2
Fail-Safe Input Resistors
(MAX9174)
V
V
= 3.6V, 0V or open, Figure 1
= 3.6V, 0V or open, Figure 1
kΩ
CC
CC
200
Input Resistors
(MAX9175)
R
212
450
4.5
kΩ
IN3
Input Capacitance
C
IN+ or IN- to GND (Note 4)
pF
IN
PD0 PD1
)
LVTTL/LVCMOS INPUTS (
,
V
+
CC
1
Input High Voltage
V
2.0
V
IH
Input Low Voltage
V
-1.0
-1.5
+0.8
V
IL
-1.0V ≤ PD_ ≤ 0V
mA
Input Current
I
0V ≤ PD_ ≤ V
-20
+20
µA
IN
CC
V
≤ PD_ ≤ V
+ 1.0V
CC
+1.5
mA
CC
LVDS OUTPUTS (OUT_+, OUT_-)
Differential Output Voltage
V
Figure 2
Figure 2
Figure 3
250
393
1.0
475
15
mV
mV
V
OD
Change in Differential Output
Voltage Between Logic States
∆V
OD
OS
Offset Voltage
V
1.125
1.29
1.375
2
_______________________________________________________________________________________
670MHz LVDS-to-LVDS and Anything-to-LVDS
1:2 Splitters
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, R = 100Ω 1ꢀ, PD_ = high, differential input voltage |V | = 0.05V to 1.2V, MAX9174 input common-mode
CC
L ID
= |V /2| to (2.4V - |V /2|), MAX9175 input common-mode voltage V
voltage V
= |V /2| to (V
- | V /2|), T = -40°C to
CC ID A
CM
ID
ID
CM
ID
+85°C, unless otherwise noted. Typical values are at V
= +3.3V, |V | = 0.2V, V
= +1.25V, T = +25°C.) (Notes 1, 2, 3)
CM A
CC
ID
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Change in Offset Voltage
Between Logic States
∆V
Figure 3
Figure 2
1.0
15
mV
OS
Fail-Safe Differential Output
Voltage (MAX9174)
V
250
86
393
119
475
160
mV
OD
Differential Output Resistance
R
V
= 3.6V or 0V
CC
Ω
DIFF
V
V
= open,
= 3.6V or 0V
OUT_+
OUT_-
Power-Down Single-Ended
Output Current
I
PD_ = low
-1.0
0.03
0.03
+1.0
µA
µA
PD
V
V
= open,
= 3.6V or 0V
OUT_-
OUT_+
V
V
= open,
= 3.6V or 0V
OUT_+
OUT_-
Power-Off Single-Ended Output
Current
PD0, PD1 = low,
I
-1.0
-15
+1.0
+15
OFF
V
= 0V or open
CC
V
V
= open,
= 3.6V or 0V
OUT_-
OUT_+
V
V
= +50mV or -50mV, V
= 0V or
ID
OUT_+
Output Short-Circuit Current
I
mA
mA
mA
CC
OS
V
= +50mV or -50mV, V
= 0V or V
ID
ID
OUT_-
CC
Differential Output Short-Circuit
Current Magnitude
I
V
= +50mV or -50mV, V
= 0V (Note 4)
OD
15
26
OSD
PD0 = V , PD1 = 0V or
PD0 = 0V, PD1 = V
CC
CC
17
Supply Current
I
CC
PD0 = Vcc, PD1 = Vcc
PD1, PD0 = 0V
25
35
20
Power-Down Supply Current
Output Capacitance
I
0.5
µA
pF
CCPD
C
OUT_+ or OUT_- to GND (Note 4)
5.2
O
_______________________________________________________________________________________
3
670MHz LVDS-to-LVDS and Anything-to-LVDS
1:2 Splitters
AC ELECTRICAL CHARACTERISTICS
(V
age, V
= +3.0V to +3.6V, R = 100Ω 1ꢀ, C = 5pF, differential input voltage |V | = 0.15V to 1.2V, MAX9174 input common-mode volt-
CC
L L ID
= |V /2| to (2.4V - |V /2|), MAX9175 input common-mode voltage V
= |V /2| to (V
- |V /2|), PD_ = high, T = -40°C
CC ID A
CM
ID
ID
CM
ID
to +85°C, unless otherwise noted. Typical values are at V
= +3.3V, |V | = 0.2V, V
= +1.25V, T = +25°C.) (Notes 5, 6, 7)
CM A
CC
ID
PARAMETER
SYMBOL
CONDITIONS
MIN
1.33
1.33
TYP
2.38
2.39
MAX
3.23
3.23
80
UNITS
ns
High-to-Low Propagation Delay
Low-to-High Propagation Delay
Added Deterministic Jitter
Added Random Jitter
t
t
Figures 4, 5
PHL
Figures 4, 5
ns
PLH
t
Figures 4, 5 (Note 8)
Figures 4, 5
ps
(P-P)
DJ
t
1.0
ps
(RMS)
RJ
Pulse Skew t
- t
t
Figures 4, 5
10
14
141
45
ps
PLH PHL
SKP
Output-to-Output Skew
t
Figure 6
ps
ns
SKOO
t
t
Figures 4, 5 (Note 9)
Figures 4, 5 (Note 10)
Figures 4, 5
0.4
1.3
SKPP1
SKPP2
Part-to-Part Skew
1.9
Rise Time
t
110
110
257
252
10
365
365
13
ps
ps
ns
µs
R
Fall Time
t
Figures 4, 5
F
Power-Down Time
t
t
Figures 7, 8
PD
PD0, PD1 = L → H, Figures 7, 8
18
35
Power-Up Time
PD0 = H, PD1 = L → H, Figures 7, 8
PD1 = H, PD0 L → H, Figures 7, 8
92
103
103
PU
ns
92
Figures 4, 5, V ≥ 250mV
(Note 11)
OD
Maximum Data Rate
D
800
670
Mbps
MHz
mA
RMAX
Maximum Switching Frequency
Switching Supply Current
PRBS Supply Current
f
Figures 4, 5, V ≥ 250mV (Note 11)
OD
MAX
f
f
= 670MHz
= 155MHz
55
35
37
65
44
46
IN
IN
I
CCSW
23
I
D
= 800Mbps, 2 - 1 PRBS input
R
mA
CCPR
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V , V , V , V , and ∆V
.
OD
TH TL ID OD
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100ꢀ tested at
= +25°C.
T
A
Note 3: Tolerance on all external resistors (including figures) is 1ꢀ.
Note 4: Guaranteed by design.
Note 5: AC parameters are guaranteed by design and characterization and are not production tested. Limits are set at 6 sigma.
Note 6: C includes scope probe and test jig capacitance.
L
Note 7: Pulse-generator output for differential inputs IN+, IN- (unless otherwise noted): f = 670MHz, 50ꢀ duty cycle, R = 50Ω, t
=
R
O
700ps, and t = 700ps (0ꢀ to 100ꢀ). Pulse-generator output for single-ended inputs PD0, PD1: t = t = 1.5ns (0.2V to
F
R
F
CC
0.8V ), 50ꢀ duty cycle, V
= V
OD
+ 1.0V settling to V , V = -1.0V settling to zero, f = 10kHz.
CC
OH
CC CC OL
Note 8: Pulse-generator output for t : |V | = 0.15V, V = 1.25V, data rate 800Mbps, 223 - 1 PRBS, R = 50Ω, t = 700ps, and t
DJ
OS
O
R
F
= 700ps (0ꢀ to 100ꢀ).
Note 9: t is the magnitude of the difference of any differential propagation delays between devices operating under identical
SKPP1
conditions.
Note 10:t is the magnitude of the difference of any differential propagation delays between devices operating over rated con-
SKPP2
ditions.
Note 11:Meets all AC specifications.
4
_______________________________________________________________________________________
670MHz LVDS-to-LVDS and Anything-to-LVDS
1:2 Splitters
Typical Operating Characteristics
((MAX9174) V
= +3.3V, |V | = 0.15V, V
= 1.25V, T = +25°C, R = 100Ω 1ꢀ, C = 5pf, PD_ = V , unless otherwise noted.)
CC
ID
CM A L L CC
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
DIFFERENTIAL OUTPUT VOLTAGE
vs. FREQUENCY
SUPPLY CURRENT vs. TEMPERATURE
300
290
280
270
260
250
240
230
220
210
38
37
36
35
34
33
32
410
400
390
380
370
360
350
340
330
320
310
300
f
IN
= 155MHz
f
= 155MHz
IN
t
R
t
F
-40
-15
10
35
60
85
-40
-15
10
35
60
85
0
100 200 300 400 500 600 700 800
FREQUENCY (MHz)
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT-TO-OUTPUT SKEW
vs. TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
SUPPLY CURRENT vs. FREQUENCY
20
18
16
14
12
10
8
60
55
50
45
40
35
30
25
20
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
f
IN
= 155MHz
f
IN
= 155MHz
t
PHL
6
4
t
PLH
2
0
-40
-15
10
35
60
85
0
100 200 300 400 500 600 700 800
FREQUENCY (MHz)
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT RISE/FALL TIME
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. DATA RATE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
300
290
280
270
260
250
240
230
220
210
200
45
40
35
30
25
20
15
40
39
38
37
36
35
34
33
32
31
30
PRBS 223 - 1
f
IN
= 155MHz
f
IN
= 155MHz
t
R
t
F
3.0
3.1
3.2
3.3
3.4
3.5
3.6
0
100 200 300 400 500 600 700 800
DATA RATE (Mbps)
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
5
670MHz LVDS-to-LVDS and Anything-to-LVDS
1:2 Splitters
Typical Operating Characteristics (continued)
((MAX9174) V
= +3.3V, |V | = 0.15V, V
= 1.25V, T = +25°C, R = 100Ω 1ꢀ, C = 5pf, PD_ = V , unless otherwise noted.)
CC
ID
CM
A
L
L
CC
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
OUTPUT-TO-OUTPUT SKEW
vs. SUPPLY VOLTAGE
DIFFERENTIAL OUTPUT VOLTAGE
vs. LOAD RESISTANCE
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
10
9
8
7
6
5
4
3
2
1
0
500
450
400
350
300
250
200
f
= 155MHz
f = 155MHz
IN
IN
t
PHL
t
PLH
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
50 60 70 80 90 100 110 120 130 140 150
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
LOAD RESISTANCE (Ω)
PROPAGATION DELAY
vs. INPUT COMMON-MODE VOLTAGE
PROPAGATION DELAY
vs. INPUT COMMON-MODE VOLTAGE
2.8
2.7
2.6
2.5
2.4
2.3
2.2
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
MAX9174
IN
f
= 155MHz
IN
f
= 155MHz
t
t
PHL
PHL
t
PLH
t
PLH
0.075
0.825
1.575
2.325
0.075 0.525 0.975 1.425 1.875 2.325 2.775 3.225
INPUT COMMON-MODE VOLTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
OUTPUT-TO-OUTPUT SKEW
vs. INPUT COMMON-MODE VOLTAGE
OUTPUT-TO-OUTPUT SKEW
vs. INPUT COMMON-MODE VOLTAGE
8.0
7.8
7.6
7.4
7.2
7.0
6.8
6.6
6.4
6.2
6.0
6.0
MAX9175
= 155MHz
MAX9174
IN
f
IN
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
f
= 155MHz
0.075
0.825
1.575
2.325
0.075 0.525 0.975 1.425 1.875 2.325 2.775 3.225
INPUT COMMON-MODE VOLTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
6
_______________________________________________________________________________________
670MHz LVDS-to-LVDS and Anything-to-LVDS
1:2 Splitters
Pin Description
PIN
NAME
FUNCTION
µMAX
QFN
1
2
3
1
2
3
IN+
IN-
Noninverting Differential Input
Inverting Differential Input
Ground
GND
LVTTL/LVCMOS Input. OUT0+, OUT0- are high impedance to ground when PD0 is low.
4
5
4
5
PD0
PD1
Internal pulldown resistor to GND.
LVTTL/LVCMOS Input. OUT1+, OUT1- are high impedance to ground when PD1 is low.
Internal pulldown resistor to GND.
6
7
6
7
OUT0-
Inverting LVDS Output 0
Noninverting LVDS Output 0
Power Supply
OUT0+
8
8
V
CC
9
9
OUT1-
Inverting LVDS Output 1
Noninverting LVDS Output 1
10
10
OUT1+
Exposed
Pad
—
EP
Exposed Pad. Solder to ground.
A differential output voltage is produced by steering
Detailed Description
current through the parallel combination of the integrat-
ed differential output resistor and transmission line
impedance/termination resistor. When driving a 100Ω
termination resistor, a differential voltage of 250mV to
475mV is produced. For loads greater than 100Ω, the
output voltage is larger, and for loads less than 100Ω,
the output voltage is smaller. See the Differential Output
Voltage vs. Load Resistance curve in Typical Operating
Characteristics for more information. The outputs are
short-circuit current limited for single-ended and differ-
ential shorts.
The MAX9174/MAX9175 are 670MHz, low-jitter, low-
skew 1:2 splitters ideal for protection switching, loop-
back, and clock and signal distribution. The devices
feature ultra-low 80ps
deterministic jitter (max) that
P-P
ensures reliable operation in high-speed links that are
highly sensitive to timing error.
The MAX9174 has a fail-safe LVDS input and LVDS out-
puts. The MAX9175 has an anything differential input
(CML/LVDS/LVPECL) and LVDS outputs. The outputs
can be put into high impedance using the power-down
inputs. The MAX9174 features a fail-safe circuit that dri-
ves the outputs high when the input is open, undriven
and shorted, or undriven and terminated. The MAX9175
has a bias circuit that forces the outputs high when the
input is open. The power-down inputs are compatible
with standard LVTTL/LVCMOS logic.
MAX9174 Input Fail-Safe
The fail-safe feature of the MAX9174 sets the outputs
high when the differential input is:
• Open
• Undriven and shorted
• Undriven and terminated
The power-down inputs tolerate undershoot of -1V and
overshoot of VCC + 1V. The MAX9174/MAX9175 are
available in 10-pin µMAX and 10-lead thin QFN pack-
ages, and operate from a single +3.3V supply over the
-40°C to +85°C temperature range.
Without a fail-safe circuit, when the input is undriven,
noise at the input may switch the outputs and it may
appear to the system that data is being sent. Open or
undriven terminated input conditions can occur when a
cable is disconnected or cut, or when a driver output is
in high impedance. A shorted input can occur because
of a cable failure.
Current-Mode LVDS Outputs
The LVDS outputs use a current-steering configuration.
This approach results in less ground bounce and less
output ringing, enhancing noise margin and system
speed performance.
_______________________________________________________________________________________
7
670MHz LVDS-to-LVDS and Anything-to-LVDS
1:2 Splitters
When the input is driven with a differential signal of |V |
ID
Table 1. Input Function Table
= 50mV to 1.2V within a voltage range of 0 to 2.4V, the
fail-safe circuit is not activated. If the input is open,
undriven and shorted, or undriven and terminated, an
internal resistor in the fail-safe circuit pulls the input
above VCC - 0.3V, activating the fail-safe circuit and
forcing the outputs high (Figure 1).
INPUT
OUTPUTS
(IN+) - (IN-)
≥ +50mV
(OUT_+) - (OUT_-)
H
≤ -50mV
L
-50mV < VID < +50mV
Indeterminate
Overshoot and Undershoot Voltage
Protection
The MAX9174/MAX9175 are designed to protect the
power-down inputs (PD0 and PD1) against latchup due
to transient overshoot and undershoot voltage. If the
input voltage goes above VCC or below GND by up to
1V, an internal circuit limits input current to 1.5mA.
MAX9175
Open
Open, undriven
short, or undriven
parallel termination
H
MAX9174
Table 2. Power-Down Function Table
Applications Information
PD1
PD0
OUT_+, OUT_-
Both outputs enabled
H
H
Power-Supply Bypassing
pin with high-frequency surface-mount
Bypass the V
CC
Shutdown to minimum power,
outputs high impedance to ground
L or open
L or open
High
L or open
High
ceramic 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smaller valued
OUT0 enabled, OUT1 high
impedance to ground
capacitor closest to V
.
CC
Differential Traces
OUT1 enabled, OUT0 high
impedance to ground
L or open
Input and output trace characteristics affect the perfor-
mance of the MAX9174/MAX9175. Use controlled-
impedance differential traces (100Ω typ). To reduce
radiated noise and ensure that noise couples as com-
mon mode, route the differential input and output sig-
nals within a pair close together. Reduce skew by
matching the electrical length of the two signal paths
that make up the differential pair. Excessive skew can
result in a degradation of magnetic field cancellation.
Maintain a constant distance between the differential
traces to avoid discontinuities in differential impedance.
Minimize the number of vias to further prevent imped-
ance discontinuities.
V
CC
V
CC
R
IN2
R
R
IN3
IN3
COMPARATOR
- 0.3V
IN+
IN-
IN+
R
IN1
TO
OUTPUT
V
CC
R
IN1
Cables and Connectors
Interconnect for LVDS typically has a controlled differ-
ential impedance of 100Ω. Use cables and connectors
that have matched differential impedance to minimize
impedance discontinuities.
IN-
DIFFERENTIAL
RCVR
MAX9174 INTERNAL FAIL-SAFE CIRCUIT
MAX9175 INPUT
Figure 1. Input Structure
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to magnetic field canceling effects.
Balanced cables pick up noise as common mode,
which is rejected by the LVDS receiver.
termination resistor across the differential input and at
the far end of the interconnect driven by the LVDS out-
puts. Place the input termination resistor as close to the
receiver input as possible. Termination resistors should
match the differential impedance of the transmission
line. Use 1ꢀ surface-mount resistors.
Termination
The MAX9174/MAX9175 require external input and out-
put termination resistors. For LVDS, connect an input
8
_______________________________________________________________________________________
670MHz LVDS-to-LVDS and Anything-to-LVDS
1:2 Splitters
OUT_+
5kΩ
OUT_+
R /2
L
1.25V
1.25V
IN+
IN-
IN+
IN-
1.20V
1.25V
1.20V
1.25V
V
OD
V
= 0 TO V
TEST CC
R
L
VOS
1.20V
1.20V
R /2
L
OUT_ -
5kΩ
OUT_ -
Figure 2. V
Test Circuit
OD
Figure 3. V Test Circuit
OS
5kΩ
OUT1+
R
L
OUT1-
5kΩ
5kΩ
C
C
L
L
V
= 0 TO V
CC
TEST
OUT0+
IN+
IN-
PULSE
GENERATOR
R
L
OUT0-
5kΩ
50Ω
50Ω
C
C
L
L
Figure 4. Transition Time, Propagation Delay, and Output-to-Output Skew Test Circuit
The MAX9174/MAX9175 feature an integrated differen-
tial output resistor. This resistor reduces jitter by damp-
ing reflections produced by a mismatch between the
transmission line and termination resistor at the far end
of the interconnect.
IEC 61000-4-2 Level 4
ESD Protection
The IEC 61000-4-2 standard (Figure 9) specifies ESD
tolerance for electronic systems. The IEC 61000-4-2
model specifies a 150pF capacitor that is discharged
into the device through a 330Ω resistor. The MAX9174/
MAX9175 differential inputs and outputs are rated for
IEC 61000-4-2 level 4 ( 8kV Contact Discharge and
15kV Air-Gap Discharge). The Human Body Model
(HBM, Figure 10) specifies a 100pF capacitor that is
discharged into the device through a 1.5kΩ resistor.
IEC 61000-4-2 level 4 discharges higher peak current
and more energy than the HBM due to the lower series
resistance and larger capacitor.
Board Layout
Separate the differential and single-ended signals to
reduce crosstalk. A four-layer printed circuit board with
separate layers for power, ground, differential signals,
and single-ended logic signals is recommended.
Separate the differential signals from the logic signals
with power and ground planes for best results.
_______________________________________________________________________________________
9
670MHz LVDS-to-LVDS and Anything-to-LVDS
1:2 Splitters
IN-
IN+
t
t
PHL
PLH
OUT_-
OUT_+
V
= ((V
+) + (V
))/2
OUT_-
OS
OUT_
80%
0V
20%
80%
0V
V
OD+
V
OD-
20%
(OUT_+) - (OUT_-)
t
t
F
R
Figure 5. Transition Time and Propagation Delay Timing
IN+
IN-
OUT0+
OUT0-
OUT1+
OUT1-
t
SKOO
t
SKOO
Figure 6. Output-to-Output Skew
10 ______________________________________________________________________________________
670MHz LVDS-to-LVDS and Anything-to-LVDS
1:2 Splitters
V
V
+ 1V
CC
CC
PD_
V
0
/2
CC
-1.0V
t
t
PD
PU
V
OH
OUT_+ WHEN V = +50mV
ID
50%
50%
50%
50%
OUT_- WHEN V = -50mV
ID
1.25V
1.25V
OUT_+ WHEN V = -50mV
ID
OUT_- WHEN V = +50mV
ID
V
OL
t
t
PU
PD
Figure 7. Power-Up/Down Delay Waveform
OUT1+
MAX9174
MAX9175
R /2
L
1.25V
1.20V
IN+
IN-
1.25V
R /2
L
OUT1-
OUT0+
1.25V
1.20V
R /2
L
1.25V
R /2
L
OUT0-
PULSE
GENERATOR
50Ω
Figure 8. Power-Up/Down Delay Test Circuit
______________________________________________________________________________________ 11
670MHz LVDS-to-LVDS and Anything-to-LVDS
1:2 Splitters
R
R
R
R
D
1.5kΩ
C
D
C
50Ω TO 100Ω
330Ω
1MΩ
DISCHARGE
RESISTANCE
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
CHARGE-CURRENT-
LIMIT RESISTOR
HIGH-
VOLTAGE
DC
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
C
C
STORAGE
CAPACITOR
s
STORAGE
CAPACITOR
s
100pF
150pF
SOURCE
SOURCE
Figure 9. IEC 61000-4-2 Contact Discharge ESD Test Model
Figure 10. Human Body ESD Test Model
Functional Diagram
Pin Configurations
TOP VIEW
OUT1+
MAX9174
MAX9175
IN+
IN-
1
2
3
4
5
10 OUT1+
IN+
IN-
1
2
3
4
5
10 OUT1+
LVDS
DRIVER 0
9
8
7
6
OUT1-
9
8
7
6
OUT1-
IN+
IN-
MAX9174
MAX9175
OUT1-
OUT0+
MAX9174
MAX9175
GND
PD0
PD1
V
CC
GND
V
CC
DIFFERENTIAL
RECEIVER
OUT0+ PD0
OUT0- PD1
OUT0+
OUT0-
EXPOSED PAD
µMAX
THIN QFN
(LEADS UNDER PACKAGE)
LVDS
DRIVER 1
OUT0-
PD0
PD1
Chip Information
TRANSISTOR COUNT: 693
PROCESS: CMOS
12 ______________________________________________________________________________________
670MHz LVDS-to-LVDS and Anything-to-LVDS
1:2 Splitters
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
e
4X S
10
10
INCHES
DIM MIN
MAX
MILLIMETERS
MIN
-
MAX
1.10
0.15
0.95
3.05
3.00
3.05
3.00
5.05
0.70
A
-
0.043
0.006
0.037
0.120
0.118
0.120
0.118
0.199
A1
A2
D1
D2
E1
E2
H
0.002
0.030
0.116
0.114
0.116
0.114
0.187
0.05
0.75
2.95
2.89
2.95
2.89
4.75
0.40
H
ÿ 0.50 0.1
0.6 0.1
L
0.0157 0.0275
0.037 REF
L1
b
0.940 REF
0.007
0.0106
0.177
0.090
0.270
1
1
e
0.0197 BSC
0.500 BSC
0.6 0.1
c
0.0035 0.0078
0.0196 REF
0.200
BOTTOM VIEW
0.498 REF
S
TOP VIEW
α
0∞
6∞
0∞
6∞
D2
E2
GAGE PLANE
A2
c
A
E1
b
L
α
A1
D1
L1
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0061
I
1
______________________________________________________________________________________ 13
670MHz LVDS-to-LVDS and Anything-to-LVDS
1:2 Splitters
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
L
A
D2
D
A2
PIN 1 ID
1
N
1
C0.35
b
[(N/2)-1] x e
REF.
E
E2
PIN 1
INDEX
AREA
DETAIL A
e
k
A1
C
L
C
L
L
L
e
e
A
DALLAS
SEMICONDUCTOR
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 6, 8 & 10L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY
1
2
21-0137
D
COMMON DIMENSIONS
SYMBOL
MIN.
0.70
2.90
2.90
0.00
0.20
MAX.
A
0.80
3.10
3.10
0.05
0.40
D
E
A1
L
k
0.25 MIN.
0.20 REF.
A2
PACKAGE VARIATIONS
PKG. CODE
T633-1
N
6
D2
E2
e
JEDEC SPEC
b
[(N/2)-1] x e
1.90 REF
1.95 REF
2.00 REF
1.50 0.10 2.30 0.10 0.95 BSC
1.50 0.10 2.30 0.10 0.65 BSC
MO229 / WEEA
MO229 / WEEC
0.40 0.05
0.30 0.05
T833-1
8
T1033-1
10
1.50 0.10 2.30 0.10 0.50 BSC MO229 / WEED-3 0.25 0.05
DALLAS
SEMICONDUCTOR
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 6, 8 & 10L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
2
2
21-0137
D
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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