MAX9217ECM+ [MAXIM]
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer;
| 型号： | MAX9217ECM+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer 驱动 接口集成电路 驱动器 |
| 文件： | 总15页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-±558; Rev 4; 8/09
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
MAX9217
General Description
Features
♦ Proprietary Data Encoding for DC Balance and
The MAX9217 digital video parallel-to-serial converter
serializes 27 bits of parallel data into a serial data stream.
Eighteen bits of video data and 9 bits of control data are
encoded and multiplexed onto the serial interface, reduc-
ing the serial data rate. The data enable input determines
when the video or control data is serialized.
Reduced EMI
♦ Control Data Sent During Video Blanking
♦ Five Control Data Inputs Are Single-Bit-Error
Tolerant
♦ Output Common-Mode Filter Reduces EMI
♦ Greater than 10m STP Cable Drive
♦ Wide 2ꢀ Reference Clock Tolerance
♦ ISO 10605 ESD Protection
The MAX9217 pairs with the MAX9218 deserializer to
form a complete digital video serial link. Interconnect
can be controlled-impedance PCB traces or twisted-pair
cable. Proprietary data encoding reduces EMI and pro-
vides DC balance. DC balance allows AC-coupling,
providing isolation between the transmitting and receiv-
ing ends of the interface. The LVDS output is internally
terminated with 100Ω.
♦ Separate Input Supply Allows Interface to 1.8V to
3.3V Logic
♦ +3.3V Core Supply
ESD tolerance is specified for ISO 10605 with ±10kV
contact discharge and ±±0kV air discharge.
♦ Space-Saving Thin QFN and LQFP Packages
♦ -40°C to +85°C Operating Temperature
The MAX9217 operates from a +±.±V core supply and
features a separate input supply for interfacing to 1.8V
to ±.±V logic levels. This device is available in 48-lead
Thin QFN and LQFP packages and is specified from
-40°C to +85°C.
Ordering Information
PIN-
PACKAGE
PART
TEMP RANGE
MAX9217ECM+
MAX9217ECM/V+
MAX9217ETM+
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
48 LQFP
Applications
48 LQFP
Navigation System Display
In-Vehicle Entertainment System
Video Camera
48 Thin QFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
*EP = Exposed pad.
LCD Displays
Pin Configurations
TOP VIEW
GND 37
38
24 I.C.
V
23 PCLK_IN
22 DE_IN
CC
24
23
I.C
PCLK_IN
37
38
39
40
41
42
43
44
45
46
47
48
GND
RGB_IN0 39
RGB_IN1 40
RGB_IN2 41
RGB_IN3 42
RGB_IN4 43
RGB_IN5 44
RGB_IN6 45
V
CC
21 CNTL_IN8
20 CNTL_IN7
19 CNTL_IN6
18 CNTL_IN5
17 CNTL_IN4
16 CNTL_IN3
22
21
20
19
18
17
16
15
14
13
DE_IN
RGB_IN0
RGB_IN1
RGB_IN2
RGB_IN3
RGB_IN4
RGB_IN5
RGB_IN6
RGB_IN7
RGB_IN8
RGB_IN9
CNTL_IN8
CNTL_IN7
CNTL_IN6
CNTL_IN5
CNTL_IN4
CNTL_IN3
CNTL_IN2
MAX9217
MAX9217
RGB_IN7
RGB_IN8
RGB_IN9
CNTL_IN2
46
47
48
15
14
13
V
CC
GND
V
CC
+
GND
+
LQFP
THIN QFN-EP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
ABSOLUTE MAXIMUM RATINGS
CC_
Any Ground to Any Ground...................................-0.5V to +0.5V
OUT+, OUT- to LVDS GND ...................................-0.5V to +4.0V
OUT+, OUT- Short Circuit to LVDS GND
V
to _GND........................................................-0.5V to +4.0V
ESD Protection
Machine Model (R = 0Ω, C = 200pF)
D
S
All Pins to GND ..............................................................±200V
Human Body Model (R = 1.5kΩ, C = 100pF)
D
S
or V
.............................................................Continuous
All Pins to GND ................................................................±2kV
CCLVDS
OUT+, OUT- Short Through 0.125µF (or smaller),
25V Series Capacitor..........................................-0.5V to +16V
RGB_IN[17:0], CNTL_IN[8:0], DE_IN,
ISO 10605 (R = 2kΩ, C = ±±0pF)
D
S
Contact Discharge (OUT+, OUT-) to GND ....................±10kV
Air Discharge (OUT+, OUT-) to GND ............................±±0kV
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+±00°C
RNG0, RNG1, PCLK_IN,
PWRDWN, CMF to GND......................-0.5V to (V
MAX9217
+ 0.5V)
CCIN
Continuous Power Dissipation (T = +70°C)
A
48-Lead LQFP (derate 21.7mW/°C above +70°C) ....17±9mW
48-Lead Thin QFN (derate ±7mW/°C above +70°C) .296±mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +±.0V to +±.6V, R = 100Ω ±1ꢀ, PWRDWN = high, T = -40°C to +85°C, unless otherwise noted. Typical values are at
CC_
L
A
V
= +±.±V, T = +25°C.) (Notes 1, 2)
CC_
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (RGB_IN[17:0], CNTL_IN[8:0], DE_IN, PCLK_IN, PWRDWN, RNG_)
V
= 1.71V to <±V
0.65V
2
V
V
+ 0.±
CCIN
CCIN
CCIN
CCIN
High-Level Input Voltage
Low-Level Input Voltage
V
V
V
IH
+ 0.±
V
= 1.71V to <±V
-0.±
-0.±
0.±V
CCIN
CCIN
V
I
IL
+0.8
V
V
= -0.±V to (V
+ 0.±V),
IN
CCIN
= 1.71V to ±.6V,
Input Current
-70
+70
-1.5
µA
V
CCIN
IN
PWRDWN = high or low
I = -18mA
CL
Input Clamp Voltage
V
CL
LVDS OUTPUTS (OUT+, OUT-)
Differential Output Voltage
V
Figure 1
Figure 1
Figure 1
Figure 1
250
1.125
-15
±±5
450
20
mV
mV
V
OD
Change in V
Between
OD
ΔV
OD
OS
Complementary Output States
Common-Mode Voltage
V
1.29
1.±75
20
Change in V Between
OS
Complementary Output States
ΔV
mV
mA
mA
OS
Output Short-Circuit Current
I
V
V
or V = 0 or ±.6V
OUT-
±8
+15
15
OS
OUT+
Magnitude of Differential Output
Short-Circuit Current
I
= 0
OD
5.5
OSD
V
V
= 0,
= ±.6V
OUT+
OUT-
PWRDWN = low
or
Output High-Impedance Current
I
-1
+1
µA
OZ
V
V
= ±.6V,
= 0
OUT+
OUT-
V
= 0
CC_
2
_______________________________________________________________________________________
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
MAX9217
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= +±.0V to +±.6V, R = 100Ω ±1ꢀ, PWRDWN = high, T = -40°C to +85°C, unless otherwise noted. Typical values are at
CC_
L
A
V
CC_
= +±.±V, T = +25°C.) (Notes 1, 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
110
15
MAX
147
25
UNITS
Differential Output Resistance
Worst-Case Supply Current
Power-Down Supply Current
R
78
Ω
O
±MHz
R = 100Ω 1ꢀ,
L
5MHz
18
25
C = 5pF,
L
I
continuous 10
transition words,
modulation off
10MHz
20MHz
±5MHz
2±
28
mA
µA
CCW
±±
±9
50
70
I
(Note ±)
50
CCZ
AC ELECTRICAL CHARACTERISTICS
(V
= +±.0V to +±.6V, R = 100Ω ±1ꢀ, C = 5pF, PWRDWN = high, T = -40°C to +85°C, unless otherwise noted. Typical values
CC_
L
L
A
are at V
= +±.±V, T = +25°C.) (Note 4)
CC_
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PCLK_IN TIMING REQUIREMENTS
Clock Period
t
Figure 2
28.57
±
±±±.00
±5
ns
T
Clock Frequency
f
MHz
CLK
Clock Frequency Difference from
Deserializer Reference Clock
Δf
-2
+2
ꢀ
CLK
Clock Duty Cycle
DC
t /t or t
HIGH T
/t Figure 2
LOW T,
±5
50
65
ꢀ
Clock Transition Time
t , t
R
Figure 2
2.5
ns
F
SWITCHING CHARACTERISTICS
20ꢀ to 80ꢀ, V
modulation off, Figure ±
≥ 250mV,
OD
Output Rise Time
Output Fall Time
t
215
206
±50
±50
ps
ps
RISE
80ꢀ to 20ꢀ, V ≥ 250mV,
OD
t
FALL
modulation off, Figure ±
Input Setup Time
Input Hold Time
t
Figure 4
Figure 4
±
±
ns
ns
SET
t
HOLD
±.15 x
±.2 x
t
T
Serializer Delay
t
Figure 5
ns
SD
t
T
16±85 x
PLL Lock Time
t
Figure 6
Figure 7
ns
µs
LOCK
t
T
Power-Down Delay
t
1
PD
_______________________________________________________________________________________
3
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
AC ELECTRICAL CHARACTERISTICS (continued)
(V
are at V
= +±.0V to +±.6V, R = 100Ω ±1ꢀ, C = 5pF, PWRDWN = high, T = -40°C to +85°C, unless otherwise noted. Typical values
CC_
L
L
A
= +±.±V, T = +25°C.) (Note 4)
CC_
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
700Mbps data rate,
CMF open, Figure 8
22
70
Peak-to-Peak Output Offset
Voltage
V
mV
OSp-p
700Mbps data rate,
CMF 0.1µF to ground, Figure 8
12
50
MAX9217
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V , ΔV , and ΔV
.
OS
OD
OD
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T = +25°C.
A
Note 3: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.±V or ≥ V
- 0.±V. PWRDWN is ≤ 0.±V.
CCIN
Note 4: AC parameters are guaranteed by design and characterization and are not production tested. Limits are set at ±6 sigma.
Typical Operating Characteristics
(T = +25°C, V
= +±.±V, R = 100Ω, modulation off, unless otherwise noted.)
A
CC_
L
WORST-CASE PATTERN
SUPPLY CURRENT vs. FREQUENCY
60
50
40
30
20
10
0
3
7
11 15 19 23 27 31 35
FREQUENCY (MHz)
4
_______________________________________________________________________________________
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
MAX9217
Pin Description
PIN
NAME
FUNCTION
1, 1±, ±7
GND
Input Buffer Supply and Digital Supply Ground
Input Buffer Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
2
V
CCIN
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Inputs. Eighteen data bits are loaded
into the input latch on the rising edge of PCLK_IN when DE_IN is high. Internally pulled down to
GND.
±–10,
±9–48
RGB_IN[17:0]
CNTL_IN[8:0]
LVTTL/LVCMOS Control Data Inputs. Control data are latched on the rising edge of PCLK_IN
when DE_IN is low. Internally pulled down to GND.
11, 12, 15–21
14, ±8
Digital Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
V
CC
LVTTL/LVCMOS Data Enable Input. Logic-high selects RGB_IN[17:0] to be latched. Logic-low
selects CNTL_IN[8:0] to be latched. DE_IN must be switching for proper operation. Internally
pulled down to GND.
22
2±
DE_IN
LVTTL/LVCMOS Parallel Clock Input. Latches data and control inputs and provides the PLL
reference clock. Internally pulled down to GND.
PCLK_IN
24, 25
26
I.C.
Internally connected to GND. Connect to GND or leave unconnected.
PLL Supply Ground
PLL GND
PLL Supply Voltage. Bypass to PLL GND with 0.1µF and 0.001µF capacitors in parallel as close
to the device as possible, with the smallest value capacitor closest to the supply pin.
27
28
29
V
CCPLL
PWRDWN
LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.
Common-Mode Filter. Optionally connect a capacitor between CMF and ground to filter
common-mode switching noise.
CMF
±0, ±1
±2
LVDS GND
OUT-
LVDS Supply Ground
Inverting LVDS Serial Data Output
Noninverting LVDS Serial Data Output
±±
OUT+
LVDS Supply Voltage. Bypass to LVDS GND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
±4
±5
V
CCLVDS
RNG1
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table ±. Internally pulled down to GND.
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table ±. Internally pulled down to GND.
±6
—
RNG0
EP
Exposed Pad (Thin QFN Package Only). Connect Thin QFN exposed pad to PCB GND.
_______________________________________________________________________________________
5
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
Functional Diagram
RGB_IN
1
OUT+
OUT-
DC BALANCE/
INPUT LATCH
PAR-TO-SER
ENCODE
0
CNTL_IN
DE_IN
MAX9217
CMF
PCLK_IN
RNG0
PLL
TIMING AND CONTROL
RNG1
MAX9217
PWRDWN
R / 2
L
OUT+
OUT-
V
OD
V
OS
R / 2
L
GND
((OUT+) + (OUT-)) / 2
OUT-
OUT+
V
(-)
V (+)
OS
V
OS
(-)
OS
ΔV = |V (+) - V (-)|
OS
OS
OS
V
OD
(+)
V
= 0V
OD
V
OD
(-)
V
OD
(-)
ΔV = |V (+) - V (-)|
OD
OD
OD
(OUT+) - (OUT-)
Figure 1. LVDS DC Output Load and Parameters
6
_______________________________________________________________________________________
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
MAX9217
t
T
V
IHmin
t
HIGH
PCLK_IN
V
ILmax
t
R
t
F
t
LOW
Figure 2. Parallel Clock Requirements
OUT+
OUT-
R
L
C
L
C
L
80%
80%
20%
20%
(OUT+) - (OUT-)
t
t
FALL
RISE
Figure ±. Output Rise and Fall Times
V
IHmin
PCLK_IN
V
ILmax
t
t
HOLD
SET
RGB_IN[17:0]
CNTL_IN[8:0]
V
V
V
IHmin
IHmin
V
ILmax
ILmax
DE_IN
Figure 4. Synchronous Input Timing
_______________________________________________________________________________________
7
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
EXPANDED TIME SCALE
RGB_IN
N
N + 2
N + 3
N + 4
N + 1
CNTL_IN
PCLK_IN
OUT_
MAX9217
N - 1
N
t
SD
BIT 0
BIT 19
Figure 5. Serializer Delay
V
ILmax
PWRDWN
t
LOCK
V
OD
= 0V
HIGH-Z
(OUT+) - (OUT-)
PCLK_IN
Figure 6. PLL Lock Time
PWRDWN
V
ILmax
t
PD
HIGH-Z
(OUT+) - (OUT-)
PCLK_IN
Figure 7. Power-Down Delay
8
_______________________________________________________________________________________
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
MAX9217
OUT-
OUT+
((OUT+) + (OUT-)) / 2
V
V
OS(P-P)
OS(P-P)
Figure 8. Peak-to-Peak Output Offset Voltage
tains DC balance across the serial cable. Two transition
Detailed Description
words, which contain a unique bit sequence, are insert-
ed at the transition boundaries of video-to-control and
control-to-video phases.
The MAX9217 DC-balanced serializer operates at a
parallel clock frequency of ±MHz to ±5MHz, serializing
18 bits of parallel video data RGB_IN[17:0] when the
data enable input DE_IN is high, or 9 bits of parallel
control data CNTL_IN[8:0] when DE_IN is low. The
RGB video input data are encoded using 2 overhead
bits, EN0 and EN1, resulting in a serial word length of
20 bits (Table 1). Control inputs are mapped to 19 bits
and encoded with 1 overhead bit, EN0, also resulting in
a 20-bit serial word. Encoding reduces EMI and main-
Control data inputs C0 to C4 are mapped to ± bits each
in the serial control word (Table 2). At the deserializer,
2 or ± bits at the same state determine the state of the
recovered bit, providing single bit-error tolerance for
C0 to C4. Control data that may be visible if an error
occurs, such as VSYNC and HSYNC, can be connect-
ed to these inputs. Control data inputs C5 to C8 are
mapped to 1 bit each.
Table 1. Serial Video Phase Word Format
0
1
2
±
4
5
6
7
8
9
10
S8
11
S9
12
1±
14
15
16
17
18
19
EN0 EN1 S0
S1
S2
S±
S4
S5
S6
S7
S10 S11 S12 S1± S14 S15 S16 S17
Bit 0 is the LSB and is serialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols.
Table 2. Serial Control Phase Word Format
0
1
2
±
4
5
6
7
8
9
10
11
12
1±
14
15
16
17
18
19
EN0 C0
C0
C0
C1
C1
C1
C2
C2
C2
C±
C±
C±
C4
C4
C4
C5
C6
C7
C8
Bit 0 is the LSB and is serialized first. C[8:0] are the control inputs.
_______________________________________________________________________________________
9
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
TRANSITION
PHASE
TRANSITION
PHASE
CONTROL
PHASE
CONTROL
PHASE
VIDEO PHASE
PCLK_IN
MAX9217
CNTL_IN
DE_IN
RGB_IN
= NOT SAMPLED BY PCLK_IN
Figure 9. Transition Timing
Figure 10 shows an AC-coupled serializer and deserial-
izer with two capacitors per link, and Figure 11 is the
AC-coupled serializer and deserializer with four capaci-
tors per link.
Transition Timing
The transition words require interconnect bandwidth
and displace control data. Therefore, control data is not
sampled (see Figure 9):
• Two clock cycles before DE_IN goes high.
• During the video phase.
Selection of AC-Coupling Capacitors
See Figure 12 for calculating the capacitor values for
AC-coupling, depending on the parallel clock frequen-
cy. The plot shows capacitor values for two- and four-
capacitor-per-link systems. For applications using less
than 18MHz clock frequency, use 0.1µF capacitors.
• Two clock cycles after DE_IN goes low.
The last sampled control data are latched at the deserial-
izer control data outputs during the transition and video
phases. Video data are latched at the deserializer RGB
data outputs during the transition and control phases.
Frequency-Range Setting RNG[1:0]
The RNG[1:0] inputs select the operating frequency
range of the MAX9217 serializer. An external clock with-
in this range is required for operation. Table ± shows
the selectable frequency ranges and corresponding
data rates for the MAX9217.
Applications Information
AC-Coupling Benefits
AC-coupling increases the common-mode voltage to
the voltage rating of the capacitor. Two capacitors are
sufficient for isolation, but four capacitors—two at the
serializer output and two at the deserializer input—pro-
vide protection if either end of the cable is shorted to a
high voltage. AC-coupling blocks low-frequency
ground shifts and common-mode noise. The MAX9217
serializer can also be DC-coupled to the MAX9218
deserializer.
10 ______________________________________________________________________________________
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
MAX9217
V
CC
130Ω
130Ω
82Ω
R/F
OUTEN
RGB_OUT
*
RGB_IN
1
0
1
0
OUT
IN
*
CNTL_OUT
DE_OUT
CNTL_IN
82Ω
CMF
DE_IN
PCLK_OUT
REF_IN
RNG0
RNG1
PLL
PCLK_IN
RNG0
RNG1
TIMING AND
CONTROL
PLL
PWRDWN
LOCK
TIMING AND
CONTROL
PWRDWN
MAX9217
MAX9218
CERAMIC RF SURFACE-MOUNT CAPACITOR
*CAPACITORS CAN BE AT EITHER END.
100Ω DIFFERENTIAL STP CABLE
Figure 10. AC-Coupled Serializer and Deserializer with Two Capacitors per Link
V
CC
130Ω
82Ω
130Ω
R/F
OUTEN
RGB_OUT
RGB_IN
1
0
1
0
IN
OUT
CNTL_OUT
DE_OUT
CNTL_IN
82Ω
CMF
DE_IN
PCLK_OUT
REF_IN
RNG0
RNG1
PLL
PCLK_IN
RNG0
RNG1
TIMING AND
CONTROL
PLL
PWRDWN
LOCK
TIMING AND
CONTROL
PWRDWN
MAX9217
MAX9218
CERAMIC RF SURFACE-MOUNT CAPACITOR
100Ω DIFFERENTIAL STP CABLE
Figure 11. AC-Coupled Serializer and Deserializer with Four Capacitors per Link
______________________________________________________________________________________ 11
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
Table 3. Parallel Clock Frequency Range
Select
AC-COUPLING CAPACITOR VALUE
vs. PARALLEL CLOCK FREQUENCY
PARALLEL
CLOCK (MHz)
SERIAL DATA RATE
(Mbps)
140
125
110
95
RNG1
RNG0
0
0
1
1
0
1
0
1
± to 5
5 to10
60 to 100
100 to 200
200 to 400
400 to 700
FOUR CAPACITORS PER LINK
TWO CAPACITORS PER LINK
10 to 20
20 to ±5
MAX9217
80
65
50
35
OUT+
CMF
20
18
21
24
27
30
33
36
PARALLEL CLOCK FREQUENCY (MHz)
R / 2
O
Figure 12. AC-Coupling Capacitor Values vs. Clock Frequency
of 18MHz to ±5MHz
R / 2
O
C
CMF
OUT-
Termination
The MAX9217 has an integrated 100Ω output-termina-
tion resistor. This resistor damps reflections from
induced noise and mismatches between the transmis-
sion line impedance and termination resistors at the
deserializer input. With PWRDWN = low or with the sup-
ply off, the output termination is switched out and the
LVDS output is high impedance.
Figure 1±. Common-Mode Filter Capacitor Connection
Common-Mode Filter
The integrated 100Ω output termination is made up of
two 50Ω resistors in series. The junction of the resistors
is connected to the CMF pin for connecting an optional
common-mode filter capacitor. Connect the filter
capacitor to ground close to the MAX9217 as shown in
Figure 1±. The capacitor shunts common-mode switch-
ing current to ground to reduce EMI.
12 ______________________________________________________________________________________
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
MAX9217
Power-Down and Power-Off
Power-Supply Circuits and Bypassing
Driving PWRDWN low stops the PLL, switches out the
integrated 100Ω output termination, and puts the output
in high impedance to ground and differentially. With
PWRDWN ≤ 0.±V and all LVTTL/LVCMOS inputs ≤ 0.±V or
The MAX9217 has isolated on-chip power domains. The
digital core supply (V ) and single-ended input supply
CC
(V
CCIN
) are isolated but have a common ground (GND).
The PLL has separate power and ground (V
and
CCPLL
≥ V
- 0.±V, supply current is reduced to 50µA or less.
V
GND) and the LVDS input also has separate
CCIN
CCPLL
power and ground (V
and V
GND). The
CCLVDS
CCLVDS
Driving PWRDWN high starts PLL lock to PCLK_IN and
switches in the 100Ω output termination resistor. The
LVDS output is not driven until the PLL locks. The LVDS
output is high impedance to ground and 100Ω differen-
tial. The 100Ω integrated termination pulls OUT+ and
grounds are isolated by diode connections. Bypass each
, V , V , and V pin with high-frequen-
V
CC CCIN CCPLL
CCLVDS
cy, surface-mount ceramic 0.1µF and 0.001µF capacitors
in parallel as close to the device as possible, with the
smallest value capacitor closest to the supply pin.
OUT- together while the PLL is locking so that V
= 0V.
OD
If V = 0, the output resistor is switched out and the LVDS
CC
LVDS Output
The LVDS output is a current source. The voltage swing
is proportional to the termination resistance. The output
is rated for a differential load of 100Ω ±1ꢀ.
outputs are high impedance to ground and differentially.
PLL Lock Time
The PLL lock time is set by an internal counter. The lock
time is 16,±85 PCLK_IN cycles. Power and clock should
be stable to meet the lock-time specification.
Cables and Connectors
Interconnect for LVDS typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Input Buffer Supply
The single-ended inputs (RGB_IN[17:0], CNTL_IN[8:0],
DE_IN, RNG0, RNG1, PCLK_IN, and PWRDWN) are
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
powered from V
. V
can be connected to a
CCIN
CCIN
1.71V to ±.6V supply, allowing logic inputs with a nomi-
nal swing of V
. If no power is applied to V
CCIN
CCIN
when power is applied to V , the inputs are disabled
CC
and PWRDWN is internally driven low, putting the
device in the power-down state.
______________________________________________________________________________________ 13
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
specifies ESD tolerance for electronic systems. The
Board Layout
Separate the LVTTL/LVCMOS inputs and LVDS output to
prevent crosstalk. A four-layer PCB with separate layers
for power, ground, and signals is recommended.
Human Body Model, Machine Model, discharge com-
ponents are C = 100pF and R = 1.5kΩ (Figure 14).
S
D
The ISO 10605 discharge components are C = ±±0pF
S
and R = 2kΩ (Figure 15). The Machine Model dis-
D
ESD Protection
The MAX9217 ESD tolerance is rated for Human Body
Model, Machine Model, and ISO 10605. ISO 10605
charge components are C = 200pF and R = 0Ω
S
D
(Figure 16).
MAX9217
R
0Ω
D
R
D
1MΩ
1.5kΩ
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
DEVICE
UNDER
TEST
S
STORAGE
CAPACITOR
C
S
STORAGE
CAPACITOR
200pF
100pF
SOURCE
SOURCE
Figure 14. Human Body ESD Test Circuit
Figure 16. Machine Model ESD Test Circuit
R
D
50Ω TO 100Ω
2kΩ
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
330pF
SOURCE
Figure 15. ISO 10605 Contact-Discharge ESD Test Circuit
Package Information
Chip Information
For the latest package outline information and land patterns, go
PROCESS: CMOS
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
48 LQFP
48 TQFN
C48+5
21-0054
21-0141
T4866+1
14 ______________________________________________________________________________________
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
MAX9217
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
Corrected LQFP package, removed MOD function pins, added Machine Model
ESD, and corrected diagrams
±
4
5/08
1, 2, 5, 6, 10–15
1
8/09
Added automotive qualified part to Ordering Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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