MAX9217EVKIT_技术文档

19-4939; Rev 0; 9/09

MAX9217/MAX9218 Evaluation Kit

General Description

Features

The MAX9217/MAX9218 evaluation kit (EV kit) provides a

proven design to evaluate the MAX9217 27-bit, 3MHz to

35MHz DC-balanced LVDS serializer and the MAX9218

27-bit, 3MHz to 35MHz DC-balanced LVDS deserializer.

The MAX9217 serializes 27 bits of parallel input data, 18

bits of video, and 9 bits of control to a serial data stream.

The MAX9218 deserializes the LVDS serial input, which

converts to 18 bits of parallel video data and 9 bits of

parallel control data.

Sꢀ 27-Bit_Parallel_Interface

Sꢀ Rosenberger_Connector_(Cable_Included)

Sꢀ Independent_Evaluation_of_the_MAX9217/MAX9218_

Serializer/Deserializer_(SerDes)

Sꢀ Proven_PCB_Layout

Sꢀ Fully_Assembled_and_Tested

TheMAX9217/MAX9218EVkitPCBhasaMAX9217ECM+

and a MAX9218ECM+ installed.

Ordering Information

PART

TYPE

MAX9217EVKIT+

or

EV Kit

MAX9218EVKIT+

+Denotes lead(Pb)-free and RoHS compliant.

Component List

DESIGNATION QTY

DESCRIPTION

DESIGNATION QTY

DESCRIPTION

C1–C15,

0

Not installed, ceramic capacitors

(0603)

LVDS connectors, waterblue

(with EMI/EMC washer)

Rosenberger D4S20D-40ML5-Z

C27–C41

P1, P2

P3, P4

2

10FF Q10%, 16V X5R ceramic

capacitors (0805)

Murata GRM21BR61C106K

C16–C20, C48,

10

SMA vertical-mount connectors

C58–C61

R1, R2, R3, R6,

R7, R9, R10,

R11, R13, R15,

R16, R20–R48

C21, C25, C42,

0

Not installed, resistors (0603)

0.001FF Q10%, 50V X7R ceramic

capacitors (0603)

Murata GRM188R71H102K

C44, C46, C51,

C54, C57, C62,

10

C64

R4, R14

R5, R12

R8, R19

R17, R18

2

82.5I Q5% resistors (0603)

130I Q5% resistors (0603)

49.9I Q1% resistors (0603)

1kI Q1% resistors (0603)

C22, C23, C24,

C26, C43, C45,

0.1FF Q10%, 16V X7R ceramic

capacitors (0603)

Murata GCM188R71C104K

C47, C49, C50,

C52, C53, C55,

C56, C63, C65

15

27-bit deserializer (48 LQFP)

Maxim MAX9218ECM+

U1

U2

1

JU1–JU5

JU6, JU7, JU8

JU9–JU21

5

3

4-pin headers

3-pin headers

2-pin headers

27-bit serializer (48 LQFP)

Maxim MAX9217ECM+

13

Cable assembly (2m)

MD Elektronik PT1482

—

1

16

1

2 x 20 shrouded-plug connec-

tors (0.100in centers)

H1, H2

H3–H9

2

7

Shunts

2 x 10 shrouded-plug connec-

tors (0.100in centers)

PCB: MAX9217/9218

EVALUATION KIT+

_ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ _Maxim Integrated Products_ _ 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

MAX9217/MAX9218 Evaluation Kit

Component Suppliers

SUPPLIER

MD Elektronik GmbH

PHONE

WEBSITE

www.md-elektronik-gmbh.de

www.murata-northamerica.com

www.rosenberger.de

011-49-86-38-604-0

770-436-1300

Murata Electronics North America, Inc.

Rosenberger Hochfrequenztechnik GmbH

011-49-86 84-18-0

Note: Indicate that you are using the MAX9217 and the MAX9218 when contacting these component suppliers.

4) Connect the GND1 and GND2 pads together.

Quick Start

5) Connect the Rosenberger cable from the P1 to the P2

Required Equipment

connector of the EV kit.

• MAX9217/MAX9218 EV kit (cable included)

6) Connect the data generator to the H6–H9 connectors

• Two 3.3V DC power supplies

and set to generate 27-bit parallel data at LVCMOS/

• Digital data generator (e.g., HP/Agilent 16522A)

LVTTL levels. See Table 2 for input bit locations.

• Two low-phase-noise clock generators (e.g., HP/

Agilent 8133A)

7) Connect the first clock generator to the P4 SMA con-

nector and set its output frequency between 3MHz

and 35MHz (see Table 3 for PCLK_IN location).

• Logic analyzer or data-acquisition system (e.g., HP/

Agilent 16500C)

8) Connect the second clock generator to the P3 SMA

connector and set to within Q2% of the MAX9217 seri-

alizer PCLK_IN frequency (see Table 3 for REFCLK

location).

• High-performance oscilloscope (e.g., HP/Agilent

DSO80304B; see the Pseudo-Random Bit Sequence

(PRBS) Mode section)

9) Connect the logic analyzer or data-acquisition system

to connectors H1 and H2, as shown in Table 4.

Procedure

The MAX9217/MAX9218 EV kit is fully assembled and

tested. Follow the steps below to verify board operation.

Caution:_Do_not_turn_on_the_power_supplies_or_signal_

sources_until_all_connections_are_completed.

10) Turn on the power supplies.

11) Enable the clock generators.

12) Enable the data generator.

1) Verify that all jumpers (JU1–JU21) are in their default

positions, as shown in Table 1.

13) Enable the logic analyzer or data-acquisition system

and begin sampling data.

2) Connect the first 3.3V power supply across the

DVCC1 and GND1 pads of the EV kit.

3) Connect the second 3.3V power supply across the

DVCC2 and GND2 pads of the EV kit.

Table_1._MAX9217/MAX9218_EV_Kit_Jumper_Descriptions_(JU1−JU21)

SHUNT_

JUMPER

FUNCTION

DESCRIPTION

POSITION

1-2*

MAX9218 falling latch

edge

Connects the R/F pin of the MAX9218 to GND2 for falling output latch

edge

JU1

MAX9218 latch edge

1-3

Connects the R/F pin of the MAX9218 to header H4-9

MAX9218 rising latch

edge

Connects the R/F pin of the MAX9218 to DVCC2 for rising output latch

edge

1-4

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MAX9217/MAX9218 Evaluation Kit

Table_1._MAX9217/MAX9218_EV_Kit_Jumper_Descriptions_(JU1−JU21)_(continued)

SHUNT_

POSITION

JUMPER

FUNCTION

DESCRIPTION

MAX9218 LVTLL/

LVCMOS range input

Connects the RNG1 pin of the MAX9218 to GND2 for logic 0 (refer to the

MAX9218 IC data sheet to determine the frequency range)

1-2*

MAX9218 LVTLL/

LVCMOS range input

JU2

1-3

1-4

1-2*

1-3

1-4

Connects the RNG1 pin of the MAX9218 to header H4-7

MAX9218 LVTLL/

LVCMOS range input

Connects the RNG1 of the MAX9218 to DVCC2 for logic 1 (refer to the

MAX9218 IC data sheet to determine the frequency range)

MAX9218 LVTLL/

LVCMOS range input

Connects the RNG0 pin of the MAX9218 to GND2 for logic 0 (refer to the

MAX9218 IC data sheet to determine frequency range)

MAX9218 LVTLL/

LVCMOS range input

JU3

Connects the RNG0 pin of the MAX9218 to header H4-5.

MAX9218 LVTLL/

LVCMOS range input

Connects RNG0 pin of the MAX9218 to DVCC2 for logic 1 (refer to the

MAX9218 IC data sheet to determine the frequency range)

MAX9218

power-down

1-2

1-3

Pulls the PWRDWN pin of the MAX9218 to low for shutdown

Connects the PWRDWN pin of the MAX9218 to header H4-3

Pulls the PWRDWN pin of the MAX9218 high for full functionality

MAX9218

power-down

JU4

MAX9218

power-down

1-4*

1-2

MAX9218 output

enable

Connects the OUTEN pin of the MAX9218 to GND2 for disabling the 27-bit

output

MAX9218 output

enable

JU5

JU6

JU7

1-3

Connects the OUTEN pin of the MAX9218 to header H4-1

MAX9218 output

enable

Connects the OUTEN pin of the MAX9218 to DVCC2 for enabling the

27-bit output

1-4*

1-2*

2-3

MAX9217 hardwired

inputs

Connects even pins of headers H5–H9 to DVCC2

Connects even pins of headers H5–H9 to GND2

MAX9217 hardwired

inputs

MAX9217

preemphasis

or MOD1

1-2*

2-3

Connects the I.C. pin (25) of the MAX9217 to DVCC2

MAX9217

preemphasis

or MOD1

Connects the I.C. pin (25) of the MAX9217 to GND2 for enabling PRBS

mode

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MAX9217/MAX9218 Evaluation Kit

Table_1._MAX9217/MAX9218_EV_Kit_Jumper_Descriptions_(JU1−JU21)_(continued)

SHUNT_

POSITION

JUMPER

FUNCTION

DESCRIPTION

MAX9217

MOD0

1-2*

Connects the I.C. pin (24) of the MAX9217 to DVCC

JU8

MAX9217

MOD0

Connects the I.C. pin (24) of the MAX9217 to GND2 for enabling PRBS

mode

2-3

JU9

MAX9217 IN+

MAX9217 IN-

Open*

Used for probing IN+

Used for probing IN-

JU10

JU11

JU12

JU13

MAX9217 REFCLK

MAX9218 OUT-

MAX9218 OUT+

Used for probing REFCLK

Used for probing OUT-

Used for probing OUT+

MAX9217

LVTLL/LVCMOS range

input

Connects the RNG1 pin of the MAX9217 to DVCC1 for logic 1 (refer to the

MAX9217 IC data sheet to determine the frequency range)

1-2*

Open

1-2*

JU14

JU15

MAX9217

LVTLL/LVCMOS range

input

Internally connects the RNG1 pin of the MAX9217 to ground when left

unconnected

MAX9217

LVTLL/LVCMOS range

input

Connects the RNG0 pin of the MAX9217 to DVCC1 for logic 1 (refer to the

MAX9217 IC data sheet to determine the frequency range)

MAX9217

LVTLL/LVCMOS range

input

Internally connects the RNG0 pin of the MAX9217 to ground when left

unconnected

Open

Board-supply

connectivity

Connects DVCC2 to PVCC2. This shunt reduces the number of supplies

required to operate the EV kit.

1-2*

Open

1-2*

JU16

JU17

JU18

JU19

JU20

Board-supply

connectivity

Disconnects DVCC2 from PVCC2. The 2-pin header can be utilized for

supply current measurements.

Board-supply

connectivity

Connects DVCC2 to LVCC2. This shunt reduces the number of supplies

required to operate the EV kit.

Board-supply

connectivity

Disconnects DVCC2 from LVCC2. The 2-pin header can be utilized for

supply current measurements.

Open

1-2*

Board-supply

connectivity

Connects DVCC2 to OVCC. This shunt reduces the number of supplies

required to operate the EV kit.

Board-supply

connectivity

Disconnects DVCC2 from OVCC. The 2-pin header can be utilized for sup-

ply current measurements.

Open

1-2*

Board-supply

connectivity

Connects DVCC1 to IVCC. This shunt reduces the number of supplies

required to operate the EV kit.

Board-supply

connectivity

Disconnects DVCC1 from IVCC. The 2-pin header can be utilized for sup-

ply current measurements.

Open

1-2*

Board-supply

connectivity

Connects DVCC1 to PVCC1. This shunt reduces the number of supplies

required to operate the EV kit.

Board-supply

connectivity

Disconnects DVCC1 from PVCC1. The 2-pin header can be utilized for

supply current measurements.

Open

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MAX9217/MAX9218 Evaluation Kit

Table_1._MAX9217/MAX9218_EV_Kit_Jumper_Descriptions_(JU1−JU21)_(continued)

SHUNT_

POSITION

JUMPER

FUNCTION

DESCRIPTION

Board-supply

connectivity

Connects DVCC1 to LVCC1. This shunt reduces the number of supplies

required to operate the EV kit.

1-2*

JU21

Board-supply

connectivity

Disconnects DVCC1 from LVCC1. The 2-pin header can be utilized for

supply current measurements.

Open

*Default position.

Table_2._Video_and_Control_Data_Inputs

Detailed Description of Hardware

INPUT_SIGNALS

DESIGNATION

DESCRIPTION

Input video bit 0

Input video bit 1

Input video bit 2

Input video bit 3

Input video bit 4

Input video bit 5

Input video bit 6

Input video bit 7

Input video bit 8

Input video bit 9

Input video bit 10

Input video bit 11

Input video bit 12

Input video bit 13

Input video bit 14

Input video bit 15

Input video bit 16

Input video bit 17

Input control bit 0

Input control bit 1

Input control bit 2

Input control bit 3

Input control bit 4

Input control bit 5

Input control bit 6

Input control bit 7

Input control bit 8

The MAX9217/MAX9218 EV kit provides a proven

design to evaluate the MAX9217 27-bit, 3MHz to 35MHz

DC-balanced LVDS serializer and the MAX9218 27-bit,

3MHz to 35MHz DC-balanced LVDS deserializer. The

MAX9217 serializes 27 bits of parallel input data, 18 bits

of video, and 9 bits of control to a serial data stream.

The MAX9218 deserializes the LVDS serial input, which

converts to 18 bits of parallel video data and 9 bits of

parallel control data.

RGB_IN0

H9-1

RGB_IN1

H9-3

RGB_IN2

H9-5

RGB_IN3

H9-7

RGB_IN4

H9-9

RGB_IN5

H9-11

H9-13

H8-1

RGB_IN6

RGB_IN7

Input Signals

The MAX9217 accepts 27-bit parallel data (18 video data

bits and 9 control data bits). The 27-bit pattern is sup-

plied to the EV kit by connecting a data generator to the

four 20-pin headers (H6–H9), or by connecting selected

pins of H6–H9 to high/low LVCMOS/LVTTL states. See

Table 2 for input bit locations designated on H6–H9.

RGB_IN8

H8-3

RGB_IN9

H8-5

RGB_IN10

RGB_IN11

RGB_IN12

RGB_IN13

RGB_IN14

RGB_IN15

RGB_IN16

RGB_IN17

CNTL_IN0

CNTL_IN1

CNTL_IN2

CNTL_IN3

CNTL_IN4

CNTL_IN5

CNTL_IN6

CNTL_IN7

CNTL_IN8

H8-7

H8-9

H8-11

H8-13

H7-1

Data-Enable Input (DE_IN)

The MAX9217 DE_IN pin is accessible through header

H6-13._Driving the pin high selects RGB_IN[17:0] to be

latched. Driving the pin low selects CNTL_IN[8:0] to be

latched.

H7-3

H7-5

H7-7

H7-9

H7-11

H7-13

H6-1

Input and Output Clocks

The MAX9217 parallel input clock (PCLK_IN) is acces-

sible through H5-5 or SMA connector P4 (see Table 3).

Apply a clock frequency to the access points, which

latches data and control inputs and provides the PLL

clock.

H6-3

H6-5

H6-7

The MAX9218 reference clock (REFCLK) input is acces-

sible through H3-5 or SMA connector P3 (see Table 3).

Apply a reference clock to the access point that is within

Q2% of the MAX9217 serializer PCLK_IN frequency.

H6-9

H6-11

Table_3._Input/Output_Clock_Locations

Output Signals

The MAX9218 outputs 27-bit parallel data, 18 video data

bits, and 9 control data bits at LVCMOS/LVTTL levels on

the 40-pin headers (H1 and H2). To sample the 27-bit

SIGNAL

PCLK_IN

REFCLK

DESIGNATION

H5-5 or P4

H3-5 or P3

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MAX9217/MAX9218 Evaluation Kit

pattern, connect a logic analyzer or data-acquisition sys-

tem to H1 and H2. See Table 4 for the output bit locations

on the H1 and H2 headers.

position of JU5 to activate single-ended outputs. Drive

the pin low by placing a shunt in the 1-2 position of JU5

to place the single-ended outputs in high impedance.

Data-Enable Output (DE_OUT)

The MAX9218 DE_OUT pin is accessible through header

H2-21. A high output indicates that RGB_OUT[17:0] are

active and a low output indicates that CNTL_OUT[8:0]

are active.

Rising and Falling Input Latch Edge (R/F)

The MAX9218 has a selectable rising or falling output

latch edge through logic setting on the R/F pin. Drive

the R/F pin low by placing a shunt in the 1-2 position of

jumper JU1 (see Table 1). Drive the R/F pin high by plac-

ing a shunt in the 1-4 position of JU1.

Output Enable (OUTEN)

The MAX9218 OUTEN pin is accessible through jumper

JU5. Drive the pin high by placing a shunt in the 1-4

Frequency Range Setting (RNG1 and RNG0)

The parallel clock frequency range for the MAX9217 can

be configured through jumpers JU14 and JU15. Place a

shunt on JU14 and JU15 to drive RNG1 and RNG0 high,

or leave JU14 and JU15 unconnected to drive RNG1 and

RNG0 low. Refer to the MAX9217 IC data sheet for actual

frequency settings.

Table_4._Video_and_Control_Data_Outputs

OUTPUT_

DESIGNATION

DESCRIPTION

SIGNALS

CNTL_OUT0

CNTL_OUT1

CNTL_OUT2

CNTL_OUT3

CNTL_OUT4

CNTL_OUT5

CNTL_OUT6

CNTL_OUT7

CNTL_OUT8

RGB_OUT0

RGB_OUT1

RGB_OUT2

RGB_OUT3

RGB_OUT4

RGB_OUT5

RGB_OUT6

RGB_OUT7

RGB_OUT8

RGB_OUT9

RGB_OUT10

RGB_OUT11

RGB_OUT12

RGB_OUT13

RGB_OUT14

RGB_OUT15

RGB_OUT16

RGB_OUT17

H2-3

H2-5

Output control bit 0

Output control bit 1

Output control bit 2

Output control bit 3

Output control bit 4

Output control bit 5

Output control bit 6

Output control bit 7

Output control bit 8

Output video bit 0

Output video bit 1

Output video bit 2

Output video bit 3

Output video bit 4

Output video bit 5

Output video bit 6

Output video bit 7

Output video bit 8

Output video bit 9

Output video bit 10

Output video bit 11

Output video bit 12

Output video bit 13

Output video bit 14

Output video bit 15

Output video bit 16

Output video bit 17

The operating frequency range for the MAX9218 can

be configured through jumpers JU2 and JU3. Place a

shunt in the 1-4 position of JU2 and JU3 to drive RNG1

and RNG0 high, or place a shunt in the 1-2 position of

JU2 and JU3 to drive RNG1 and RNG0 low. Refer to the

MAX9218 IC data sheet for actual frequency settings.

H2-7

H2-9

H2-11

H2-13

H2-15

H2-17

H2-19

H2-27

H2-29

H2-31

H1-3

Power-Down (PWRDWN)

The power-down mode in the MAX9217 and MAX9218

puts the outputs in high impedance, stops the PLL, and

reduces supply current to 50FA or less.

The MAX9217 PWRDWN pin is accessible through

header H6-15. Drive the pin high for normal operation

of the MAX9217 or drive the pin low to power down the

MAX9217.

H1-5

The MAX9218 PWRDWN pin is accessible through

jumper JU4 (see Table 1). Drive the pin high by placing

a shunt in the 1-4 position of JU4 for normal operation.

Drive the pin low by placing a shunt in the 1-2 position of

JU4 to power down the MAX9218.

H1-7

H1-9

H1-11

H1-13

H1-15

H1-17

H1-19

H1-21

H1-23

H1-25

H1-27

H1-29

H1-31

Pseudo-Random Bit Sequence (PRBS) Mode

The MAX9217/MAX9218 EV kit offers the user an internal

test mode to quickly check full functionality and verify

the quality of the SerDes link. This mode is called the

pseudo-random bit sequence, or PRBS mode.

The MAX9217 features an on-chip PRBS generator that

can be utilized to generate a pseudo-random bit stream

to evaluate the quality and performance by comparing

the output of the serializer (prior to the link/cable) with the

input of the deserializer (after the link/cable).

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MAX9217/MAX9218 Evaluation Kit

To activate this feature, the MAX9217 must first enter

Power Supplies

The MAX9217 is powered by connecting PVCC1, LVCC1,

IVCC, and DVCC1 to a DC power supply at 3.0V to 3.6V.

The MAX9217 can be configured to reduce wiring to the

supply and ground pads by placing shunts on jumpers

JU19, JU20, and JU21. The MAX9218 is powered by

applying 3.0V to 3.6V to the PVCC2, LVCC2, OVCC,

and DVCC2 pads. The MAX9218 can be configured to

reduce wiring to the supply and ground pads by placing

shunts on jumpers JU16, JU17, and JU18.

power-down mode by driving H6-15 low. Place a shunt

in the 2-3 position of JU7 and JU8. Activate the internal

PRBS mode by applying a negative DC voltage (-1.0V to

-3.0V) to the VNEG pad.

To monitor the SerDes signal integrity, connect one

channel of the digital oscilloscope with differential probe

capabilities to OUT+ and OUT- signal lines from jumpers

JU12 and JU13 (MAX9217). Repeat the same test for

the deserializer (MAX9218) on signal lines IN+ and IN-,

accessible through jumpers JU9 and JU10.

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ_ _ 7

MAX9217/MAX9218 Evaluation Kit

V C C O G N D

V C C O

D E _ O U T

3 7

3 8

3 9

4 0

4 1

4 2

4 3

4 4

4 5

4 6

4 7

4 8

2 4

C N T L _ O U T 8

2 3

R G B _ O U T 8

R G B _ O U T 9

R G B _ O U T 1 0

R G B _ O U T 1 1

R G B _ O U T 1 2

R G B _ O U T 1 3

R G B _ O U T 1 4

R G B _ O U T 1 5

R G B _ O U T 1 6

R G B _ O U T 1 7

C N T L _ O U T 7

2 2

C N T L _ O U T 6

2 1

C N T L _ O U T 5

2 0

C N T L _ O U T 4

1 9

C N T L _ O U T 3

1 8

C N T L _ O U T 2

1 7

C N T L _ O U T 1

1 6

C N T L _ O U T 0

1 5

O U T E N

1 4

P W R D W N

1 3

O V C C

P V C C 2

L V C C 2

D V C C 2

V T E S T

G N D 2

Figure 1a. MAX9217/MAX9218 EV Kit Schematic (Sheet 1 of 2)

8_ _ _ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

MAX9217/MAX9218 Evaluation Kit

V N E G

P V C C 1

L V C C 1

D V C C 1

I V C C

G N D 1

G N D

V C C

I . C .

2 4

3 7

3 8

3 9

4 0

4 1

4 2

4 3

4 4

4 5

4 6

4 7

4 8

P C L K _ I N

2 3

H 9 - 2

H 9 - 4

H 9 - 6

H 9 - 8

H 9 - 1

R G B _ I N 0

R G B _ I N 1

R G B _ I N 2

R G B _ I N 3

R G B _ I N 4

R G B _ I N 5

R G B _ I N 6

R G B _ I N 7

R G B _ I N 8

R G B _ I N 9

D E _ I N

2 2

H 9 - 3

C N T L _ I N 8

2 1

H 9 - 5

C N T L _ I N 7

2 0

H 9 - 7

C N T L _ I N 6

1 9

H 9 - 1 0

H 9 - 9

C N T L _ I N 5

1 8

H 9 - 1 2

H 9 - 1 4

H 9 - 1 6

H 9 - 1 8

H 9 - 2 0

H 9 - 1 1

H 9 - 1 3

H 9 - 1 5

H 9 - 1 7

H 9 - 1 9

C N T L _ I N 4

1 7

C N T L _ I N 3

1 6

C N T L _ I N 2

1 5

V C C

1 4

G N D

1 3

H 8 - 2

H 8 - 1

H 8 - 4

H 8 - 6

H 8 - 8

H 8 - 3

H 8 - 5

H 8 - 7

H 8 - 1 0

H 8 - 9

H 8 - 1 2

H 8 - 1 4

H 8 - 1 6

H 8 - 1 8

H 8 - 2 0

H 8 - 1 1

H 8 - 1 3

H 8 - 1 5

H 8 - 1 7

H 8 - 1 9

H 7 - 2

H 7 - 1

H 7 - 4

H 7 - 6

H 7 - 8

H 7 - 3

H 7 - 5

H 7 - 7

H 7 - 1 0

H 7 - 9

H 7 - 1 2

H 7 - 1 4

H 7 - 1 6

H 7 - 1 8

H 7 - 2 0

H 7 - 1 1

H 7 - 1 3

H 7 - 1 5

H 7 - 1 7

H 7 - 1 9

H 6 - 2

H 6 - 1

H 6 - 4

H 6 - 6

H 6 - 8

H 6 - 3

H 6 - 5

H 6 - 7

H 6 - 1 0

H 6 - 9

H 6 - 1 2

H 6 - 1 4

H 6 - 1 6

H 6 - 1 8

H 6 - 2 0

H 6 - 1 1

H 6 - 1 3

H 6 - 1 5

H 6 - 1 7

H 6 - 1 9

H 5 - 2

H 5 - 1

H 5 - 4

H 5 - 6

H 5 - 8

H 5 - 3

H 5 - 5

H 5 - 7

H 5 - 1 0

H 5 - 9

H 5 - 1 2

H 5 - 1 4

H 5 - 1 6

H 5 - 1 8

H 5 - 2 0

H 5 - 1 1

H 5 - 1 3

H 5 - 1 5

H 5 - 1 7

H 5 - 1 9

Figure 1b. MAX9217/MAX9218 EV Kit Schematic (Sheet 2 of 2)

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ_ _ 9

MAX9217/MAX9218 Evaluation Kit

Figure 2. MAX9217/MAX9218 EV Kit Component Placement Guide—Component Side

Figure 3. MAX9217/MAX9218 EV Kit PCB Layout—Component Side

10_ _ _ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

MAX9217/MAX9218 Evaluation Kit

Figure 4. MAX9217/MAX9218 EV Kit PCB Layout—Inner Layer 2

Figure 5. MAX9217/MAX9218 EV Kit PCB Layout—Inner Layer 3

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ_ _ 11

MAX9217/MAX9218 Evaluation Kit

Figure 6. MAX9217/MAX9218 EV Kit PCB Layout—Solder Side

Figure 7. MAX9217/MAX9218 EV Kit Component Placement Guide—Solder Side

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.

Maxim reserves the right to change the circuitry and specifications without notice at any time.

12_____________________ ________ Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

©

2009 Maxim Integrated Products

Maxim is a registered trademark of Maxim Integrated Products, Inc.


型号：	MAX9217EVKIT
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Fully Assembled and Tested
文件：	总12页 (文件大小：1437K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX9217EVKIT [MAXIM]

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MAX9218ECM-T

MAX9218ECM/V+GB

MAX9218ECM/V+TGB

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MAX9218ETM-T