MAX9235EVKIT [MAXIM]

Allows Common-Mode Testing;


型号：	MAX9235EVKIT
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Allows Common-Mode Testing
文件：	总5页 (文件大小：151K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

19-4067; Rev 0; 3/08

MAX9235 Evaluation Kit

Evluates:35/MAX9206

General Description

Features

♦ 3.3V Single Supply

The MAX9235 evaluation kit (EV kit) is a fully assembled

and tested printed-circuit board (PCB) that simplifies

the evaluation of the MAX9235 400Mbps, 10-bit LVDS

serializer and the MAX9206 400Mbps, 10-bit LVDS

deserializer. The MAX9235 serializer transforms 10-bit-

wide parallel LVCMOS/LVTTL data into a serial high-

speed, low-voltage differential signaling (LVDS) data

stream. The serializer pairs with a deserializer, the

MAX9206, which receives the serial output and trans-

forms it back to 10-bit-wide parallel LVCMOS/LVTTL

data.

♦ 10-Bit Parallel LVCMOS/LVTTL Interface

♦ Allows Common-Mode Testing

♦ Independent Evaluation of Serializer (MAX9235)

and Deserializer (MAX9206)

♦ Low-Voltage, Low-Power Operation

♦ Fully Assembled and Tested

The EV kit requires a single 3.3V supply and two refer-

ence clock inputs with a 16MHz to 40MHz range to

operate. The 10-bit parallel input data is connected to a

24-pin header and the output data is sampled at a sep-

arate 24-pin header. The EV kit circuit can be modified

to isolate and evaluate the MAX9235 and MAX9206

independently.

Ordering Information

PART

TYPE

MAX9235EVKIT+

EV Kit

+Denotes lead-free and RoHS-compliant.

Component List

DESIGNATION QTY

DESCRIPTION

DESIGNATION QTY

DESCRIPTION

50Ω SMA PC-mount receptacles

2-pin header

10nF 10ꢀ, 50V X5R ceramic

capacitors (0603)

TDK C1608X5R1H103K

J2, J3

C1, C3, C5, C8

C2, C4, C6, C7

JU1–JU4

R1–R4, R7

R5, R6

TP1

3-pin headers

100nF 10ꢀ, 50V X5R ceramic

capacitors (0603)

TDK C1608X5R1H104K

100Ω 1ꢀ resistors (0603)

49.9Ω 1ꢀ resistors (0603)

Test point

10µF 10ꢀ, 6.3V X5R ceramic

capacitor (0805)

10-bit LVDS serializer

TDK C2012X5R0J106K

(16-pin thin QFN-EP*, 3mm x 3mm)

Maxim MAX9235ETE+

470Ω at 100MHz, 1000mA ferrite

beads (0603)

Murata BLM18PG471SH1B

FB1, FB2, FB3

10-bit LVDS deserializer

(28-pin SSOP)

Maxim MAX9206EAI+

J1, J4

2 x 12-pin headers

—

Shunts

*EP = Exposed pad.

PCB: MAX9235 Evaluation Kit+

Component Suppliers

SUPPLIER

Murata Mfg. Co., Ltd.

TDK Corp.

PHONE

WEBSITE

770-436-1300

847-803-6100

www.murata.com

www.component.tdk.com

Note: Indicate that you are using the MAX9235 or MAX9206 when contacting these component suppliers.

________________________________________________________________ Maxim Integrated Products

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

MAX9235 Evaluation Kit

Quick Start

Recommended Equipment

Before beginning, the following equipment is needed:

Detailed Description

The MAX9235 EV kit is a fully assembled and tested

PCB that simplifies the evaluation of the MAX9235

400Mbps, 10-bit LVDS serializer and the MAX9206

400Mbps, 10-bit LVDS deserializer.

• 3.3V DC power supply

• Two clock generators

The serializer/deserializer data transfer starts with the

serializer initially locking onto the reference clock and

then sending the serialized data to the deserializer.

• Data generator for LVCMOS/LVTTL 10-bit parallel

signal input

• Logic analyzer or data-acquisition system or oscillo-

scope

A start-bit high and a stop-bit low frame the 10-bit data

and function as the embedded clock edge in the serial

data stream. The serial rate is the TCLK frequency

times the data and appended bits. For example, if

TCLK is 40MHz, the serial rate is 40 x 12 (10 + 2 bits) =

480Mbps. Since only 10 bits are from input data, the

payload rate is 40 x 10 = 400Mbps.

Procedure

The MAX9235 EV kit is fully assembled and tested.

Follow the steps below to verify board operation.

Caution: Do not turn on the power supply or enable

the clock generators until all connections are

completed.

The serializer output pins (OUT+ and OUT-) are held in

high impedance when V

is first applied and while the

1) Verify that all shunts are in their default positions.

See Table 1 for default shunt positions.

PLL is locking to the local reference clock. If the serial-

izer goes into high impedance, the deserializer loses

PLL lock and needs to reestablish phase lock before

data transfer can resume. This is done by transmitting

all zeros for at least one frame.

2) Connect the 3.3V power supply to the +3.3V pad.

Connect the ground terminal of this supply to the

GND pad.

3) Connect the data generator to 24-pin connector J1

and set it to generate 10-bit parallel data at

LVCMOS/LVTTL levels (high-level input from 2V to

VCC and low-level input from 0.8V to GND). See

Table 2 for input bit locations.

The EV kit requires a single 3.3V supply to operate and

two reference clock inputs in the 16MHz to 40MHz

range. The 10-bit parallel input data can be supplied to

24-pin header J1 with a data generator running at the

same frequency as the reference clock, or the bits can

be configured by manually installing shunts across

header J1 pins. The output 10-bit parallel data can be

sampled or individually tested at 24-pin header J4.

4) Connect the first clock generator to SMA connector

J2 and set it for an output with a frequency of

16MHz to 40MHz. Use LVCMOS/LVTTL levels. Note

that the TCLK SMA connector is terminated with

two parallel-connected 100Ω resistors.

Evluates:35/MAX9206

The first reference clock is for the serializer PLL reference.

The second reference clock is for the deserializer PLL ref-

erence. The tolerance between the two references should

not be larger than 1ꢀ. They can share a clock signal by a

splitter. In real applications, the serializer and deserializer

references may connect to a single system clock.

5) Connect the second clock generator to SMA con-

nector J3 and set it for the same frequency as the

first clock generator. The frequency tolerance

between the two clocks should not be larger than

1ꢀ. Note that the REFCLK SMA connector is termi-

nated with two parallel-connected 100Ω resistors.

Input Signal

The MAX9235 EV kit accepts 10-bit parallel data at

6) Set the logic analyzer or data-acquisition system for

LVCMOS/LVTTL level signal input.

LVCMOS/LVTTL levels (high-level input from 2V to V

and low-level input from 0.8V to GND). The 10-bit pat-

tern can be supplied to the EV kit by connecting a data

generator to 24-pin header J1 or by connecting select-

ed J1 pins to a high/low LVCMOS/LVTTL state. See

Table 2 for input bit locations on 24-pin header J1.

7) Connect the logic analyzer or data-acquisition sys-

tem or oscilloscope to the signal output 24-pin con-

nector J4. See Table 2 for output bit locations.

8) Turn on the power supply.

9) Enable the first clock generator.

10) Enable the second clock generator.

11) Enable the data generator.

Output Signal

The MAX9235 EV kit outputs 10-bit parallel data at

LVCMOS/LVTTL levels on 24-pin header J4. To sample

the 10-bit pattern, connect a logic analyzer or data-

acquisition system to J4. See Table 2 for the output bit

locations on 24-pin header J4.

12) Enable the logic analyzer or data-acquisition sys-

tem and begin sampling data.

_______________________________________________________________________________________

MAX9235 Evaluation Kit

Evluates:35/MAX9206

MAX9235 Reference Clock TCLK

The MAX9235 EV kit allows the MAX9235 to accept an

input clock from either a data generator/logic analyzer

or an input clock from an individual function generator

by changing jumper JU1. The TCLK input clock is 50Ω

terminated on the EV kit by two parallel-connected

100Ω resistors. See Table 1 for TCLK input selections.

Jumper Settings

The MAX9235 EV kit circuit contains four jumpers that

allow the user to put the serializer and deserializer into

several operational modes. See Table 1 for jumper set-

tings and EV kit operation descriptions.

Table 1. EV Kit Jumper Settings

SHUNT

POSITION

JUMPER

DESCRIPTION

1-2

2-3*

1-2*

2-3

TCLK connected to a clock applied on J1-22

TCLK connected to an external clock applied on J2

JU1

JU2

JU3

Deserializer output data on RCLK rising edge

Deserializer output data on RCLK falling edge

Deserializer in normal operation

1-2*

2-3

Deserializer in sleep mode, outputs in high-Z

Deserializer parallel outputs enabled

1-2*

2-3

JU4

Deserializer ROUT0–ROUT9 and RCLK pins in high-Z mode, LOCK pin is still working

*Default position.

Table 2. Input/Output Bit Locations

SIGNAL

Input (J1)

Output (J4)

BIT0

J1-2

J4-1

BIT1

J1-4

J4-3

BIT2

J1-6

J4-5

BIT3

J1-8

J4-7

BIT4

J1-10

J4-9

BIT5

J1-12

J4-11

BIT6

J1-14

J4-13

BIT7

J1-16

J4-15

BIT8

J1-18

J4-17

BIT9

J1-20

J4-19

_______________________________________________________________________________________

MAX9235 Evaluation Kit

Evluates:35/MAX9206

Figure 1. MAX9235 EV Kit Schematic

_______________________________________________________________________________________

MAX9235 Evaluation Kit

Evluates:35/MAX9206

Figure 2. MAX9235 EV Kit Component Placement Guide—

Component Side

Figure 3. MAX9235 EV Kit PCB Layout—Component Side

Figure 4. MAX9235 EV Kit PCB Layout—Solder Side

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 5

is a registered trademark of Maxim Integrated Products, Inc.

MAX9235EVKIT [MAXIM]

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