MAX9250GCM+T [MAXIM]
Line Receiver, CMOS, PQFP48,;
| 型号： | MAX9250GCM+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Line Receiver, CMOS, PQFP48, |
| 文件： | 总20页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3943; Rev 3; 4/09
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
48/MAX9250
General Description
Features
The MAX9248/MAX9250 digital video serial-to-parallel
converters deserialize a total of 27 bits during data and
control phases. In the data phase, the LVDS serial input is
converted to 18 bits of parallel video data and in the con-
trol phase, the input is converted to 9 bits of parallel con-
trol data. The separate video and control phases take
advantage of video timing to reduce the serial-data rate.
The MAX9248/MAX9250 pair with the MAX9247 serializer
to form a complete digital video transmission system. For
operating frequencies less than 35MHz, the MAX9248/
MAX9250 can also pair with the MAX9217 serializer.
o Programmable ±±4 or ±ꢀ4 %ꢁreaꢂꢃ%ꢁepꢄrtm
Otꢄꢁtꢄ for Reꢂtpeꢂ EMI (MAX9ꢀ±8)
o Proꢁrieꢄary Daꢄa Depoꢂing for DC Balanpe anꢂ
Reꢂtpeꢂ EMI
o Conꢄrol Daꢄa Deserializeꢂ Dtring Viꢂeo Blanking
o Five Conꢄrol Daꢄa Inꢁtꢄs are %ingleꢃBiꢄꢃError
Toleranꢄ
o Otꢄꢁtꢄ Transiꢄion Time is %paleꢂ ꢄo Oꢁeraꢄing
Freqtenpy for Reꢂtpeꢂ EMI
o %ꢄaggereꢂ Otꢄꢁtꢄ %wiꢄphing Reꢂtpes EMI
The MAX9248 features spread-spectrum capability,
allowing output data and clock to spread over a speci-
fied frequency range to reduce EMI. The data and
clock outputs are programmable for a spectrum spread
of 4ꢀ or 2ꢀ. The MAX9250 features output enable
input control to allow data busing.
o Otꢄꢁtꢄ Enable Allows Btsing of Otꢄꢁtꢄs
(MAX9ꢀ50)
o Clopk Ptlse %ꢄreꢄph on Lopk
o Wiꢂe ±ꢀ4 Referenpe Clopk Toleranpe
o %ynphronizes ꢄo MAX9ꢀ±7 %erializer Wiꢄhotꢄ
Proprietary data decoding reduces EMI and provides
DC balance. The DC balance allows AC-coupling, pro-
viding isolation between the transmitting and receiving
ends of the interface. The MAX9248/MAX9250 feature a
selectable rising or falling output latch edge.
Exꢄernal Conꢄrol
o I%O 10605 anꢂ IEC 61000ꢃ±ꢃꢀ Level ±
E%D Proꢄepꢄion
o %eꢁaraꢄe Otꢄꢁtꢄ %tꢁꢁly Allows Inꢄerfape ꢄo 1.8V
ꢄo 3.3V Logip
ESD tolerance is specified for ISO 10605 with 10kV
Contact Discharge and 30kV Air-ꢁap Discharge.
o +3.3V Core Power %tꢁꢁly
The MAX9248/MAX9250 operate from a +3.3V 10ꢀ
core supply and feature a separate output supply for
interfacing to 1.8V to 3.3V logic-level inputs. These
devices are available in a 48-lead LQFP package and
are specified from -40°C to +85°C or -40°C to +105°C.
o %ꢁapeꢃ%aving LQFP Papkage
o ꢃ±0°C ꢄo +85°C anꢂ ꢃ±0°C ꢄo +105°C Oꢁeraꢄing
Temꢁeraꢄtre Ranges
Applications
Ordering Information
Navigation System Displays
In-Vehicle Entertainment Systems
Video Cameras
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +105°C
PINꢃPACKAGE
48 LQFP
48 LQFP
48 LQFP
48 LQFP
48 LQFP
48 LQFP
48 LQFP
48 LQFP
MAX9ꢀ±8ECM+
MAX9248ECM/V+
MAX9248ꢁCM+
LCD Displays
MAX9248ꢁCM/V+ -40°C to +105°C
MAX9ꢀ50ECM+
MAX9250ECM/V+
MAX9250ꢁCM+
-40°C to +85°C
-40°C to +85°C
-40°C to +105°C
MAX9250ꢁCM/V+ -40°C to +105°C
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Pin Configtraꢄion aꢁꢁears aꢄ enꢂ of ꢂaꢄa sheeꢄ.
________________________________________________________________ Maxim Inꢄegraꢄeꢂ Proꢂtpꢄs
1
For ꢁriping, ꢂelivery, anꢂ orꢂering informaꢄion, ꢁlease ponꢄapꢄ Maxim Direpꢄ aꢄ 1ꢃ888ꢃ6ꢀ9ꢃ±6±ꢀ,
or visiꢄ Maxim’s websiꢄe aꢄ www.maximꢃip.pom.
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
AB%OLUTE MAXIMUM RATING%
CC_
Any ꢁround to Any ꢁround...................................-0.5V to +0.5V
V
to _ꢁND........................................................-0.5V to +4.0V
ESD Protection
Machine Model (R = 0Ω, C = 200pF)
D
S
IN+, IN- to LVDSꢁND............................................-0.5V to +4.0V
All Pins to ꢁND............................................................ 200V
IN+, IN- Short Circuit to LVDSꢁND or V
........Continuous
Human Body Model (R = 1.5kΩ, C = 100pF)
D
S
CCLVDS
(R/F, OUTEN, RNꢁ_, REFCLK, SS
PWRDWN) to ꢁND................................. -0.5V to (V
All Pins to ꢁND.............................................................. 2kV
+ 0.5V)
ISO 10605 (R = 2kΩ, C = 330pF)
CC
D
S
(RꢁB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT,
LOCK) to V .............................-0.5V to (V + 0.5V)
Contact Discharge (IN+, IN-) to ꢁND ............................ 10kV
Air-ꢁap Discharge (IN+, IN-) to ꢁND ............................ 30kV
IEC 61000-4-2 (R = 330Ω, C = 150pF)
D S
CCOꢁND
CCO
Continuous Power Dissipation (T = +70°C)
A
48-Lead LQFP (derate 21.7mW/°C above +70°C).....1739mW
Contact Discharge (IN+, IN-) to ꢁND ............................ 10kV
Air-ꢁap Discharge (IN+, IN-) to ꢁND ............................ 15kV
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
48/MAX9250
DC ELECTRICAL CHARACTERI%TIC%
CC_
(V
= +3.0V to +3.6V, PWRDWN = high, differential input voltage ⏐V ⏐ = 0.05V to 1.2V, input common-mode voltage V
= ⏐V / 2⏐
CM ID
ID
to V
- ⏐V / 2⏐, T = -40°C to +105°C, unless otherwise noted. Typical values are at V
= +3.3V, ⏐V ⏐ = 0.2V, V
= 1.2V,
CC
ID
A
CC_
ID
CM
T
A
= +25°C.) (Notes 1, 2)
PARAMETER
%YMBOL
CONDITION%
MIN
TYP
MAX
UNIT%
%INGLEꢃENDED INPUT% (R/F, OUTEN, RNG0, RNG1, REFCLK, PWRDWN, %%)
High-Level Input Voltage
Low-Level Input Voltage
V
2.0
V
+ 0.3
CC
V
V
IH
V
-0.3
+0.8
IL
V
= -0.3V to 0 (MAX9248/
IN
MAX9250ECM),
-100
-20
+20
PWRDWN =
high or low
V
= -0.15V to 0 (MAX9248/
IN
Input Current
I
µA
V
IN
MAX9250ꢁCM),
V
= 0 to (V + 0.3V)
+20
-1.5
IN
CC
Input Clamp Voltage
V
I
CL
= -18mA
CL
%INGLEꢃENDED OUTPUT% (RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT, LOCK)
I
I
I
I
I
I
= -100µA
V
V
V
- 0.1
- 0.35
- 0.4
OH
OH
OH
OL
OL
OL
CCO
CCO
CCO
High-Level Output Voltage
Low-Level Output Voltage
V
= -2mA, RNꢁ1 = high
= -2mA, RNꢁ1 = low
= 100µA
V
V
OH
0.1
0.3
V
= 2mA, RNꢁ1 = high
= 2mA, RNꢁ1 = low
OL
0.35
PWRDWN = low or OUTEN = low,
= -0.3V to (V + 0.3V)
High-Impedance Output Current
Output Short-Circuit Current
I
I
-10
+10
µA
OZ
OS
V
O
CCO
RNꢁ1 = high, V = 0
-10
-7
-50
-40
O
mA
RNꢁ1 = low, V = 0
O
ꢀ
_______________________________________________________________________________________
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
48/MAX9250
DC ELECTRICAL CHARACTERI%TIC% (ponꢄinteꢂ)
(V
= +3.0V to +3.6V, PWRDWN = high, differential input voltage ⏐V ⏐ = 0.05V to 1.2V, input common-mode voltage V
= ⏐V / 2⏐
CM ID
CC_
ID
to V
- ⏐V / 2⏐, T = -40°C to +105°C, unless otherwise noted. Typical values are at V
= +3.3V, ⏐V ⏐ = 0.2V, V
= 1.2V,
CC
ID
A
CC_
ID
CM
T
A
= +25°C.) (Notes 1, 2)
PARAMETER
%YMBOL
CONDITION%
MIN
TYP
MAX
UNIT%
LVD% INPUT (IN+, INꢃ)
Differential Input High Threshold
Differential Input Low Threshold
Input Current
V
(Note 3)
(Note 3)
50
mV
mV
µA
TH
V
-50
-40
42
TL
I
I
PWRDWN = high or low (Note 3)
+40
78
IN+, IN-
MAX9248/MAX9250ECM
60
60
PWRDWN =
high or low
MAX9248/MAX9250ꢁCM
42
88
V
=
CC_
MAX9248/MAX9250ECM
42
60
60
78
Input Bias Resistor (Note 3)
R
kΩ
IB
0 or open,
PWRDWN =
0 or open,
Figure 1
MAX9248/MAX9250ꢁCM
42
88
V
= 0 or open,
CC_
Power-Off Input Current
I
I
-60
+60
µA
INO+, INO-
PWRDWN = 0 or open (Note 3)
POWER %UPPLY
2.5MHz
5MHz
19
33
28
49
33
59
45
89
31
48
40
70
49
87
68
100
120
50
RNꢁ1 = low
RNꢁ0 = low
MAX9250
C = 8pF,
L
worst-case
pattern,
Figure 2
5MHz
RNꢁ1 = low
RNꢁ0 = high
10MHz
10MHz
20MHz
20MHz
42MHz
2.5MHz
5MHz
RNꢁ1 = high
RNꢁ0 = low
RNꢁ1 = high
RNꢁ0 = high
Worst-Case Supply Current
mA
RNꢁ1 = low
RNꢁ0 = low
5MHz
RNꢁ1 = low
RNꢁ0 = high
MAX9248
C = 8pF,
L
worst-case
pattern,
Figure 2
10MHz
10MHz
20MHz
20MHz
35MHz
42MHz
RNꢁ1 = high
RNꢁ0 = low
RNꢁ1 = high
RNꢁ0 = high
Power-Down Supply Current
I
(Note 4)
µA
CCZ
_______________________________________________________________________________________
3
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
AC ELECTRICAL CHARACTERI%TIC%
(V
= +3.0V to +3.6V, C = 8pF, PWRDWN = high, differential input voltage ⏐V ⏐ = 0.1V to 1.2V, input common-mode voltage
L ID
CC_
V
CM
V
CM
= ⏐V / 2⏐ to V
- ⏐V / 2⏐, T = -40°C to +105°C, unless otherwise noted. Typical values are at V
= +3.3V, ⏐V ⏐ = 0.2V,
CC_ ID
ID
CC
ID
A
= 1.2V, T = +25°C.) (Notes 3, 5)
A
PARAMETER
%YMBOL
CONDITION%
MIN
TYP
MAX
UNIT%
REFCLK TIMING REQUIREMENT%
MAX9248/MAX9250ECM
MAX9248/MAX9250ꢁCM
MAX9248/MAX9250ECM
MAX9248/MAX9250ꢁCM
REFCLK to serializer PCLK_IN
23.8
28.6
2.5
400.0
400.0
42.0
35.0
+2.0
60
Period
t
ns
T
Frequency
f
MHz
CLK
2.5
Frequency Variation
Duty Cycle
Δf
CLK
-2.0
40
ꢀ
ꢀ
ns
DC
50
Transition Time
t
20ꢀ to 80ꢀ
6
TRAN
%WITCHING CHARACTERI%TIC%
MAX9248/
MAX9250ECM
2.2
2.2
2.8
2.8
1.9
2.3
4.6
4.9
5.2
6.1
4.0
4.3
48/MAX9250
RNꢁ1 = high
MAX9248/
MAX9250ꢁCM
Output Rise Time
t
Figure 3
ns
R
MAX9248/
MAX9250ECM
RNꢁ1 = low
RNꢁ1 = high
RNꢁ1 = low
MAX9248/
MAX9250ꢁCM
MAX9248/
MAX9250ECM
MAX9248/
MAX9250ECM
Output Fall Time
t
Figure 3
ns
R
MAX9248/
MAX9250ꢁCM
2.3
5.2
0.4 x
0.45 x
0.6 x
t
T
PCLK_OUT High Time
PCLK_OUT Low Time
t
Figure 4
Figure 4
ns
ns
HIꢁH
t
T
t
T
0.4 x
0.45 x
0.6 x
t
T
t
LOW
t
T
t
T
Data Valid Before PCLK_OUT
Data Valid After PCLK_OUT
t
Figure 5
Figure 5
0.35 x t
0.35 x t
0.4 x t
0.4 x t
ns
ns
DVB
DVA
T
T
T
T
t
MAX9248, Figure 8
MAX9250, Figure 7
33,600 x t
16,928 x t
T
PLL Lock to REFCLK
t
ns
PLLREF
T
Maximum output
f
f
f
REFCLK REFCLK REFCLK
frequency
+ 3.6ꢀ + 4.0ꢀ + 4.4ꢀ
SS = high,
Figure 11
Minimum output
frequency
f
f
f
REFCLK REFCLK REFCLK
- 4.4ꢀ
- 4.0ꢀ
- 3.6ꢀ
Spread-Spectrum Output
Frequency (MAX9248)
f
MHz
PCLK_OUT
Maximum output
frequency
f
f
f
REFCLK REFCLK REFCLK
+ 1.8ꢀ + 2.0ꢀ + 2.2ꢀ
SS = low,
Figure 11
Minimum output
frequency
f
f
f
REFCLK REFCLK REFCLK
- 2.2ꢀ
- 2.0ꢀ
- 1.8ꢀ
±
_______________________________________________________________________________________
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
48/MAX9250
AC ELECTRICAL CHARACTERI%TIC% (ponꢄinteꢂ)
(V
= +3.0V to +3.6V, C = 8pF, PWRDWN = high, differential input voltage ⏐V ⏐ = 0.1V to 1.2V, input common-mode voltage
L ID
CC_
V
CM
V
CM
= ⏐V / 2⏐ to V
- ⏐V / 2⏐, T = -40°C to +105°C, unless otherwise noted. Typical values are at V
= +3.3V, ⏐V ⏐ = 0.2V,
CC_ ID
ID
CC
ID
A
= 1.2V, T = +25°C.) (Notes 3, 5)
A
PARAMETER
%YMBOL
CONDITION%
MIN
TYP
MAX
UNIT%
Spread-Spectrum Modulation
Frequency
f
/
REFCLK
1024
f
t
Figure 11
kHz
SSM
PDD
Power-Down Delay
SS Change Delay
Figures 7, 8
100
ns
ns
32,800
t
MAX9248, Figure 17
ΔSSPLL
x t
T
Output Enable Time
Output Disable Time
t
t
MAX9250, Figure 8
MAX9250, Figure 9
10
10
30
30
ns
ns
OE
OZ
Noꢄe 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V and V
.
TL
TH
Noꢄe ꢀ: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T = +25°C.
A
Noꢄe 3: Parameters are guaranteed by design and characterization, and are not production tested. Limits are set at 6 sigma.
Noꢄe ±: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ V
- 0.3V. PWRDWN is ≤ 0.3V, REFCLK is static.
CC
Noꢄe 5: C includes probe and test jig capacitance.
L
_______________________________________________________________________________________
5
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
Typical Operating Characteristics
(V _ = +3.3V, C = 8pF, T = +25°C, unless otherwise noted.)
CC
L
A
WORST-CASE PATTERN SUPPLY CURRENT
vs. FREQUENCY
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (V
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (V
)
)
CCO
CCO
6
10
9
70
60
50
40
30
20
10
5
4
3
2
t
t
R
8
R
MAX9248
7
6
5
4
t
F
t
F
3
2
1
MAX9250
1
0
RNG1 = HIGH
RNG1 = LOW
0
0
0
5
10 15 20 25 30 35 40 45
FREQUENCY (MHz)
1.8
2.1
2.4
2.7
3.0
3.3
1.8
2.1
2.4
2.7
3.0
3.3
48/MAX9250
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT POWER SPECTRUM vs. FREQUENCY
(REFCLK = 42MHz, NO SPREAD,
4%, AND 2% SPREAD)
CABLE LENGTH vs. FREQUENCY
BIT-ERROR RATE < 10-9
BIT-ERROR RATE vs. CABLE LENGTH
45
40
35
30
25
20
15
1.00E-14
1.00E-13
1.00E-12
1.00E-11
1.00E-10
0
CAT5 CABLE
RESOLUTION BW = 30kHz
VIDEO BW = 100kHz
NO SPREAD
2% SPREAD
4% SPREAD
-10
-20
-30
-40
-50
-60
-70
REFCLK = 42MHz
840Mbps DATA RATE
FOR CABLE LENGTH < 10m
10
5
-12
BER < 10
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10
12
39
40
41
42
43
44
45
CABLE LENGTH (m)
CAT5 CABLE LENGTH (m)
FREQUENCY (MHz)
6
_______________________________________________________________________________________
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
48/MAX9250
Pin Description
PIN
NAME
R/F
FUNCTION
MAX9ꢀ±8 MAX9ꢀ50
Rising or Falling Latch Edge Select. LVTTL/LVCMOS input. Selects the edge of PCLK_OUT
for latching data into the next chip. Set R/F = high for a rising latch edge. Set R/F = low for a
falling latch edge. Internally pulled down to ꢁND.
1
1
LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel
clock input frequency. Internally pulled down to ꢁND.
2
3
2
3
RNꢁ1
LVDS Supply Voltage. Bypass to LVDSꢁND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
V
CCLVDS
4
5
6
7
4
5
6
7
IN+
IN-
Noninverting LVDS Serial-Data Input
Inverting LVDS Serial-Data Input
LVDS Supply ꢁround
LVDSꢁND
PLLꢁND
PLL Supply ꢁround
PLL Supply Voltage. Bypass to PLLꢁND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible with the smallest value capacitor closest to the supply pin.
8
8
V
CCPLL
LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel
clock input frequency. Internal pulldown to ꢁND.
9
9
RNꢁ0
ꢁND
10
10
Digital Supply ꢁround
Digital Supply Voltage. Supply for LVTTL/LVCMOS inputs and digital circuits. Bypass to
ꢁND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible with
the smallest value capacitor closest to the supply pin.
11
11
V
CC
LVTTL/LVCMOS Reference Clock Input. Apply a reference clock that is within 2ꢀ of the
serializer PCLK_IN frequency. Internally pulled down to ꢁND.
12
13
14
12
13
—
REFCLK
PWRDWN
SS
LVTTL/LVCMOS Power-Down Input. Internally pulled down to ꢁND.
LVTTL/LVCMOS Spread-Spectrum Input. SS selects the frequency spread of PCLK_OUT and
output data relative to PCLK_IN. Drive SS high for 4ꢀ spread and pull low for 2ꢀ spread.
LVTTL/LVCMOS Control Data Outputs. CNTL_OUT[8:0] are latched into the next chip on the
rising or falling edge of PCLK_OUT as selected by R/F when DE_OUT is low, and are held
at the last state when DE_OUT is high.
CNTL_OUT0–
CNTL_OUT8
15–23
15–23
LVTTL/LVCMOS Data-Enable Output. High indicates RꢁB_OUT[17:0] are active. Low
indicates CNTL_OUT[8:0] are active.
24
24
DE_OUT
25, 37
26, 38
25, 37
26, 38
V
Output Supply ꢁround
CCOꢁND
Output Supply Voltage. Bypass to ꢁND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible with the smallest value capacitor closest to the supply pin.
V
CCO
_______________________________________________________________________________________
7
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
Pin Description (continued)
PIN
NAME
FUNCTION
MAX9ꢀ±8 MAX9ꢀ50
27
28
27
28
LOCK
LVTTL/LVCMOS Lock Indicator Output. Outputs are valid when LOCK is low.
PCLK_OUT LVTTL/LVCMOS Parallel Clock Output. Latches data into the next chip on the edge selected by R/F.
RꢁB_OUT0–
RBꢁ_OUT7,
RꢁB_OUT8–
RꢁB_OUT17
LVTTL/LVCMOS Red, ꢁreen, and Blue Digital Video Data Outputs. RꢁB_OUT[17:0] are
latched into the next chip on the edge of PCLK_OUT selected by R/F when DE_OUT is high,
and are held at the last state when DE_OUT is low.
29–36,
39–48
29–36,
39–48
LVTTL/LVCMOS Output Enable Input. High activates the single-ended outputs. Driving
—
14
OUTEN
low places the single-ended outputs in high impedance except LOCK. Internally pulled
down to ꢁND.
48/MAX9250
Functional Diagram
R/F
R/F
OUTEN
IN+
IN-
1
0
IN+
IN-
1
0
RGB_OUT
RGB_OUT
CNTL_OUT
DE_OUT
CNTL_OUT
DE_OUT
PCLK_OUT
PCLK_OUT
REF_IN
REFCLK
PLL
REFCLK
PLL
SSPLL
SS
PWRDWN
LOCK
PWRDWN
LOCK
TIMING AND
CONTROL
TIMING AND
CONTROL
MAX9248
MAX9250
RNG[0:1]
RNG[0:1]
8
_______________________________________________________________________________________
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
48/MAX9250
PCLK_OUT
IN+
R
IB
ODD
RGB_OUT
CNTL_OUT
LVDS
RECEIVER
1.2V
EVEN
RGB_OUT
CNTL_OUT
R
IB
IN-
RISING LATCH EDGE SHOWN (R/F = HIGH).
Figure 1. LVDS Input Bias
Figure 2. Worst-Case Output Pattern
0.9 x V
0.1 x V
CCO
PCLK_OUT
DE_OUT
2.0V
0.8V
t
HIGH
LOCK
PCLK_OUT
CCO
RGB_OUT[17:0]
CNTL_OUT[8:0]
t
R
t
F
t
LOW
Figure 3. Output Rise and Fall Times
Figure 4. High and Low Times
2.0V
PCLK_OUT
0.8V
PCLK_OUT SHOWN FOR R/F = HIGH (RISING LATCH EDGE)
DE_OUT
t
t
DVB
DVA
2.0V
0.8V
2.0V
0.8V
LOCK
RGB_OUT[17:0]
CNTL_OUT[8:0]
Figure 5. Synchronous Output Timing
20 SERIAL BITS
PCLK_OUT SHOWN FOR R/F = HIGH
SERIAL-WORD N
SERIAL-WORD N + 1
IN+, IN-
t
DELAY
PCLK_OUT
CNTL_OUT
RGB_OUT
PARALLEL-WORD N - 1
PARALLEL-WORD N
Figure 6. Deserializer Delay
_______________________________________________________________________________________
9
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
2.0V
0.8V
PWRDWN
REFCLK
TRANSITION
WORD
FOUND
t
PLLREF
t
PDD
RECOVERED CLOCK
HIGH IMPEDANCE
HIGH IMPEDANCE
PCLK_OUT
CLOCK STRETCH
VALID DATA
RGB_OUT
CNTL_OUT
DE_OUT
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
48/MAX9250
LOCK
NOTE: R/F = HIGH
Figure 7. PLL Lock to REFCLK and Power-Down Delay for MAX9250
2.0V
0.8V
PWRDWN
REFCLK
TRANSITION
WORD
FOUND
t
PLLREF
t
288 CLOCK CYCLES
PDD
OUTPUT CLOCK SPREAD
HIGH IMPEDANCE
HIGH IMPEDANCE
PCLK_OUT
OUTPUT DATA SPREAD
VALID DATA
CLOCK STRETCH
RGB_OUT
CNTL_OUT
DE_OUT
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
LOCK
NOTE: R/F = HIGH
Figure 8. PLL Lock to REFCLK and Power-Down Delay for MAX9248
10 ______________________________________________________________________________________
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
48/MAX9250
2.0V
OUTEN
OUTEN
0.8V
MAX9250
MAX9250
t
OE
t
OZ
DE_OUT
DE_OUT
RGB_OUT[17:0]
CNTL_OUT[8:0]
RGB_OUT[17:0]
CNTL_OUT[8:0]
HIGH IMPEDANCE
ACTIVE
ACTIVE
HIGH IMPEDANCE
Figure 9. Output Enable Time
Figure 10. Output Disable Time
FREQUENCY
1 / f
SSM
f
(MAX)
RxCLKOUT
f
TIME
RxCLKIN
f
(MIN)
RxCLKOUT
Figure 11. Simplified Modulation Profile
______________________________________________________________________________________ 11
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
The MAX9247 serializer can also be DC-coupled to the
Detailed Description
MAX9248/MAX9250 deserializers. Figures 12 and 14
show the AC-coupled serializer and deserializer with
two capacitors per link, and Figures 13 and 15 show
the AC-coupled serializer and deserializer with four
capacitors per link.
The MAX9248/MAX9250 DC-balanced deserializers
operate at a 2.5MHz-to-42MHz parallel clock frequen-
cy, deserializing video data to the RꢁB_OUT[17:0] out-
puts when the data-enable output DE_OUT is high, or
control data to the CNTL_OUT[8:0] outputs when
DE_OUT is low. The outputs on the MAX9248 are pro-
grammable for 2ꢀ or 4ꢀ spread relative to the
LVDS input clock frequency, while the MAX9250 has no
spread, but has an output-enable input that allows out-
put busing. The video phase words are decoded using
two overhead bits, EN0 and EN1. Control phase words
are decoded with one overhead bit, EN0. Encoding,
performed by the MAX9247 serializer, reduces EMI and
maintains DC balance across the serial cable. The seri-
al-input word formats are shown in Tables 1 and 2.
Applications Information
Selection of AC-Coupling Capacitors
See Figure 16 for calculating the capacitor values for
AC-coupling depending on the parallel clock frequen-
cy. The plot shows capacitor values for two- and four-
capacitor-per-link systems. For applications using less
than 18MHz clock frequency, use 0.1µF capacitors.
Termination and Input Bias
The IN+ and IN- LVDS inputs are internally connected
to +1.2V through 42kΩ (min) to provide biasing for AC-
coupling (Figure 1). Assuming 100Ω interconnect, the
LVDS input can be terminated with a 100Ω resistor.
Match the termination to the differential impedance of
the interconnect.
Control data inputs C0 to C4, each repeated over three
serial bit times by the serializer, are decoded using
majority voting. Two or three bits at the same state
determine the state of the recovered bit, providing sin-
gle bit-error tolerance for C0 to C4. The state of C5 to
C8 is determined by the level of the bit itself (no voting
is used).
48/MAX9250
Use a Thevenin termination, providing 1.2V bias, on an
AC-coupled link in noisy environments. For intercon-
nect with 100Ω differential impedance, pull each LVDS
AC-Coupling Benefits
AC-coupling increases the input voltage of the LVDS
receiver to the voltage rating of the capacitor. Two
capacitors are sufficient for isolation, but four capaci-
tors—two at the serializer output and two at the deseri-
alizer input—provide protection if either end of the
cable is shorted to a high voltage. AC-coupling blocks
low-frequency ground shifts and common-mode noise.
line up to V
with 130Ω and down to ground with 82Ω
CC
at the deserializer input (Figures 12 and 15). This termi-
nation provides both differential and common-mode
termination. The impedance of the Thevenin termination
should be half the differential impedance of the inter-
connect and provide a bias voltage of 1.2V.
Table 1. %erial Viꢂeo Phase Worꢂ Formaꢄ
0
1
2
3
4
5
6
7
8
9
10
S8
11
S9
12
13
14
15
16
17
18
19
EN0 EN1 S0
S1
S2
S3
S4
S5
S6
S7
S10 S11 S12 S13 S14 S15 S16 S17
Bit 0 is the LSB and is deserialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols.
Table ꢀ. %erial Conꢄrol Phase Worꢂ Formaꢄ
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
EN0 C0
C0
C0
C1
C1
C1
C2
C2
C2
C3
C3
C3
C4
C4
C4
C5
C6
C7
C8
Bit 0 is the LSB and is deserialized first. C[8:0] are the mapped control inputs.
1ꢀ ______________________________________________________________________________________
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
48/MAX9250
V
CC
130Ω
130Ω
82Ω
PRE
R/F
OUTEN
RGB_OUT
*
RGB_IN
1
0
1
0
OUT
IN
*
CNTL_OUT
DE_OUT
CNTL_IN
82Ω
CMF
DE_IN
PCLK_OUT
REF_IN
RNG0
RNG1
PLL
PCLK_IN
RNG0
RNG1
TIMING AND
CONTROL
PLL
PWRDWN
LOCK
TIMING AND
CONTROL
PWRDWN
MAX9247
MAX9250
CERAMIC RF SURFACE-MOUNT CAPACITOR
100Ω DIFFERENTIAL STP CABLE
*CAPACITORS CAN BE AT EITHER END.
Figure 12. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Two Capacitors per Link
V
CC
130Ω
82Ω
130Ω
82Ω
PRE
R/F
OUTEN
RGB_OUT
RGB_IN
1
0
1
0
IN
OUT
CNTL_OUT
DE_OUT
CNTL_IN
CMF
DE_IN
PCLK_OUT
REF_IN
RNG0
RNG1
PLL
PCLK_IN
RNG0
RNG1
TIMING AND
CONTROL
PLL
PWRDWN
LOCK
TIMING AND
CONTROL
PWRDWN
MAX9247
MAX9250
CERAMIC RF SURFACE-MOUNT CAPACITOR
100Ω DIFFERENTIAL STP CABLE
Figure 13. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Four Capacitors per Link
______________________________________________________________________________________ 13
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
V
CC
130Ω
130Ω
R/F
PRE
*
IN+
RGB_IN
1
0
RGB_OUT
1
0
OUT
*
IN-
CNTL_OUT
DE_OUT
CNTL_IN
82Ω
82Ω
CMF
DE_IN
PCLK_OUT
REFCLK
PLL
PCLK_IN
RNG0
RNG1
SSPLL
SS
TIMING AND
CONTROL
PLL
PWRDWN
LOCK
TIMING AND
CONTROL
PWRDWN
MAX9247
MAX9248
48/MAX9250
RNG[0:1]
CERAMIC RF SURFACE-MOUNT CAPACITOR
*CAPACITORS CAN BE AT EITHER END.
100Ω DIFFERENTIAL STP CABLE
Figure 14. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Two Capacitors per Link
V
CC
130Ω
82Ω
130Ω
R/F
PRE
IN+
RGB_IN
1
0
RGB_OUT
1
0
OUT
IN-
CNTL_OUT
DE_OUT
CNTL_IN
82Ω
CMF
DE_IN
PCLK_OUT
REFCLK
PLL
PCLK_IN
RNG0
RNG1
SSPLL
SS
TIMING AND
CONTROL
PLL
PWRDWN
LOCK
TIMING AND
CONTROL
PWRDWN
MAX9247
MAX9248
RNG[0:1]
CERAMIC RF SURFACE-MOUNT CAPACITOR
100Ω DIFFERENTIAL STP CABLE
Figure 15. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Four Capacitors per Link
1± ______________________________________________________________________________________
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
48/MAX9250
Input Frequency Detection
A frequency-detection circuit detects when the LVDS
input is not switching. When not switching, all outputs
except LOCK are low, LOCK is high, and PCLK_OUT
follows REFCLK. This condition occurs, for example, if
the serializer is not driving the interconnect or if the
interconnect is open.
140
120
100
80
FOUR CAPACITORS PER LINK
Frequency Range Setting (RNG[1:0])
The RNꢁ[1:0] inputs select the operating frequency
range of the MAX9248/MAX9250 and the transition time
of the outputs. Select the frequency range that includes
the MAX9247 serializer PCLK_IN frequency. Table 3
shows the selectable frequency ranges and the corre-
sponding data rates and output transition times.
60
40
20
TWO CAPACITORS PER LINK
0
18 21 24 27 30 33 36 39 42
PARALLEL CLOCK FREQUENCY (MHz)
Table 3. Freqtenpy Range Programming
PARALLEL
CLOCK
(MHz)
%ERIALꢃ
DATA RATE TRAN%ITION
OUTPUT
Figure 16. AC-Coupling Capacitor Values vs. Clock Frequency
of 18MHz to 42MHz
RNG1 RNG0
(Mbꢁs)
TIME
When the MAX9248/MAX9250 complete their lock to
REFCLK, the serial input is monitored for a transition
word. When a transition word is found, LOCK output is
driven low, indicating valid output data and the parallel
rate clock recovered from the serial input is output on
PCLK_OUT. The MAX9248 SSPLL waits an additional
288 clock cycles after the transition word is found
before LOCK is driven low and sequence takes effect.
PCLK_OUT is stretched on the change from REFCLK to
recovered clock (or vice versa) at the time when the
transition word is found.
If a transition word is not detected within 222 cycles of
PCLK_OUT, LOCK is driven high, the other outputs
except PCLK_OUT are driven low. REFCLK is output on
PCLK_OUT and the deserializer continues monitoring
the serial input for a transition word. See Figure 7 for
the MAX9250 and Figure 8 for the MAX9248 regarding
the synchronization timing diagram.
0
0
1
1
0
1
0
1
2.5 to 5.0
5 to 10
50 to 100
100 to 200
200 to 400
400 to 840
Slow
10 to 20
20 to 42
Fast
Power Down
Driving PWRDWN low puts the outputs in high imped-
ance and stops the PLL. With PWRDWN ≤ 0.3V and all
LVTTL/LVCMOS inputs ≤ 0.3V or ≥ V
ply current is reduced to less than 50µA. Driving
PWRDWN high initiates lock to the local reference clock
(REFCLK) and afterwards to the serial input.
- 0.3V, the sup-
CC
Lock and Loss-of-Lock (LOCK)
When PWRDWN is driven high, the PLL begins locking
to REFCLK, drives LOCK from high impedance to high
and the other outputs from high impedance to low,
except PCLK_OUT. PCLK_OUT outputs REFCLK while
the PLL is locking to REFCLK. Lock to REFCLK takes a
maximum of 16,928 REFCLK cycles for the MAX9250.
The MAX9248 has an additional spread-spectrum PLL
(SSPLL) that also begins locking to REFCLK. Locking
both PLLs to REFCLK takes a maximum of 33,600 REFCLK
cycles for the MAX9248.
The MAX9248 input-to-output delay can be as low as
(4.5t + 8.0)ns or as high as (36t + 16)ns due to
T
T
spread-spectrum variations (see Figure 6).
The MAX9250 input-to-output delay can be as low as
(3.575t + 8)ns or as high as (3.725t + 16)ns.
T
T
______________________________________________________________________________________ 15
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
Any spread change causes a delay time of 32,000 x t
Spread-Spectrum Selection
The MAX9248 single-ended data and clock outputs are
programmable for a variation of 2ꢀ or 4ꢀ around
the LVDS input clock frequency. The modulation rate of
the frequency variation is 32kHz for a 33MHz LVDS
clock input and scales linearly with the clock frequency
(see Table 4). The output spread is controlled through
the SS input (see Table 5). Driving SS high spreads all
data and clock outputs by 4ꢀ, while pulling low
spreads 2ꢀ.
T
before output data is valid. When the spread amount is
changed from 2ꢀ to 4ꢀ or vice versa, the data out-
puts go low for one t
delay (see Figure 17). The
ΔSSPLL
data outputs stay low, but are not valid when the
spread amount is changed.
Output Enable (OUTEN) and
Busing Outputs
The outputs of two MAX9250s can be bused to form a
2:1 mux with the outputs controlled by the output
enable. Wait 30ns between disabling one deserializer
(driving OUTEN low) and enabling the second one (dri-
ving OUTEN high) to avoid contention of the bused out-
puts. OUTEN controls all outputs except LOCK.
Table ±. Moꢂtlaꢄion Raꢄe
f
f (kHz) = f
M
/ 10ꢀ±
PCLK_IN
PCLK_IN
7.81
8
Rising or Falling Output Latch Edge (R/F)
The MAX9248/MAX9250 have a selectable rising or
falling output latch edge through a logic setting on R/F.
Driving R/F high selects the rising output latch edge,
which latches the parallel output data into the next chip
on the rising edge of PCLK_OUT. Driving R/F low
selects the falling output latch edge, which latches the
parallel output data into the next chip on the falling
edge of PCLK_OUT. The MAX9248/MAX9250 output-
latch-edge polarity does not need to match the
MAX9247 serializer input-latch-edge polarity. Select the
latch-edge polarity required by the chip being driven
by the MAX9248/MAX9250.
10
16
32
40
42
9.77
15.63
31.25
39.06
41.01
48/MAX9250
Table 5. %% Ftnpꢄion
%% INPUT LEVEL
OUTPUT %PREAD
Data and clock output spread 4ꢀ
relative to REFCLK
High
Low
Data and clock output spread 2ꢀ
relative to REFCLK
SS
4% OR 2% SPREAD
4% OR 2% SPREAD
t
(32,800 x t )
T
ΔSSPLL
PCLK_OUT
RGB_OUT[17:0]
CNTL_OUT8:0]
LOW
LOCK
Figure 17. Output Waveforms when Spread Amount is Changed
16 ______________________________________________________________________________________
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
48/MAX9250
CONTROL DATA
VIDEO DATA
CONTROL DATA
PCLK_OUT
CNTL_OUT
DE_OUT
RGB_OUT
PCLK_OUT TIMING SHOWN FOR R/F = HIGH (RISING OUTPUT LATCH EDGE)
= OUTPUT DATA HELD
Figure 18. Output Timing
•
•
Power up the MAX9247 first
Wait for at least t of MAX9247 (or 17100 x t )
Staggered and Transition Time
Adjusted Outputs
RꢁB_OUT[17:0] are grouped into three groups of six, with
each group switching about 1ns apart in the video phase
to reduce EMI and ground bounce. CNTL_OUT[8:0]
switch during the control phase. Output transition times
are slower in the 2.5MHz to 5MHz and 5MHz to 10MHz
ranges and faster in the 10MHz to 20MHz and 20MHz to
42MHz ranges.
LOCK
T
to get activity on the link
•
Power up the MAX9248
Power-Supply Circuits and Bypassing
There are separate on-chip power domains for digital
circuits and LVTTL/LVCMOS inputs (V
ꢁND), outputs (V
supply and
CCOꢁND
CC
supply and V
), PLL
CCO
(V
(V
supply and PLLꢁND), and the LVDS input
supply and LVDSꢁND). The grounds are iso-
CCPLL
CCLVDS
Data-Enable Output (DE_OUT)
The MAX9248/MAX9250 deserialize video and control
data at different times. Control data is deserialized during
the video blanking time. DE_OUT high indicates that
video data is being deserialized and output on
RꢁB_OUT[17:0]. DE_OUT low indicates that control data
is being deserialized and output on CNTL_OUT[8:0].
When outputs are not being updated, the last data
received is latched on the outputs. Figure 18 shows the
DE_OUT timing.
lated by diode connections. Bypass each V , V
,
CC CCO
pin with high-frequency, sur-
V
, and V
CCPLL
CCLVDS
face-mount ceramic 0.1µF and 0.001µF capacitors in
parallel as close to the device as possible, with the
smallest value capacitor closest to the supply pin. The
outputs are powered from V
, which accepts a
CCO
1.71V to 3.6V supply, allowing direct interface to inputs
with 1.8V to 3.3V logic levels.
Cables and Connectors
Interconnect for LVDS typically has a differential
impedance of 100Ω. Use cables and connectors that
have matched differential impedance to minimize
impedance discontinuities.
Power-Supply Sequencing of MAX9247
and MAX9248/MAX9250 Video Link
The MAX9247 and MAX9248/MAX9250 video link can
be powered up in several ways. The best approach is
to keep both MAX9247 and MAX9248 powered down
while supplies are ramping up and PCLK_IN of the
MAX9247 and REFCLK of the MAX9248/MAX9250 are
stabilizing. After all of the power supplies of the
MAX9247 and MAX9248/MAX9250 are stable, including
PCLK_IN and REFCLK, do the following:
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
______________________________________________________________________________________ 17
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
R
R2
D
1MΩ
1.5kΩ
330Ω
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
C
C
S
150pF
S
STORAGE
CAPACITOR
STORAGE
CAPACITOR
100pF
SOURCE
SOURCE
Figure 19. Human Body ESD Test Circuit
Figure 20. IEC 61000-4-2 Contact Discharge ESD Test Circuit
R
2kΩ
D
R
D
0Ω
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
HIGH-
VOLTAGE
DC
48/MAX9250
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
C
S
200pF
C
S
330pF
STORAGE
CAPACITOR
STORAGE
CAPACITOR
SOURCE
SOURCE
Figure 21. ISO 10605 Contact Discharge ESD Test Circuit
Figure 22. Machine Model ESD Test Circuit
Board Layout
Pin Configuration
Separate the LVTTL/LVCMOS outputs and LVDS inputs
to prevent crosstalk. A four-layer PCB with separate lay-
ers for power, ground, and signals is recommended.
TOP VIEW
ESD Protection
The MAX9248/MAX9250 ESD tolerance is rated for
Human Body Model, Machine Model, IEC 61000-4-2 and
ISO 10605. The ISO 10605 and IEC 61000-4-2 standards
specify ESD tolerance for electronic systems. All LVDS
inputs on the MAX9248/MAX9250 meet ISO 10605 ESD
protection at 30kV Air-ꢁap Discharge and 10kV
Contact Discharge and IEC 61000-4-2 ESD protection at
15kV Air-ꢁap Discharge and 10kV Contact
Discharge. All other pins meet the Human Body Model
ESD tolerance of 2kV. The Human Body Model dis-
R/F
1
2
36 RGB_OUT7
35 RGB_OUT6
34 RGB_OUT5
33 RGB_OUT4
32 RGB_OUT3
31 RGB_OUT2
RNG1
V
3
CCLVDS
IN+
4
IN-
5
LVDSGND
PLLGND
6
MAX9248/MAX9250
7
30 RGB_OUT1
29 RGB_OUT0
28 PCLK_OUT
V
8
CCPLL
RNG0
GND
9
LOCK
10
11
12
27
26
25
V
V
CC
CCO
charge components are C = 100pF and R = 1.5kΩ
S
D
REFCLK
V
CCOGND
(Figure 19). The IEC 61000-4-2 discharge components
are C = 150pF and R = 330Ω (see Figure 20). The ISO
S
D
10605 discharge components are C = 330pF and R =
S
D
2kΩ (Figure 21). The Machine Model discharge compo-
nents are C = 200pF and R = 0Ω (Figure 22).
S
D
LQFP
18 ______________________________________________________________________________________
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
48/MAX9250
Package Information
Chip Information
For the latest package outline information and land patterns, go
PROCESS: CMOS
to www.maximꢃip.pom/ꢁapkages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
48 LQFP
C48+3
ꢀ1ꢃ005±
______________________________________________________________________________________ 19
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
Revision History
REVI%ION
NUMBER
REVI%ION
DATE
PAGE%
CHANGED
DE%CRIPTION
Replaced TQFP and TQFN packages with LQFP package, changed temperature
limits for +105°C part, and added Machines Model ESD text and diagram
2
3
5/08
4/09
1–5, 7, 16–19
1, 17
Added /V parts in the Ordering Information table and added new Power-
Supply Sequencing of MAX9247 and MAX9248/MAX9250 Video Link section
48/MAX9250
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
ꢀ0 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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