MAX9258AGCM/V+TGB [MAXIM]
Line Receiver;
| 型号： | MAX9258AGCM/V+TGB |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Line Receiver 接口集成电路 |
| 文件： | 总53页 (文件大小：2966K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5891; Rev 1; 9/11
E V A L U A T I O N K I T A V A I L A B L E
General Description
Features
The MAX9257A serializer pairs with the MAX9258A
deserializer to form a complete digital video serial link.
The devices feature programmable parallel data width,
parallel clock frequency range, spread spectrum, and
preemphasis. An integrated control channel transfers
data bidirectionally at power-up during video blank-
ing over the same differential pair used for video data.
This feature eliminates the need for external CAN or LIN
interface for diagnostics or programming. The clock is
recovered from input serial data at MAX9258A, hence
eliminating the need for an external reference clock.
S 10/12/14/16/18-Bit Programmable Parallel Data
Width
S MAX9258A Does Not Require Reference Clock
S Parity Protection for Video and Control Channels
S Programmable Spread Spectrum
S Programmable Rising or Falling Edge for HSYNC,
VSYNC, and Clock
S Up to 10 Remotely Programmable GPIO on
MAX9257A
S Automatic Resynchronization in Case of Loss of
The MAX9257A serializes 10, 12, 14, 16, and 18 bits
with the addition of two encoding bits for AC-coupling.
The MAX9258A deserializer links with the MAX9257A to
deserialize a maximum of 20 (data + encoding) bits per
pixel/parallel clock period for a maximum serial-data rate
of 840Mbps. The word length can be adjusted to accom-
modate a higher pixel/parallel clock frequency. The pixel
clock can vary from 5MHz to 70MHz, depending on the
serial-word length. Enabling parity adds two parity bits to
the serial word. The encoding bits reduce ISI and allow
AC-coupling.
Lock
S MAX9257A Parallel Clock Jitter Filter PLL with
Bypass
S DC-Balanced Coding Allows AC-Coupling
S Levels of Preemphasis for Up to 20m STP Cable
Drive
S Integrity Test Using On-Chip Programmable PRBS
Generator and Checker
S LVDS I/O Meet ISO 10605 ESD Protection (±10kV
Contact and ±±0kV Air Discharge)
The MAX9258A receives programming instructions from
the electronic control unit (ECU) during the control
channel and transmits to the MAX9257A over the serial
video link. The instructions can program or update the
MAX9257A, MAX9258A, or an external peripheral device,
such as a camera. The MAX9257A communicates with
S LVDS I/O Meet IEC 61000-4-2 ESD Protection
(±8kV Contact and ±20kV Air Discharge)
S LVDS I/O Meet ±200V Machine Model ESD
Protection
S -40NC to +105NC Operating Temperature Range
2
the peripheral device with I C or UART.
S Space-Saving, 40-Pin TQFN (5mm x 5mm) with
The devices operate from a +3.3V core supply and fea-
ture separate supplies for interfacing to +1.8V to +3.3V
logic levels. These devices are available in 40-lead TQFN
or 48-pin LQFP packages. These devices are specified
over the -40NC to +105NC temperature range.
Exposed Pad or 48-Pin LQFP Packages
S ±.±V Core Supply and 1.8V to ±.±V I/O Supply
Applications
Ordering Information appears at end of data sheet.
Automotive Cameras
Typical Operating Circuit and Pin Configurations appear at
end of data sheet.
Industrial Cameras
Navigation Systems Display
In-Vehicle Entertainment Systems
For related parts and recommended products to use with this part,
refer to www.maxim-ic.com/MAX9257A.related.
����������������������������������������������������������������� Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
ABSOLUTE MAXIMUM RATINGS
CC_
Any Ground to Any Ground .................................-0.5V to +0.5V
SDI+, SDI-, SDO+, SDO- to GND........................-0.5V to +4.0V
V
to GND........................................................-0.5V to +4.0V
IEC 61000-4-2 (RD = 330I, CS = 150pF)
Contact Discharge
(SDI+, SDI-, SDO+, SDO-) to GND..............................Q8kV
Air Discharge
SDO+, SDO- Short Circuit to GND or V
.......Continuous
CCLVDS
DIN[0:15], GPIO[0:9], PCLK_IN, HSYNC_IN, VSYNC_IN,
(SDI+, SDI-, SDO+, SDO-) to GND............................Q20kV
ISO 10605 (RD = 2kI, CS = 330pF)
Contact Discharge
(SDI+, SDI-, SDO+, SDO-) to GND............................Q10kV
Air Discharge
(SDI+, SDI-, SDO+, SDO-) to GND............................Q30kV
Machine Model (RD = 0I, CS = 200pF)
SCL/TX, SDA/RX, REM to GND......... -0.5V to (V
DOUT[0:15], PCLK_OUT, CCEN, HSYNC_OUT,
VSYNC_OUT, RX, LOCK, TX, PD,
+ 0.5V)
+ 0.5V)
CCIO
ERROR to GND ..............................-0.5V to (V
Continuous Power Dissipation (TA = +70NC)
40-Lead TQFN
CCOUT
Multilayer PCB (derate 35.7mW/NC above +70NC) ...2857mW
48-Lead LQFP
Multilayer PCB (derate 21.7mW/NC above +70NC) ...1739mW
ESD Protection
Human Body Model (RD = 1.5kI, CS = 100pF)
All Pins to GND ............................................................Q3kV
All Pins to GND ......................................................... Q200V
Storage Temperature Range............................ -65NC to +150NC
Junction Temperature .....................................................+150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
Junction-to-Ambient Thermal Resistance (q
)
Junction-to-Case Thermal Resistance (q
)
JA
JC
40-Pin TQFN................................................................28NC/W
40-Pin TQFN...............................................................1.7NC/W
48-Pin LQFP ................................................................46NC/W
48-Pin LQFP ................................................................10NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
MAX9257A DC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, V
= +1.71V to +3.6V, R = 50IQ1%, T = -40NC to +105NC, unless otherwise noted. Typical values are
CC_
CCIO
L
A
at V
= +3.3V, T = +25NC.) (Notes 2, 3)
CC_
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS
0.65 x
V
V
+
CCIO
0.3
V
V
= +1.71V to +3V
CCIO
V
CCIO
+
+
CCIO
0.3
High-Level Input Voltage
V
= +3V to +3.6V
2
V
IH
CCIO
V
CC
0.3
REM input
2
0
0.3 x
V
V
= +1.71V to +3V
= +3V to +3.6V
CCIO
V
CCIO
0.8
Low-Level Input Voltage
V
V
IL
0
0
CCIO
REM input
0.8
����������������������������������������������������������������� Maxim Integrated Products
2
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
MAX9257A DC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, V
= +1.71V to +3.6V, R = 50IQ1%, T = -40NC to +105NC, unless otherwise noted. Typical values are
CC_
CCIO
L
A
at V
= +3.3V, T = +25NC.) (Notes 2, 3)
CC_
A
PARAMETER
SYMBOL
CONDITIONS
MIN
-20
-20
TYP
MAX UNITS
V
V
= 0 to V
+20
FA
IN
CCIO
Input Current
I
IN
= 0 to V
CC,
REM input
+20
IN
Input Clamp Voltage
V
I
= -18mA
-1.5
V
CL
CL
SINGLE-ENDED OUTPUTS
V
V
-
-
CCIO
0.1
I
I
= -100FA
OH
High-Level Output Voltage
Low-Level Output Voltage
V
V
V
OH
CCIO
0.35
= -2mA
OH
I
I
= 100FA
0.1
0.3
-4
OL
V
OL
= 2mA
OL
V
V
V
V
= +1.71V to +3V
= +3V to +3.6V
= +1.71V to +3V
= +3V to +3.6V
-40
-50
4
CCIO
CCIO
CCIO
CCIO
Shorted to GND
-10
40
Output Short-Circuit Current
I
mA
OS
Shorted to V
CCIO
10
50
2
I C/UART I/O
Input Leakage Current
I
V = V
CCIO
-1
+1
FA
ILKG
I
0.7 x
High-Level Input Voltage SDA/RX
V
V
IH2
V
CCIO
0.3 x
Low-Level Input Voltage SDA/RX
V
V
V
IL2
V
CCIO
Low-Level Output Voltage
SCL, SDA
V
R
= 1.6kI to V
0.4
OL2
PULLUP CCIO
LVDS OUTPUTS (SDO+, SDO-)
Differential Output Voltage
V
250
1.050
-15
350
460
25
mV
mV
V
OD
Change in V
OD
Between
Complementary Output States
DV
OD
Preemphasis off
(Figure 1)
Common-Mode Voltage
V
1.25
1.375
30
OS
Change in V
OS
Between
Complementary Output States
DV
mV
mA
mA
OS
Output Short-Circuit Current
I
V
V
or V = 0 or 3.6V
SDO-
+15
15
OS
SDO+
Magnitude of Differential Output
Short-Circuit Current
I
= 0V
OD
OSD
CONTROL CHANNEL TRANSCEIVER
Differential Output Voltage
V
250
25
350
90
460
165
-165
mV
mV
OD
Differential low-to-high threshold
Differential high-to-low threshold
Input Hysteresis
(Figure 2)
VHYST+
V
-25
-90
HYST-
����������������������������������������������������������������� Maxim Integrated Products
±
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
MAX9257A DC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, V
= +1.71V to +3.6V, R = 50IQ1%, T = -40NC to +105NC, unless otherwise noted. Typical values are
CC_
CCIO
L
A
at V
= +3.3V, T = +25NC.) (Notes 2, 3)
CC_
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
POWER SUPPLY
Q2% spread, preemphasis off,
PRATE = 60MHz, SRATE = 840Mbps
102
101
102
111
113
80
138
130
135
137
139
104
100
111
No spread, preemphasis off,
PRATE = 60MHz, SRATE = 840Mbps
No spread, preemphasis = 20%,
PRATE = 60MHz, SRATE = 840Mbps
No spread, preemphasis = 60%,
PRATE = 60MHz, SRATE = 840Mbps
No spread, preemphasis = 100%,
PRATE = 60MHz, SRATE = 840Mbps
Q2% spread, preemphasis off,
PRATE = 28.57MHz, SRATE = 400Mbps
No spread, preemphasis off,
PRATE = 28.57MHz, SRATE = 400Mbps
79
No spread, preemphasis = 100%,
PRATE = 28.57MHz, SRATE = 400Mbps
88
Worst-Case Supply Current
(Figure 3)
Q2% spread, preemphasis off,
PRATE = 14.29MHz, SRATE = 200Mbps
I
56
74
72
78
59
57
61
45
44
mA
CCW
C = 8pF, 12 bits
L
No spread, preemphasis off,
PRATE = 14.29MHz, SRATE = 200Mbps
55
No spread, preemphasis = 100%,
PRATE = 14.29MHz, SRATE = 200Mbps
61
Q2% spread, preemphasis off,
PRATE = 7.14MHz, SRATE = 100Mbps
45
No spread, preemphasis off,
PRATE = 7.14MHz, SRATE = 100Mbps
44
No spread, preemphasis = 100%,
PRATE = 7.14MHz, SRATE = 100Mbps
47
Q2% spread, preemphasis off,
PRATE = 5MHz, SRATE = 70Mbps
34
No spread, preemphasis off,
PRATE = 5MHz, SRATE = 70Mbps
34
No spread, preemphasis = 100%,
PRATE = 5MHz, SRATE = 70Mbps
36
47
92
Sleep Mode Supply Current
I
Sleep mode
FA
CCS
����������������������������������������������������������������� Maxim Integrated Products
4
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
MAX9257A AC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, V
= +1.71V to +3.6V, R = 50IQ1%, T = -40NC to +105NC, unless otherwise noted. Typical values are
CC_
CCIO
L
A
at V
= +3.3V, T = +25NC.) (Notes 5, 9)
CC_
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PCLK�IN TIMING REQUIREMENTS
Clock Period
t
14.28
5
200.00
ns
MHz
%
T
Clock Frequency
f
1/t
70
65
4
CLK
DC
T
Clock Duty Cycle
t
/t or t
/t
35
50
HIGH T
LOW T
Clock Transition Time
SWITCHING CHARACTERISTICS
LVDS Output Rise Time
LVDS Output Fall Time
t , t
(Figure 7)
ns
R
F
t
20% to 80% (Figure 4)
20% to 80% (Figure 4)
315
315
970
1140
386
370
370
ps
ps
R
t
F
t
, t
642
810
290
0
1390
1420
490
R1A F1A
Control Transceiver Transition
t
, t
20% to 80% (Figure 16)
ps
R2 F2
Time
t
, t
R1B F1B
Input Setup Time
Input Hold Time
t
(Figure 5)
(Figure 5)
ns
ns
S
t
3
H
(4.55 x t
+ 11
T)
t
t
Spread off (Figure 6)
PSD1
PSD2
Parallel-to-Serial Delay
ns
ns
(36.55 x t
+ 11
T)
Q4% spread
32,768
x t
PLL Lock Time
Random Jitter
t
Combined FPLL and SPLL; PCLK_IN stable
LOCK
T
420MHz LVDS output, spread off,
FPLL = bypassed
ps
(RMS)
t
12
RJ
18
2
- 1 PRBS, SRATE = 840Mbps, 18 bits,
Deterministic Jitter
SCL/TX, SDA/RX
Rise Time
t
142
ps (P-P)
DJ
no spread
R
R
= 10kI
= 1.6kI
400
60
0.3 x V
to 0.7 x
, C = 30pF
PULLUP
CCIO
t
ns
ns
RS
V
CCIO
L
PULLUP
Fall Time
t
0.7 x V
to 0.3 x V
CCIO,
C = 30pF
40
FS
CCIO
L
95kbps to 400kbps
100
50
400kbps to 1000kbps
Pulse Width of Spike Suppressed
in SDA
t
ns
SPK
1000kbps to 4250kbps
10
DC to 10Mbps (bypass mode)
400kbps
10
100
60
Data Setup Time
Data Hold Time
t
ns
ns
SETUP
4.25Mbps, C = 10pF
L
400kbps
100
0
t
HOLD
4.25Mbps, C = 10pF
L
����������������������������������������������������������������� Maxim Integrated Products
5
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
MAX9257A AC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, V
= +1.71V to +3.6V, R = 50IQ1%, T = -40NC to +105NC, unless otherwise noted. Typical values are
CC_
CCIO
L
A
at V
= +3.3V, T = +25NC.) (Notes 5, 9)
CC_
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I2C TIMING (Note 8)
Maximum SCL Clock Frequency
Minimum SCL Clock Frequency
Start Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
f
f
4.25
95
MHz
kHz
Fs
SCL
SCL
t
t
(Figure 30)
(Figure 30)
(Figure 30)
0.6
1.1
0.6
HD:STA
t
Fs
LOW
t
Fs
HIGH
Repeated START Condition
Setup Time
(Figure 30)
0.5
Fs
SU:STA
Data Hold Time
t
(Figure 30)
(Figure 30)
(Figure 30)
(Figure 30)
0
0.9
Fs
ns
Fs
Fs
HD:DAT
Data Setup Time
t
t
100
0.5
1.1
SU:DAT
Setup Time for STOP Condition
Bus Free Time
SU:STO
t
BUF
MAX9258A DC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, V
= +1.71V to +3.6V, R = 50I Q1%, differential input voltage |V | = 0.05V to 1.2V, input common-
CC_
CCIO L ID
mode voltage V
= |V /2| to V
- |V /2|, T = -40NC to +105NC, unless otherwise noted. Typical values are at V
= +3.3V, |V
|
CM
ID
CC
ID
A
CC_
ID
= 0.2V, V
= 1.2V, T = +25NC) (Notes 2, 3)
CM
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS
0.65 x
V
V
CCOUT
+ 0.3
V
V
= +1.71V to +3V
CCOUT
V
CCOUT
High-Level Input Voltage
V
V
V
IH
CCOUT
+ 0.3
= +3V to +3.6V
2.0
CCOUT
0.3 x
V
V
V
= +1.71V to +3V
= +3V to +3.6V
0
CCOUT
V
Low-Level Input Voltage
V
CCOUT
0.8
IL
0
CCOUT
TXIN
-60
-20
+60
+20
-1.5
Input Current
I
= 0 to V
FA
IN
IN
CCOUT
PD
Input Clamp Voltage
V
I
= -18mA
V
CL
CL
����������������������������������������������������������������� Maxim Integrated Products
6
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
MAX9258A DC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, V
= +1.71V to +3.6V, R = 50I Q1%, differential input voltage |V | = 0.05V to 1.2V, input common-
CC_
CCIO L ID
mode voltage V
= |V /2| to V
- |V /2|, T = -40NC to +105NC, unless otherwise noted. Typical values are at V
= +3.3V, |V
|
CM
ID
CC
ID
A
CC_
ID
= 0.2V, V
= 1.2V, T = +25NC) (Notes 2, 3)
CM
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED OUTPUTS
V
V
CCOUT
- 0.1
I
I
= -100FA
OH
High-Level Output Voltage
V
V
OH
CCOUT
-0.35
= -2mA
OH
I
I
= 100FA
0.1
0.3
OL
Low-Level Output Voltage
V
I
V
OL
= 2mA
OL
High-Impedance Output Current
-1
-4
+1
FA
PD = low, V = 0 to V
OZ
O
CCOUT
V
V
V
V
= +1.71V to +3V
-44
-65
-55.1
-80
V
= 0V
CCOUT
CCOUT
CCOUT
CCOUT
O
(Note 4)
= +3V to +3.6V
= +1.71V to +3.6V
= +3V to +3.6V
-16
-5
Output Short-Circuit Current
I
mA
OS
PCLK_OUT,
V
= 0V
-22
O
OPEN-DRAIN OUTPUTS
V
V
V
= +3V, I = 6.4mA
0.55
0.3
1
CCOUT
OL
Output Low Voltage
V
V
OL
= +1.71V, I = 1.95mA
OL
CCOUT
Leakage Current
I
= 0V or V
FA
LEAK
O
CCOUT
LVDS INPUTS (SDI+, SDI-)
Differential Input High Threshold
Differential Input Low Threshold
Input Current
V
50
mV
mV
FA
FA
TH
V
-50
-60
-70
TL
I
I
+60
+70
IN+, IN-
Power-Off Input Current
I
I
V
= 0 or open
INO+, INO- CC_
ACTOFFSET = 00
ACTOFFSET = 01
ACTOFFSET = 10
ACTOFFSET = 11
23
11
59
75
Activity-Detector Input Offset
V
mV
OFFSET
CONTROL CHANNEL TRANSCEIVER
Differential Output Voltage
V
250
25
460
165
-165
mV
mV
OD
V
Differential low-to-high threshold
Differential high-to-low threshold
90
Input Hysteresis
(Figure 2)
HYST+
V
-25
-90
HYST-
����������������������������������������������������������������� Maxim Integrated Products
7
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
MAX9258A DC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, V
= +1.71V to +3.6V, R = 50I Q1%, differential input voltage |V | = 0.05V to 1.2V, input common-
CC_
CCIO L ID
mode voltage V
= |V /2| to V
- |V /2|, T = -40NC to +105NC, unless otherwise noted. Typical values are at V
= +3.3V, |V |
CC_ ID
CM
ID
CC
ID
A
= 0.2V, V
= 1.2V, T = +25NC) (Notes 2, 3)
CM
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
Q4% spread, PRATE = 60MHz,
SRATE = 840Mbps
95
80
67
57
55
46
42
135
120
102
84
Spread off, PRATE = 60MHz,
SRATE = 840Mbps
Q4% spread, PRATE = 28.57MHz,
SRATE = 400Mbps
Spread off, PRATE = 28.57MHz,
SRATE = 400Mbps
Worst-Case Supply Current
C = 8pF, 12 bits
I
mA
L
CCW
Q4% spread, PRATE = 14.29MHz,
SRATE = 200Mbps
(Figure 8)
82
Spread off, PRATE = 14.29MHz,
SRATE = 200Mbps
67
Q4% spread, PRATE = 5MHz,
SRATE = 70Mbps
57
Spread off, PRATE = 5MHz,
SRATE = 70Mbps
34
10
49
50
Power-Down Supply Current
I
FA
PD = low
CCZ
MAX9258A AC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, V
= +1.71V to +3.6V, R = 50I Q1%, C = 8pF, differential input voltage |V | = 0.1V to 1.2V, input
CC_
CCIO L L ID
common-mode voltage V
= |V /2| to V
- |VID/2|, T = -40NC to +105NC, unless otherwise noted. Typical values are at V
=
CM
ID
CC
A
CC_
+3.3V, |V | = 0.2V, V
= 1.2V, T = +25NC) (Notes 5, 6 and 7)
ID
CM
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SWITCHING CHARACTERISTICS
Output Transition Time
t
t
t
t
t
(Figure 9)
(Figure 9)
0.7
0.5
1.0
0.7
2.2
1.5
2.8
2.2
ns
ns
ns
ns
R, F
Output Transition Time,
PCLK_OUT
t
R, F
Output Transition Time
t
V
= 1.71V (Figure 9)
= 1.71V (Figure 9)
R, F
CCOUT
CCOUT
Output Transition Time,
PCLK_OUT
t
V
R, F
t
t
t
R1A, F1A,
Control Channel Transition Time
(Figure 16)
0.5
1.2
ns
t
R1B, F1B
Control Channel Transition Time
PCLK_OUT High Time
t
t
(Figure 16)
(Figure 10)
(Figure 10)
0.6
1.3
ns
ns
ns
R2, F2
t
0.4 x t
0.6 x t
HIGH
T
T
T
PCLK_OUT Low Time
t
0.4 x t
0.6 x t
LOW
T
����������������������������������������������������������������� Maxim Integrated Products
8
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
MAX9258A AC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, V
= +1.71V to +3.6V, R = 50I Q1%, C = 8pF, differential input voltage |V | = 0.1V to 1.2V, input
CC_
CCIO L L ID
common-mode voltage V
= |V /2| to V
- |VID/2|, T = -40NC to +105NC, unless otherwise noted. Typical values are at V
=
CC_
CM
ID
CC
A
+3.3V, |V | = 0.2V, V
= 1.2V, T = +25NC) (Notes 5, 6 and 7)
ID
CM
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ns
Data Valid Before PCLK_ OUT
Data Valid After PCLK_OUT
t
t
(Figure 11)
(Figure 11)
0.35 x t
0.35 x t
DVB
DVA
T
ns
T
t
Spread off (Figure 14)
Q4% spread
8t
T
SPD1
SPD2
Serial-to-Parallel Delay
ns
t
40t
T
Power-Up Delay
t
(Figure 12)
100
100
ns
ns
PUD
PDD
Power-Down to High Impedance
t
(Figure 13)
Each half of the UI, 12 bit,
SRATE = 840Mbps, PRBS No spread
pattern (Figure 15)
Jitter Tolerance
t
0.25
0.30
UI
JT
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V and V
.
TL
TH
Note ±: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T = +105NC.
A
Note 4: One output at a time.
Note 5: AC parameters are guaranteed by design and characterization, and are not production tested.
Note 6: C includes probe and test jig capacitance.
L
Note 7: t is the period of the PCLK_OUT.
T
Note 8: For high-speed mode timing, see the Detailed Description section.
2
2
Note 9: I C timing parameters are specified for fast-mode I C. Max data rate = 400kbps.
Typical Operating Characteristics
(V
= +3.3V, R = 50O, C = 8pF, T = +25NC, unless otherwise noted.)
L L A
CC_
MAX9257A SUPPLY CURRENT
vs. FREQUENCY
MAX9257A SUPPLY CURRENT
vs. FREQUENCY
MAX9258A SUPPLY CURRENT
vs. FREQUENCY
120
100
80
60
40
20
0
140
120
100
80
120
100
80
60
40
20
0
PRBS PATTERN
18-BIT
PRBS PATTERN
10-BIT
PRBS PATTERN
18-BIT
100% PREEMPHASIS
4% SPREAD
100% PREEMPHASIS
60
NO SPREAD
NO PREEMPHASIS
NO PREEMPHASIS
40
20
0
5
10 15 20 25 30 35 40 45
PCLK FREQUENCY (MHz)
5
15
25
35
45
55
65
75
5
10 15 20 25 30 35 40 45
PCLK FREQUENCY (MHz)
PCLK FREQUENCY (MHz)
����������������������������������������������������������������� Maxim Integrated Products
9
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
Typical Operating Characteristics (continued)
(V
= +3.3V, R = 50O, C = 8pF, T = +25NC, unless otherwise noted.)
L L A
CC_
SERIAL LINK SWITCHING PATTERN WITH
PREEMPHASIS (BIT RATE = 840MHz, 2m STP CABLE)
(PREEMPHASIS = 100%)
SERIAL LINK SWITCHING PATTERN WITHOUT
PREEMPHASIS (BIT RATE = 840MHz, 2m STP CABLE)
MAX9258A SUPPLY CURRENT
vs. FREQUENCY
120
100
80
60
40
20
0
PRBS PATTERN
10-BIT
4% SPREAD
NO SPREAD
5
10 15 20 25 30 35 40 45
PCLK FREQUENCY (MHz)
MAX9257A OUTPUT POWER
SPECTRUM vs. PCLK FREQUENCY
MAX9257A OUTPUT POWER
SPECTRUM vs. PCLK FREQUENCY
MAX9258A OUTPUT POWER
SPECTRUM vs. PCLK FREQUENCY
20
10
20
20
10kHz BW
NO SPREAD
10kHz BW
NO SPREAD
10kHz BW
4% SPREAD
NO SPREAD
2% SPREAD
0
4% SPREAD
0
0
2% SPREAD
2% SPREAD
-10
-20
-30
1.5% SPREAD
-20
-20
-40
-50
-60
-70
-80
-40
-60
-80
-40
-60
-80
18
19
20
21
22
38
40
42
44
46
38
40
42
44
46
PCLK FREQUENCY (MHz)
PCLK FREQUENCY (MHz)
PCLK FREQUENCY (MHz)
BIT ERROR RATE (< 10-9) vs.
CABLE LENGTH
BIT ERROR RATE (< 10-9) vs.
CABLE LENGTH
900
800
700
900
800
700
NO SPREAD
STP CABLE
2% SPREAD ON
MAX9257, STP CABLE
100% PREEMPHASIS
NO PREEMPHASIS
100% PREEMPHASIS
NO PREEMPHASIS
600
500
400
600
500
400
-12
-12
BER CAN BE AS LOW AS 10 FOR
CABLE LENGTHS LESS THAN 10m.
BER CAN BE AS LOW AS 10 FOR
CABLE LENGTHS LESS THAN 10m.
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
CABLE LENGTH (m)
CABLE LENGTH (m)
���������������������������������������������������������������� Maxim Integrated Products 10
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
Pin Configuration
TOP VIEW
30 29 28 27 26 25 24 23 22 21
N.C. 37
DIN1 38
DIN2 39
24 N.C.
23
22 GND
21
20 SDA/RX
DIN1
DIN2
20
19
18
17
16
15
V
CC
31
32
33
34
V
CC
GND
V
V
CC
CCIO
V
40
V
CC
CCIO
GND
SDA/RX
SCL/TX
PCLK_IN
GND 41
DIN3 42
SCL/TX
19
18
17
16
15
14
13
DIN3 35
DIN4 36
MAX9257A
MAX9257A
DIN4
DIN5
PCLK_IN
VSYNC_IN
HSYNC_IN
DIN15/GPIO7
GND
43
44
45
46
47
48
37
38
39
40
14 VSYNC_IN
DIN5
DIN6
DIN6
HSYNC_IN
13
DIN7
DIN15/GPIO7
12
DIN7
DIN8/GPIO0
N.C.
+
GND
11
DIN8/GPIO0
N.C.
+
1
2
3
4
5
6
7
8
9
10
TQFN-EP
CONNECT EP TO GND
LQFP
N.C. 37
24 N.C.
23 GNDOUT
22
GNDOUT 38
V
39
V
CCOUT
CCOUT
DOUT6 40
DOUT5 41
DOUT4 42
21 DOUT15
20 HSYNC_OUT
19 VSYNC_OUT
MAX9258A
DOUT3
DOUT2
DOUT1
DOUT0
CCEN
PCLK_OUT
LOCK
TX
43
44
45
46
47
48
18
17
16
15
14
13
RX
GND
GNDOUT
N.C.
+
LQFP
���������������������������������������������������������������� Maxim Integrated Products 11
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
MAX9257A Pin Description
PIN
NAME
FUNCTION
TQFN
LQFP
Single-Ended Input/Output Buffer Supply Voltage. Bypass V
CCIO
to GND with 0.1FF and
0.001FF capacitors in parallel as close as possible to the device with the smallest value
capacitor closest to V
1, 18
2, 21
V
CCIO
.
CCIO
2, 11,
19, 34
3, 14,
22, 41
GND
Digital Supply Ground
Data Input/General Purpose Input/Output. When a serial-data word is less than 18 bits word
length, DIN_ not programmed as data inputs becomes GPIO (Table 22). DIN[9:14] are inter-
nally pulled down to ground.
DIN[9:14]/
GPIO[1:6]
3–8
9
4–9
10
GNDFPLL Filter PLL Ground
Filter PLL Supply Voltage. Bypass V
to GNDFPLL with 0.1FF and 0.001FF capacitors
CCFPLL
10
11
V
in parallel as close as possible to the device with the smallest value capacitor closest to
CCFPLL
V
.
CCFPLL
Data Input/General Purpose Input/Output. When a serial-data word is less than 18 bits word
12
15
DIN15/GPIO7 length, DIN_ not programmed as data input becomes GPIO (Table 22). DIN15 is internally
pulled down to ground.
13
14
16
17
HSYNC_IN Horizontal SYNC Input. HSYNC_IN is internally pulled down to ground.
VSYNC_IN Vertical SYNC Input. VSYNC_IN is internally pulled down to ground.
Parallel Clock Input. PCLK_IN latches data and sync inputs and provides the PLL reference
clock. PCLK_IN is internally pulled down to ground.
15
16
18
19
PCLK_IN
2
Open-Drain Control Channel Output. SCL/TX becomes SCL output when UART-to-I C is active.
SCL/TX
2
SCL/TX becomes TX output when UART-to-I C is bypassed. Externally pull up to V
.
CC
Open-Drain Control Channel Input/Output. SDA/RX becomes bidirectional SDA when UART-
2
2
17
20
SDA/RX
to-I C is active. SDA/RX becomes RX input when UART-to-I C is bypassed. SDA output
requires a pullup to V
.
CC
Digital Supply Voltage. Bypass V
CC
to ground with 0.1FF and 0.001FF capacitors in parallel
20, 33
23, 40
V
CC
as close as possible to the device with the smallest value capacitor closest to V
.
CC
21
22
26
27
GPIO8
GPIO9
General Purpose Input/Output
General Purpose Input/Output
Spread PLL Supply Voltage. Bypass V
to GNDSPLL with 0.1FF and 0.001FF capaci-
CCSPLL
23
28
V
tors in parallel as close as possible to the device with the smallest value capacitor closest to
CCSPLL
V
.
CCSPLL
24
25
26
27
29
30
31
32
GNDSPLL SPLL Ground
GNDLVDS LVDS Ground
SDO-
Serial LVDS Inverting Output
Serial LVDS Noninverting Output
LVDS Supply Voltage. Bypass V
SDO+
to GNDLVDS with 0.1FF and 0.001FF capacitors
CCLVDS
28
33
V
in parallel as close as possible to the device with the smallest value capacitor closest to
CCLVDS
V
.
CCLVDS
���������������������������������������������������������������� Maxim Integrated Products 12
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
MAX9257A Pin Description (continued)
PIN
NAME
REM
FUNCTION
TQFN
LQFP
Remote Power-Up/Power-Down Select Input. Connect REM to ground for power-up to follow
29
34
V
. Connect REM high to V
through 10kI resistor for remote power-up. REM is internally
CC
CC
pulled down to GND.
30, 31, 32, 35, 38, 39,
DIN[0:7]
Data Inputs. DIN[0:7] are internally pulled down to ground.
35–39
42–46
Data Input/General Purpose Input/Output. When a serial-data word is less than 18 bits word
40
47
DIN8/GPIO0 length, DIN_ not programmed as data input becomes GPIO (Table 22). DIN8 is internally
pulled down to ground.
1, 12, 13
24, 25, 36,
37, 48
—
—
N.C.
EP
No Connection. Not internally connected.
—
Exposed Pad for TQFN Package Only. Connect EP to ground.
MAX9258A Pin Description
PIN
NAME
FUNCTION
1, 12, 13, 24,
25, 36, 37
N.C.
No Connection. Not internally connected.
Digital Supply Voltage. Bypass V to GND with 0.1FF and 0.001FF capacitors in parallel as close
CC
2
V
CC
as possible to the device with the smallest value capacitor closest to V
.
CC
3, 14
GND
Digital Supply Ground
LVCMOS/LVTTL Power-Down Input. Drive PD high to power up the device and enable all outputs.
Drive PD low to put all outputs in high impedance and reduce supply current. PD is internally
pulled down to ground.
4
PD
LVDS Supply Voltage. Bypass V
as close as possible to the device with the smallest value capacitor closest to V
to GNDLVDS with 0.1FF and 0.001FF capacitors in parallel
CCLVDS
5
V
CCLVDS
.
CCLVDS
6
7
8
9
SDI-
Serial LVDS Inverting Input
SDI+
Serial LVDS Noninverting Input
GNDLVDS LVDS Supply Ground
GNDPLL
PLL Supply Ground
PLL Supply Voltage. Bypass V
close to the device as possible with the smallest value capacitor closest to V
to GNDPLL with 0.1FF and 0.001FF capacitors in parallel as
CCPLL
10
V
CCPLL
.
CCPLL
Active-Low, Open-Drain Error Output. ERROR asserts low to indicate a data transfer error was
detected (parity, PRBS, or UART control channel error). ERROR is high to indicate no error detect-
ed. ERROR resets when the error registers are read for parity, control channel errors, and when
11
15
ERROR
RX
PRBS enable bit is reset for PRBS errors. Pull up to V
with a 1kI resistor.
CCOUT
LVCMOS/LVTTL Control Channel UART Output
���������������������������������������������������������������� Maxim Integrated Products 1±
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
MAX9258A Pin Description (continued)
PIN
NAME
FUNCTION
16
TX
LVCMOS/LVTTL Control Channel UART Input. TX is internally pulled up to V
.
CCOUT
Open-Drain Lock Output. LOCK asserts high to indicate PLLs are locked with correct serial-word
boundary alignment. LOCK asserts low to indicate PLLs are not locked or incorrect serial-word
17
LOCK
boundary alignment was detected. Pull up to V
with a 1kI resistor.
CCOUT
18
19
20
PCLK_OUT LVCMOS/LVTTL Recovered Clock Output
VSYNC_OUT LVCMOS/LVTTL Vertical SYNC Output
HSYNC_OUT LVCMOS/LVTTL Horizontal SYNC Output
21, 28–35,
40–46
DOUT[15:0] LVCMOS/LVTTL Data Outputs
Output Supply Voltage. V
is the supply for all output buffers. Bypass V
to GNDOUT
CCOUT
CCOUT
22, 39
23, 38, 48
26
V
with 0.1FF and 0.001FF capacitors in parallel as close as possible to the device with the smallest
CCOUT
value capacitor closest to V
.
CCOUT
GNDOUT
Output Supply Ground
Spread-Spectrum PLL Supply Voltage. Bypass V
to GNDSPLL with 0.1FF and 0.001FF
CCSPLL
V
capacitors in parallel as close as possible to the device with the smallest value capacitor closest to
CCSPLL
V
.
CCSPLL
27
47
GNDSPLL
CCEN
SPLL Ground
LVCMOS/LVTTL Control Channel Enabled Output. CCEN asserts high to indicate that control chan-
nel is enabled.
���������������������������������������������������������������� Maxim Integrated Products 14
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
R /2
L
SDO+
V
OD
SDO-
V
OS
R /2
L
GND
((SDO+) + (SDO-))/2
SDO-
SDO+
V
(-)
OS
V
(+)
V
(-)
OS
OS
V
V
= |V (+) - V (-)|
OS OS
OS
V
(+)
OD
V
OD
= 0V
V
OD
(-)
V
(-)
OD
= |V (+) - V (-)|
OD
OD
OD
(SDO+) - (SDO-)
Figure 1. MAX9257A LVDS DC Output Parameters
V
OUT
PCLK_IN
DIN
V
V
HYST+
NOTE: PCLK_IN PROGRAMMED FOR RISING LATCH EDGE.
HYST-
-V
ID
+V
ID
V
= 0V
ID
Figure 2. Input Hysteresis
Figure 3. MAX9257A Worst-Case Pattern Input
���������������������������������������������������������������� Maxim Integrated Products 15
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
SDO+
R
L
SDO-
C
L
C
L
80%
80%
20%
20%
(SDO+) - (SDO-)
t
t
FALL
RISE
Figure 4. MAX9257A LVDS Control Channel Output Load and Output Rise/Fall Times
V
IHMIN
PCLK_IN
V
ILMAX
t
t
HOLD
SET
V
V
V
V
IHMIN
IHMIN
DIN, VSYNC_IN, HSYNC_IN
ILMAX
ILMAX
NOTE: PCLK_IN PROGRAMMED FOR RISING LATCHING EDGE.
Figure 5. MAX9257A Input Setup and Hold Times
���������������������������������������������������������������� Maxim Integrated Products 16
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
EXPANDED TIME SCALE
DIN, HSYNC_IN,
VSYNC_IN
N
N+2
N+3
N+4
N+1
PCLK_IN
N-1
N
SDO
t
PSD1
FIRST BIT
LAST BIT
Figure 6. MAX9257A Parallel-to-Serial Delay
t
T
V
V
IHMIN
t
HIGH
PCLK_IN
ILMAX
t
R
t
F
t
LOW
Figure 7. MAX9257A Parallel Input Clock Requirements
C
L
PCLK_OUT
MAX9258A
SINGLE-ENDED OUTPUT LOAD
0.9 x V
CCOUT
DOUT
NOTE: PCLK_OUT PROGRAMMED FOR RISING LATCH EDGE.
0.1 x V
CCOUT
t
R
t
F
Figure 8. MAX9258A Worst-Case Pattern Output
Figure 9. MAX9258A Output Rise and Fall Times
���������������������������������������������������������������� Maxim Integrated Products 17
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
t
T
V
OHMIN
t
HIGH
PCLK_OUT
V
OLMAX
t
LOW
Figure 10. MAX9258A Clock Output High and Low Time
V
OHMIN
PCLK_OUT
V
OLMAX
t
t
DVB
DVA
V
V
OHMIN
DOUT, VSYNC_OUT,
HSYNC_OUT, LOCK
OLMAX
NOTE: PCLK_OUT PROGRAMMED FOR RISING LATCHING EDGE.
Figure 11. MAX9258A Output Data Valid Times
V
IHMIN
PD
PD
V
ILMAX
t
PUD
t
PDD
DOUT,
VSYNC,
HSYNC
HIGH IMPEDANCE
POWERED DOWN
POWERED UP
(OUTPUTS ACTIVE)
POWERED UP
POWERED DOWN
Figure 12. MAX9258A Power-Up Delay
Figure 13. MAX9258A Power-Down Delay
���������������������������������������������������������������� Maxim Integrated Products 18
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
SERIAL-WORD LENGTH
SERIAL WORD N
SERIAL WORD N+1
SERIAL WORD N+2
SDI
FIRST BIT
LAST BIT
DOUT,
HSYNC_OUT,
VSYNC_OUT
PARALLEL WORD N-1
PARALLEL WORD N
PARALLEL WORD N-2
PCLK_OUT
t
SPD1
NOTE: PCLK_OUT PROGRAMMED FOR RISING LATCHING EDGE.
Figure 14. MAX9258A Serial-to-Parallel Delay
INPUT TEMPLATE FOR LVDS SERIAL
V
- V
SDI-
SDI+
+100mV
0V
-100mV
+25mV
-25mV
t
JT
t
S
t
S
t
JT
0.0UI
0.25UI
0.50UI
0.75UI
1.0UI
- V ).
NOTE: UI IS ONE SERIAL BIT. TIME INPUT IS MEASURED DIFFERENTIALLY (V
SDI+
SDI-
Figure 15. MAX9258A Jitter Tolerance
1
0
0.8V
0.8V
OD(+)
OD(+)
0.8 x | V
+ V
OD(-)
|
0.8 x | V
+ V
OD(-)
|
OD(+)
OD(+)
0.2V
0.2V
OD(+)
OD(+)
(SDO+) - (SDO-)
0.2V
0.8V
0.2V
0.8V
OD(-)
OD(-)
t
t
F1B
R1A
0.2 x | V
+ V
OD(-)
|
0.2 x | V + V
OD(+)
|
OD(+)
OD(-)
OD(-)
OD(-)
t
F2
t
R2
t
t
F1A
R1B
Figure 16. Control Channel Transition Time
���������������������������������������������������������������� Maxim Integrated Products 19
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
ECU
CAMERA
MAX9257A
MAX9258A
VIDEO DATA
VIDEO DATA
PIXEL CLOCK
HSYNC_OUT
VSYNC_OUT
PIXEL CLOCK
HSYNC_IN
DESERIALIZER
SERIALIZER
100
100
VSYNC_IN
GPIO
PD
CCEN
ERROR
LOCK
RX
TX
SDA
SCL
UART-
TO-I C
2
UART
UART
I C
2
2
Figure 17. Serial Link with I C Camera Programming Interface (Base Mode)
ECU
CAMERA
MAX9257A
MAX9258A
VIDEO DATA
VIDEO DATA
PIXEL CLOCK
HSYNC_OUT
VSYNC_OUT
PIXEL CLOCK
HSYNC_IN
DESERIALIZER
SERIALIZER
100
100
VSYNC_IN
GPIO
PD
CCEN
ERROR
LOCK
RX
TX
RX
TX
UART
UART
UART
UART
Figure 18. Serial Link with UART Camera Programming Interface (Bypass Mode)
���������������������������������������������������������������� Maxim Integrated Products 20
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
The MAX9257A/MAX9258A DC-balanced serializer and
Detailed Description
deserializer operate from a 5MHz-to-70MHz parallel
clock frequency, and are capable of serializing and
deserializing programmable 10, 12, 14, 16, and 18
bits parallel data during the video phase. The devices
have two phases of operation: video and control chan-
nel (Figure 19 and 20). During the video phase, the
MAX9257A accepts parallel video data and transmits
serial encoded data over the LVDS link. The MAX9258A
accepts the encoded serial LVDS data and converts
it back to parallel output data. The MAX9257A has
dedicated inputs for HSYNC and VSYNC. The selected
VSYNC edge causes the MAX9257A/MAX9258A to enter
the control channel phase. Nonactive VSYNC edge can
be asserted after eight pixel clock cycles.
The MAX9257A serializer pairs with the MAX9258A
deserializer to form a complete digital video serial link.
The electronic control unit (ECU) programs the registers
in the MAX9257A, MAX9258A, and peripheral devices,
such as a camera, during the control channel phase that
occurs at startup or during the vertical blanking time.
All control channel communication is half-duplex. The
UART communication between the MAX9258A and the
MAX9257A is encoded to allow transmission through
AC-coupling capacitors. The MAX9257A communicates
2
to the peripheral device through UART or I C.
8t
T
VSYNC_IN
SDI/O
VIDEO
HSK
CONTROL
VIDEO
SDI/O
CCEN
HSK = HANDSHAKING
Figure 19. Video and Control Channel Phases (Spread Off)
0.5/f
SSM
(max)
VSYNC_IN
SDI/O
VIDEO
HSK
VIDEO
CONTROL
SPREAD
PROFILE
SDI/O
CCEN
HSK = HANDSHAKING
Figure 20. Video and Control Channel Phases (MAX9257A Spread is Enabled)
���������������������������������������������������������������� Maxim Integrated Products 21
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
The video data are coded using two overhead bits (EN0
that the control channel is open. Programmable timers
and ECU signal activity determine how long the control
channel stays open. The timers are reset by ECU signal
activity. ECU programming must not exceed the vertical
blanking time to avoid loss of video data.
and EN1) resulting in a serial-word length of N+2 bits.
The devices feature programmable parity encoding that
adds two parity bits to the serial word. Bit 0 (EN0) is the
LSB that is serialized first without parity enabled. The par-
ity bits are serialized first when parity is enabled.
After the control channel phase closes, the MAX9257A
sends a 546 or 1090 word pattern as handshaking (HSK)
to synchronize the MAX9258A’s internal clock recovery
circuit to the MAX9257A’s transmitted data. Following
the handshaking, the control channel is closed and the
video phase begins. The serial LVDS data is recovered
and parallel data is valid on the programmed edge of the
recovered pixel clock.
The ECU programs the MAX9258A, MAX9257A, and
peripheral devices at startup and during the control
channel phase. In a digital video system, the control
channel phase occurs during the vertical blanking time
and synchronizes to the VSYNC signal. The programma-
ble active edge of VSYNC initiates the control channel
phase. Nonactive edge of VSYNC can transition at any
time after 8 x t if MAX9257A spread is not enabled and
T
Table 1 and 2 show the default power-up values for the
MAX9257A/MAX9258A registers. Tables 3 and 4 show
the input and output supply references.
0.5/f
when enabled. At the end of video phase, the
SSM
MAX9258A drives CCEN high to indicate to the ECU
Table 1. MAX9257A Power-Up Default Register Map (see the MAX9257A Register Table)
REGISTER
ADDRESS (hex)
POWER-UP VALUE
(hex)
REGISTER NAME
POWER-UP DEFAULT SETTINGS
PRATE = 10, 20MHz to 40MHz
SRATE = 11, 400Mbps to 840Mbps
PAREN = 0, parity disabled
REG0
0x00
0xB5
PWIDTH = 101, parallel data width = 18
SPREAD = 000, spread = off
Reserved = 11111
REG1
REG2
REG3
0x01
0x02
0x03
0x1F
0xA0
0xA0
STODIV = 1010, STO clock is pixel clock divided by 1024
STOCNT = 0000, STO counter counts to 1
ETODIV = 1010, ETO clock is pixel clock divided by 1024
ETOCNT = 0000, ETO counter counts to 1
VEDGE = 0, VSYNC active edge is falling
Reserved = 0
CKEDGE = 1, pixel clock active edge is rising
PD: 1) If REM = 0, PD = 0
1) REM = 0, 0x28
2) REM = 1, 0x30 SEREN: 1) If REM = 0, SEREN = 1
2) If REM = 1, SEREN = 0
2) If REM = 1, PD = 1
REG4
0x04
BYPFPLL = 0, filter PLL is active
Reserved = 0
PRBSEN = 0, PRBS test disabled
���������������������������������������������������������������� Maxim Integrated Products 22
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
Table 1. MAX9257A Power-Up Default Register Map (continued)
REGISTER
ADDRESS (hex)
POWER-UP VALUE
REGISTER NAME
POWER-UP DEFAULT SETTINGS
(hex)
0xFA
0xFF
0xF8
REG5
REG6
REG7
0x05
0x06
0x07
MAX9257A address = 1111 1010
End frame = 1111 1111
MAX9258A address = 1111 1000
INTMODE = 0, interface with peripheral is UART
INTEN = 0, interface with peripheral is disabled
FAST = 0, UART bit rate = DC to 4.25Mbps
CTO = 000, never come back
REG8
REG9
0x08
0x09
0x00
0x00
BITRATE = 00, base mode bit rate = 95kbps to 400kbps
PRBSLEN = 0000, PRBS word length = 221
GPIO9DIR = 0, GPIO9 = input
GPIO8DIR = 0, GPIO8 = input
GPIO9 = 0
GPIO8 = 0
GPIO7DIR = 0, GPIO7 = input
GPIO6DIR = 0, GPIO6 = input
GPIO5DIR = 0, GPIO5 = input
GPIO4DIR = 0, GPIO4 = input
GPIO3DIR = 0, GPIO3 = input
GPIO2DIR = 0, GPIO2 = input
GPIO1DIR = 0, GPIO1 = input
GPIO0DIR = 0, GPIO0 = input
REG10
0x0A
0x00
GPIO7 = 0
GPIO6 = 0
GPIO5 = 0
GPIO4 = 0
GPIO3 = 0
GPIO2 = 0
GPIO1 = 0
GPIO0 = 0
REG11
0x0B
0x00
PREEMP = 111, preemphasis = 0%
Reserved = 00000
REG12
REG13
REG14
0x0C
0x0D
0x0E
0xE0
0x00
0x00
Reserved = 000000
I2CFILT = 00, I2C glitch filter settings:
1) 95kbps to 400kbps = 100ns
2) 400kbps to 1000kbps = 50ns
3) 1000kbps to 4250kbps = 10ns
Reserved = 0000 000
LOCKED = read only
���������������������������������������������������������������� Maxim Integrated Products 2±
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
Table 2. MAX9258A Power-Up Default Register Map (see the MAX9258A Register Table)
REGISTER
ADDRESS (hex)
POWER-UP VALUE
(hex)
REGISTER NAME
POWER-UP DEFAULT SETTINGS
PRATE = 10, 20MHz to 40MHz
SRATE = 11, 400Mbps to 840Mbps
PAREN = 0, parity disabled
PWIDTH = 101, parallel data width = 18
REG0
0x00
0x01
0xB5
0x00
SPREAD = 00, spread spectrum = off
AER = 0, error count is reset by reading error registers
ACTOFFSET = 00, 23mV offset
REG1
Reserved = 000
STODIV = 1010, STO clock is pixel clock divided by 1024
STOCNT = 0000, STO counter counts to 1
REG2
REG3
0x02
0x03
0xA0
0xA0
ETODIV = 1010, ETO clock is pixel clock divided by 1024
ETOCNT = 0000, ETO counter counts to 1
VEDGE = 0, VSYNC active edge is falling
HEDGE = 0, HSYNC active edge is falling
CKEDGE = 1, pixel clock active edge is rising
Reserved = 0
REG4
0x04
0x20
ACTLP = 0, short stretcher output pulse
Reserved = 00
PRBSEN = 0, PRBS test disabled
REG5
REG6
0x05
0x06
0xF8
0xFF
MAX9258 address = 1111 1000
End frame = 1111 1111
INTMODE = 0, interface with peripheral is UART
INTEN = 0, interface with peripheral is disabled
FAST = 0, UART bit rate = DC to 4.25Mbps
CTO = 000, never come back
REG7
0x07
0x00
BITRATE = 00, base mode bit rate = 95kbps to 400kbps
PATHRLO = 0001 0000
parity threshold = 16
REG8
REG9
0x08
0x09
0x10
0x00
PATHRHI = 0000 0000,
parity threshold = 16
REG10
REG11
REG12
0x0A
0x0B
0x0C
0x00
0x00
0x00
Parity errors video (8 LSBs) = read only
Parity errors video (8 MSBs) = read only
PRBS bit errors = read only
Reserved = 000
Parity error, communication with MAX9258A = read only
Frame error, communication with MAX9258A = read only
Parity error, communication with MAX9257A = read only
Frame error, communication with MAX9257A = read only
I2C error, communication with peripheral = read only
REG13
0x0D
0x00
���������������������������������������������������������������� Maxim Integrated Products 24
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
serial-data rate, and parity. Table 16 shows the parallel-
word width.
Parallel-Word Width
The parallel-word width is made up of the video data
bits, HSYNC, and VSYNC. The video data bits are pro-
grammable from 8 to 16 depending on the pixel clock,
Serial-Word Length
The serial-word length is made up of the parallel-word
width, encoding bits, and parity bits. Tables 5–9 show the
serial video format and serial-word lengths without parity.
Tables 10–13 show with parity bits included.
Table ±. MAX9257A I/O Supply
INPUTS/OUTPUTS
SUPPLY
PCLK_IN, HSYNC_IN, VSYNC_IN,
DIN[0:7], DIN[8:15]/GPIO[0:7],
GPIO8, GPIO9, SCL/TX, SDA/RX
Table 4. MAX9258A I/O Supply
V
CCIO
INPUTS/OUTPUTS
All inputs and outputs
SDI+, SDI-
SUPPLY
SDO+, SDO-
REM
V
V
CCOUT
CCLVDS
V
V
CCLVDS
CC
Table 5. Serial Video Data Format for 20-Bit Serial-Word Length (Parallel-Word Width = 18)
BIT
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
NAME EN0 EN1 HSYNC VSYNC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
Table 6. Serial Video Data Format for 18-Bit Serial-Word Length (Parallel-Word Width = 16)
BIT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
NAME EN0 EN1 HSYNC VSYNC D0
D1
D2
D3
D4
D5
D6
D7
D8
D9 D10 D11 D12 D13
Table 7. Serial Video Data Format for 16-Bit Serial-Word Length (Parallel-Word Width = 14)
BIT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NAME EN0 EN1 HSYNC VSYNC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
Table 8. Serial Video Data Format for 14-Bit Serial-Word Length (Parallel-Word Width = 12)
BIT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NAME EN0 EN1 HSYNC VSYNC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Table 9. Serial Video Data Format for 12-Bit Serial-Word Length (Parallel-Word Width = 10)
BIT
1
2
3
4
5
6
7
8
9
10
11
12
NAME EN0 EN1 HSYNC VSYNC
D0
D1
D2
D3
D4
D5
D6
D7
Table 10. Format for 20-Bit Serial-Word Length with Parity (Parallel-Word Width = 16)
BIT
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17
18
19
20
NAME PR PRB EN0 EN1 HSYNC VSYNC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
���������������������������������������������������������������� Maxim Integrated Products 25
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
Table 11. Format for 18-Bit Serial-Word Length with Parity (Parallel-Word Width = 14)
BIT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
NAME PR PRB EN0 EN1 HSYNC VSYNC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
Table 12. Format for 16-Bit Serial-Word Length with Parity (Parallel-Word Width = 12)
BIT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NAME PR PRB EN0 EN1 HSYNC VSYNC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Table 1±. Format for 14-Bit Serial-Word Length with Parity (Parallel-Word Width = 10)
BIT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NAME PR PRB EN0 EN1 HSYNC VSYNC
D0
D1
D2
D3
D4
D5
D6
D7
LVDS Serial Data
Serial LVDS data is transmitted least significant bit (LSB)
to most significant bit (MSB) as shown in Tables 5 through
13. The ECU at startup can program the parallel word
width, serial frequency range, parity, spread-spectrum,
and pixel clock frequency range (see the MAX9257A
Register Table and the MAX9258A Register Table).
Table 14. MAX9257A Pixel Clock Range
(PCLK�IN)
FREQUENCY (MHz)
PRATE (REG0[7:6])
5–10
10–20
20–40
40–70
00
01
10
11
Pixel Clock Frequency Range
The devices each have registers that can be configured
at startup. Depending on the word length, the MAX9257A
multiplies PCLK_IN (pixel clock) by 12, 14, 16, 18, or
20 using an internal PLL to generate the serial clock.
Use Table 20 for proper selection of available PCLK fre-
quency and serial-data ranges. Parallel data is serialized
using the serial-clock and serialized bits are transmitted
at the MAX9257A LVDS outputs. The devices support
a wide range for PCLK_IN (Table 14). If the pixel clock
frequency needs to change to a frequency outside the
programmed range, the ECU must program both the
MAX9257A and the MAX9258A in the same control chan-
nel session.
Table 15. Serial-Data Rate Range
SERIAL-DATA RATE (Mbps)
SRATE (REG0[5:4])
60–100
100–200
200–400
400–840
00
01
10
11
the serial-word length is 20 bits, the maximum PCLK_IN
frequency is 42MHz. The serial-data rate can vary from
60Mbps to 840Mbps and can be programmed at power-
up (Table 15). Use Table 20 for proper selection of avail-
able PCLK frequency and serial data ranges. Operating
in the incorrect range for either the serial-data rate or
PCLK_IN can result in excessive current dissipation and
failure of the MAX9258A to lock to the MAX9257A.
Serial-Data Rate Range
The word length and pixel clock is limited by the maxi-
mum serial-data rate of 840Mbps. The following formula
shows the relation between word length, pixel clock, and
serial clock:
Serial-word length x pixel clock = serial-data rate =
840Mbps
LVDS Common-Mode Bias
The output common-mode bias is 1.2V at the LVDS
inputs on the MAX9258A and LVDS outputs on the
MAX9257A. No external resistors are required to provide
bias for AC-coupling the LVDS inputs and outputs.
For example, if PCLK_IN is 70MHz, the serial-word length
has to be 12 bits including DC balance bits if parity is not
enabled to keep the serial-data rate under 840Mbps. If
���������������������������������������������������������������� Maxim Integrated Products 26
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
Table 16. Parallel-Word Width
FREQUENCY
PARALLEL-WORD WIDTH
PWIDTH (REG0[2:0])
1/f
SSM
10
12
14
16
18
000
001
010
011
1XX
f
(MAX)
SPREAD
f
TIME
PCLK_IN
Table 17. MAX9258A Spread
f
(MIN)
SPREAD
PRATE (REG1[7:6])
SPREAD (%)
00
01
10
11
Off
Q2
Off
Q4
Figure 21. Simplified Modulation Profile for the MAX9257A/
MAX9258A
LVDS Termination
Terminate the LVDS link at both ends with the charac-
teristic impedance of the transmission line (typically
100O differential). The LVDS inputs and outputs are high
impedance to GND and differentially.
Table 18. MAX9258A Modulation Rate
PRATE
(REG1[7:6])
Spread-Spectrum Selection
The devices each have spread-spectrum options. Both
should not be turned on at the same time. When the
MAX9257A is programmed for spread spectrum, the
MAX9258A tracks and passes the spread to its clock and
data outputs. The MAX9257A/MAX9258A are both center
spread (Figure 21). The control channel does not use
spread spectrum, but has slower transition times.
MODULATION RATE
f
RANGE (kHz)
SSM
00
01
10
11
PCLK/312
PCLK/520
PCLK/1040
PCLK/1248
16 to 32
19.2 to 38.5
19.2 to 38.5
32 to 56
Table 19. MAX9257A LVDS Output Spread
MAX9258A Spread Spectrum
The MAX9258A features a programmable spread-spectrum
clock and data outputs for reduced EMI. The single-ended
data outputs are programmable for no spread, Q2%, or
Q4% (see the Typical Operating Characteristics) around the
recovered pixel clock frequency. The output spread is pro-
grammed in register REG1[7:6]. Table 17 shows the spread
options, and Table 18 shows the various modulation rates.
REG1[7:5]
000
SPREAD (%)
Off
Q1.5
Q1.75
Q2
001
010
011
100
Off
MAX9257A Spread Spectrum
The MAX9257A features programmable spread spec-
trum for the LVDS outputs. Table 19 shows various
spread options, and Table 20 shows the various modu-
lation rates. Only one device (the MAX9257A or the
MAX9258A) should be programmed for spread spectrum
at a time. If the MAX9257A is programmed for spread,
the MAX9258A tracks and passes the spread to the data
and clock outputs. The PRATE range of 00 and 01 (5MHz
≤ PCLK ≤ 20MHz) supports all the spread options. The
PRATE range of 10 and 11 (20MHz ≤ PCLK ≤ 70MHz)
requires that the spread be 2% or less.
101
Q3
110
Q3.5
Q4
111
Pixel Clock Jitter Filter
The MAX9257A has a PLL to filter high-frequency pixel
clock jitter on PCLK_IN. The FPLL can be bypassed by
writing 1 to REG4[2]. The FPLL improves the MAX9258A’s
data recovery by filtering out the high-frequency compo-
nents from the pixel clock that the MAX9258A cannot
track. The 3dB bandwidth of the FPLL is 100kHz (typ).
���������������������������������������������������������������� Maxim Integrated Products 27
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
Table 20. MAX9257A Modulation Rate
SERIAL-WORD LENGTH
SRATE
11
11
10
10
01
01
00
11
11
10
10
01
01
00
11
11
10
10
01
01
00
11
11
10
10
01
01
00
11
11
10
01
PRATE
11
10
10
01
01
00
00
11
10
10
01
01
00
00
11
10
10
01
01
00
00
11
10
10
01
01
00
00
11
10
01
00
PCLK RANGE (MHz)
40–70
MODULATION RATE
PCLK/2728
PCLK/1736
PCLK/1612
PCLK/992
f
RANGE (kHz)
SSM
14.7 to 25.7
19.2 to 23.0
12.4 to 20.7
16.7 to 20.2
9.0 to 14.9
11.2 to 13.4
5.8 to 9.6
33.3–40
20–33.3
16.6–20
10–16.6
8.3–10
12
PCLK/1116
PCLK/744
5–8.3
PCLK/868
40–60
PCLK/2304
PCLK/1728
PCLK/1440
PCLK/1008
PCLK/1008
PCLK/720
17.4 to 26.0
16.6 to 23.1
13.9 to 19.9
14.2 to 19.8
9.9 to 14.2
9.9 to 13.9
6.9 to 9.9
28.6–40
20–28.6
14.3–20
10–14.3
7.1–10
14
5–7.1
PCLK/720
40–52.5
25–40
PCLK/1968
PCLK/1640
PCLK/1312
PCLK/984
20.3 to 26.7
15.2 to 24.4
15.2 to 19.1
12.7 to 20.3
12.2 to 15.2
9.5 to 15.2
7.6 to 9.5
20–25
16
12.5–20
10–12.5
6.25–10
5–6.25
PCLK/820
PCLK/656
PCLK/656
40–46.6
22.2–40
20–22.2
11.1–20
10–11.1
5.6–10
PCLK/1840
PCLK/1472
PCLK/1104
PCLK/920
21.7 to 25.3
15.1 to 27.2
18.1 to 20.1
12.1 to 21.7
13.6 to 15.1
7.6 to 13.6
9.1 to 10.1
24.5 to 25.7
12.3 to 24.5
9.8 to 19.6
6.1 to 12.3
18
20
PCLK/736
PCLK/736
5–5.6
PCLK/552
40–42
PCLK/1632
PCLK/1632
PCLK/1020
PCLK/816
20–40
10–20
5–10
���������������������������������������������������������������� Maxim Integrated Products 28
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
LVDS Output Preemphasis (SDO )
Table 21. Preemphasis
The MAX9257A features programmable preemphasis
where extra current is added when the LVDS outputs
transition on the serial link. Preemphasis provides addi-
tional current to the normal drive current. For example,
20% preemphasis provides 20% greater current than
the normal drive current. Current is boosted only on the
transitions and returns to the normal drive current after
switching. Select the preemphasis level to optimize the
eye diagram. Preemphasis boosts the high-frequency
content of the LVDS outputs to enable driving greater
cable lengths. The amount of preemphasis is pro-
grammed in REG12[7:5] (Table 21).
REG12[7:5]
000,101,110
001
PREEMPHASIS (%)
20
40
60
80
100
0
010
011
100
111
Table 22. GPIOs vs. Parallel-Word Width
VSYNC, HSYNC, and Pixel Clock Polarity
PCLK: The MAX9257A is programmable to latch data
on either rising or falling edge of PCLK. The polarity of
PCLKOUT at the MAX9258A can be independent of the
MAX9257A PCLK active edge. The polarity of PCLK can
be programmed using REG4[5] of the MAX9257A and
PARALLEL-WORD WIDTH (N)
GPIOs AVAILABLE
GPIO[8:9]
18
16
14
12
10
GPIO[6:9]
GPIO[4:9]
GPIO[2:9]
the MAX9258A.
GPIO[0:9]
VSYNC: The MAX9257A and the MAX9258A enter con-
trol channel on the falling edge of VSYNC. The default
register settings are VSYNC active falling edge for both
the MAX9257A and the MAX9258A. If the VSYNC active
edge is programmed for rising edge at the MAX9257A,
the MAX9258A VSYNC active edge must also be pro-
grammed for rising edge to reproduce VSYNC rising
edge at the MAX9258A output. However, matching
the polarity of the VSYNC active edge between the
MAX9257A and the MAX9258A is not a requirement for
proper operation.
Open-Drain Outputs (LOCK, ERROR)
LOCK and ERROR are open-drain outputs that require a
pullup resistor to an external supply. ERROR asserts low
when an error occurs and LOCK is high impedance when
the MAX9258A is locked to the MAX9257A and remains
high under the locked condition. When the devices are
in shutdown, the channel is not locked and LOCK goes
high impedance, is pulled high, and should be ignored.
ERROR is high impedance at shutdown and remains
high. In choosing pullup resistors, there is a tradeoff
between power dissipation and speed; 10kI pullup
should be sufficient.
HSYNC: HSYNC active-edge polarity is programmable
for the MAX9258A.
General-Purpose I/Os (GPIOs)
The MAX9257A has up to 10 GPIOs available. GPIO8 and
GPIO9 are always available while GPIO[0:7] are avail-
able depending on the parallel-word width (Table 22).
If GPIOs are not available, the corresponding GPIO bits
are not used.
The LOCK and ERROR outputs can be wired in an AND
configuration if you have multiple serializers and deserial-
izers, or a single serializer fanned out to multiple deseri-
alizers through a repeater. For such situations, wire the
multiple LOCK outputs together and use a single pullup
resistor to pull up all the lines high. LOCK is high if all
the devices are locked. Do the same thing for ERROR;
ERROR is low if any MAX9258A reports errors.
A GPIO can be programmed to drive an LVCMOS logic level
or to read a logic input. The register bit that sets the output
level when the GPIO is programmed as an output stores the
input level when the GPIO is programmed as an input.
���������������������������������������������������������������� Maxim Integrated Products 29
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
STO Timer
The STO (start timeout) timer closes the control chan-
nel if the ECU does not start using the control channel
within the STO timeout period. The STO timer is config-
ured by register REG2 for both the MAX9257A and the
MAX9258A. The four bits of REG2[7:4] select the divide
ratio (STODIV) for the STO clock as a function of the pixel
clock (Table 24). The timeout period is determined by
counter bits REG2[3:0] that increment once every STO
clock period. Write to REG2[3:0] to determine the counter
end time. The STO counter counts to the programmed
STOCNT + 1. The ECU must begin communicating
before STO times out, otherwise, the control channel
closes (Figure 22). The STO timeout period is given by:
Base Mode and Bypass Mode (Basics)
In the control channel phase, there are two modes: base
and bypass. In base mode, ECU always communicates
using the MAX9257A/MAX9258A UART protocol and
communication with a peripheral device is performed
2
in I C by the MAX9257A. Packets not addressed to
2
the MAX9257A or the MAX9258A get converted to I C
2
and passed to the peripheral device. Similarly, I C
packets from the peripheral device get converted to
UART packets in the reverse direction. ECU can disable
communication to the peripheral device by writing a 0 to
INTEN (REG8[6] in the MAX9257A and REG7[6] in the
MAX9258A). Base mode is the default mode. Bypass
mode is entered by writing a 0 to INTMODE and 1 to
INTEN (Table 23). Bypass mode is exited if there is no
activity from ECU in the control channel for the duration of
CTO. When CTO times out, INTEN reverts back to 0 and
the devices revert back to base mode. To permanently
stay in bypass mode, ECU can lock the CTO timer or
program CTO to be longer than ETO and STO.
1
t
=
× STODIV × (STOCNT + 1)
STO
f
CLK
For example:
If the pixel clock frequency is set to 16MHz, STODIV is
set to 1010 (STODIV = 1024), and STOCNT is set to 1001
(STOCNT = 9), the STO timer counts with 15.625kHz STO
clock (16MHz/1024) internally until it reaches 10 and
Timers
The devices feature three different timers. The start time-
out (STO) and end timeout (ETO) control the duration of
the control channel. The come-back timeout (CTO) con-
trols the duration of bypass mode.
timer expires. The t
is equal to t x 1024 x 10 = 640Fs.
STO
T
The default value for STODIV is 1024 while the default
value for STOCNT is 0. That means the STO timeout
period is equal 1024 pixel clock cycles. Activity from the
ECU on the control channel shuts off the STO timer and
starts the ETO timer.
Table 2±. Selection of Base Mode or
Bypass Mode
INTEN
INTMODE
Table 24. STO Clock Divide Ratio
MAX9257A REG8[6], MAX9257A REG8[7],
MAX9258A REG7[6] MAX9258A REG7[7]
MODE
REG2[7:4]
00XX
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
STODIV
16
Base mode, com-
munication
with peripheral is
not enabled
16
0
1
X
1
32
64
Base mode,
128
communication
with peripheral is
256
2
enabled (I C)
512
Bypass mode,
communication
with MAX9257A/
MAX9258A is not
enabled, commu-
nication
1024
2048
4096
8192
16,384
32,768
1
0
with peripheral is
enabled (UART)
���������������������������������������������������������������� Maxim Integrated Products ±0
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
VSYNC_IN
T3
T1
T2
SDI/O
CCEN
VIDEO
HSK
VIDEO
TX
RX
FROZEN
DOUT_
T1 = TIME TO ENTER CONTROL CHANNEL
T2 = STO TIMEOUT PERIOD
T3 = CONTROL CHANNEL EXIT TIME DUE TO STO
HSK = HANDSHAKING BETWEEN THE MAX9257 AND THE MAX9258
Figure 22. Control Channel Closing Due to STO Timeout
ETO Timer
Table 25. ETO Clock Divide Ratio
The ETO (end timeout) timer closes the control channel if
the ECU stops communicating for the ETO timeout period.
Configure register REG3[7:4] for both the MAX9257A and
the MAX9258A to select the divide ratio (ETODIV) for the
ETO clock as a function of the pixel clock (Table 25). The
timeout period is determined by counter bits REG3[3:0]
that increment once every ETO clock period. Write to
REG3[3:0] to determine the counter end time. The ETO
counter counts to the programmed ETOCNT + 1. Any
ECU activity resets the ETO timer. When the ECU stops
transmitting data for the ETO timeout period, the control
channel closes (Figure 23).
REG±[7:4]
00XX
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ETODIV
16
16
32
64
128
256
512
1024
2048
4096
8192
16,384
32,768
1
t
=
×ETODIV × (ETOCNT +1)
ETO
f
CLK
For example:
If the pixel clock frequency is set to 16MHz, ETODIV is
set to 1010 (ETODIV = 1024), and ETOCNT is set to 1001
(ETOCNT = 9), the ETO timer counts with the 15.625kHz
ETO clock (16MHz/1024) internally until it reaches 10 and
The default value for ETODIV is 1024 while the default
value for ETOCNT is 0. That means the ETO timeout
period is equal to 1,024 pixel clock cycles.
timer expires. The t
is equal to t x 1024 x 10 = 640Fs.
ETO
T
���������������������������������������������������������������� Maxim Integrated Products ±1
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
VSYNC_IN
T1
T5
ECU
ACTIVITY
VIDEO
SDI/O
CCEN
HSK
VIDEO
T4 (BASE MODE)
T4 (BYPASS MODE)
TX
RX
FROZEN
DOUT_
T1 = TIME TO ENTER CONTROL CHANNEL
T4 = ETO TIMEOUT PERIOD
T5 = CONTROL CHANNEL EXIT TIME DUE TO ETO
HSK = HANDSHAKING BETWEEN MAX9257 AND MAX9258
Figure 23. Control Channel Closing Due to ETO Timeout
Closing the Control Channel
After the MAX9257A detects the active VSYNC edge, it
sends three synchronization words. Once the MAX9258A
sees the active VSYNC transition and detects three syn-
chronization words, it enters the control channel phase
and CCEN goes high. There is a brief delay of T1 between
the VSYNC transition and CCEN transitioning high. The
ECU is allowed to communicate when CCEN is high.
Another way to close the control channel in base mode
is for the ECU to send an end frame (EF) to close the
control channel without waiting for ETO to time out.
Whenever EF is received by both the devices, control
channel closes immediately and CCEN goes low. A syn-
chronization frame must precede EF. End frame cannot
be used in bypass mode. The control channel must close
by EF to report errors back to the ECU.
If the ECU does not communicate while CCEN is high
(Figure 22), the link remains silent and STO starts counting
towards its preset timeout counter value. If STO times out
(T2), CCEN transitions low and the control channel closes.
After the control channel closes, there is a brief handshake
period (T3 in Figure 22 and T5 in Figure 23) between the
MAX9257A and the MAX9258A. The MAX9258A sends a
special lock frame to the MAX9257A to indicate if PLL is
still locked. The MAX9258A sends the lock frame if the
number of decoding errors didn’t exceed a threshold in
the last LVDS video phase session. The MAX9258A fea-
tures a proprietary VCO lock that prevents frequency drift
while in the control channel for extended periods of time.
If MAX9257A receives the lock frame, it understands that
the MAX9258A is in a locked state and sends a short
training sequence. If the lock frame is not received by the
MAX9257A, it assumes that the MAX9258A is not locked
and sends a long training sequence. After the short
or long training sequence is complete, the MAX9257A
If the ECU communicates while CCEN is high and before
STO expires (Figure 23), the STO timer is turned off and
ETO timer is enabled. The ETO counter (ETOCNT+1) is
reset to 0 whenever activity from ECU (base mode) or
ECU and Camera (bypass mode) is detected. As long
as there is activity from ECU (base mode) or ECU and
Camera (bypass mode) on the link, the channel does not
close and the ETO counter resets. After the ECU (base
mode) or ECU and Camera (bypass mode) ceases link
activity, ETO times out (T4), CCEN transitions low, and
the control channel closes.
���������������������������������������������������������������� Maxim Integrated Products ±2
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
sends three special synchronization words before enter-
ing the video phase. Training sequence is used to resyn-
chronize the devices before the video phase starts.
Table 26. CTO Counter Timeout Period
MAX9257A REG2[7:4]
MAX9258A REG±[7:4]
COUNTER USING UART BIT
TIMES
The MAX9257A/MAX9258A control channel duration is
independent of VSYNC. The control channel does not
close when VSYNC deasserts, which allows the use
of a VSYNC interrupt signal on VSYNC_IN. The control
channel must be closed by STO, ETO, or EF. If the con-
trol channel does not close before video data becomes
available, video data can be lost.
Never come back
(lockout)
000
001
010
011
100
101
110
111
16
32
48
64
STO/ETO Timer Programming
STO and ETO can be programmed given the values of
T2, T4, and maximum values of T1, T3, and T5 (Figures
28, 23):
80
96
112
t = pixel clock period, t
= UART period
T
UCLK
When spread spectrum is not enabled in MAX9257A:
max(T1) = 2.5Fs + (3 x t ) + (4 x t
CTO uses the UART bit times. The UART period t
synchronizes with the UART bit times, which synchronize
every time the SYNC frame is sent.
UCLK
)
UCLK
T
When spread spectrum is enabled in MAX9257A:
When the CTO timer times out, INTEN bit in both devices
is set to 0 and the devices revert back to base mode.
If communication with the MAX9257A/MAX9258A is not
needed after initial programming is complete, CTO may
be set to 000 (never come back). In this case, CTO never
expires and the devices stay in bypass mode until they
are powered down. This prevents accidental program-
ming of the devices while ECU communicates with the
peripheral using a different UART protocol from the
MAX9257A/MAX9258A UART protocol.
max(T1) = 2.5Fs + (1400 x t ) + (4 x t
)
T
UCLK
T2 = t
STO
T4 = t
ETO
When pixel clock frequency range (PRATE) is 00 or 01:
t
t
STO
8
max(T3) =
max(T5) =
+ 546 × t + (20× t
)
)
T
UCLK
UCLK
ETO
8
+ 546 × t + (20× t
T
The overall CTO timeout is calculated as follows:
t
= t
x CTO
CTO
UCLK
Assuming a UART bit rate of 2Mbps, REG2[7:4],
REG3[7:4] = 100 (Table 26), CTO = 64, CTO timeout
calculated as:
When pixel clock frequency range (PRATE) is 10 or 11:
t
STO
8
t
= (0.5Fs) O 64 = 32Fs
max(T3) =
max(T5) =
+1090 × t + (20× t
)
CTO
T
UCLK
UCLK
Link Power-Up
t
ETO
8
The MAX9258A powers up when the power-down input
PD goes high. After approximately 130Fs, CCEN goes
high, indicating the control channel is available. This delay
is required because the analog circuitry has to fully wake
up. There are two ways to power up the MAX9257A. The
MAX9257A powers up according to the state of REM. ECU
powers up MAX9257A remotely (ECU sends command to
+1090 × t + (20× t
)
T
CTO Timer
The CTO (come-back timeout) timer temporarily or
permanently blocks programming to the MAX9257A/
MAX9258A registers. CTO keeps the devices in bypass
mode for the CTO timeout period (Table 26). Bypass
mode can only be exited when the CTO timer expires.
The CTO timer uses the UART bit times for its counter.
Note that STO and ETO timers use the pixel clock while
power up) when REM is pulled to V . The MAX9257A
CC
powers up according to the supply voltage when REM is
grounded.
���������������������������������������������������������������� Maxim Integrated Products ±±
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
Powering the MAX9257A with Serialization Enabled
MAX9258A Error Checking and Reporting
The MAX9258A has an open-drain ERROR output. This
output indicates various error conditions encountered
during the operation of the system. When an error con-
dition is detected and needs to be reported, ERROR
asserts low. ERROR indicates three error conditions:
UART, video parity, and PRBS errors.
(REM = Ground at Power-Up)
When REM is grounded, the MAX9257A fully pow-
ers up when power is applied. The power-down bit
PD (REG4[4]) is disabled and serialization bit SEREN
(REG4[3]) is enabled. If PCLK_IN is not running, the
MAX9257A stays in the control channel. After PCLK_IN
is applied, the control channel times out due to STO,
ETO, or EF. The MAX9257A starts the handshaking after
the MAX9257A locks to PCLK after 32,768 clock cycles.
If PCLK_IN is running, serialization starts automatically
after PLL of the MAX9257A locks to PCLK_IN with default
values in the registers.
UART Errors
During control channel communication in base mode, the
devices record UART frame, parity, and packet errors.
2
2
I C errors are also recorded by MAX9257A when I C
interface is enabled. If ECU closes the control channel
by using end frame (EF), the MAX9257A sends a special
internal UART frame back to the MAX9258A called error
Remote Power-Up of the MAX9257A
(REM = Pulled Up to V
)
CC
2
frame. The MAX9257A UART and I C errors are reset at
When REM is pulled up to V , the MAX9257A wakes
CC
the next control channel. The MAX9258A receives the
error frame and records the error status in its UART error
register (REG13). ECU must use end frame to the close
control channel for the MAX9257A to report back UART
up in a low power state, drawing less than 100FA supply
current. To wake-up the MAX9257A, the ECU first trans-
mits a dummy frame 0xDB and then waits at least 100Fs
to allow the MAX9257A’s internal analog circuitry to fully
power up. Then the ECU configures the MAX9257A reg-
isters, including a write to disable the PD bit (REG4[4])
so that the MAX9257A does not return back to the low
power state. Every packet needs to start with a synchro-
nization frame (see the UART section). If the PD bit is not
disabled within 70ms after transmitting the dummy frame,
the MAX9257A returns to the low power state and the
whole power-up sequence needs to be repeated. After
configuration is complete, the ECU also needs to enable
the SEREN bit to start the video phase.
2
and I C errors to the MAX9258A. Whenever one of the
bits in the UART error register is 1, ERROR asserts low.
The UART error register is reset when ECU reads it, and
ERROR deasserts high immediately if UART errors were
the only reason that ERROR was asserted low. If the
MAX9258A is not locked (LOCK = low), UART error is not
reported.
Video Parity Errors
When video parity check is enabled (REG0[3] in both
devices), the MAX9258A counts the number of video
parity errors by checking recovered video words. Value
of this counter is reflected in PAERRHI (8 MSB bits,
REG11) and PAERRLO (8 LSB bits, REG10). If the num-
ber of detected parity errors is greater than or equal
to the parity error threshold PATHRHI (REG9) and
PATHRLO (REG8), then ERROR asserts low. In this case,
ERROR deasserts high after next video phase starts if
video parity errors were the only reason that ERROR was
asserted low. To report parity errors in bypass mode,
program autoerror reset (AER) to 1 (REG1[5] = 1).
At initial power-up with REM pulled to V , default value
CC
of SEREN bit is 0, so STO and ETO timers are not active.
Control channel is enabled as long as SEREN is 0. This
allows the control channel to be used for extensive pro-
gramming at initial power-up without the channel timing
out. UART, parity, framing and packet errors in the con-
trol channel communications are reported if end frame is
used to close control channel (see the MAX9258A Error
Checking and Reporting section). For faster identification
of errors, verify every write command by reading back
the registers before enabling serialization.
Autoerror Reset
The default method to reset errors is to read the respec-
tive error registers in the MAX9258A (registers 10, 11,
and 13). If errors were present before the next control
channel, the error count gets incremented to the previ-
ous number. By setting the autoerror reset (AER) bit to 1,
the error registers reset when the control channel ends.
Setting AER to 1 does not reset PRBS errors.
Link Power-Down
When the control channel is open, the ECU writes to the
PD bit to power down the MAX9257A. In this case, to
power up the MAX9257A again, the power-up sequence
explained in the Remote Power-Up of the MAX9257A
(REM = Pulled Up to VCC) section needs to be repeated.
The MAX9258A has a PD input that powers down the device.
���������������������������������������������������������������� Maxim Integrated Products ±4
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
PRBS Errors
Table 27. Link Status
During the PRBS test, the MAX9258A checks received
PRBS data words by comparing them to internally gener-
ated PRBS data. Detected errors are counted in the PRBS
error register (REG12) in the MAX9258A. Whenever the
number of detected PRBS errors is more than 0, ERROR
asserts low. The PRBS error register is reset when ECU
writes a 0 to PRBSEN register (REG4[0]). In this case,
ERROR deasserts high immediately if PRBS errors were
the only reason that ERROR was asserted low.
LOCK
CCEN
INDICATION
LVDS channel active
Control channel active
PLL loss of lock
1
1
0
0
1
X
exceeds a certain threshold, the MAX9258A loses lock,
LOCK goes low, and the lock frame is not sent. The
MAX9258A also loses lock if handshaking is not suc-
cessful. If the MAX9257A does not receive the lock frame,
it transmits a long synchronization pattern before the start
of next video phase. When REM = 1, if the lock frame
is not received by the MAX9257A after 62 consecutive
attempts to synchronize, SEREN is disabled so that the
control channel opens permanently for troubleshooting.
Short Synchronization Pattern
The short synchronization pattern is part of the handshak-
ing procedure between the MAX9257A and MAX9258A
after the control channel phase. It is used to resynchro-
nize the MAX9258A’s clock and data recovery circuit
to the MAX9257A before the video phase begins. The
MAX9257A transmits the short synchronization pattern
when it receives the lock frame from the MAX9258A. The
length of short synchronization pattern is dependant on
the PRATE range. When PRATE is 00 or 01, the short
synchronization pattern consists of 546 words and when
PRATE is 10 or 11, the short synchronization pattern con-
sists of 1090 words. Every word is one pixel clock period.
Link Status (LOCK and CCEN)
The LOCK output indicates whether the MAX9258A is
locked to the MAX9257A. LOCK is an open-drain out-
put that needs to be pulled up to V . LOCK asserts
CC
low to indicate that the MAX9258A is not locked to the
MAX9257A and high when it is. In the control channel
phase, LOCK stays high if LOCK is high in the video
phase. While in the control channel phase, the MAX9258A
PLL frequency is held constant, PCLK output is active
and data outputs are frozen at their last valid value before
entering the control channel. CCEN output indicates
whether the devices are in the control channel phase
or video phase. CCEN goes high when the devices are
in the control channel phase (Table 27). Only at initial
power-up, CCEN goes high before communication in the
control channel is ready (see the Link Power-Up section).
Long Synchronization Pattern
At power-up or when the MAX9257A does not receive a
lock frame from the MAX9258A, the MAX9257A transmits
a long synchronization pattern. The long synchronization
pattern consists of 17,410 words. Every word is one pixel
clock period. When REM is high, if synchronization is not
achieved after 62 attempts, the MAX9257A resets SEREN
to 0 so that the control channel stays open to allow trou-
bleshooting. When REM is low, the MAX9257A/MAX9258A
continuously tries to reestablish the connection.
Control Channel
Lock Verification (Handshaking)
At the end of every vertical blanking time, the MAX9257A
verifies that the MAX9258A did not lose lock. The
MAX9258A handshakes with the MAX9257A to indicate
lock status. The handshaking occurs after the channel
closes (Figures 28 and 23). If the number of decoding
errors in a time window did not exceed a certain thresh-
old during the last video phase, the MAX9258A sends
back the lock frame that indicates lock. If the MAX9257A
receives the lock frame, the MAX9257A transmits a short
synchronization pattern. The MAX9258A features a pro-
prietary VCO mechanism that prevents frequency drift
while in the control channel. This allows for successful
resynchronization after extended use of control chan-
nel. If the number of decoding errors in a time window
Overview of Control Channel Operation
The control channel is used by the ECU to program
registers in the MAX9257A, MAX9258A, and peripheral
devices (such as a camera) during vertical blanking, after
power-up, or when serialization is disabled. Control chan-
nel communication is half-duplex UART. The peripheral
2
interface on the MAX9257A can be programmed to be I C
or UART. Operation of the control channel is synchronized
with the VSYNC input after the ECU starts serialization of
video data. Programmable timers, ECU signal activity,
and end frame determine how long the control channel
stays open. The control channel remains open as long
as there is signal activity from the ECU. When the control
channel closes, the LVDS serial link is reestablished.
���������������������������������������������������������������� Maxim Integrated Products ±5
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
Once serialization is enabled, the programming of regis-
MAX9258A (Figures 28 and 29). Packets not addressed
to the MAX9257A/MAX9258A get converted to I C by
2
ters (including the control channel overhead time) must
be completed within the vertical blanking time to avoid
loss of video data. VSYNC can deassert while control
channel remains open after eight pixel clock cycles.
the MAX9257A and pass to the peripheral device. The
2
MAX9257A receives I C packets from the peripheral
device and converts them to UART packets to send back
to the ECU. To disable communication to the peripheral
device, write a 0 to INTEN (REG8[6] in the MAX9257A
and REG7[6] in the MAX9258A).
The control channel phase begins on the transition of
the programmed active edge of VSYNC_IN. In video
applications, the VSYNC signal of the peripheral device
is connected to VSYNC_IN on the MAX9257A. In other
applications, a different signal can be used to trigger
the control channel phase. When the devices detect the
VSYNC_IN transition, the LVDS video phase disables and
the control channel phase is enabled.
In base mode, the STO/ETO timers and the EF command
are used to control the duration of the control channel.
STO and ETO count up and expire when they reach their
programmed value. STO and ETO are not enabled at
the same time. STO is enabled after CCEN goes high. If
there is activity from the ECU before STO times out, STO
is disabled and ETO is enabled. The ECU must begin
a transaction within an STO timeout or else the channel
closes. The ECU can close the channel by allowing ETO
to time-out. Activity from the ECU resets the ETO timer.
Another way to close the control channel is by send-
ing an end frame (EF). EF closes the channel within 2
to 3 bit times after being received by the MAX9257A/
MAX9258A. The default value of EF is 0xFF, but can be
programmed to any other value besides the MAX9257A
and the MAX9258A device addresses. The control chan-
nel must be closed with EF for control channel errors to
be reported.
The control channel operates in two modes: base and
bypass. In base mode, the ECU issues UART com-
mands in a specified format to program the MAX9257A/
MAX9258A registers. GPIO on the MAX9257A are also
programmed in base mode. UART commands are trans-
2
lated to I C and output to peripheral devices connected
to the MAX9257A when not addressed to either the
MAX9257A or the MAX9258A.
In bypass mode, programming of the MAX9257A/
MAX9258A registers are temporarily or permanent-
ly blocked depending on the programmed value of
CTO. Blocking prevents unintentional programming of
the MAX9257A/MAX9258A registers when the ECU
communicates with the peripheral using a UART protocol
different than the one specified to program the devices.
When the control channel is open, the MAX9258A con-
tinues outputting the pixel clock while HSYNC and video
data are held at the last value. If spread is enabled on the
MAX9258A, the pixel clock is spread.
Program STO to be longer than the time the ECU takes to
respond to opening of channel. Program ETO to be lon-
ger than the time the ECU pauses between transactions.
As long as the ECU performs transactions, ETO is reset
and the channel stays open.
The ECU must wait 14 or more bit times before address-
ing another device during the same control channel
session. Failure to wait 14 bit times may result in the
packet boundary not being reset. Internal handshaking
operations are automatically performed after the channel
is closed and before the video phase begins.
Control Channel Overhead
Control channel overhead consists of lock frame, short
synchronization sequence, and error frame. The lock
frame is transmitted between the MAX9257A and the
MAX9258A without action by the ECU. The error frame
is only sent in response to end frame. When MAX9257A
spread spectrum is enabled, the control channel is
entered after spread reaches center frequency. The over-
head from VSYNC falling edge to control channel enable
accounts for a maximum of 1400 pixel clock cycles.
UART-to-I2C Converter
2
The UART-to-I C converter accepts UART read or write
2
packets issued by the ECU and converts them to an I C
master protocol when in base mode. A slave can use an
ACK or NACK to indicate a busy or wait state, but cannot
hold SCL low to indicate a wait state. Multiple slaves are
Base Mode (Details)
2
supported. The UART-to-I C conversion delay is less than
Base mode allows the ECU to communicate with the
22 UART bit times and needs to be taken into account
when setting the ETO and STO timeout periods for read
2
devices in UART and a peripheral device in I C. UART
programming of the peripheral device is not possible in
base mode. UART packets from the ECU need to follow
a certain protocol to program the MAX9257A and the
2
commands. UART-to-I C converter converts standard
2
UART format to standard I C format (Figure 25). This
���������������������������������������������������������������� Maxim Integrated Products ±6
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
includes data-bit ordering conversion because UART
with the peripheral device. Once bypass mode is entered,
the devices stay in bypass mode until CTO times out.
2
transmits the LSB in first while I C transmits the MSB first.
2
UART/I C read delay is a maximum 34 bit times when
In bypass mode, the STO and ETO timers determine the
control channel duration. CTO timer determines whether to
revert back to base mode or not, and EF is not recognized.
2
reading from an I C peripheral.
The devices store their own 7-bit device addresses
in register REG5. All packets not addressed to the
MAX9257A/MAX9258A are forwarded to the UARTto-
A useful setting in bypass mode is to set STO > CTO >
ETO because this setting is an alternative to permanent
bypass (Figure 24). Use this setting to stay in bypass
mode to avoid the overhead of entering from base mode
every time the control channel opens. If the ECU uses
the channel within a CTO timeout, ETO is activated and
then ETO times out before CTO. The channel closes
because ETO times out, but channel stays in bypass
mode because CTO does not time out. At the next verti-
cal blanking time, bypass mode continues with CTO
reset and the ECU can immediately send commands to
the camera. If the ECU or camera does not use the chan-
nel, CTO times out before STO. STO closes the channel
(because ETO is not enabled) if no communication is
sent, but since CTO timed out, bypass mode ends and
base mode is active for the next vertical blanking period.
2
2
I C converter. The I C interfaces (SDA and SCL) are
open drain and actively drive a low state. When idle,
SDA and SCL are high impedance and pulled high by a
pullup resistor. SDA and SCL are idle when packets are
addressed to the MAX9257A or MAX9258A. SDA and
2
SCL are also idle when the I C interface is programmed
to be disabled.
Bypass Mode (Details)
In bypass mode, ECU activity and UART communication
from the camera reset the ETO and CTO timers. This
allows the control channel to stay in bypass as long as
there is camera activity. In base mode, only ECU activity
resets the ETO and CTO timers.
Bypass mode temporarily or permanently blocks pro-
gramming of the devices. Bypass mode allows only UART
programming of peripheral device by ECU. There is no
With STO > CTO > ETO, bypass mode can be made
continuous by having the ECU send real commands or
dummy commands (such as a command to a nonexisting
address) each time the control channel opens. Then the
ECU does not have to send a command to enter bypass
mode each time it wants to program the peripheral device.
2
I C connection in bypass mode. Bypass mode is entered
by writing a 0 to INTMODE and by writing a 1 to INTEN
(Table 23). Bypass mode disables ECU programming of
the devices to allow any UART communication protocol
VSYNC_IN
ECU
ACTIVITY
T1
T2
T5
T1
T2
T5
SDI/O
CCEN
VIDEO
HSK
VIDEO
VIDEO
HSK
VIDEO
T4
T3
TX
RX
DOUT_
FROZEN
FROZEN
T3
CONTROL
CHANNEL
BYPASS MODE
BYPASS MODE
BASE MODE
T1 = TIME TO ENTER CONTROL CHANNEL
T2 = STO TIMER
STO > CTO > ETO
T3 = CTO TIMER
T4 = ETO TIMER
T5 = CONTROL CHANNEL EXIT TIME
HSK = HANDSHAKING BETWEEN THE MAX9257 & THE MAX9258
= TIMER RESET
Figure 24. CTO Timing
���������������������������������������������������������������� Maxim Integrated Products ±7
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
synchronization frame sets the operating baud rate of the
control channel. At power-up, UART data rate must be
between 95kbps to 400kbps. After power-up, UART data
rate can be programmed according to Tables 28 and 29.
Data is serialized starting with the LSB first. The synchro-
nization frame is 0x54 as shown in Figure 27.
UART
UART Frame Format
The UART frame used to program the MAX9257A and the
MAX9258A has a low start bit, eight data bits, an even
parity bit and a high stop bit. The data following the start
bit is the LSB. With even parity, when there are an odd
number of 1s in the data bits (D0 through D7) the parity
bit is set to 1. The stop bit is sampled and if it is not high,
a frame error is generated (Figure 26).
Write Packet
The ECU writes the sync frame, 7-bit device address plus
read/write bit (R/W = 0 for write), 8-bit register address,
number of bytes to be written, and data bytes (Figure 28).
The ECU must follow this UART protocol to correctly pro-
gram the devices.
UART Synchronization Frame
The synchronization frame must precede any read or
write packets (Figure 26). Transitions in the frame cali-
brate the oscillators on the devices. The baud rate of the
UART
MAX9258
ECU
LSB
MSB LSB
MSB
LSB
MSB
2
REG ADDR
DATA 0
DATA N
I C SLAVE ADDRESS + Wr
2
I C
PERIPHERAL
DATA 0
MAX9257
REG ADDRESS
S
A
DATA N
A
P
W
SLAVE ADDRESS
A
A
MSB
LSB
MSB
MSB
LSB
LSB
2
Figure 25. UART-to-I C Conversion
D1
D3
D5
D6
D7
STOP
START
D0
D2
D4
PARITY
Figure 26. UART Frame Format
SYNCHRONIZATION FRAME
STOP
DEV ADDR +
R/W
REG ADDRESS
SYNC
NUMBER OF BYTES
BYTE 1
BYTE N
0
1
1
1
1
1
0
0
0
0
0
PARITY
START
4
5
Figure 27. UART Synchronization Frame
Figure 28. UART Write Packet to MAX9257A/MAX9258A
���������������������������������������������������������������� Maxim Integrated Products ±8
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
Read Packet
The ECU writes the sync frame, 7-bit device address plus
DEV ADDR +
R/W
SYNC
REG ADDRESS
NUMBER OF BYTES
read/write bit (R/W = 1 for read), 8-bit register address,
and number of bytes to be read. The addressed device
responds with read data bytes (Figure 29). UART read
delay is maximum 4 bit times when reading from the
MAX9257A or the MAX9258A.
BYTE N
BYTE 1
Figure 29. UART Read Packet
Time Between Frames
Up to two high bit times are allowed between frames.
Table 28. Control Channel Data Rate in
Base Mode
Reset of Packet Boundary
A high time ranging from 14 UART bit times or more
resets the packet boundary. In this case, the next frame
received is assumed to belong to a new packet by
MAX9257A REG8[1:0]
RANGE
MAX9258A REG7[1:0]
2
the MAX9257A/MAX9258A and UART-to-I C converter.
95kbps–400kbps
Resetting the boundary is required. Not resetting the
boundary treats the following packets as part of the first
packet, and they may be processed incorrectly.
00
(default)
01
10
11
400kbps–1Mbps
1Mbps–4.25Mbps
1Mbps–4.25Mbps
Data Rate
The control channel data rate in base mode is between
95kbps to 4.25Mbps (Table 28). In bypass mode, the
allowed data rate is DC to 10Mbps (Table 29). For data
rates faster than 4.25Mbps in bypass mode, REG8[5]
in MAX9257A and REG7[5] in MAX9258A must be set
high. Set the control channel data rate in base mode by
writing to REG8[1:0] in the MAX9257A and REG7[1:0] in
the MAX9258A. These write commands take effect in the
next control channel.
Table 29. Control Channel Data Rate in
Bypass Mode
MAX9257A REG8[5]
RANGE
MAX9258A REG7[5]
0
1
DC–4.25Mbps
Programming the FAST bit takes effect in the same con-
trol channel. Both the MAX9257A and the MAX9258A
should have the same settings for FAST. It is recom-
mended to first program the FAST bit in the MAX9257A.
Programming FAST to 1 results in shorter UART pulses
on the differential link.
4.25Mbps–10Mbps
Table ±0. Default Device Address
DEFAULT
DEVICE
BINARY
MAX9257A/MAX9258A
Device Address Programming
The MAX9257A/MAX9258A have device addresses that
can be programmed to any 7-bit address. Table 30
shows the default addresses.
HEX
0xFA
0xF8
MAX9257A
MAX9258A
1111 1010
1111 1000
���������������������������������������������������������������� Maxim Integrated Products ±9
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
2
2
I C Timing
I C
2
2
The MAX9257A acts like a master in I C communication
with the peripheral device. The MAX9257A takes less
than 22 UART bit times to convert UART packets into I C.
The SCL and SDA timings are based on the UART bit
clock. The I C data rate is determined by UART and can
range from 95kbps to 4.25Mbps. The I C timing require-
ments scale linearly from fast mode to higher speeds.
Table 31 shows the I C timing information for data rates
greater than 400kbps. The I C parameters scale with
The MAX9257A features a UART-to-I C converter that
converts UART packets to I C. The UART-to-I C con-
verter works as a repeater between the ECU and external
I C slave devices. The MAX9257A acts as the master
and converts UART read/write packets from the ECU to
I C read/write for external I C slave devices. For writes,
the UART-to-I C converts the UART packets received
directly into I C. For reads, the UART-to-I C converter
follows the UART packet protocol. The I C SCL clock
2
2
2
2
2
2
2
2
2
2
2
2
2
2
t
. See Figure 30 for timing parameters.
period is approximately the same as the UART bit clock
period (tUCLK). The I C speed varies with UART speed.
UCLK
2
2
I C reads from the peripheral device do not disable the
2
ETO timer. Choose ETO large enough so that I C read
commands are not lost due to ETO timing out.
2
Table ±1. Timing Information for I C Data Rates Greater than 400kbps
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
SCL Clock Frequency
f
1
1
t
UCLK*
SCL
Start Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
Repeated START Condition Setup Time
Data Hold Time
t
1
1
t
HD:STA
UCLK
UCLK
UCLK
UCLK
UCLK
UCLK
UCLK
UCLK
t
0.5
0.5
0.25
0.25
0.25
0.25
0.5
0.5
0.5
0.25
0.25
0.25
0.25
0.5
t
LOW
t
t
t
t
t
t
t
HIGH
t
SU:STA
HD:DAT
t
Data Setup Time
t
SU:DAT
SU:STO
Setup Time for STOP Condition
Bus Free Time
t
t
BUF
*t
is equal to one UART period.
UCLK
t
F
t
R
t
t
LOW
HD;STA
SCL
t
t
t
HD;DAT
t
SU;STA
HD;STA
SU;STO
t
SU;DAT
t
HIGH
SDA
t
BUF
S
P
S
P
2
Figure 30. I C Timing Parameters
���������������������������������������������������������������� Maxim Integrated Products 40
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
Activity Detector
Applications Information
Most applications use the default activity-detector set-
tings. If there is excessive noise on the link when the link
is not driven (during control channel mode), increase
the activity-detector offset to filter out noise amplitudes.
Using a larger offset threshold affects the maximum data
lists the maximum recommended
data rate at different input offset settings for a 150mV
peak input signal.
PRBS Test
The devices have built-in circuits for testing bit errors
on the serial link. The MAX9257A has a PRBS generator
and the MAX9258A has a PRBS checker. The length of
the PRBS pattern is programmable from 221 to 235 word
length or continuous by programming REG9[7:4] in the
MAX9257A. In case of errors, errors are counted in the
MAX9258A PRBSERR register (REG12), and the ERROR
output on the MAX9258A goes low. To start the test, the
ECU writes a 1 to PRBSEN bit of both the MAX9257A
and the MAX9258A. The PRBS test can be performed
with or without spread spectrum. If the PRBS test is
programmed to run continuously, the MAX9257A must
be powered down to stop the test. When programmed
for a finite number of repetitions, the control channel is
enabled after the PRBS test finishes and serialization
enable (SEREN) is reset to 0. To start normal operation,
the ECU must disable PRBSEN and enable SEREN.
Table 32
rate available.
AC-Coupling Benefits
AC-coupling increases the input voltage of the LVDS
receiver to the voltage rating of the capacitor. Two from
18MHz to 42MHz capacitors are sufficient for isolation,
but four capacitors—two at the serializer output and two at
the deserializer input—provide protection if either end of
the cable is shorted to a high voltage. AC-coupling blocks
low-frequency ground shifts and common-mode noise.
Selection of AC-Coupling Capacitors
See Figure 31 for calculating the capacitor values for
AC-coupling depending on the parallel clock frequency.
The plot shows minimum capacitor values for two- and
four-capacitor-per-link systems. To block the highest
common-mode frequency shift, choose the minimum
capacitor value shown in Figure 31. In general, 0.1FF
capacitors are sufficient.
Video Data Parity
Parity protection of video data is programmable for par-
allel-word widths of 16 bits or less. When programmed,
two parity bits are appended to each parallel word
latched into the MAX9257A. In the MAX9258A, a 16-bit
parity error counter logs parity errors. The ERROR out-
put on the MAX9258A goes low if parity errors exceed a
programmable threshold.
AC-COUPLING CAPACITOR VALUE
vs. SERIAL-DATA RATE
Table ±2. Maximum Data Rate at Different
Input Offset Settings
60
FOUR CAPACITORS PER LINK
OFFSET BITS
(REG1[4:±)
TYPICAL INPUT
OFFSET (mV)
MAXIMUM
FREQUENCY (Mbps)
40
00
01
10
11
23
11
59
75
780
940
520
400
20
TWO CAPACITORS PER LINK
0
360 420 480 540 600 660 720 780 840
SERIAL-DATA RATE (Mbps)
Figure 31. AC-Coupling Capacitor Values vs. Clock Frequency
from 18MHz to 42MHz
���������������������������������������������������������������� Maxim Integrated Products 41
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
Optimally Choosing AC-Coupling Capacitors
Jitter due to droop is proportional to the droop and tran-
sition time:
Voltage droop and the digital sum variaton (DSV) of
transmitted symbols cause signal transitions to start
from different voltage levels. Because the transition time
is finite, starting the signal transition from different volt-
age levels causes timing jitter. The time constant for an
AC-coupled link needs to be chosen to reduce droop
and jitter to an acceptable level. The RC network for an
AC-coupled link consists of the LVDS receiver termina-
t = t x D
J
TT
where:
t = jitter(s)
J
t
= transition time(s) (0 to 100%)
TT
D = droop (% of signal amplitude)
Jitter due to 2% droop and assumed 1ns transition time is:
tion resistor (R ), the LVDS driver termination resistor
TR
(R ), and the series AC-coupling capacitors (C). The
TD
t = 1ns x 0.02
J
RC time constant for four equal-value series capacitors is
t = 20ps
J
(C x (R + R ))/4. RTD and RTR are required to match
TD
TR
The transition time in a real system depends on the fre-
quency response of the cable driven by the serializer.
the transmission line impedance (usually 100I). This
leaves the capacitor selection to change the system time
constant. In the following example, the capacitor value
for a droop of 2% is calculated:
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter.
Use high-frequency, surface-mount ceramic capacitors.
4×t ×DSV
B
C = −
ln(1- D)×(R +R
)
TD
Power-Supply Circuits and Bypassing
All single-ended inputs and outputs on the MAX9257A
TR
where:
C = AC-coupling capacitor (F)
are powered from V
MAX9258A are powered from V
can be connected to a +1.71V to +3.6V supply. The input
levels or output levels scale with these supply rails.
. All single-ended outputs on the
CCIO
. V
and V
CCOUT CCIO CCOUT
t = bit time(s)
B
DSV = digital sum variation (integer)
ln = natural log
Board Layout
Separate the LVCMOS/LVTTL signals and LVDS signals
to prevent crosstalk. A four-layer PCB with separate
layers for power, ground, LVDS, and digital signals is
recommended. Layout PCB traces for 100I differential
characteristic impedance. The trace dimensions depend
on the type of trace used (microstrip or stripline). Note
that two 50I PCB traces do not have 100I differential
impedance when brought close together—the imped-
ance goes down when the traces are brought closer.
D = droop (% of signal amplitude)
R
R
= driver termination resistor (I)
TD
= receiver termination resistor (I)
TR
The bit time (t ) is the serial-clock period or the period
B
of the pixel clock divided by the total number of bits. The
maximum DSV for the MAX9257A encoding equals to the
total number of bits transmitted in one pixel clock cycle.
This means that t x DSV = t .
B
T
Route the PCB traces for an LVDS channel (there are
two conductors per LVDS channel) in parallel to maintain
the differential characteristic impedance. Place the 100I
(typ) termination resistor at both ends of the LVDS driver
and receiver. Avoid vias. If vias must be used, use only
one pair per LVDS channel and place the via for each
line at the same point along the length of the PCB traces.
This way, any reflections occur at the same time. Do not
make vias into test points for ATE. Make the PCB traces
that make up a differential pair the same length to avoid
skew within the differential pair.
The capacitor for 2% maximum droop at 16MHz parallel
rate clock is:
4×t ×DSV
B
C = -
ln(1- D)×(R +R
)
TD
TR
Total number of bits is = 10 (data) + 2 (HSYNC and
VSYNC) + 2 (encoding) + 2 (parity) = 16
4×3.91ns×16
C = -
ln(1- .02)×(100Ω+100Ω)
C ≥ 0.062FF
���������������������������������������������������������������� Maxim Integrated Products 42
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
Cables and Connectors
Choosing I2C Pullup Resistors
2
Interconnect for LVDS typically has a differential imped-
ance of 100I. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Twisted-pair and shielded twisted-pair
cables offer superior signal quality compared to ribbon
cable and tend to generate less EMI due to magnetic
field canceling effects. Balanced cables pick up noise
as common mode that is rejected by the LVDS receiver.
I C requires pullup resistors to provide a logic-high level
to data and clock lines. There are tradeoffs between
power dissipation and speed, and a compromise must
be made in choosing pullup resistor values. Every device
connected to the bus introduces some capacitance even
2
when device is not in operation. I C specifies 300ns
rise times to go from low to high (30% to 70%) for fast
mode, which is defined for a date rate up to 400kbps
(see I C specifications for details). To meet the rise time
2
requirement, choose the pullup resistors so the rise time
t
= 0.85R
x C
< 300ns. If the transition time
R
PULLUP
BUS
becomes too slow, the setup and hold times may not be
met and waveforms will not be recognized.
MAX9257A Register Table
ADDRESS
BITS
DEFAULT
NAME
DESCRIPTION
Pixel clock frequency range
00 = 5MHz to 10MHz
7:6
10
PRATE
01 = 10MHz to 20MHz
10 = 20MHz to 40MHz (default)
11 = 40MHz to 70MHz
Serial-data rate range
00 = 60Mbps to 100Mbps
01 = 100Mbps to 200Mbps
10 = 200Mbps to 400Mbps
11 = 400Mbps to 840Mbps (default)
5:4
3
11
0
SRATE
PAREN
0
Parity enable
0 = disabled (default), 1 = enabled
Parallel data width
(includes HSYNC and VSYNC, excludes DCB, INV, and parity bits)
000 = 10
001 = 12
010 = 14
011 = 16
100 = 18
101 = 18 (default)
110 = 18
2:0
101
PWIDTH
111 = 18
Spread-spectrum setting
For PRATE ranges 00, 01: all spread options possible
For PRATE ranges 10, 11: maximum spread is 2%
7:5
4:0
000
SPREAD
000 = Off (default)
001 = 1.5%
010 = 1.75%
011 = 2%
100 = Off
101 = 3%
110 = 3.5%
111 = 4%
1
11111
Reserved (set to 11111)
���������������������������������������������������������������� Maxim Integrated Products 4±
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
MAX9257A Register Table (continued)
ADDRESS
BITS
DEFAULT
NAME
DESCRIPTION
Control channel start timeout: (STO) times out if ECU does not start using control channel within this amount of
time after control channel session is enabled.
Control channel start timeout divider
Pixel clock is first divided by:
0000 = 16
0001 = 16
0010 = 16
0011 = 16
0100 = 16
0101 = 32
0110 = 64
0111 = 128
1000 = 256
1001 = 512
1010 = 1024 (default)
1011 = 2048
1100 = 4096
1101 = 8192
1110 = 16,384
1111 = 32,768
2
7:4
1010
STODIV
Control channel start timeout counter
Divided pixel clock is used to count up to (STOCNT + 1)
3:0
0000
STOCNT
Control channel end timeout: (ETO) times out if ECU does not use control channel for this amount of time after it
has already used at least once.
Control channel end timeout divider
Pixel clock is first divided by:
0000 = 16
0001 = 16
0010 = 16
0011 = 16
0100 = 16
0101 = 32
0110 = 64
0111 = 128
1000 = 256
1001 = 512
1010 = 1024 (default)
1011 = 2048
1100 = 4096
1101 = 8192
1110 = 16,384
1111 = 32,768
3
7:4
3:0
1010
0000
ETODIV
Control channel end timeout counter
Divided pixel clock is used to count up to (ETOCNT + 1)
ETOCNT
���������������������������������������������������������������� Maxim Integrated Products 44
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
MAX9257A Register Table (continued)
ADDRESS
BITS
DEFAULT
NAME
DESCRIPTION
VSYNC active edge at camera interface
7
6
5
0
0
1
VEDGE
0 = falling (default), 1 = rising
Reserved (set to 0)
PCLK active edge at camera interface
0 = falling, 1 = rising (default)
CKEDGE
PD
Power mode
0 = power-up, 1 = power-down
(when REM = 1 default is 1)
4
3
0
1
4
Serialization enable
0 = disabled, 1 = enabled
(when REM = 1 default is 0)
SEREN
Bypass filter PLL
0 = active (default), 1 = bypass
2
1
0
0
0
0
BYPFPLL
Reserved (set to 0)
PRBS test enable
0 = disabled (default), 1 = enabled
PRBSEN
7:1
0
1111101
DEVICEID
7-bit address of MAX9257A
Reserved (set to 0)
5
6
7
0
7:1
0
1111111
EF
End frame to close control channel
Reserved (set to 1)
1
1111100
0
7:1
0
DESID
7-bit address ID of MAX9258A
Reserved (set to 0)
Interface mode
7
6
5
0
0
0
INTMODE
INTEN
0 = UART (default), 1 = I2C
Interface enable
0 = disabled (default), 1 = enabled
Fast UART transceiver
0 = bit rate = DC to 4.25Mbps (default), 1 = bit rate = 4.25Mbps to 10Mbps
FAST
Timer to come back from bypass mode (in bit time)
8
000 = never come back (default)
100 = 64
101 = 80
110 = 96
111 = 112
4:2
1:0
000
00
CTO
001 = 16
010 = 32
011 = 48
Control channel bit rate range in base mode
00 = 95kbps to 400kbps (default)
01 = 400kbps to 1000kbps
BITRATE
10 = 1000kbps to 4250kbps
11 = 1000kbps to 4250kbps
���������������������������������������������������������������� Maxim Integrated Products 45
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
MAX9257A Register Table (continued)
ADDRESS
BITS
DEFAULT
NAME
DESCRIPTION
PRBS test number of words
1111 = continuous
7:4
0000
PRBSLEN
else = 2(PRBSLEN + 21)
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIO9DIR
GPIO8DIR
GPIO9*
GPIO 9 direction
GPIO 8 direction
0 = input (default), 1 = output
0 = input (default), 1 = output
9
General purpose input output 9
General purpose input output 8
GPIO8*
GPIO7DIR
GPIO6DIR
GPIO5DIR
GPIO4DIR
GPIO3DIR
GPIO2DIR
GPIO1DIR
GPIO0DIR
GPIO7*
GPIO 7 direction
GPIO 6 direction
GPIO 5 direction
GPIO 4 direction
GPIO 3 direction
GPIO 2 direction
GPIO 1 direction
GPIO 0 direction
0 = input (default), 1 = output
0 = input (default), 1 = output
0 = input (default), 1 = output
0 = input (default), 1 = output
0 = input (default), 1 = output
0 = input (default), 1 = output
0 = input (default), 1 = output
0 = input (default), 1 = output
10
General purpose input output 7
General purpose input output 6
General purpose input output 5
General purpose input output 4
General purpose input output 3
General purpose input output 2
General purpose input output 1
General purpose input output 0
LVDS driver preemphasis setting
GPIO6*
GPIO5*
GPIO4*
11
GPIO3*
GPIO2*
GPIO1*
GPIO0*
000 = 20%
001 = 40%
010 = 60%
011 = 80%
100 = 100%
111 = off (default)
101 = 20%
110 = 20%
7:5
111
PREEMP
12
13
4:0
7:2
00000
Reserved (set to 00000)
Reserved (set to 000000)
I2C glitch filter setting
00 = set according to programmed bit rate (default)
100ns at (95kbps to 400kbps) bit rate
50ns at (400kbps to 1000kbps) bit rate
10ns at (1000kbps to 4250kbps) bit rate
01 = 10ns, 10 = 50ns, 11 = 100ns
000000
1:0
00
I2CFILT
7:1
0
(RO)
(RO)
(RO)
Reserved
14
15
LOCKED
PLL locked to pixel clock
Reserved
7:0
���������������������������������������������������������������� Maxim Integrated Products 46
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
MAX9258A Register Table
ADDRESS
BITS
DEFAULT
NAME
DESCRIPTION
Pixel clock frequency range
00 = 5MHz to 10MHz
7:6
10
PRATE
01 = 10MHz to 20MHz
10 = 20MHz to 40MHz (default)
11 = 40MHz to 70MHz
Serial-data rate range
00 = 60Mbps to 100Mbps
01 = 100Mbps to 200Mbps
10 = 200Mbps to 400Mbps
11 = 400Mbps to 840Mbps (default)
5:4
3
11
0
SRATE
PAREN
0
Parity enable
0 = disabled (default), 1 = enabled
Parallel data width
(includes HSYNC and VSYNC, excludes encoding and parity bits)
000 = 10
001 = 12
010 = 14
011 = 16
100 = 18
101 = 18 (default)
110 = 18
2:0
101
PWIDTH
111 = 18
Spread-spectrum setting
00 = Off (default)
01 = 2%
7:6
5
00
0
SPREAD
AER
10 = Off
11 = 4%
Autoerror reset
1 = Reset error count when control channel ends.
0 = Reset upon reading error registers 10, 11, 13 (default)
1
Activity detector offset level
00 = 23mV offset
4:3
2:0
00
ACTOFFSET 01 = 11mV offset
10 = 59mV offset
11 = 75mV offset
000
Reserved (set to 000)
Control channel start timeout: (STO) times out if ECU does not start using control channel within this amount of
time after control channel session is enabled.
Control channel start timeout divider
Pixel clock is first divided by :
0000 = 16
0001 = 16
0010 = 16
0011 = 16
0100 = 16
0101 = 32
0110 = 64
0111 = 128
1000 = 256
1001 = 512
1010 = 1024 (default)
1011 = 2048
1100 = 4096
1101 = 8192
1110 = 16,384
1111 = 32,768
2
7:4
3:0
1010
0000
STODIV
Control channel start timeout counter
Divided pixel clock is used to count up to (STOCNT + 1)
STOCNT
���������������������������������������������������������������� Maxim Integrated Products 47
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
MAX9258A Register Table (continued)
ADDRESS
BITS
DEFAULT
NAME
DESCRIPTION
Control channel end timeout: (ETO) times out if ECU does not use control channel for this amount of time after it
has already used at least once.
Control channel end timeout divider
Pixel clock is first divided by:
0000 = 16
0001 = 16
0010 = 16
0011 = 16
0100 = 16
0101 = 32
0110 = 64
0111 = 128
1000 = 256
1001 = 512
1010 = 1024 (default)
1011 = 2048
1100 = 4096
1101 = 8192
1110 = 16,384
1111 = 32,768
3
7:4
1010
ETODIV
Control channel end timeout counter
Divided pixel clock is used to count up to (ETOCNT + 1)
3:0
7
0000
ETOCNT
VEDGE
VSYNC active edge at ECU interface
0 = falling (default), 1 = rising
0
0
HSYNC active edge at ECU interface
0 = falling (default), 1 = rising
6
HEDGE
CKEDGE
PCLK active edge at ECU interface
0 = falling, 1 = rising (default)
5
4
1
0
4
Reserved (set to 0)
0 = stretcher output pulse is short
1 = stretcher output pulse is long
3
0
ACTLP
2:1
0
00
0
Reserved (set to 00)
PRBS test enable
0 = disabled (default), 1 = enabled
PRBSEN
7:1
0
1111100
DEVICEID
7-bit address of MAX9258A
Reserved (set to 0)
5
6
0
1111111
1
7:1
0
EF
End frame to close control channel
Reserved (set to 1)
���������������������������������������������������������������� Maxim Integrated Products 48
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
MAX9258A Register Table (continued)
ADDRESS
BITS
DEFAULT
NAME
DESCRIPTION
7
6
0
0
INTMODE
INTEN
Interface mode
0 = UART (default), 1 = I2C
0 = disabled (default), 1 = enabled
Interface enable
Fast UART transceiver
0 = bit rate = DC to 4.25Mbps (default), 1 = bit rate = 4.25Mbps to 10 Mbps
5
0
FAST
Timer to come back from bypass mode (in bit time)
000 = never come back (default)
100 = 64
101 = 80
110 = 96
111 = 112
4:2
000
CTO
001 = 16
010 = 32
011 = 48
7
Control channel bit rate range in base mode
00 = 95kbps to 400kbps (default)
01 = 400kbps to 1000kbps
1:0
00
BITRATE
10 = 1000kbps to 4250kbps
11 = 1000kbps to 4250kbps
Threshold for number of video parity errors (8 LSBs)
If the number of errors exceeds this value, ERR pin is asserted.
8
9
7:0
7:0
00010000
00000000
PATHRLO
PATHRHI
Threshold for number of video parity errors (8 MSBs)
If the number of errors exceeds this value, ERR pin is asserted.
10
11
7:0
7:0
(RO)
(RO)
PAERRLO
PAERRHI
Number of video parity errors (8 LSBs)
Number of video parity errors (8 MSBs)
PRBS test number of bit errors
12
7:0
(RO)
PRBSERR
Automatically reset when PRBS test is disabled
0xFF indicates 255 or more errors
7:5
4
(RO)
(RO)
(RO)
(RO)
(RO)
(RO)
(RO)
Reserved
DESPERR
DESFERR
SERPERR
SERFERR
I2CERR
Parity error during communication with deserializer
Frame error during communication with deserializer
Parity error during communication with serializer
Frame error during communication with serializer
Error during communication with camera in I2C mode
Reserved
3
13
14
2
1
0
7:0
���������������������������������������������������������������� Maxim Integrated Products 49
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
Body Model and Machine Model ESD tolerances. The
Human Body Model discharge components are C
ESD Protection
The MAX9257A/MAX9258A ESD tolerance is rated for
Human Body Model, Machine Model, IEC 61000-4-2
and ISO 10605. The ISO 10605 and IEC 61000-4-2
standards specify ESD tolerance for electronic systems.
LVDS outputs on the MAX9257A and LVDS inputs on
the MAX9258A meet ISO 10605 ESD protection and IEC
61000-4-2 ESD protection. All other pins meet the Human
=
S
100pF and R = 1.5kI (Figure 33). The IEC 61000-4-2
D
discharge components are C = 150pF and R = 330I
S
D
(Figure 32). The ISO 10605 discharge components are
= 330pF and R = 2kI (Figure 34). The Machine
C
S
D
Model discharge components are C = 200pF and R
0I (Figure 35).
=
S
D
R
R
D
D
1MI
330I
1.5kI
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
C
S
C
S
100pF
STORAGE
CAPACITOR
STORAGE
CAPACITOR
150pF
SOURCE
SOURCE
Figure 32. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Figure 33. Human Body ESD Test Circuit
R
D
R
D
2kI
0I
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
C
S
200pF
C
S
330pF
STORAGE
CAPACITOR
STORAGE
CAPACITOR
SOURCE
SOURCE
Figure 34. ISO 10605 Contact Discharge ESD Test Circuit
Figure 35. Machine Model ESD Test Circuit
���������������������������������������������������������������� Maxim Integrated Products 50
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
Functional Diagram
BYPASS
MAX9257A SERIALIZER
PCLK_IN
DIN[0:15]
1.5% TO 4%
LVDS Tx
FILTER PLL
SPREAD PLL
1x
CLK IN
CLK OUT
ENCODE/
DC BALANCE
+
PARALLEL TO
SERIAL
SDO-
FIFO
HSYNC_IN
VSYNC_IN
1.2V
BIAS
DIN WIDTH
100
BLANK
DETECT/TIMER
SDO+
OSC
VSYNC
POLARITY
SCL(TX)
SDA(RX)
CONTROL
Tx/Rx
UART
TO I C
2
2
UART-TO-I C BYPASS
TRANSMISSION LINE
= 100
Z
D
MAX9258A DESERIALIZER
2% OR 4%
FREQ
DETECT
PCLK_OUT
DOUT[0:15]
SPREAD PLL
PLL
LVDS Rx
1x
CLK OUT
CLK IN
DECODE/
DC BALANCE
+
SERIAL TO
PARALLEL
FIFO
SDI+
HSYNC_OUT
VSYNC_OUT
DOUT WIDTH
ADDRESS
1.2V
BIAS
100
BLANK
DETECT/TIMER
SDI-
VSYNC
POLARITY
CONTROL
TX/RX
TX
RX
UART
OSC
���������������������������������������������������������������� Maxim Integrated Products 51
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
Typical Operating Circuit
10
UP TO 20m
CABLE LENGTH
10
DATA
PCLK
DATA
PCLK
SERIAL
I/O
SERIAL
I/O
HSYNC
VSYNC
LOCK
100I
100I
ECU
HSYNC
VSYNC
SCL
CMOS
IMAGE
SENSOR
SERIALIZED
DIGITAL VIDEO
MAX9258A
MAX9257A
TX
RX
C
SDA
CONTROL
CHANNEL
CONTROL UNIT
REMOTE CAMERA ASSEMBLY
Chip Information
Ordering Information
PROCESS: BiCMOS
PART
MAX9257AGTL/V+
TEMP RANGE
PIN-PACKAGE
-40NC to +105NC 40 TQFN-EP*
MAX9257AGCM/V+ -40NC to +105NC 48 LQFP
MAX9258AGCM/V+ -40NC to +105NC 48 LQFP
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
40 TQFN
48 LQFP
T4055+1
C48+3
21-0140
21-0054
90-0016
90-009±
���������������������������������������������������������������� Maxim Integrated Products 52
MAX9257A/MAX9258A
Fully Programmable Serializer/Deserializer
2
with UART/I C Control Channel
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
DESCRIPTION
CHANGED
0
1
6/11
9/11
Initial release
—
Changed ACTOFFSET range settings from 00 = 11mV to 23mV and 01 =
23mV to 11mV
7, 24, 41, 47
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
5±
©
2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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