MAX9265GCM/V+W [MAXIM]
Line Driver;
| 型号： | MAX9265GCM/V+W |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Line Driver |
| 文件： | 总50页 (文件大小：1991K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5646; Rev 0; 12/10
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
General Description
Features
The MAX9265 gigabit multimedia serial link (GMSL)
serializer features an LVDS system interface and
high-bandwidth digital content protection (HDCP)
encryption for content protection of DVD and Blu-ray™
video and audio data. The serializer pairs with any HDCP
GMSL deserializer to form a digital serial link for the
transmission of control data and HDCP-encrypted video
and audio data. GMSL is an HDCP technology approved
by Digital Content Protection (DCP), LLC.
S Pairs with Any GMSL Deserializer
S HDCP Encryption Enable/Disable Programmable
with the Control Channel
S Control Channel Handles All HDCP Protocol
Transactions—Separate Control Bus Not Required
S HDCP Keys Preprogrammed in Secure Nonvolatile
Memory
S 2.5Gbps Payload Data Rate (3.125Gbps with
Overhead)
The 3-channel mode serializes three lanes of LVDS data
(21 bits), UART control signals, and three audio inputs.
The 4-channel mode serializes four lanes of LVDS data
(28 bits), UART control signals, three audio inputs, and
auxiliary control inputs. The three audio inputs are for
I2S audio, supporting a sampling frequency from 8kHz
to 192kHz and a sample depth of 4 to 32 bits. The
embedded control channel forms a full-duplex differ-
ential 9.6kbps to 1Mbps UART link between the serial-
izer and deserializer. An electronic control unit (ECU),
or microcontroller (FC), can be located on the serial-
izer side of the link (typical for video display), on the
deserializer side of the link (typical for image sensing),
or on both sides. The control channel enables ECU/FC
control of peripherals on the remote side, such as back-
light control, touch screen, and perform HDCP-related
operations.
S AC-Coupled Serial Link with 8b/10b Line Coding
S 8.33MHz to 104MHz (3-Channel LVDS) or 6.25MHz
to 78MHz (4-Channel LVDS) Pixel Clock
S 4-Bit to 32-Bit Sample Depth, 8kHz to 192kHz I2S
Audio Channel Supports High-Definition Audio
S Embedded Half-/Full-Duplex Bidirectional Control
Channel
Base Mode: 9.6kbps to 1Mbps
Bypass Mode: 9.6kbps to 1Mbps
S Two 3-Level Inputs Support 9 Slave Addresses
S Interrupt Supports Touch-Screen Displays
S Remote-End I2C Master for Peripherals
S Programmable Pre/Deemphasis
S Programmable Spread Spectrum on the Serial
The serial link signaling is AC-coupled CML with 8b/10b
coding. For driving longer cables, the serializer has
programmable driver pre/deemphasis, and for reduced
EMI, has programmable spread spectrum on the serial
output. The serial output meets ISO 10605 and IEC
61000-4-2 ESD standards.
Link and Deserializer Outputs Reduce EMI
S Auto Data-Rate Detection Allows “On-The-Fly”
Data-Rate Change
S Bypassable PLL on LVDS Clock Input for Jitter
Attenuation
The serializer operates with a 1.8V core supply, a 1.8V
to 3.3V I/O supply, and a 3.3V LVDS supply. This device
is available in a 48-pin TQFP package with an exposed
pad and is specified over the -40NC to +105NC automo-
tive temperature range.
S Built-In PRBS Generator for BER Testing of the
Serial Link
S Fault Detection of Serial Link Shorted Together, to
Ground, to Battery, or Open
S ISO 10605 and IEC 61000-4-2 ESD Tolerance
Applications
High-Resolution Automotive Navigation
Rear-Seat Infotainment
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
Megapixel Camera Systems
MAX9265GCM/V+
-40NC to +105NC 48 TQFP-EP*
MAX9265GCM/V+T -40NC to +105NC 48 TQFP-EP*
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape and reel.
Blu-ray is a trademark of Blu-ray Disc Association.
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ....................................................-0.5V to +1.9V
DVDD to GND ......................................................-0.5V to +1.9V
IOVDD to GND .....................................................-0.5V to +3.9V
LVDSVDD to AGND..............................................-0.5V to +3.9V
Any Ground to Any Ground .................................-0.5V to +0.5V
RXIN__, RXCLKIN_ to AGND...............................-0.5V to +3.9V
OUT+, OUT- to AGND .........................................-0.5V to +1.9V
LMN_ to AGND (15mA current limit)....................-0.5V to +3.9V
Junction-to-Case Thermal Resistance (B ) (Note 1)
JC
48-Lead TQFP.................................................................2NC/W
Junction-to-Ambient Thermal Resistance (B ) (Note 1)
JA
48-Lead TQFP............................................................27.6NC/W
Operating Temperature Range........................ -40NC to +105NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
All Other Pins to GND ........................-0.5V to (V
+ 0.5V)
IOVDD
Continuous Power Dissipation (T = +70NC )
A
48-Lead TQFP (derate 36.2mW/NC above +70NC)..2898.6mW
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
AVDD
= V
= 1.7V to 1.9V, V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100I Q1% (differential), T = -40NC to
IOVDD L A
DVDD
LVDSVDD
+105NC, unless otherwise noted. Differential input voltage |V | = 0.1V to 1.2V, input common-mode voltage V
= |V /2| to 2.4V -
ID
ID
CM
|V /2|. Typical values are at V
ID
= V
= V
= 1.8V, V = 3.3V, T = +25NC.)
LVDSVDD A
AVDD
DVDD
IOVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (SD/CNTL0, SCK, WS, CNTL1, CNTL2, SSEN, DRS, BWS, PWDN , CDS, MS, AUTOS)
0.65 x
PWDN, SSEN, BWS, DRS, MS, CDS,
V
AUTOS
IOVDD
High-Level Input Voltage
V
V
V
IH1
0.7 x
V
SD/CNTL0, SCK, WS, CNTL_
IOVDD
0.35 x
Low-Level Input Voltage
Input Current
V
IL1
V
IOVDD
I
V
IN
= 0 to V
IOVDD
-10
+10
FA
IN1
Input Clamp Voltage
V
CL
I
= -18mA
-1.5
V
CL
SINGLE-ENDED OUTPUT (INT)
V
V
IOVDD
- 0.2
High-Level Output Voltage
Low-Level Output Voltage
Output Short-Circuit Current
V
I
I
= -2mA
= 2mA
V
V
OH1
OUT
OUT
V
0.2
64
21
OL1
V
V
= 3.0V to 3.6V
= 1.7V to 1.9V
16
3
35
12
IOVDD
I
V
= V
GND
mA
OS
O
IOVDD
I2C/UART, I/O, AND OPEN-DRAIN OUTPUTS (RX/SDA, TX/SCL, LFLT)
0.7 x
IOVDD
High-Level Input Voltage
V
V
IH2
0.3 x
IOVDD
+5
Low-Level Input Voltage
Input Current
V
V
FA
V
IL2
IN2
OL2
V
I
V
= 0 to V
(Note 2)
-110
IN
IOVDD
V
= 1.7V to 1.9V
= 3.0V to 3.6V
0.4
IOVDD
Low-Level Output Voltage
V
I
= 3mA
OUT
V
0.3
IOVDD
2
______________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
DC ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= 1.7V to 1.9V, V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100I Q1% (differential), T = -40NC to
IOVDD L A
DVDD
LVDSVDD
+105NC, unless otherwise noted. Differential input voltage |V | = 0.1V to 1.2V, input common-mode voltage V
= |V /2| to 2.4V -
ID
ID
CM
|V /2|. Typical values are at V
ID
= V
= V
= 1.8V, V = 3.3V, T = +25NC.)
LVDSVDD A
AVDD
DVDD
IOVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIFFERENTIAL OUTPUTS (OUT+, OUT-)
Differential Output Voltage
Change in V Between
Preemphasis off (Figure 1)
300
350
240
400
500
610
425
V
3.3dB preemphasis setting (Figure 2)
3.3dB deemphasis setting (Figure 2)
mV
OD
OD
DV
15
1.56
15
mV
V
OD
Complementary Output States
Output Offset Voltage
V
OS
Preemphasis off
1.1
-60
1.4
(V
OUT+
+ V )/2 = V
OUT- OS
Change in V
Complementary Output States
Between
OS
DV
mV
mA
mA
I
OS
V
V
or V
or V
= 0V
OUT+
OUT-
Output Short-Circuit Current
I
OS
= 1.9V
25
25
OUT+
OUT-
Magnitude of Differential Output
Short-Circuit Current
I
V
OD
= 0V
OSD
Output Termination Resistance
(Internal)
R
O
From OUT+, OUT- to V
45
54
63
27
AVDD
REVERSE CONTROL-CHANNEL RECEIVER (OUT+, OUT-)
High Switching Threshold
Low Switching Threshold
V
mV
mV
CHR
V
-27
CLR
LINE-FAULT-DETECTION INPUTS (LMN0, LMN1)
Short-to-GND Threshold
Normal Thresholds
V
V
Figure 3
Figure 3
0.3
V
V
TG
TN
0.57
1.45
1.07
V
IO
+
Open Thresholds
V
TO
Figure 3
V
60mV
Open Input Voltage
V
Figure 3
Figure 3
1.47
2.47
1.75
V
V
IO
Short-to-Battery Threshold
V
TE
THREE-LEVEL LOGIC INPUTS (ADD0, ADD1)
0.7 x
High-Level Input Voltage
Low-Level Input Voltage
Mid-Level Input Current
V
V
V
IH
V
IOVDD
0.3 x
V
IL
V
IOVDD
Unconnected or connected to a driver with
output in high-impedance state (Note 3)
I
-10
+10
FA
INM
Input Current
I
-150
+150
-1.5
FA
IN
Input Clamp Voltage
V
I
= -18mA
CL
V
CL
_______________________________________________________________________________________
3
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
DC ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= 1.7V to 1.9V, V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100I Q1% (differential), T = -40NC to
IOVDD L A
DVDD
LVDSVDD
+105NC, unless otherwise noted. Differential input voltage |V | = 0.1V to 1.2V, input common-mode voltage V
= |V /2| to 2.4V -
ID
ID
CM
|V /2|. Typical values are at V
ID
= V
= V
= 1.8V, V = 3.3V, T = +25NC.)
LVDSVDD A
AVDD
DVDD
IOVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVDS INPUTS (RXIN_+/-, RXCLKIN_)
Differential Input High Threshold
Differential Input Low Threshold
V
50
mV
mV
TH
V
-50
85
TL
Input Differential Termination
R
110
135
I
TERM
Resistance
PWDN = high or low, IN+ and IN- are
shorted
Input Current
I
I
-25
-40
+25
+40
FA
FA
IN+, IN-
Power-Off Input Current
I
I
V
AVDD
= V
= V
= 0V
IN0+, IN0-
DVDD
IOVDD
POWER SUPPLY
f
= 16.6MHz
= 33.3MHz
= 66.6MHz
= 104MHz
137
146
166
195
95
178
186
206
242
225
180
RXCLKIN_
f
HDCP enabled, RXCLKIN_
Worst-Case Supply Current
(Figure 4)
I
mA
WCS
BWS = low
f
f
RXCLKIN_
RXCLKIN_
Sleep Mode Supply Current
Power-Down Supply Current
ESD PROTECTION
I
LVDS inputs are not driven
PWDN = GND, LVDS inputs are not driven
FA
FA
CCS
CCZ
I
60
Human Body Model, R = 1.5kI,
C = 100pF (Note 4)
S
D
Q8
Contact discharge
Q10
IEC 61000-4-2,
= 330I,
R
D
C = 150pF
S
(Note 5)
Air discharge
Q12
OUT+, OUT-
V
ESD
kV
Contact discharge
Air discharge
Q10
Q20
ISO 10605,
R
D
= 2kI,
C = 330pF
S
(Note 5)
RXIN_+, RXIN_-, RXCLKIN+,
RXCLKIN-
Human Body Model, R = 1.5kI,
D
C = 100pF (Note 4)
S
V
V
Q8
kV
kV
ESD
Human Body Model, R = 1.5kI,
D
All Other Pins
Q3.5
ESD
C = 100pF (Note 4)
S
4
______________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
AC ELECTRICAL CHARACTERISTICS
(V
DVDD
= V
= 1.7V to 1.9V, V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100I Q1% (differential), T = -40NC to
IOVDD L A
AVDD
LVDSVDD
+105NC, unless otherwise noted. Differential input voltage |V | = 0.15V to 1.2V, input common-mode voltage V
= |V /2| to 2.4V
ID
ID
CM
- |V /2|. Typical values are at V
ID
= V
= V
= 1.8V, V = 3.3V, T = +25NC.)
LVDSVDD A
DVDD
AVDD
IOVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK INPUTS (RXCLKIN_)
BWS = GND, V = V
8.33
16.66
6.25
16.66
104
12.5
78
DRS
IOVDD
BWS = GND, DRS = GND
Clock Frequency
f
MHz
RXCLKIN_
V
BWS
V
BWS
= V
, V
= V
IOVDD DRS IOVDD
= V
, DRS = GND
12.5
IOVDD
I2C/UART PORT TIMING
I2C/UART Bit Rate
9.6
20
1000
150
kbps
ns
30% to 70%, C = 10pF to 100pF,
L
Output Rise Time
Output Fall Time
t
R
1kI pullup to V
IOVDD
70% to 30%, C = 10pF to 100pF,
L
t
20
150
ns
F
1kI pullup to V
IOVDD
Input Setup Time
Input Hold Time
t
I2C only (Figure 5, Note 6)
I2C only (Figure 5, Note 6)
100
0
ns
ns
SET
t
HOLD
SWITCHING CHARACTERISTICS
20% to 80%, V
serial bit rate = 3.125Gbps (Note 6)
R 400mV, R = 100I,
L
OD
Differential Output Rise/Fall Time
t , t
90
150
ps
UI
R
F
3.125Gbps PRBS signal, measured at V
= 0V differential, preemphasis disabled
(Figure 6)
OD
Total Serial Output Jitter
t
0.25
0.15
TSOJ1
Deterministic Serial Output Jitter
CNTL_ Input Setup Time
CNTL_ Input Hold Time
RXIN__ Skew Margin
t
3.125Gbps PRBS signal
CNTL_ (Figure 7) (Note 6)
CNTL_ (Figure 7) (Note 6)
Figure 8 (Note 6)
UI
ns
ns
UI
DSOJ2
t
3
SET
t
1.5
0.3
HOLD
RSKM
t
Spread spectrum enabled
Spread spectrum disabled
2950
550
3.5
6
Serializer Delay (Notes 6, 7)
t
(Figure 9)
Bits
SD
Link Start Time
t
(Figure 10)
(Figure 11)
ms
ms
LOCK
Power-Up Time
t
PU
I2S INPUT TIMING
WS Frequency
f
See Table 4
See Table 4
8
4
192
32
kHz
Bits
WS
Sample Word Length
n
WS
(8 x
4) x 2
(192 x
32) x 2
SCK Frequency
f
f
= f
x n x 2
WS
kHz
SCK
SCK
WS
_______________________________________________________________________________________
5
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
AC ELECTRICAL CHARACTERISTICS (continued)
(V
DVDD
= V
= 1.7V to 1.9V, V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100I Q1% (differential), T = -40NC to
IOVDD L A
AVDD
LVDSVDD
+105NC, unless otherwise noted. Differential input voltage |V | = 0.15V to 1.2V, input common-mode voltage V
= |V /2| to 2.4V
ID
ID
CM
- |V /2|. Typical values are at V
ID
= V
= V
= 1.8V, V = 3.3V, T = +25NC.)
LVDSVDD A
DVDD
AVDD
IOVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.35
SCK Clock High Time
t
V
V
R V , t
= 1/f
(Note 6)
(Note 6)
ns
HC
SCK
IH SCK
SCK
t
SCK
0.35
SCK Clock Low Time
t
P V , t
= 1/f
ns
LC
SCK
IL SCK
SCK
t
SCK
SD, WS Setup Time
SD, WS Hold Time
t
(Figure 12, Note 6)
(Figure 12, Note 6)
2
ns
ns
SET
t
2
HOLD
Note 2: Minimum I due to voltage drop across the internal pullup resistor.
IN
Note 3: To provide a mid level, leave the input unconnected, or, if driven, put driver in high impedance. High-impedance leakage
current must be less than Q10FA.
Note 4: Tested terminal to all grounds.
Note 5: Tested terminal to AGND.
Note 6: Guaranteed by design and not production tested.
Note 7: Measured in CML bit times. Bit time = 1/(30 x f
) for BWS = GND. Bit time = 1/(40 x f
) for V
= V
.
RXCLKIN
RXCLKIN
BWS
IOVDD
6
______________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Typical Operating Characteristics
(V
AVDD
= V
DVDD
= V
IOVDD
= 1.8V, V
= 3.3V, T = +25°C, unless otherwise noted.)
LVDSVDD
A
SUPPLY CURRENT vs.
RXCLKIN_ FREQUENCY (32-BIT MODE)
OUTPUT POWER SPECTRUM vs.
RXCLKIN_ FREQUENCY (VARIOUS SPREAD)
SUPPLY CURRENT vs.
RXCLKIN_ FREQUENCY (24-BIT MODE)
200
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
200
190
180
170
160
150
140
130
PRBS ON, HDCP ON
f
= 33MHz
RXCLKIN
PRBS ON, HDCP ON
190
0.5% SPREAD
PREEMPHASIS =
0x0B TO 0x0F
PREEMPHASIS =
0x0B TO 0x0F
0% SPREAD
180
170
160
PREEMPHASIS =
150
PREEMPHASIS =
0x01 TO 0x04
0x01 TO 0x04
PREEMPHASIS = 0x00
140
130
PREEMPHASIS = 0x00
2% SPREAD
4% SPREAD
34
5
20
35
50
65
80
30
31
32
33
35
36
5
25
45
65
85
105
RXCLKIN FREQUENCY (MHz)
RXCLKIN FREQUENCY (MHz)
RXCLKIN FREQUENCY (MHz)
MAXIMUM RXCLKIN_ FREQUENCY
vs. ADDITIONAL DIFFERENTIAL
MAXIMUM RXCLKIN_ FREQUENCY
vs. STP CABLE LENGTH (BER < 10 )
OUTPUT POWER SPECTRUM vs.
RXCLKIN_ FREQUENCY (VARIOUS SPREAD)
-9
-9
C (BER < 10 )
L
120
100
80
60
40
20
0
120
100
80
60
40
20
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
f
= 66MHz
RXCLKIN
10m STP CABLE
0.5% SPREAD
0% SPREAD
OPTIMUM
PE/EQ SETTINGS
OPTIMUM
PE/EQ SETTINGS
NO PE, 10.7dB
EQUALIZATION
NO PE, 10.7dB
EQUALIZATION
NO PE, 5.2dB
EQUALIZATION
NO PE, 5.2dB EQUALIZATION
-12
BER CAN BE AS LOW AS 10 FOR
CABLE LENGTHS LESS THAN 10m
-12
BER CAN BE AS LOW AS 10 FOR C < 4pF
L
FOR OPTIMUM PE/EQ SETTINGS
4% SPREAD
67
2% SPREAD
65
0
5
10
15
20
0
2
4
6
8
10
61
63
69
71
STP CABLE LENGTH (m)
ADDITIONAL DIFFERENTIAL LOAD CAPACITANCE (pF)
RXCLKIN FREQUENCY (MHz)
_______________________________________________________________________________________
7
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Pin Configuration
TOP VIEW
36 35 34 33 32 31 30 29 28 27 26 25
IOVDD 37
24 IOVDD
23 GND
GND 38
DVDD 39
ADD0 40
BWS 41
PWDN 42
CDS 43
22 DVDD
21 AGND
20 CNTL2
19 CNTL1
18 WS
MAX9265
MS 44
17 SCK
AUTOS 45
ADD1 46
AVDD 47
AGND 48
16 SD/CNTL0
15 AVDD
14 LVDSVDD
13 AGND
*EP
+
1
2
3
4
5
6
7
8
9
10 11 12
TQFP
*CONNECT EXPOSED PAD TO AGND
Pin Description
PIN
1
NAME
RXIN0-
RXIN0+
RXIN1-
RXIN1+
FUNCTION
Differential LVDS Data Input 0-
Differential LVDS Data Input 0+
Differential LVDS Data Input 1-
Differential LVDS Data Input 1+
2
3
4
3.3V LVDS Power Supply. Bypass LVDSVDD to AGND with 0.1FF and 0.001FF capacitors as close as
possible to the device with the smaller value capacitor closest to LVDSVDD.
5, 14
LVDSVDD
AGND
6, 13, 21,
29, 48
Analog Ground
7
8
RXIN2-
Differential LVDS Data Input 2-
Differential LVDS Data Input 2+
RXIN2+
RXCLKIN-,
RXCLKIN+
9, 10
11
LVDS Input for the LVDS Clock
Differential LVDS Data Input 3-. RXIN3- is not available in 3-channel mode. To use RXIN3-, drive BWS
high (4-channel mode) (see Table 3).
RXIN3-
8
______________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Pin Description (continued)
PIN
NAME
FUNCTION
Differential LVDS Data Input 3+. RXIN3+ is not available in 3-channel mode. To use RXIN3+, drive
BWS high (4-channel mode) (see Table 3).
12
RXIN3+
1.8V Analog Power Supply. Bypass AVDD to AGND with 0.1FF and 0.001FF capacitors as close as
possible to the device with the smaller capacitor closest to AVDD.
15, 32, 47
16
AVDD
I2S Serial-Data Input with Internal Pulldown to GND. Disable I2S to use SD/CNTL0 as an additional
control/data input latched every RXCLKIN_ cycle (Figure 7). Encrypted when HDCP is enabled.
SD/CNTL0
17
18
SCK
WS
I2S Serial-Clock Input with Internal Pulldown to GND
I2S Word-Select Input with Internal Pulldown to GND
Control Input 1 with Internal Pulldown to GND. Data is latched every RXCLKIN cycle (Figure 7).
CNTL1 is not available in 3-channel mode. To use CNTL1, drive BWS high (4-channel mode).
CNTL1 or RES (RES from VESA Standard Panel Specification) is mapped to DIN27 (see the
Reserved Bit (RES) section). CNTL1 is not encrypted when HDCP is enabled (see Table 3).
19
20
CNTL1
CNTL2
Control Input 2 with Internal Pulldown to GND. Data is latched every RXCLKIN cycle (Figure 7).
CNTL2 is not available in 3-channel mode. To use CNTL2, drive BWS high (4-channel mode).
CNTL2 is mapped to DIN28. CNTL2 is not encrypted when HDCP is enabled (see Table 3).
1.8V Digital Power Supply. Bypass DVDD to GND with 0.1FF and 0.001FF capacitors as close as
possible to the device with the smaller value capacitor closest to DVDD.
22, 39
23, 38
DVDD
GND
Digital and I/O Ground
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to GND with 0.1FF and
0.001FF capacitors as close as possible to the device with the smallest value capacitor closest to
IOVDD.
24, 37
IOVDD
RX/SDA
TX/SCL
Receive/Serial Data. UART receive or I2C serial-data input/output with internal 30kIpullup to IOVDD.
In UART mode, RX/SDA is the Rx input of the serializer’s UART. In the I2C mode, RX/SDA is the SDA
input/output of the MAX9265’s I2C master. RX/SDA has an open-drain driver and requires a pullup
resistor.
25
Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kIpullup to IOVDD.
In UART mode, TX/SCL is the Tx output of the MAX9265’s UART. In the I2C mode, TX/SCL is the SCL
output of the serializer’s I2C master. TX/SCL has an open-drain driver and requires a pullup resistor.
26
Spread-Spectrum Enable. Serial link spread-spectrum enable input requires external pulldown or
pullup resistor. The state of SSEN latches upon power-up or when resuming from power-down mode
(PWDN = low). Set SSEN = high for Q0.5% spread spectrum on the serial link. Set SSEN = low to use
the serial link without spread spectrum.
27
SSEN
LMN1
28
30, 31
33
Line-Fault Monitor Input 1 (See Figure 3 for Details)
Differential CML Output -/+. Differential outputs of the serial link.
Line-Fault Monitor Input 0 (See Figure 3 for Details)
OUT-,
OUT+
LMN0
Line Fault. Active-low open-drain line-fault output. LFLT has a 60kIinternal pullup resistor.
LFLT = low indicates a line fault. LFLT is high impedance when PWDN = low.
34
LFLT
Interrupt Output. INT indicates remote-side requests. INT = low upon power-up and when PWDN =
low. A transition on the INT input of the GMSL deserializer toggles the MAX9265’s INT output.
35
INT
_______________________________________________________________________________________
9
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Pin Description (continued)
PIN
NAME
FUNCTION
Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup resistor. The
state of DRS latches upon power-up or when resuming from power-down mode (PWDN = low).
Set DRS = high for RXCLKIN frequencies of 8.33MHz to 16.66MHz (3-channel mode) or 6.25MHz
to 12.5MHz (4-channel mode). Set DRS = low for RXCLKIN frequencies of 16.66MHz to 104MHz
(3-channel mode) or 12.5MHz to 78MHz (4-channel mode).
36
DRS
Address Selection Input 0. Three-level input to select the MAX9265’s device address (see Table 2).
The state of ADD0 latches upon power-up or when resuming from power-down mode (PWDN = low).
40
ADD0
Bus-Width Select Input. BWS requires external pulldown or pullup resistor. Set BWS = low for
3-channel mode. Set BWS = high for 4-channel mode.
41
42
BWS
PWDN
Active-Low Power-Down Input. PWDN requires external pulldown or pullup resistor.
Control Direction Selection. Control link direction selection input requires external pulldown or pullup
resistor. Set CDS = low for FC use on the MAX9265 side of the serial link. Set CDS = high for FC use
on the GMSL deserializer side of the serial link.
43
44
45
CDS
MS
Mode Select. Control link mode selection input requires external pulldown or pullup resistor. Set
MS = low to select base mode. Set MS = high to select bypass mode.
Active-Low Autostart Setting. AUTOS requires external pulldown or pullup resistor. Set AUTOS = high
to power up the device with no link active. Set AUTOS = low to have the serializer power up the serial
link with autorange detection (see Tables 9 and 10).
AUTOS
Address Selection Input 1. Three-level input to select the serializer’s device address (see Table 2).
The state of ADD1 latches upon power-up or when resuming from power-down mode (PWDN = low).
46
—
ADD1
EP
Exposed Pad. EP internally is connected to AGND. MUST connect EP to the AGND plane for proper
thermal and electrical performance.
10 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Functional Diagram
LFLT
FILTER
SSPLL
PLL
RXCLKIN+/-
LMN0
LINE
FAULT
DETECT
7x PLL
LMN1
CLKDIV
RGB
RGB[17:0]
HDCP
ENCRYPT
RXIN0+/-
RXIN1+/-
RXIN2+/-
OUT+
OUT-
PARALLEL
TO
SERIAL
HS
VS
DE
HS
VS
DE
VIDEO
LVDS TO
PARALLEL
CML Tx
SCRAMBLE/
PARITY/
8b/10b
RGB[23:18]
(4-CH)
HDCP
KEYS
HDCP
CONTROL
ENCODE
RES/CNTL1
(4-CH)
CNTL1/RES (4-CH)
CNTL2 (4-CH)
FIFO
RXIN3+/-
(4-CH)
Rx
REVERSE
CONTROL
CHANNEL
ACB
FCC
CNTL1
(4-CH)
HDCP
ENCRYPT
AUDIO
CNTL2
(4-CH)
MAX9265
2
UART/I C
SD/
CNTLO
WS SCK
TX/SCL RX/SDA ADD0 ADD1
R /2
L
OUT+
V
OD
V
OS
OUT-
R /2
L
GND
((OUT+) + (OUT-))/2
OUT-
OUT+
V
V
OS(+)
V
OS(-)
OS(-)
DV = |V
- V
|
OS(+) OS(-)
OS
V (+)
OD
V
OD
= 0V
V
OD(-)
V
OD(-)
DV = |V |
- V
OD(+) OD(-)
OD
(OUT+) - (OUT-)
Figure 1. Serial-Output Parameters
______________________________________________________________________________________ 11
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
OUT+
V
OD(P)
V
OD(D)
V
OS
OUT-
SERIAL-BIT
TIME
Figure 2. Output Waveforms at OUT+, OUT-
1.7V TO 1.9V
MAX9265
45kI*
45kI*
5kI*
LMN0
LMN1
5kI*
OUTPUT
LOGIC
(OUT+)
TWISTED PAIR
OUT+
OUT-
50kI*
50kI*
CONNECTORS
LFLT
REFERENCE
VOLTAGE
GENERATOR
OUTPUT
LOGIC
(OUT-)
*Q1% TOLERANCE
Figure 3. Line-Fault Detector Circuit
12 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
RXCLKIN+
RXCLKIN-
RXIN0+ TO RXIN3+
RXIN0- TO RXIN3-
CNTL_
Figure 4. Worst-Case Pattern Input
t
F
t
R
TX/
SCL
t
t
HOLD
SET
RX/
SDA
S
P
S
P
2
Figure 5. I C Timing Parameters
RXCLKIN-
RXCLKIN+
800mV
P-P
RXIN_+/RXIN_-
CNTL_
t
t
HOLD
SET
V
IHMIN
V
ILMAX
t
t
TSOJ1
2
TSOJ1
2
Figure 6. Differential Output Template
Figure 7. Input Setup and Hold Times
______________________________________________________________________________________ 13
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
IDEAL SERIAL-BIT TIME
t
t
RSKM
RSKM
IDEAL
MIN
MAX
INTERNAL STROBE
Figure 8. LVDS Receiver Input Skew Margin
EXPANDED TIME SCALE
N-1
N
N+1
N+2
N+3
RXIN_+/RXIN_-
RXCLKIN+
RXCLKIN-
N-1
N
OUT+/OUT-
FIRST BIT
LAST BIT
t
SD
Figure 9. Serializer Delay
RXCLKIN-
RXCLKIN+
t
LOCK
350µs
SERIAL LINK INACTIVE
SERIAL LINK ACTIVE
REVERSE CONTROL
CHANNEL ENABLED
CHANNEL
DISABLED
REVERSE CONTROL
CHANNEL ENABLED
PWDN MUST BE HIGH
Figure 10. Link Startup Time
14 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
RXCLKIN+
RXCLKIN-
V
PWDN
IH1
t
PU
POWERED UP, SERIAL
LINK INACTIVE
POWERED DOWN
POWERED UP, SERIAL LINK ACTIVE
350µs
REVERSE CONTROL
CHANNEL DISABLED
REVERSE CONTROL
CHANNEL ENABLED
REVERSE CONTROL
CHANNEL DISABLED
REVERSE CONTROL
CHANNEL ENABLED
Figure 11. Power-Up Delay
WS
SCK
t
SCK
t
t
SET
HOLD
t
LC
t
t
t
HC
HOLD
SET
SD/CNTL0
2
Figure 12. Input I S Timing Parameters
______________________________________________________________________________________ 15
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
mat. A bypass mode enables full-duplex communication
using a user-defined UART format.
Detailed Description
The MAX9265 GMSL serializer with LVDS interface
utilizes Maxim’s GMSL technology and HDCP. When
HDCP is enabled, the serializer encrypts video and
audio data on the serial link. When HDCP is disabled,
the serializer is backward compatible with the MAX9249
LVDS input serializer.
The serializer pre/deemphasis, along with the GMSL
deserializer channel equalizer, extends the link length
and enhances the link reliability. Spread spectrum is
available to reduce EMI on the serial output. The CML
and LVDS connections comply with ISO 10605 and IEC
61000-4-2 ESD protection standards.
The serializer has a maximum serial payload data rate
of 2.5Gbps for 15m or more of shielded twisted-pair
(STP) cable. The serializer operates up to a maximum
input clock of 104MHz for 3-channel mode, or 78MHz for
4-channel mode, respectively. This serial link supports a
wide range of display panels from QVGA (320 x 240) up
to WXGA (1280 x 800) and higher with 24-bit color.
Register Mapping
The FC configures various operating conditions of the
serializer and the GMSL deserializer through internal
registers. Table 1 lists the default register values for the
serializer. The device addresses are stored in registers
0x00 and 0x01 of both the serializer and the GMSL
deserializer. Write to registers 0x00 and 0x01 in both
devices to change the device address of the serializer
or the GMSL deserializer.
The 3-channel mode handles three lanes of LVDS data
(21 bits), UART control signals, and three audio signals.
The 4-channel mode handles four lanes of LVDS data
(28 bits), UART control signals, three audio signals, and
auxiliary parallel inputs. The three audio inputs form a
standard I2S interface, supporting sample rates from
8kHz to 192kHz and audio word lengths of 4 to 32 bits.
The embedded control channel forms a full-duplex,
differential 9.6kbps to 1Mbps UART link between the
serializer and deserializer for HDCP-related control
operations. In addition, the control channel enables
electronic control unit (ECU) or microcontroller (FC) con-
trol of peripherals in the remote side, such as backlight
control, gray-scale Gamma correction, camera module,
and touch screen. An ECU/FC can be located on the
serializer side of the link (typical for video display), on
the GMSL deserializer side of the link (typical for image
sensing), or on both sides. Base-mode communication
with peripherals uses either I2C or the GMSL UART for-
HDCP Bitmapping and Bus-Width Selection
The LVDS input has two selectable modes, 3-channel
mode and 4-channel mode. In 3-channel mode, RXIN3_
is not used. For both modes, the SD/CNTL0, SCK, and
WS pins are for I2S audio. The serializer uses RXCLKIN
rates from 8.33MHz to 104MHz for 3-channel mode and
6.25MHz to 78MHz for 4-channel mode.
Table 3 lists the bit mapping for the LVDS input. The
serializer has HDCP encryption on 18 RGB input bits and
the I2S input. Four-channel mode has additional HDCP
encryption on the additional RGB bits.
The control signals (CNTL_) do not have HDCP encryp-
tion. SD/CNTL0, when used as an additional control input
(AUDIOEN = 0), also does not have HDCP encryption.
16 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 1. Power-Up Default Register Map (see Table 17 and Table 18)
REGISTER
ADDRESS
(hex)
POWER-UP
DEFAULT
(hex)
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
0x40, 0x48, 0x48,
0x80, 0x84, 0x88,
0xC0, 0xC4, 0xC8
SERID = XX00XX0, serializer device address is determined by ADD0 and ADD1
(Table 2)
CFGBLOCK = 0, registers 0x00 to 0x1F are read/write
0x00
0x01
0x50, 0x58, 0x58,
0x90, 0x94, 0x98,
0xD0, 0xD4, 0xD8
DESID = XX00XX0, deserializer device address is determined by ADD0 and
ADD1 (Table 2)
RESERVED = 0
SS = 000 (SSEN = low), SS = 001 (SSEN = high), spread-spectrum settings
depend on SSEN pin state at power-up
0x02
0x03
0x1F, 0x3F
0x00
AUDIOEN = 1, I2S channel enabled
PRNG = 11, automatically detect the pixel clock range
SRNG = 11, automatically detect serial-data rate
AUTOFM = 00, calibrate spread-modulation rate only once after locking
SDIV = 000000, autocalibrate the sawtooth divider
SEREN = 0 (AUTOS = high), SEREN = 1 (AUTOS = low), serial link enable
default depends on AUTOS pin state at power-up
CLINKEN = 0, configuration link disabled
PRBSEN = 0, PRBS test disabled
0x03, 0x13, 0x83, or
0x93
0x04
0x05
SLEEP = 0 or 1, sleep mode state depends on CDS and AUTOS pin state at
power-up (see the Link Startup Procedure section)
INTTYPE = 00, base mode uses I2C
REVCCEN = 1, reverse control channel active (receiving)
FWDCCEN = 1, forward control channel active (sending)
I2CMETHOD = 0, I2C packets include register address
DISFPLL = 1, filter PLL disabled
CMLLVL = 11, 400mV CML signal level
PREEMP = 0000, preemphasis disabled
0x70
0x06
0x07
0x40
0x22
RESERVED = 01000000
RESERVED = 00100010
RESERVED = 0000
LFNEG = 10, no faults detected
LFPOS = 10, no faults detected
0x0A
(read only)
0x08
0x0C
0x70
0x0F
RESERVED = 01110000
SETINT = 0, interrupt output set to low
INVVSYNC = 0, serializer does not invert VSYNC
INVHSYNC = 0, serializer does not invert HSYNC
DISRES = 0, RES mapped to DIN27
0x0D
0x1E
SKEWADJ = 1111, No X7PLL clock skew adjust
0x07
(read only)
ID = 00000111, device ID is 0x07
______________________________________________________________________________________ 17
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 1. Power-Up Default Register Map (see Table 17 and Table 18) (continued)
REGISTER
ADDRESS
(hex)
POWER-UP
DEFAULT
(hex)
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
RESERVED = 000
CAPS = 1, serializer is HDCP capable
REVISION = XXXX, revision number
0x1X
(read only)
0x1F
0x80 to 0x84
0x85 to 0x86
0x87
0x0000000000
0x0000
BKSV = 0x0000000000, HDCP receiver KSV is 0x0000000000
RI = 0x0000, RI of the transmitter is 0x0000
0x00
PJ = 0x00, PJ of the transmitter is 0x00
0x0000000000000000
(read only)
0x88 to 0x8F
0x90 to 0x94
AN = 0000000000000000, session random number (read only)
0xXXXXXXXXXX
(read only)
AKSV = 0xXXXXXXXXXXXXXXXX, HDCP transmitter KSV is 0xXXXXXXXXXX
(read only)
PD_HDCP = 0, HDCP circuits powered up
EN_INT_COMP = 0, internal link verification disabled
FORCE_AUDIO = 0, normal I2S audio operation
FORCE_VIDEO = 0, normal video link operation
RESET_HDCP = 0, normal HDCP operation
0x95
0x00
START_AUTHENTICATION = 0, HDCP authentication not started
VSYNC_DET = 0, VSYNC rising edge not detected
ENCRYPTION_ENABLE = 0, HDCP encryption disabled
RESERVED = 0000
V_MATCHED = 0, SHA-1 hash value not matched
PJ_MATCHED = 0, enhanced link verification response not matched
R0_RI_MATCHED = 0, link verification response not matched
BKSV_INVALID = 0, invalid receiver KSV
0x00
(read only)
0x96
0x97
RESERVED = 0000000
REPEATER = 0, HDCP receiver is not a repeater
0x00
0x98 to 0x9C
0x9D to 0x9F
0xA0 to 0xA3
0xA4 to 0xA7
0xA8 to 0xAB
0xAC to 0xAF
0xB0 to 0xB3
0x0000000000
0x000000
ASEED = 0x0000000000, optional RNG seed value is 0x0000000000
DFORCE = 0x000000, video data forced to 0x000000 when FORCE_VIDEO = 1
H0 part of SHA-1 hash value is 0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
H1 part of SHA-1 hash value is 0x00000000
H2 part of SHA-1 hash value is 0x00000000
H3 part of SHA-1 hash value is 0x00000000
H4 part of SHA-1 hash value is 0x00000000
Reserved = 0000
0xB4
0xB5
0x00
0x00
MAX_CASCADE_EXCEEDED = 0, less than 7 cascaded HDCP devices attached
DEPTH = 000, device cascade depth is zero
MAX_DEVS_EXCEEDED = 0, less than 127 HDCP devices attached
DEVICE_COUNT = 0000000, zero attached devices
0xB6
0x00
GPMEM = 00000000, 0x00 stored in general-purpose memory
Reserved = 0x000000
0xB7 to 0xB9
0xBA to 0xFF
0x000000
All zero
KSV_LIST = all zero, no KSVs stored
X = Don’t care.
18 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 2. Device Address Defaults (Register 0x00, 0x01)
DEVICE ADDRESS
(bin)
SERIALIZER DEVICE
ADDRESS
DESERIALIZER DEVICE
ADDRESS
PIN
(hex)
(hex)
ADD1
Low
ADD0
D7
1
D6
0
D5
0
D4
X*
X*
X*
X*
X*
X*
X*
X*
X*
D3
0
D2 D1
D0
Low
High
Open
Low
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
80
84
88
C0
C4
C8
40
44
48
90
94
98
D0
D4
D8
50
54
58
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Low
1
0
0
0
Low
1
0
0
1
High
High
High
Open
Open
Open
1
1
0
0
High
Open
Low
1
1
0
0
1
1
0
1
0
1
0
0
High
Open
0
1
0
0
0
1
0
1
*X = 0 for the serializer address, X = 1 for the deserializer address.
Table 3. LVDS, HDCP Mapping and Bus Width Selection (see Figures 13 and 14)
3-CHANNEL MODE
(BWS = LOW)
4-CHANNEL MODE
(BWS = HIGH)
INPUT BITS
AUXILIARY
SIGNALS
MAPPING
HDCP
ENCRYPTION
CAPABILITY
AUXILIARY
SIGNALS
MAPPING
HDCP
ENCRYPTION
CAPABILITY
BITMAPPING
BITMAPPING
DIN[0:5]
DIN[6:11]
DIN[12:17]
DIN[18:20]
DIN[21:22]
DIN[23:24]
DIN[25:26]
DIN27
R[0:5]
G[0:5]
—
Yes
Yes
Yes
No
—
R[0:5]
G[0:5]
B[0:5]
HS, VS, DE
R6, R7
G6, G7
B6, B7
RES*
—
Yes
Yes
Yes
No
—
—
—
B[0:5]
—
HS, VS, DE
Not available
Not available
Not available
Not available
—
—
—
—
—
Yes
Yes
Yes
No
—
—
—
—
—
—
Not available
Not available
SD/CNTL0
—
CNTL1*
CNTL2
SD/CNTL0
DIN28
—
I2S**
—
No
I2S**
SD
—
—
*See the Reserved Bit (RES) section for details.
2
**HDCP encryption on SD when used as an I S signal.
______________________________________________________________________________________ 19
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
RXCLKIN-
RXCLKIN+
CYCLE N-1
CYCLE N
DIN3
RXIN0+/RXIN0-
RXIN1+/RXIN1-
RXIN2+/RXIN2-
RXIN3+/RXIN3-
CNTL1
DIN1
DIN8
DIN0
DIN6
DIN13
DIN20
DIN27
DIN27
DIN28
SD*
DIN5
DIN12
DIN19
DIN26
DIN4
DIN11
DIN18
DIN25
DIN2
DIN9
DIN1
DIN8
DIN0
DIN7
DIN7
DIN14
DIN21
DIN10
DIN17
DIN24
DIN15
DIN22
DIN16
DIN23
DIN15
DIN22
DIN14
DIN21
CNTL2
SD/CNTL0*
2
*WITH I S ENABLED; OTHERWISE CNTL0
Figure 13. LVDS Input Timing
RXCLKIN-
RXCLKIN+
CYCLE N-1
CYCLE N
RXIN0+/RXIN0-
RXIN1+/RXIN1-
RXIN2+/RXIN2-
RXIN3+/RXIN3-
R1
G2
B3
R7
R0
G1
B2
R6
G0
B1
R5
B0
VS
B7
R4
G5
HS
B6
R3
G4
B5
G7
R2
G3
B4
G6
R1
G2
B3
R7
R0
G1
B2
R6
DE
RES
Figure 14. Panel Clock and Bit Assignment
20 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Serial Link Signaling and Data Format
Reserved Bit (RES)
In 4-channel mode, the serializer serializes all bits of all four
lanes, including RES, by default. Set DISRES (D4 of register
0x0D) to 1 to map CNTL1 to DIN27 instead of RES.
The serializer uses CML signaling with programmable pre-
emphasis and AC-coupling. The GMSL deserializer uses
AC-coupling and programmable channel equalization.
Together, the GMSL link can operate at full speed over STP
cable lengths to 15m or more.
Reverse Control Channel
The serializer uses the reverse control channel to receive
I2C/UART and interrupt signals from the GMSL deserial-
izer in the opposite direction of the video stream. The
reverse control channel and forward video data coexist
on the same twisted pair forming a bidirectional link. The
reverse control channel operates independently from the
forward control channel. The reverse control channel is
available 500Fs after power-up. The serializer temporarily
disables the reverse control channel for 350Fs after start-
ing/stopping the forward serial link.
In addition to HDCP encryption (when enabled), the
serializer scrambles and encodes the input data and sends
the 8b/10b coded signal through the serial link. Figures 15
and 16 show the serial-data packet format before HDCP
encryption, scrambling and 8b/10b encoding. In 3-chan-
nel or 4-channel mode, 21 or 29 bits map from the LVDS
input. The audio channel bit (ACB) contains an encoded
audio signal derived from the three I2S signals (SD, SCK,
and WS). The forward control-channel (FCC) bit carries the
forward control data. The last bit (PCB) is the parity bit of
the previous 23 or 31 bits.
24 BITS
DIN0 DIN1
R0 R1
DIN17 DIN18 DIN19 DIN20 ACB FCC PCB
B5
HS
VS
DE
RGB DATA
CONTROL BITS
AUDIO
CHANNEL OR
CNTL0 BIT
LVDS DATA
(3 CHANNELS)
FORWARD
CONTROL-
CHANNEL BIT
NOTE: VS/HS MUST BE SET AT DIN[19:18]
FOR HDCP FUNCTIONALITY.
ONLY DIN[17:0] AND ACB HAVE HDCP ENCRYPTION.
PACKET
PARITY CHECK BIT
Figure 15. 3-Channel Mode Serial Link Data Format
32 BITS
DIN0 DIN1
R0 R1
DIN17 DIN18 DIN19 DIN20 DIN21 DIN22 DIN23 DIN24 DIN25 DIN26 DIN27 DIN28 ACB
RES/
FCC
PCB
B5
HS
VS
DE
R6
R7
G6
G7
B6
B7
CNTL2
CNTL1*
AUDIO
CHANNEL OR
CNTL0 BIT
RGB DATA
CONTROL BITS
RGB DATA
AUX
CONTROL
BITS
FORWARD
CONTROL-
CHANNEL BIT
LVDS DATA
(RXIN[2:0]_)
LVDS DATA
(RXIN3_)
NOTE: VS/HS MUST BE SET AT DIN[19:18] FOR HDCP FUNCTIONALITY.
PACKET
PARITY
ONLY DIN[17:0], DIN[26:21] AND ACB HAVE HDCP ENCRYPTION.
*DIN27 FROM LVDS DATA (RXIN3_) OR EXTERNAL PIN (CNTL1).
CHECK BIT
Figure 16. 4-Channel Mode Serial Link Data Format
______________________________________________________________________________________ 21
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
serializer or GMSL deserializer, with the UART packets
Data-Rate Selection
The serializer uses the DRS input to set the RXCLKIN_
frequency range. Set DRS high for an RXCLKIN_
frequency range of 6.25MHz to 12.5MHz (4-channel
mode) or 8.33MHz to 16.66MHz (3-channel mode).
Set DRS low for normal operation with an RXCLKIN_
frequency range of 12.5MHz to 78MHz (4-channel
mode) or 16.66MHz to 104MHz (3-channel mode).
converted to I2C by the device on the remote side of the link
(GMSL deserializer for LCD or serializer for image-sensing
applications). The FC communicates with a UART periph-
eral in base mode (through INTTYPE register settings),
using the half-duplex default GMSL UART protocol of the
serializer/GMSL deserializer. The device addresses of
the serializer and GMSL deserializer in base mode are
programmable. The default value is determined by the pin
settings of ADD0 and ADD1 (Table 2).
Audio Channel
The I2S audio channel supports audio sampling rates
from 8kHz to 192kHz, and audio word lengths from 4
bits to 32 bits. The audio bit clock (SCK) does not have
to be synchronized with RXCLKIN_. The serializer auto-
matically encodes audio data into a single bit stream
synchronous with RXCLKIN_. The GMSL deserializer
decodes the audio stream and stores audio words in a
FIFO. Audio rate detection uses an internal oscillator to
continuously determine the audio data rate and output
the audio in I2S format. The audio channel is enabled by
default. When the audio channel is disabled, SD/CNTL0
on the serializer and GMSL deserializer is treated as an
additional control signal (CNTL0).
When the peripheral interface uses I2C (default), the
serializer/GMSL deserializer convert packets to I2C
that have device addresses different from those of the
serializer or GMSL deserializer. The converted I2C bit rate
is the same as the original UART bit rate.
The GMSL deserializer uses a proprietary differential
line coding to send signals back towards the serializer.
The speed of the control channel ranges from 9.6kbps
to 1Mbps in both directions. The serializer and GMSL
deserializer automatically detect the control-channel bit
rate in base mode. Packet bit rates can vary up to 3.5x
from the previous bit rate (see the Changing the Clock
Frequency section).
Since the audio data sent through the serial link is
synchronized with RXCLKIN, low RXCLKIN_ frequencies
limit the maximum audio sampling rate. Table 4 lists the
maximum audio sampling rate for various RXCLKIN_
frequencies. Spread-spectrum settings do not affect the
I2S data rate or WS clock frequency.
Figure 17 shows the UART protocol for writing and reading
in base mode between the FC and the serializer/GMSL
deserializer.
Figure 18 shows the UART data format. Figure 19 and
Figure 20 detail the formats of the SYNC byte (0x79) and
the ACK byte (0xC3). The FC and the connected slave
chip generate the SYNC byte and ACK byte, respectively.
Events such as device wake-up and interrupt generate
transitions on the control channel that should be ignored
by the FC. Data written to the serializer/GMSL deserializer
registers do not take effect until after the acknowledge
byte is sent. This allows the FC to verify write commands
received without error, even if the result of the write com-
mand directly affects the serial link. The slave uses the
SYNC byte to synchronize with the host UART data rate
automatically. If the INT or MS inputs of the GMSL deserial-
izer toggles while there is control-channel communication,
the control-channel communication can be corrupted. In
the event of a missed acknowledge, the FC should assume
there was an error in the packet when the slave device
receives it, or that an error occurred during the response
from the slave device. In base mode, the FC must keep
the UART Tx/Rx lines high for 16 bit-times before starting to
send a new packet.
Control Channel and Register Programming
The control channel is available for the FC to send
and receive control data over the serial link simultane-
ously with the high-speed data. Configuring the CDS pin
allows the FC to control the link from either the serializer
or the GMSL deserializer side to support video-display
or image-sensing applications. The control channel
between the FC and serializer or GMSL deserializer runs
in base mode or bypass mode according to the mode
selection (MS) input of the device connected to the FC.
Base mode is a half-duplex control channel and the
bypass mode is a full-duplex control channel.
Base Mode
In base mode, the FC is the host and can access the
core and HDCP registers of both the serializer and GMSL
deserializer from either side of the link by using the GMSL
UART protocol. The FC can also program the peripherals
on the remote side by sending the UART packets to the
22 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 4. LVDS, HDCP Mapping and Bus Width Selection (see Figures 13 and 14)
RXCLKIN_ FREQUENCY
(DRS = LOW)
(MHz)
RXCLKIN_ FREQUENCY
(DRS = HIGH)
(MHz)
WORD
LENGTH
(bits)
12.5
> 192
> 192
185.5
174.6
152.2
123.7
15
16.6
> 20
6.25
> 192
> 192
185.5
174.6
152.2
123.7
7.5
8.33
> 10
8
> 192
> 192
> 192
> 192
182.7
148.4
> 192
> 192
> 192
> 192
> 192
164.3
> 192
> 192
> 192
> 192
> 192
> 192
> 192
> 192
> 192
> 192
182.7
148.4
> 192
> 192
> 192
> 192
> 192
164.3
> 192
> 192
> 192
> 192
> 192
> 192
16
18
20
24
32
WRITE DATA FORMAT
SYNC
DEV ADDR + R/W
REG ADDR
NUMBER OF BYTES
BYTE 1
BYTE N
ACK
MASTER READS FROM SLAVE
MASTER WRITES TO SLAVE
READ DATA FORMAT
SYNC
DEV ADDR + R/W
REG ADDR NUMBER OF BYTES
MASTER WRITES TO SLAVE
ACK
BYTE 1
BYTE N
MASTER READS FROM SLAVE
Figure 17. GMSL UART Protocol for Base Mode
1 UART FRAME
D4
START
D0
D1
D2
D3
D5
D6
D7
PARITY
STOP
FRAME 1
FRAME 2
FRAME 3
STOP
START
STOP
START
Figure 18. GMSL UART Data Format for Base Mode
D0
1
D1
0
D2
0
D3
1
D4
1
D5
1
D6
1
D7
0
D0
1
D1
1
D2
0
D3
D4
0
D5
0
D6
D7
1
START
0
1
PARITY STOP
START
PARITY STOP
Figure 19. Sync Byte (0x79)
Figure 20. ACK Byte (0xC3)
______________________________________________________________________________________ 23
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
As shown in Figure 21, the remote-side device converts the
packets going to or coming from the peripherals from the
UART format to the I2C format and vice versa. The remote
device removes the byte number count and adds or receives
the ACK between the data bytes of I2C. The I2C’s data rate is
the same as the UART data rate.
the serializer by writing to the SETINT register bit. In normal
operation, the state of the interrupt output changes when
the interrupt input on the GMSL deserializer toggles. Do not
send a logic-low value longer than 100Fs in either base or
bypass mode to ensure proper interrupt functionality.
Pre/Deemphasis Driver
The serial line driver in the serializer employs current-mode
logic (CML) signaling. The driver can generate an adjust-
able preemphasized waveform according to the cable
length and characteristics. There are 13 preemphasis set-
tings as shown in Table 5. Negative preemphasis levels are
deemphasis levels in which the preemphasized swing level
is the same as normal swing, but the no-transition data is
deemphasized. Program the preemphasis levels through
register 0x05 D[3:0] of the serializer. This preemphasis
function compensates the high frequency loss of the
cable and enables reliable transmission over longer link
distances. Additionally, a lower power drive mode can be
entered by programming CMLLVL bits (0x05 D[5:4]) to
reduce the driver strength down to 75% (CMLLVL = 10) or
50% (CMLLVL = 01) from 100% (CMLLVL = 11, default).
Interfacing Command-Byte-Only I2C Devices
The serializer and GMSL deserializer UART-to-I2C conver-
sion interfaces with devices that do not require register
addresses, such as the MAX7324 GPIO expander. In this
mode, the I2C master ignores the register address byte and
directly reads/writes the subsequent data bytes (Figure 22).
Change the communication method of the I2C master using
the I2CMETHOD bit. I2CMETHOD = 1 sets command-byte-
only mode, while I2CMETHOD = 0 sets normal mode where
the first byte in the data stream is the register address.
Bypass Mode
In bypass mode, the serializer/GMSL deserializer ignore
UART commands from the FC and the FC communi-
cates with the peripherals directly using its own defined
UART protocol. The FC cannot access the serializer/GMSL
deserializer’s registers in this mode. Peripherals accessed
through the forward control channel using the UART
interface need to handle at least one RXCLKIN_ period
10ns of jitter due to the asynchronous sampling of the
UART signal by RXCLKIN_. Set MS = high to put the control
channel into bypass mode. For applications with the FC
connected to the deserializer (CDS is high), there is a 1ms
wait time between setting MS high and the bypass control
channel being active. There is no delay time in switching
to bypass mode when the FC is connected to the serial-
izer (CDS = low). Bypass mode accepts bit rates down to
9.6kbps in either direction. See the Interrupt Control section
for interrupt functionality limitations. The control-channel
data pattern should not be held low longer than 100Fs
in either base or bypass mode to ensure proper interrupt
functionality.
Spread Spectrum
To reduce the EMI generated by the transitions on the
serial link, the serializer supports spread spectrum. Turning
on spread spectrum on the serializer spreads the serial
link, which is tracked by the serializer deserializer. The
six selectable spread-spectrum rates at the serial output
are Q0.5%, Q1%, Q1.5%, Q2%, Q3%, and Q4% (Table 6).
Some spread-spectrum rates can only be used at lower
RXCLKIN_ frequencies (Table 7). There is no RXCLKIN_
frequency limit for the 0.5% spread rate.
Set the serializer’s SSEN input high to select 0.5% spread
at power-up and SSEN input low to select no spread at
power-up. The state of SSEN is latched upon power-up or
when resuming from power-down mode.
Whenever the serializer’s spread spectrum is turned on
or off, the serial link automatically restarts and remains
unavailable while the GMSL deserializer relocks to the
serial data. Turning on spread spectrum on the serializer or
GMSL deserializer does not affect the audio data stream.
Interrupt Control
The INT pin of the serializer is the interrupt output and the
INT pin of the GMSL deserializer is the interrupt input. The
interrupt output on the serializer follows the transitions at the
interrupt input. This interrupt function supports remote-side
functions such as touch-screen peripherals, remote power-
up, or remote monitoring. Interrupts that occur during
periods where the reverse control channel is disabled, such
as link startup/shutdown, are automatically resent once the
reverse control channel becomes available again. Bit D4
of register 0x06 in the GMSL deserializer also stores the
interrupt input state. The INT output of the serializer is low
after power-up. In addition, the FC can set the INT output of
The serializer includes a sawtooth divider to control the
spread-modulation rate. Autodetection or manual pro-
gramming of the RXCLKIN_ operation range guarantees
a spread-spectrum modulation frequency within 20kHz to
40kHz. Additionally, manual configuration of the sawtooth
divider (SDIV, 0x03 D[5:0]) allows the user to set a modu-
lation frequency according to the RXCLKIN_ frequency.
Always keep the modulation frequency between 20kHz to
40kHz to ensure proper operation.
24 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
2
UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)
SERIALIZER/GMSL DESERIALIZER
11
FC
11
SYNC FRAME
11
11
11
11
11
DEVICE ID + WR
REGISTER ADDRESS
NUMBER OF BYTES
DATA 0
DATA N
ACK FRAME
SERIALIZER/GMSL DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
8
1
1
S
DEV ID
W
A
REG ADDR
A
DATA 0
A
DATA N
A
P
2
UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 0)
SERIALIZER/GMSL DESERIALIZER
11
FC
11
SYNC FRAME
11
REGISTER ADDRESS
11
NUMBER OF BYTES
11
ACK FRAME
11
DATA 0
11
DATA N
DEVICE ID + RD
SERIALIZER/GMSL DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
DEV ID
W
A
REG ADDR
A
S
DEV ID
R
A
DATA 0
A
DATA N
A
P
S: START
P: STOP
A: ACKNOWLEDGE
: MASTER TO SLAVE
: SLAVE TO MASTER
2
Figure 21. Format Conversion Between GMSL UART and I C with Register Address (I2CMETHOD = 0)
2
UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)
FC
SERIALIZER/GMSL DESERIALIZER
11
11
11
REGISTER ADDRESS
11
11
DATA 0
11
DATA N
11
ACK FRAME
SYNC FRAME
DEVICE ID + WR
NUMBER OF BYTES
SERIALIZER/GMSL DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
1
S
DEV ID
W
A
DATA 0
A
DATA N
A
P
2
UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 1)
FC
SERIALIZER/GMSL DESERIALIZER
11
11
11
11
11
11
DATA 0
11
DATA N
SYNC FRAME
DEVICE ID + RD
REGISTER ADDRESS
NUMBER OF BYTES
ACK FRAME
SERIALIZER/GMSL DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
1
S
DEV ID
R
A
DATA 0
A
DATA N
A
P
: MASTER TO SLAVE
: SLAVE TO MASTER
S: START
P: STOP
A: ACKNOWLEDGE
2
Figure 22. Format Conversion Between GMSL UART and I C with Register Address (I2CMETHOD = 1)
______________________________________________________________________________________ 25
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 5. CML Driver Strength (Default Level, CMLLVL = 11)
SINGLE-ENDED VOLTAGE SWING
PREEMPHASIS LEVEL
(dB)*
PREEMPHASIS SETTING
(0x05, D[3:0])
I
I
PRE
(mA)
CML
MAX
(mV)
MIN
(mV)
(mA)
-6.0
-4.1
-2.5
-1.2
0
0100
0011
0010
0001
0000
1000
1001
1010
1011
1100
1101
1110
1111
12
13
14
15
16
16
16
16
16
15
14
13
12
4
3
2
1
0
1
2
3
4
5
6
7
8
400
400
400
400
400
425
450
475
500
500
500
500
500
200
250
300
350
400
375
350
325
300
250
200
150
100
1.1
2.2
3.3
4.4
6.0
8.0
10.5
14.0
*Negative preemphasis levels denote deemphasis.
Table 6. Serial Output Spread
SS
SPREAD (%)
000
001
010
011
100
101
110
111
No spread spectrum. Power-up default when SSEN = low.
Q0.5% spread spectrum. Power-up default when SSEN = high.
Q1.5% spread spectrum.
Q2% spread spectrum.
No spread spectrum.
Q1% spread spectrum.
Q3% spread spectrum.
Q4% spread spectrum.
Table 7. Spread-Spectrum Rate Limitations
3-CHANNEL MODE
RXCLKIN_ FREQUENCY
(MHz)
4-CHANNEL MODE
RXCLKIN_ FREQUENCY
(MHz)
SERIAL LINK BIT-RATE
(Mbps)
AVAILABLE SPREAD RATES
< 33.3
33.3 to < 66.7
66.7+
< 25
20 to <50
50+
< 1000
1000 to < 2000
2000+
All rates available
1.5%, 1%, 0.5%
0.5%
26 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
a low-power state. Entering sleep mode resets the HDCP
registers but not the configuration registers.
Manual Programming of the
Spread-Spectrum Divider
The modulation rate for the serializer relates to the
RXCLKIN_ frequency as follows:
Power-Down Mode
The serializer includes a shutdown mode to further
reduce power consumption. Set PWDN low to enter
power-down mode. While in power-down mode, the
outputs of the device remain high impedance. Entering
power-down mode resets the internal registers of the
device. In addition, upon exiting power-down mode, the
serializer relatches the state of SSEN, DRS, AUTOS,
and ADD_.
f
RXCLKIN_
f
= (1+ DRS)
M
MOD x SDIV
where:
= Modulation frequency
f
M
DRS = DRS pin input value (0 or 1)
= RXCLKIN_ frequency
f
RXCLKIN_
Configuration Link Mode
The GMSL includes a low-speed configuration link to
allow control-data connection between the two devices
in the absence of a valid clock input. In either display or
camera applications, the configuration link can be used
to program equalizer/preemphasis or other registers
before establishing the video link. An internal oscillator
provides RXCLKIN_ for establishing the serial configura-
tion link between the serializer and GMSL deserializer.
Set CLINKEN = 1 on the serializer to turn on the con-
figuration link. The configuration link remains active as
long as the video link has not been enabled. The video
link overrides the configuration link and attempts to lock
when SEREN = 1.
MOD = Modulation coefficient given in Table 8
SDIV = 6-bit SDIV setting, manually programmed by
the FC
To program the SDIV setting, first look up the modulation
coefficient according to the part number and desired
bus-width and spread-spectrum settings. Solve the
above equation for SDIV using the desired pixel clock
and modulation frequencies. If the calculated SDIV value
is larger than the maximum allowed SDIV value in Table
8, set SDIV to the maximum value.
Sleep Mode
The serializer includes a low-power sleep mode to
reduce power consumption. Set the SLEEP bit to 1 to
initiate sleep mode. The serializer sleeps immediately
after setting its SLEEP = 1. See the Link Startup
Procedure section for details on waking up the device
for different FC and starting conditions.
Link Startup Procedure
Table 9 lists four startup cases for video-display applica-
tions. Table 10 lists two startup cases for image-sensing
applications. In either video-display or image-sensing
applications, the control link is always available after
the high-speed data link or the configuration link is
The FC can only put the remote-side device to sleep.
Use the PWDN input pin to bring the FC-side device into
Table 8. Modulation Coefficients and Maximum SDIV Settings
SPREAD-SPECTRUM
SETTING (%)
MODULATION COEFFICIENT
MOD (decimal)
SDIV UPPER LIMIT
(decimal)
BIT-WIDTH MODE
1
0.5
3
104
104
152
152
204
204
80
40
63
27
54
15
30
52
63
37
63
21
42
4-Channel
1.5
4
2
1
0.5
3
80
112
112
152
152
3-Channel
1.5
4
2
______________________________________________________________________________________ 27
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
established and the serializer/GMSL deserializer regis-
ters or the peripherals are ready for programming.
to the GMSL deserializer. The GMSL deserializer exits
sleep mode after locking to the serial data and sets
SLEEP = 0. If after 8ms the GMSL deserializer does
not lock to the input serial data, the GMSL deserializer
goes back to sleep and the internal sleep bit remains set
(SLEEP = 1).
Video-Display Applications
For the video-display application with a remote display
unit, connect the FC to the serializer and set CDS = low
for both the serializer and GMSL deserializer. Table 9
summarizes the four startup cases based on the settings
of AUTOS and MS.
Case 3: Remote-Side Autostart Mode
After power-up or when PWDN transitions from low
to high, the remote device (GMSL deserializer) starts
up and tries to lock to an incoming serial signal with
sufficient power. The host side (serializer) is in standby
mode and does not try to establish a link. Use the FC and
program the serializer to set SEREN = 1 (and apply a
stable clock signal) to establish a video link, or CLINKEN
= 1 to establish the configuration link. In this case, the
GMSL deserializer ignores the short wake-up signal sent
from the serializer.
Case 1: Autostart Mode
After power-up or when PWDN transitions from low to
high for both the serializer and GMSL deserializer, the
serial link establishes if a stable clock is present. The
serializer locks to the clock and sends the serial data
to the GMSL deserializer. The GMSL deserializer then
detects activity on the serial link and locks to the input
serial data.
Case 2: Standby Start Mode
After power-up or when PWDN transitions from low to
high for both the serializer and GMSL deserializer, the
GMSL deserializer starts up in sleep mode and the
serializer stays in standby mode (does not send serial
data). Use the FC and program the serializer to set
SEREN = 1 to establish a video link, or CLINKEN = 1
to establish the configuration link. After locking to a
stable clock (for SEREN = 1) or the internal oscillator
(for CLINKEN = 1), the serializer sends a wake-up signal
Case 4: Remote Side in Sleep Mode
After power-up or when PWDN transitions from low to
high, the remote device (GMSL deserializer) starts up in
sleep mode. The high-speed link establishes automati-
cally after the serializer powers up with a stable clock
signal and sends a wake-up signal to the GMSL dese-
rializer. Use this mode in applications where the GMSL
deserializer powers up before the serializer.
Table 9. Start Mode Selection for Display Applications (CDS = Low)
SERIALIZER
POWER-UP
STATE
MS
(GMSL
DESERIALIZER)
GMSL
DESERIALIZER
POWER-UP STATE
AUTOS
(SERIALIZER)
CASE
LINK STARTUP MODE
Serialization
enabled
Normal
(SLEEP = 0)
Both devices power up with serial link
active (autostart).
1
Low
Low
The serial link is disabled and the
GMSL deserializer powers up in sleep
mode. Set SEREN = 1 or CLINKEN =
1 in the serializer to start the serial link
and wake up the GMSL deserializer.
Serialization
disabled
Sleep mode
(SLEEP = 1)
2
High
High
Both devices power up in normal mode
with the serial link disabled. Set SEREN
= 1 or CLINKEN = 1 in the serializer to
start the serial link.
Serialization
disabled
Normal
(SLEEP = 0)
3
4
High
Low
Low
The GMSL deserializer starts in sleep
mode. Link autostarts upon serializer
power-up. Use this case when the
GMSL deserializer powers up before
the serializer.
Serialization
enabled
Sleep mode
(SLEEP = 1)
High
28 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
CLINKEN = 0 OR
SEREN = 1
SEREN BIT
POWER-UP VALUE
AUTOS PIN
SETTING
LOW
HIGH
1
0
CLINKEN = 0 OR
SEREN = 1
CONFIG LINK
UNLOCKED
PWDN = HIGH,
POWER-ON
CONFIG LINK
OPERATING
POWER-DOWN
OR POWER-OFF
POWER-ON
IDLE
CONFIG
LINK STARTING
PROGRAM
REGISTERS
AUTOS = LOW
CLINKEN = 1
CONFIG LINK
LOCKED
SEREN = 0,
NO RXCLKIN_
SEREN = 1,
RXCLKIN_ RUNNING
PWDN = LOW OR
POWER-OFF
PWDN = HIGH
POWER-ON,
AUTOS = LOW
SEREN = 0, OR
NO RXCLKIN_
PRBSEN = 0
PRBSEN = 1
VIDEO LINK
LOCKED
VIDEO
LINK LOCKING
VIDEO LINK
OPERATING
VIDEO LINK
PRBS TEST
ALL STATES
VIDEO LINK
UNLOCKED
Figure 23. State Diagram, CDS = Low (LCD Application)
the sleep bit (SLEEP = 0) of the serializer using a regular
control-channel write packet to power up the device fully.
Send the sleep bit write packet at least 500Fs after the
wake-up frame. The serializer goes back to sleep mode
if its sleep bit is not cleared within 5ms (min) after detect-
ing a wake-up frame.
Image-Sensing Applications
For image-sensing applications, connect the FC to the
GMSL deserializer and set CDS = high for both the
serializer and GMSL deserializer. The GMSL deserial-
izer powers up normally (SLEEP = 0) and continuously
tries to lock to a valid serial input. Table 10 summarizes
both startup cases, based on the state of the serializer’s
AUTOS pin.
HDCP
The explanation of HDCP operation in this data
sheet is given as a guide for general understand-
ing. Implementation of HDCP in a product must
meet the requirements given in the “HDCP System
v1.3 Amendment for GMSL,” which is available from
DCP, LLC.
Case 1: Autostart Mode
After power-up, or when PWDN transitions from low to
high, the serializer locks to a stable input clock and
sends the high-speed data to the GMSL deserializer. The
GMSL deserializer locks to the serial data and outputs
the video data and clock.
HDCP uses two main phases of operation: authentication
and the link integrity check. The FC starts authentication
by writing to the START_AUTHENTICATION bit in the
serializer. The serializer generates a 64-bit random num-
ber. The host FC first reads the 64-bit random number
from the serializer and writes it to the GMSL deserializer.
The FC then reads the serializer public key selection
vector (AKSV) and writes it to the GMSL deserializer.
The FC then reads the GMSL deserializer KSV (AKSV)
Case 2: Sleep Mode
After power-up or when PWDN transitions from low to
high, the serializer starts up in sleep mode. To wake up
the serializer, use the FC to send a GMSL-protocol UART
frame containing at least three rising edges (e.g., 0x66),
at a bit rate no greater than 1Mbps. The low-power wake-
up receiver of the serializer detects the wake-up frame
over the reverse control channel and powers up. Reset
______________________________________________________________________________________ 29
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 10. Start Mode Selection for Image-Sensing Applications (CDS = High)
SERIALIZER POWER-
UP STATE
GMSL DESERIALIZER
POWER-UP STATE
AUTOS
(SERIALIZER)
CASE
LINK STARTUP MODE
Autostart.
Normal
(SLEEP = 0)
1
Low
Serialization enabled
The serializer is in sleep mode. Wake up
the serializer through the control channel
(FC attached to GMSL deserializer).
Sleep mode
(SLEEP = 1)
Normal
(SLEEP = 0)
2
High
POWER-UP VALUE
AUTOS PIN
SETTING
SEREN
SLEEP
CLINKEN = 0 OR
SEREN = 1
LOW
HIGH
1
0
0
1
CLINKEN = 0 OR
SEREN = 1
SLEEP = 1
FOR > 8ms
CONFIG LINK
UNLOCKED
CONFIG LINK
OPERATING
SLEEP = 0,
POWER-ON
IDLE
CONFIG
LINK STARTED
SLEEP
WAKE-UP
SEREN = 0
PROGRAM
REGISTERS
CLINKEN = 1
CONFIG LINK
LOCKED
REVERSE LINK
WAKE-UP SIGNAL
SEREN = 1,
RXCLKIN_ RUNNING
PWDN = HIGH,
POWER-ON,
AUTOS = HIGH
SEREN = 0 OR
NO RXCLKIN_
SLEEP = 0,
SLEEP = 1
SLEEP = 1
SEREN = 0 OR
NO RXCLKIN_
PWDN = HIGH,
POWER-ON
PRBSEN = 0
PRBSEN = 1
POWER-DOWN
OR
POWER-OFF
VIDEO LINK
LOCKED
PWDN = LOW OR
POWER-OFF
VIDEO
LINK LOCKING
VIDEO LINK
OPERATING
VIDEO LINK
PRBS TEST
ALL STATES
AUTOS = LOW
VIDEO LINK
UNLOCKED
Figure 24. State Diagram, CDS = High (Camera Application)
and writes it to the serializer. The FC begins checking
the receiver BKSV against the revocation list. Using the
cipher, the serializer and GMSL deserializer calculate
a 16-bit response value (R0 and R0’, respectively).
The GMSL amendment for HDCP reduces the 100ms
minimum wait time allowed the receiver to generate R0’
(specified in HDCP rev 1.3) to 128 pixel clock cycles in
the GMSL amendment.
reads and compares the R0/R0’ values from the serial-
izer/GMSL deserializer.
During response value generation and checking, the
host FC checks for a valid BKSV against the revocation
list. If BKSV is not on the list and the response values
match, the host authenticates the link. If the response
values do not match, the FC resamples the response
values (as described in HDCP rev 1.3 Appendix C). If
resampling fails, the FC restarts authentication. If BKSV
appears on the revocation list, the host cannot transmit
data that requires protection. The host knows when the
link is authenticated and decides when to output data
requiring protection. The FC performs a link integrity
check every 128 frames or every 2s Q0.5s. The serializer/
GMSL deserializer generate response values every 128
frames. These values are compared internally (internal
comparison mode) or can be compared in the host FC.
There are two response value comparison modes: internal
comparison and FC comparison. Set EN_INT_COMP = 1
to select internal comparison mode. Set EN_INT_COMP =
0 to select FC comparison mode. In internal comparison
mode, the FC reads the GMSL deserializer response R0’
and writes it to the serializer. The serializer compares
R0’ to its internally generated response value R0, and
sets R0_RI_MATCHED. In FC comparison mode, the FC
30 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Repeater Support
The serializer has features to build an HDCP repeater.
An HDCP repeater receives and decrypts HDCP content
and then encrypts and transmits on one or more down-
stream links. A repeater can also use decrypted HDCP
content (e.g., to display on a screen). To support HDCP
repeater authentication protocol, the GMSL deserial-
izer has a REPEATER register bit. This register bit must
be set to 1 by the FC (most likely on repeater module).
Both the serializer and GMSL deserializer use SHA-1
hash-value calculation over the assembled KSV lists.
HDCP GMSL links support a maximum of 15 receivers
(total number including the ones in repeater modules). If
the total number of receiver devices exceed 14, the FC
must set the MAX_DEVS_EXCEEDED register bit when it
assembles the KSV list.
In addition, the serializer/GMSL deserializer provide
response values for the enhanced link verification
feature. Enhanced link verification is an optional meth-
od of link verification for faster detection of loss-of-
synchronization. For this option, the serializer and GMSL
deserializer generate 16-bit values (Pj and Pj’) every 16
frames. The host must detect three consecutive Pj/Pj’
mismatches before going to the resampling.
Encryption Enable
The GMSL link transfers either encrypted or nonen-
crypted data. For encrypted data, the host FC sets the
encryption enable (ENCRYPTION_ENABLE) bit in both
the serializer and GMSL deserializer. The FC must set
ENCRYPTION_ENABLE in the same VSYNC cycle in
both the serializer and GMSL deserializer (no VSYNC
falling edges between the two writes). The same timing
applies when clearing ENCRYPTION_ENABLE to disable
encryption.
Force Video/Force Audio for Unencrypted Data
The serializer masks audio and video data through two
control bits: FORCE_AUDIO and FORCE_VIDEO. Set
FORCE_VIDEO = 1 to transmit the 24-bit data word in
the DFORCE register instead of the video data received
at the LVDS input. Set FORCE_AUDIO = 0 to transmit
0 instead of the SD input (SCK and WS continue to be
output from the deserializer). Use these features to blank
out the screen and mute the audio.
Note: ENCRYPTION_ENABLE enables/disables encryp-
tion on the GMSL irrespective of the content. To comply
with HDCP, the FC must not allow content requiring
encryption to cross the GMSL unencrypted. See the
Force Video/Force Audio for Unencrypted Data section.
The FC must complete the authentication process before
enabling encryption. In addition, encryption must be
disabled before starting a new authentication session.
HDCP Authentication Procedures
VSYNC Detection
If the FC cannot detect the video vertical sync (VSYNC)
falling edge, it can use the serializer’s VSYNC_DET
register bit. The host FC first writes 0 to the VSYNC_DET
bit. The serializer then sets VSYNC_DET = 1 once
it detects an internal VSYNC falling edge (which
may correspond to an external VSYNC rising edge if
INVVSYNC of the serializer is set). The FC continu-
ously reads VSYNC_DET and waits for the next inter-
nal VSYNC falling edge before setting ENCRYPTION_
ENABLE. Poll VSYNC_DET fast enough to allow time to
set ENCRYPTION_ENABLE in both the serializer/GMSL
deserializer within the same VSYNC cycle.
The serializer generates a 64-bit random number
exceeding the HDCP requirement. The serializer/GMSL
deserializer internal one-time programmable (OTP)
memories contain unique HDCP keyset programmed at
the factory. The host FC initiates and controls the HDCP
authentication procedure. The serializer and GMSL
deserializer generate HDCP authentication response
values for the verification of authentication. Use the
following procedures to authenticate the HDCP GMSL
encryption (refer to the HDCP 1.3 Amendment for GMSL
for details). The FC must perform link integrity checks
while encryption is enabled (see Tables 12 and 13). Any
event that indicates that the GMSL deserializer has lost
link synchronization should retrigger authentication. The
FC must first write 1 to the RESET_HDCP bit in the serial-
izer before starting a new authentication attempt.
Synchronization of Encryption
The VSYNC synchronizes the start of encryption. Once
encryption has started, the GMSL generates a new
encryption key for each frame and each line, with the
internal falling edge of VSYNC and HSYNC. Rekeying is
transparent to data and does not disrupt the encryption
of video or audio data.
HDCP Protocol Summary
Tables 11, 12, and 13 list the summaries of the HDCP
protocol. These tables serve as an implementation guide
only. Meet the requirements in the GMSL amendment for
HDCP to be in full compliance.
______________________________________________________________________________________ 31
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 11. Startup, HDCP Authentication and Normal Operation (GMSL DESERIALIZER
is not a Repeater)—First Part of the HDCP Authentication Protocol
NO.
µC
SERIALIZER
GMSL DESERIALIZER
Powers up waiting for
HDCP authentication.
Powers up waiting for
HDCP authentication.
1
Initial state after power-up.
Ensures that A/V data not requiring protection (low-value
content) is available at the serializer inputs (such as blue or
informative screen). Alternatively, use the FORCE_VIDEO
and FORCE_AUDIO bits of the serializer to mask the A/V
data at the input of the serializer. Starts the link by writing
SEREN = H or link starts automatically if AUTOS is low.
2
—
—
Starts serialization and
Locks to incoming data
3
4
—
transmits low-value content stream and outputs low-
A/V data.
value content A/V data.
Reads the locked bit of the GMSL deserializer and makes
sure link is established.
—
—
Combines seed with inter-
nally generated random
number. If no seed is pro-
vided, only internal random
number is used.
5
6
Optionally writes a random-number seed to the serializer.
—
—
If HDCP encryption is required, starts authentication by
writing 1 to the START_AUTHENTICATION bit of the
serializer.
Generates (stores) AN
and resets the START_
AUTHENTICATION bit to 0.
Reads AN and AKSV from the serializer and writes to the
GMSL deserializer.
Generates R0’ triggered by
the FC’s write of AKSV.
7
8
—
Reads the BKSV and REPEATER bit from the GMSL deseri- Generates R0, triggered by
alizer and writes to the serializer.
—
—
the FC’s write of BKSV.
Reads the INVALID_BKSV bit of the serializer and con-
tinues with authentication if it is 0. Authentication can be
restarted if it fails (set RESET_HDCP = 1 before restarting
authentication).
9
—
Reads R0’ from the GMSL deserializer and reads R0 from
the serializer. If they match, continues with authentication;
otherwise retries up to two more times (optionally, the seri-
alizer comparison can be used to detect if R0/R0’ match).
Authentication can be restarted if it fails (set RESET_HDCP
= 1 before restarting authentication).
10
—
—
Waits for the VSYNC falling edge (internal to the serial-
izer) and then sets the ENCRYPTION_ENABLE bit to 1 in
the GMSL deserializer and serializer (if the FC is not able
to monitor VSYNC, it can utilize the VSYNC_DET bit in the
serializer).
Encryption is enabled after
the next VSYNC falling
edge.
Decryption is enabled after
the next VSYNC falling
edge.
11
32 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 11. Startup, HDCP Authentication and Normal Operation (GMSL DESERIALIZER
is not a Repeater)—First Part of the HDCP Authentication Protocol (continued)
NO.
µC
SERIALIZER
GMSL DESERIALIZER
Checks that BKSV is not in the Key Revocation List and
continues if it is not. Authentication can be restarted if it
12
fails.
—
—
Note: Revocation list check can start after BKSV is read in
step 8.
Performs HDCP encryption
Starts transmission of the A/V content that needs protection. on high-value content A/V
data.
Performs HDCP decryption
on high-value content A/V
data.
13
Table 12. Link Integrity Check (Normal)—Performed Every 128 Frames After Encryption
is Enabled
NO.
µC
SERIALIZER
GMSL DESERIALIZER
Generates Ri and updates
the RI register every 128
VSYNC cycles.
Generates Ri’ and updates
the RI’ register every 128
VSYNC cycles.
1
—
—
Continues to receive,
decrypt, and output A/V
data.
Continues to encrypt and
transmit A/V data.
2
3
Every 128 video frames (VSYNC cycles) or every 2s.
—
—
4
5
Reads RI from the serializer.
—
—
—
—
Reads RI’ from the GMSL deserializer.
Reads RI again from the serializer and ensures it is stable
(matches the previous RI that it has read from the serial-
izer). If RI is not stable, go back to step 5.
6
7
—
—
—
—
If RI matches RI’, the link integrity check is successful; go
back to step 3.
If RI does not match RI’, the link integrity check fails.
After the detection of failure of link integrity check, the FC
ensures that A/V data not requiring protection (low-value
content) is available at the serializer’s inputs (such as blue
or informative screen). Alternatively, the FORCE_VIDEO
and FORCE_AUDIO bits of the serializer can be used to
mask the A/V data input of the serializer.
8
—
—
Disables encryption and
transmits low-value content
A/V data.
Disables decryption and
outputs low-value content
A/V data.
Writes 0 to the ENCRYPTION_ENABLE bit of the serializer
and GMSL deserializer.
9
Restarts authentication by writing 1 to the RESET_HDCP
bit, followed by writing 1 to the START_AUTHENTICATION
bit in the serializer.
10
—
—
______________________________________________________________________________________ 33
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 13. Optional Enhanced Link Integrity Check—Performed Every 16 Frames After
Encryption is Enabled
NO.
µC
SERIALIZER
GMSL DESERIALIZER
Generates Pj and updates
the PJ register every 16
VSYNC cycles.
Generates Pj’ and updates
the PJ’ register every 16
VSYNC cycles.
1
—
—
Continues to receive,
decrypt, and output the
A/V data.
Continues to encrypt and
transmit the A/V data.
2
Every 16 video frames: reads PJ from the serializer and PJ’
from the GMSL deserializer.
3
4
—
—
—
—
If PJ matches PJ’, enhanced link integrity check is
successful; go back to step 3.
If there is a mismatch, retry up to two more times from step
3. Enhanced link integrity check fails after three mismatch-
es. After the detection of failure of enhanced link integrity
check, the FC ensures that A/V data not requiring protec-
tion (low-value content) is available at the serializer inputs
(such as blue or informative screen). Alternatively, the
FORCE_VIDEO and FORCE_AUDIO bits of the serializer
can be used to mask the A/V data input of the serializer.
5
—
—
Disables encryption and
transmits low-value content
A/V data.
Disables decryption and
outputs low-value content
A/V data.
Writes 0 to the ENCRYPTION_ENABLE bit of the serializer
and GMSL deserializer.
6
7
Restarts authentication by writing 1 to the RESET_HDCP
bit, followed by writing 1 to the START_AUTHENTICATION
bit in the serializer.
—
—
Example Repeater Network—Two µCs
Use the following procedure to notify downstream links of
the start of a new authentication request:
The example shown in Figure 25 has one repeater
and two FCs. Table 14 summarizes the authentication
operation.
1) Host FC begins authentication with HDCP repeater’s
input receiver.
Detection and Action Upon
New Device Connection
When a new device is connected to the system, the
device must be authenticated and the device’s KSV is
checked against the revocation list. The downstream
FCs can set the NEW_DEV_CONN bit of the upstream
receiver and invoke an interrupt to notify upstream FCs.
2) When AKSV is written to HDCP repeater’s input
receiver, its AUTH_STARTED bit is automatically set
and its GPIO1 goes high (if GPIO1_FUNCTION is set
to high).
3) HDCP repeater’s FC waits for a low-to-high transition
on HDCP repeater input receiver’s AUTH_STARTED
bit and/or GPIO1 (if configured) and starts authentica-
tion downstream.
Notification of Start of Authentication and
Enable of Encryption to Downstream Links
HDCP repeaters do not immediately begin authentication
upon startup or detection of a new device, but instead
wait for an authentication request from the upstream
transmitter/repeaters.
4) HDCP repeater’s FC resets AUTH_STARTED bit.
Set GPIO0_FUNCTION to high to have GPIO0 follow the
ENCRYPTION_ENABLE bit of the receiver. The repeater
FC can use this function to be notified when encryption
is enabled/disabled by an upstream FC.
34 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
BD-DRIVE
TX_B1
REPEATER
RX_R1
DISPLAY 1
RX_D1
TX_R1
VIDEO
ROUTING
µC_B
DISPLAY 2
RX_D2
MEMORY
WITH SRM
RX_R2
µC_R
TX_R2
VIDEO CONNECTION
CONTROL CONNECTION 1 (µC_B IN BD-DRIVE IS MASTER)
CONTROL CONNECTION 2 (µC_R IN REPEATER IS MASTER)
Figure 25. Example Network with One Repeater and Two µCs (TXs are for the Serializer and RXs are for the GMSL Deserializer)
Table 14. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol
GMSL
SERIALIZER
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
NO.
µC_B
µC_R
(TX_B1, TX_R1,
TX_R2)
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
—
1
—
—
All: Power-up
waiting for HDCP
authentication.
All: Power-up
waiting for HDCP
authentication.
Initial state after power-up.
Initial state after power-up.
Writes REPEATER = 1 in RX_R1.
Retries until a proper acknowledge
frame is received. Note: This step
must be completed before the first
part of the authentication is started
between TX_B1 and RX_R1 by FC_B
(step 7). For example, to satisfy this
requirement, RX_R1 can be held at
power-down until FC_R is ready to
write the REPEATER bit. Alternatively,
FC_B can poll FC_R before starting
authentication.
2
—
—
—
______________________________________________________________________________________ 35
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 14. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol (continued)
GMSL
SERIALIZER
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
NO.
µC_B
µC_R
(TX_B1, TX_R1,
TX_R2)
Ensures that the A/V data not requir-
ing protection (low-value content)
is available at TX_B1 inputs (such
as blue or informative screen).
Alternatively, the FORCE_VIDEO
and FORCE_AUDIO bits of TX_B1
can be used to mask the A/V data
input of TX_B1. Starts the link
RX_R1: Locks to
incoming data
stream and out-
puts low-value
content A/V data.
TX_B1: Starts
serialization and
transmits low-value
content A/V data.
3
—
between TX_B1 and RX_R1 by writ-
ing SEREN = H to TX_B1 or link
starts automatically if AUTOS is low.
TX_R1, TX_R2:
Starts serialization
and transmits low-
value content A/V
data.
RX_D1, RX_D2:
Locks to incoming
data stream and
outputs low-value
content A/V data.
Starts all downstream links by writing
SEREN = H to TX_R1, TX_R2, or links
start automatically if AUTOS of the
transmitters are low.
4
5
—
Reads the locked bit of RX_D1 and
ensures link between TX_R1 and
RX_D1 is established. Reads the
locked bit of RX_D2 and ensures link
between TX_R2 and RX_D2 is estab-
lished.
Reads the locked bit of RX_R1 and
ensures link between TX_B1 and
RX_R1 is established.
—
—
—
—
Writes 1 to the GPIO_0_FUNCTION
and GPIO_1_FUNCTION bits in
RX_R1 to change GPIO functional-
ity to be used for HDCP purpose.
Optionally, writes a random-number
seed to TX_R1 and TX_R2.
Optionally, writes a random-number
seed to TX_B1.
6
TX_B1: According
to the commands
from FC_B, gen-
erates AN, com-
putes R0.
Starts and completes first part of
the authentication protocol between
TX_B1, RX_R1 (see steps 6–10 in
Table 11).
RX_R1: According
to the commands
from FC_B, com-
putes R0’.
7
8
—
When GPIO_1 = 1 is detected,
TX_R1, TX_R2:
RX_D1, RX_D2:
According to the
commands from
FC_R, computes
R0’.
starts and completes first part of
the authentication protocol between
(TX_R1, RX_D1) and (TX_R2, RX_D2)
links (see steps 6–10 in Table 11).
According to the
commands from
FC_R, generates
AN, computes R0.
—
36 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 14. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol (continued)
GMSL
SERIALIZER
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
NO.
µC_B
µC_R
(TX_B1, TX_R1,
TX_R2)
Waits for the VSYNC falling edge
and then enables encryption on the
(TX_B1, RX_R1) link. Full
authentication is not complete yet
so it ensures A/V content that needs
protection is not transmitted. Since
REPEATER = 1 was read from
RX_R1, the second part of authenti-
cation is required.
TX_B1: Encryption
is enabled after
the next VSYNC
falling edge.
RX_R1: Decryption
is enabled after
the next VSYNC
falling edge.
9
—
TX_R1, TX_R2:
Encryption is
enabled after the
RX_D1, RX_D2:
Decryption is
enabled after the
When GPIO_0 = 1 is detected,
enables encryption on the (TX_R1,
RX_D1) and (TX_R2, RX_D2) links.
10
11
—
next VSYNC falling next VSYNC falling
edge.
edge.
RX_R1: Control
channel from the
serializer side
(TX_B1) is blocked
after FWDCCEN =
REVCCEN = 0 is
written.
Blocks control channel from FC_B
side by setting REVCCEN =
FWDCCEN = 0 in RX_R1. Retries
until the proper acknowledge frame
is received.
—
RX_R1: Triggered
by FC_R’s write of
BINFO, calculates
hash value (V’)
on the KSV list,
BINFO, and the
secret value M0’.
Waits for some time to allow FC_R to
make the KSV List ready in RX_R1.
Then polls (reads) the KSV_LIST_
READY bit of RX_R1 regularly until
the proper acknowledge frame is
received and bit is read as 1.
Writes BKSVs of RX_D1 and RX_D2
to KSV List in RX_R1. Then calculates
and writes BINFO register of RX_R1.
12
—
RX_R1: Control
channel from the
serializer side (TX_
B1) is unblocked
after FWDCCEN =
REVCCEN = 1 is
written.
Writes 1 to the KSV_LIST_READY bit
of RX_R1 and then unblocks control
channel from FC_B side by set-
ting REVCCEN = FWDCCEN = 1 in
RX_R1.
13
—
______________________________________________________________________________________ 37
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 14. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol (continued)
GMSL
SERIALIZER
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
NO.
µC_B
µC_R
(TX_B1, TX_R1,
TX_R2)
Reads the KSV List and BINFO from
RX_R1 and writes them to TX_B1. If
any of the MAX_DEVS_EXCEEDED
or MAX_CASCADE_EXCEEDED bits
is 1, then authentication fails. Note:
BINFO must be written after the KSV
List.
TX_B1: Triggered
by FC_B’s write of
BINFO, calculates
hash value (V)
on the KSV list,
BINFO, and the
secret value M0.
14
—
—
—
Reads V from TX_B1 and V’ from
RX_R1. If they match, continues with
authentication; otherwise, retries up
to two more times.
15
—
—
Searches for each KSV in the KSV
List and BKSV of RX_R1 in the Key
Revocation List.
16
17
18
—
—
—
—
—
—
—
If keys are not revoked, second part
of authentication protocol is com-
pleted.
All: Perform HDCP
encryption on high-
value A/V data.
All: Perform HDCP
decryption on high-
value A/V data.
Starts transmission of the A/V con-
tent that needs protection.
are set to high. However, if the CDS pin of the serializer
is low and the same pin of the GMSL deserializer is high,
then the serializer/GMSL deserializer connect to both
FCs simultaneously. In such a case, the FCs on either
side can communicate with the serializer and GMSL.
Contentions of the control link can happen if the FCs on
both sides are using the link at the same time. The seri-
alizer/GMSL deserializer do not provide the solution for
contention avoidance. The serializer/GMSL deserializer
do not send an acknowledge frame when communica-
tion fails due to contention. Users can always implement
a higher layer protocol to avoid the contention. In addi-
tion, if UART communication across the serial link is not
required, the FCs can disable the forward and reverse
control channel through the FWDCCEN and REVCCEN
bits (0x04, D[1:0]) in the serializer/GMSL deserializer.
UART communication across the serial link is stopped
and contention between FCs no longer occurs. During
dual FC operation, if one of the CDS pins on either side
changes state, the link resumes the corresponding state
described in the Link Startup Procedure section.
Applications Information
Self PRBS Test
The serializer/GMSL deserializer link includes a PRBS
pattern generator and bit-error verification function. First,
disable the glitch filters (set DISVSFILT, DISHSFILT to 1)
in the GMSL deserializer. Next, disable VSYNC/HSYNC
inversion in both the serializer and GMSL deserialzer
(set INVVSYNC, INVHSYNC to 0). Then, set PRBSEN = 1
(0x04, D5) in the serializer and then the GMSL deserial-
izer to start the PRBS test. Set PRBSEN = 0 (0x04, D5)
first in the GMSL deserializer and then the serializer to
exit the PRBS self test.
Microcontrollers on Both Sides of the
GMSL Link (Dual µC Control)
Usually the microcontroller is either on the serializer side
for video-display applications or on the GMSL deserial-
izer side for image-sensing applications. For the former
case, both the CDS pins of the serializer/GMSL deserial-
izer are set to low, and for the later case, the CDS pins
38 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
As an example of dual FC use in an image-sensing appli-
accurately tracks the LOCK status of the video link.
LOCK asserts for video link only and not for the configu-
ration link.
cation, the serializer can be in sleep mode and waiting
for wake-up by the GMSL deserializer. After wake-up,
the serializer-side FC sets the serializer’s CDS pin low
and assumes master control of the serializer’s registers.
Software Programming of the
Device Addresses
Jitter-Filtering PLL
In some applications, the LVDS input clock to the serial-
izer (RXCLKIN_) includes noise, which reduces link reli-
ability. The serializer has a narrowband jitter-filtering PLL
to attenuate frequency components outside the PLL’s
bandwidth (< 100kHz, typ). Enable the jitter-filtering PLL
by setting DISFPLL = 0 (0x05, D6).
Both the serializer and GMSL deserializer have software-
programmable device addresses. This allows multiple
GMSL devices, along with I2C peripherals to coexist on
the same control channel. The serializer device address
is stored in registers 0x00 of each device, while the
deserializer device address is stored in register 0x01 of
each device. To change the device address, first write
to the device whose address changes (register 0x00 of
the serializer for serializer device address change, or
register 0x01 of the GMSL deserializer for deserializer
device address change). Then write the same address
into the corresponding register on the other device
(register 0x00 of the GMSL deserializer for serializer
device address change, or register 0x01 of the serializer
for deserializer device address change).
Changing the Clock Frequency
Both the video clock rate (f
) and the control-
RXCLKIN_
channel clock rate (f ) can be changed on-the-fly
UART
to support applications with multiple clock speeds. It is
recommended to enable the serial link after the video
clock stabilizes. To recalibrate any automatic settings
if a clean frequency change cannot be guaranteed,
stop the video clock for 5Fs and restart the serial link
or toggle SEREN after each change in the video clock
frequency. The reverse control channel remains unavail-
able for 350Fs after serial link start or stop. Limit on-the-
3-Level Inputs for Default Device Address
ADD0 and ADD1 are 3-level inputs that control the serial-
izer’s default device slave addresses (Table 2). Connect
ADD0/ADD1 through a pullup resistor to IOVDD, a
pulldown resistor to GND, or a high-impedance connec-
tion. For digital control, use three-state logic to drive the
3-level logic inputs.
fly changes in f
to factors of less than 3.5 at a time
UART
to ensure that the device recognizes the UART sync
pattern. For example, when lowering the UART frequen-
cy from 1Mbps to 100kbps, first send data at 333kbps
and then at 100kbps to have reduction ratios of 3 and
3.333, respectively.
ADD0/ADD1 set the device addresses in the serializer
only and not the GMSL deserializer. Set the GMSL dese-
rializer’s ADD0/ADD1 inputs to the same settings as the
serializer. Alternatively, write to register 0x00 and 0x01 of
the GMSL deserializer to reflect any changes made due
to the 3-level inputs.
Do not interrupt RXCLKIN or change its frequency while
encryption is enabled. Otherwise HDCP synchronization
is lost and authentication must be repeated. To change
the RXCLKIN_ frequency, stop the high-value content
A/V data. Then disable encryption in the serializer/GMSL
deserializer within the same VSYNC cycle—encryption
stops at the next VSYNC falling edge. RXCLKIN can now
be changed/stopped. Reenable encryption before send-
ing any high-value content A/V data.
Configuration Blocking
The serializer can block changes to its non-HDCP
registers. Set CFGBLOCK to make all non-HDCP
registers as read only. Once set, the registers remain
blocked until the supplies are removed or until PWDN
is low.
Fast Detection of Loss-of-Synchronization
A measure of link quality is the recovery time from loss
of HDCP synchronization. With the GMSL, loss of GMSL
lock usually accompanies a loss of HDCP sync. The host
can be quickly notified of loss-of-lock by connecting the
GMSL deserializer LOCK output to the INT input. If other
sources use the interrupt input, such as a touch-screen
controller, the FC can implement a routine to distin-
guish between interrupts from loss-of-sync and normal
interrupts. Reverse control-channel communication does
not require an active forward link to operate and
Backward Compatibility
The serializer is backward compatible with the non-
HDCP MAX9249 serializer, with the following exceptions:
•ꢀ Address pins: The ADD0 and ADD1 pins on the
serializer are the reserved pins on the MAX9249
serializer. Connect ADD0 and ADD1 to GND to set
the serializer’s default device addresses to the same
values as the MAX9249 serializer.
______________________________________________________________________________________ 39
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
•ꢀ First UART packet delay: The FC must wait 2.7ms
after power-up before sending the first UART packet
to the serializer. This delay is < 200Fs for the
MAX9249 serializer.
Internal Input Pulldowns
The control and configuration inputs on the serializer/
GMSL deserializer include a pulldown resistor to GND.
Pulldowns are disabled when the device is shut down
PWDN = low) or put into sleep mode. Keep all inputs
driven or use external pullup/pulldown resistors to pre-
vent additional current consumption and undesired con-
figuration due to undefined inputs.
The pinouts and packages are otherwise the same for
both devices. See Table 3 and the Pin Description for
backward-compatible pin mapping.
Key Memory
Each device has a unique HDCP key set that is stored
in secure on-chip nonvolatile memory (NVM). The HDCP
key set consists of forty 56-bit private keys and one
40-bit public key. The NVM is qualified for automotive
applications.
Choosing I2C/UART Pullup Resistors
Both I2C/UART open-drain lines require pullup resistors
to provide a logic-high level. There are tradeoffs between
power dissipation and speed, and a compromise made
in choosing pullup resistor values. Every device connect-
ed to the bus introduces some capacitance even when
the device is not in operation. I2C specifies 300ns rise
times to go from low to high (30% to 70%) for fast mode,
which is defined for data rates up to 400kbps (see the
I2C specifications in the Electrical Characteristics table
for details). To meet the fast-mode rise-time require-
Line-Fault Detection
The line-fault detector in the serializer monitors for line
failures such as short to ground, short to battery, and
open link for system fault diagnosis. Figure 3 shows the
required external resistor connections. LFLT = low when
a line fault is detected and LFLT goes high when the line
returns to normal. The line-fault type is stored in 0x08
D[3:0] of the serializer. Filter LFLT with the FC to reduce
the detector’s susceptibility to short ground shifts. The
fault detector threshold voltages are referenced to the
serializer ground. Additional passive components set the
DC level of the cable (Figure 3). If the serializer and GMSL
deserializer grounds are different, the link DC voltage dur-
ing normal operation can vary and cross one of the fault-
detection thresholds. For the fault-detection circuit, select
the resistor’s power rating to handle a short to the battery.
ment, choose the pullup resistors so that rise time t
=
R
0.85 x R
x C
< 300ns. The waveforms are not
PULLUP
BUS
recognized if the transition time becomes too slow. The
serializer/GMSL deserializer supports I2C/UART rates up
to 1Mbps.
AC-Coupling
AC-coupling isolates the receiver from DC voltages up to
the voltage rating of the capacitor. Four capacitors (two
at the serializer output and two at the deserializer input)
are needed for proper link operation and to provide
protection if either end of the cable is shorted to a high
voltage. AC-coupling blocks low-frequency ground shifts
and low-frequency common-mode noise.
To detect the short-together case, refer to Application
Note 4709: GMSL Line-Fault Detection.
Table 15 lists the mapping for line-fault types.
Table 15. Line-Fault Mapping
REGISTER ADDRESS
BITS
NAME
VALUE
00
LINE FAULT TYPE
Negative cable wire shorted to supply voltage.
Negative cable wire shorted to ground.
Normal operation.
01
D[3:2]
LFNEG
10
11
Negative cable wire disconnected.
Positive cable wire shorted to supply voltage.
Positive cable wire shorted to ground.
Normal operation.
0x08
00
01
D[1:0]
LFPOS
10
11
Positive cable wire disconnected.
*For the short-together case, refer to Application Note 4709: GMSL Line-Fault Detection.
40 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
canceling effects. Balanced cables pick up noise as
common mode rejected by the CML receiver. Table 16
lists the suggested cables and connectors used in the
GMSL link.
Selection of AC-Coupling Capacitors
Voltage droop and the digital sum variation (DSV) of
transmitted symbols cause signal transitions to start
from different voltage levels. Because the transition time
is finite, starting the signal transition from different volt-
age levels causes timing jitter. Choose the time constant
for an AC-coupled link to reduce droop and jitter to an
acceptable level. The RC network for an AC-coupled link
Board Layout
Separate the digital signals and CML/LVDS high-speed
signals to prevent crosstalk. Use a four-layer PCB with
separate layers for power, ground, CML/LVDS, and
digital signals. Lay out PCB traces close to each other
for a 100I differential characteristic impedance. The
trace dimensions depend on the type of trace used
(microstrip or stripline). Note that two 50I PCB traces
do not have 100I differential impedance when brought
close together—the impedance goes down when the
traces are brought closer.
consists of the CML receiver termination resistor (R ),
TR
the CML driver termination resistor (R ), and the series
TD
AC-coupling capacitors (C). The RC time constant for
four equal-value series capacitors is (C x (R + R ))/4.
TD
TR
R
TD
and R
are required to match the transmission
TR
line impedance (usually 100I). This leaves the capaci-
tor selection to change the system time constant. Use
at least 0.2FF high-frequency surface-mount ceramic
capacitors, with sufficient voltage rating to withstand a
short to battery, to pass the lower speed reverse control-
channel signal. Use capacitors with a case size less than
3.2mm x 1.6mm to have lower parasitic effects to the
high-speed signal.
Route the PCB traces for a CML/LVDS channel (there
are two conductors per CML/LVDS channel) in parallel to
maintain the differential characteristic impedance. Avoid
vias. Keep PCB traces that make up a differential pair
equal length to avoid skew within the differential pair.
ESD Protection
The serializer’s ESD tolerance is rated for Human Body
Model, IEC 61000-4-2, and ISO 10605. The ISO 10605
and IEC 61000-4-2 standards specify ESD tolerance
for electronic systems. CML/LVDS I/O are tested for
ISO 10605 ESD protection and IEC 61000-4-2 ESD
protection. All pins are tested for the Human Body Model.
Power-Supply Circuits and Bypassing
The serializer uses an AVDD and DVDD of 1.7V to 1.9V,
and an LVDSVDD of 3.0V to 3.6V. All single-ended inputs
and outputs derive power from an IOVDD of 1.7V to 3.6V,
which scale with IOVDD. Proper voltage-supply bypass-
ing is essential for high-frequency circuit stability.
Cables and Connectors
Interconnect for CML typically has a differential imped-
ance of 100I. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Twisted-pair and shielded twisted-pair
cables tend to generate less EMI due to magnetic-field
The Human Body Model discharge components are C
S
= 100pF and R = 1.5kI(Figure 26). The IEC 61000-4-2
D
discharge components are C = 150pF and R = 330I
S
D
(Figure 27). The ISO 10605 discharge components are
C = 330pF and R = 2kI (Figure 28).
S
D
Table 16. Suggested Connectors and
Cables for GMSL
R
D
1MI
1.5kI
VENDOR
Rosenberger
Nissei
CONNECTOR
D4S10A-40ML5-Z
GT11L-2S
CABLE
Dacar 538
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
F-2WME AWG28
A-BW-Lxxxxx
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
100pF
JAE
MX38-FF
STORAGE
CAPACITOR
SOURCE
Figure 26. Human Body Model ESD Test Circuit
______________________________________________________________________________________ 41
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
R
R
D
D
330I
2kI
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
C
S
C
S
330pF
STORAGE
CAPACITOR
STORAGE
CAPACITOR
150pF
SOURCE
SOURCE
Figure 27. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Figure 28. ISO 10605 Contact Discharge ESD Test Circuit
Table 17. Serializer GMSL Core Register Table (see Table 1)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
D[7:1]
D0
NAME
VALUE
FUNCTION
Serializer device address. Power-up default
address determined by ADD0 and ADD1
(see Table 2).
SERID
XXXXXXX
XX00XX0
0
0x00
0
1
Normal operation.
CFGBLOCK
Registers 0x00 to 0x1F are read only.
Deserializer device address. Power-up default
address determined by ADD0 and ADD1
(see Table 2).
D[7:1]
D0
DESID
—
XXXXXXX
XX01XX0
0
0x01
0
Reserved.
No spread spectrum. Power-up default when
SSEN = low.
000
±0.5% spread spectrum. Power-up default when
SSEN = high.
001
010
011
100
101
110
111
0
±1.5% spread spectrum.
D[7:5]
SS
000, 001
±2% spread spectrum.
No spread spectrum.
±1% spread spectrum.
±3% spread spectrum.
±4% spread spectrum.
Disable I2S channel.
Enable I2S channel.
0x02
D4
AUDIOEN
PRNG
1
1
00
12.5MHz to 25MHz pixel clock.
25MHz to 50MHz pixel clock.
50MHz to 104MHz pixel clock.
Automatically detect the pixel clock range.
0.5Gbps to 1Gbps serial-bit rate.
1Gbps to 2Gps serial-bit rate.
2Gbps to 3.125Gbps serial-bit rate.
Automatically detect serial-bit rate.
01
D[3:2]
11
10
11
00
01
D[1:0]
SRNG
11
10
11
42 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 17. Serializer GMSL Core Register Table (see Table 1) (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
00
FUNCTION
Calibrate spread-modulation rate only once after
locking.
Calibrate spread-modulation rate every 2ms after
locking.
01
D[7:6]
AUTOFM
00
000000
0, 1
Calibrate spread-modulation rate every 16ms after
locking.
10
0x03
Calibrate spread-modulation rate every 256ms after
locking.
11
000000
XXXXXX
Autocalibrate sawtooth divider.
D[5:0]
SDIV
Manual SDIV setting. See the Manual Programming
of the Spread-Spectrum Divider section.
Disable serial link. Power-up default when AUTOS
= high. Reverse control-channel communication
remains unavailable for 350Fs after the serializer
starts/stops the serial link.
0
1
D7
SEREN
Enable serial link. Power-up default when AUTOS
= low. Reverse control-channel communication
remains unavailable for 350Fs after the serializer
starts/stops the serial link.
0
1
0
1
Disable configuration link.
Enable configuration link.
Disable PRBS test.
D6
D5
CLINKEN
PRBSEN
0
0
Enable PRBS test.
Normal mode. Default value depends on the CDS
and AUTOS pin values at power-up).
0
1
0x04
D4
D[3:2]
D1
SLEEP
INTTYPE
REVCCEN
0, 1
00
1
Activate sleep mode. Default value depends on the
CDS and AUTOS pin values at power-up.
00
01
Base mode uses I2C peripheral interface.
Base mode uses UART peripheral interface.
Base mode peripheral interface disabled.
10, 11
Disable reverse control channel from deserializer
(receiving).
0
1
0
1
Enable reverse control channel from deserializer
(receiving).
Disable forward control channel to deserializer
(sending).
D0
FWDCCEN
1
Enable forward control channel to deserializer
(sending).
______________________________________________________________________________________ 43
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 17. Serializer GMSL Core Register Table (see Table 1) (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
D7
NAME
I2CMETHOD
DISFPLL
VALUE
FUNCTION
0
1
I2C conversion sends the register address.
Disable sending of I2C register address (command-
byte-only mode).
0
1
0
1
Filter PLL active.
D6
Filter PLL disabled.
Do not use.
00
01
200mV CML signal level.
300mV CML signal level.
400mV CML signal level.
Preemphasis off.
-1.2dB preemphasis.
-2.5dB preemphasis.
-4.1dB preemphasis.
-6.0dB preemphasis.
Do not use.
D[5:4]
CMLLVL
11
10
11
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
01000000
00100010
0x05
Do not use.
Do not use.
D[3:0]
PREEMP
0000
1.1dB preemphasis.
2.2dB preemphasis.
3.3dB preemphasis.
4.4dB preemphasis.
6.0dB preemphasis.
8.0dB preemphasis.
10.5dB preemphasis.
14.0dB preemphasis.
Reserved.
0x06
0x07
D[7:0]
D[7:0]
—
—
01000000
00100010
Reserved.
0000
(read only)
D[7:4]
—
0000
Reserved.
00
Negative cable wire shorted to supply voltage.
Negative cable wire shorted to ground.
Normal operation.
01
10
D[3:2]
LFNEG
(read only)
10
0x08
0x0C
11
Negative cable wire disconnected.
Positive cable wire shorted to supply voltage.
Positive cable wire shorted to ground.
Normal operation.
00
01
10
D[1:0]
D[7:0]
LFPOS
—
(read only)
10
11
Positive cable wire disconnected.
Reserved.
01110000
01110000
44 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 17. Serializer GMSL Core Register Table (see Table 1) (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
D7
NAME
SETINT
VALUE
FUNCTION
0
1
Set INT low when SETINT transitions from 1 to 0.
Set INT high when SETINT transitions from 0 to 1.
Serializer does not invert VSYNC.
Serializer inverts VSYNC.
0
0
0
D6
INVVSYNC
1
0
Serializer does not invert HSYNC.
Serializer inverts HSYNC.
D5
D[4:0]
D4
INVHSYNC
—
0
00000
0
1
00000
0
Reserved.
RES (LVDS interface) mapped to DIN27.
CNTL1 mapped to DIN27.
DISRES
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Adjust x7PLL clock skew +50ps.
Adjust x7PLL clock skew +100ps.
Adjust x7PLL clock skew +200ps.
Adjust x7PLL clock skew +250ps.
Adjust x7PLL clock skew +300ps.
Adjust x7PLL clock skew +350ps.
Adjust x7PLL clock skew +400ps.
Do not use.
0x0D
D[3:0]
SKEWADJ
1111
Adjust x7PLL clock skew +50ps.
Adjust x7PLL clock skew +100ps.
Adjust x7PLL clock skew +200ps.
Adjust x7PLL clock skew +250ps.
Adjust x7PLL clock skew +300ps.
Adjust x7PLL clock skew +350ps.
Adjust x7PLL clock skew +400ps.
No x7PLL clock skew adjustment.
00000111
(read only)
0x1E
0x1F
D[7:0]
D[7:5]
ID
—
00000111
000
Device identifier (MAX9265 = 0x07).
Reserved.
000
(read only)
0
1
Not HDCP capable.
HDCP capable.
Device revision.
1
D4
CAPS
(read only)
D[3:0]
REVISION
XXXX
(read only)
______________________________________________________________________________________ 45
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 18. Serializer HDCP Register Table (see Table 1)
REGISTER
ADDRESS
SIZE
(BYTES)
READ/
WRITE
DEFAULT VALUE
(hex)
NAME
FUNCTION
0x80 to 0x84
5
BKSV
Read/write HDCP receiver KSV
0x0000000000
RI (read only) of the transmitter when
EN_INT_COMP = 0
RI’ (read/write) of the receiver when
EN_INT_COMP = 1
0x85 to 0x86
2
RI/RI’
Read/write
Read/write
0x0000
PJ (read only) of the transmitter when
EN_INT_COMP = 0
PJ’ (read/write) of the receiver when
EN_INT_COMP = 1
0x87
1
PJ/PJ’
0x00
0x88 to 0x8F
0x90 to 0x94
8
5
AN
Read only
Read only
Session random number
HDCP transmitter KSV
(Read only)
(Read only)
AKSV
D7 = PD_HDCP
1 = Power down HDCP circuits
0 = HDCP circuits normal
D6 = EN_INT_COMP
1 = Internal comparison mode
0 = FC comparison mode
D5 = FORCE_AUDIO
1 = Force audio data to 0
0 = Normal operation
D4 = FORCE_VIDEO
1 = Force video data DFORCE value
0 = Normal operation
D3 = RESET_HDCP
0x95
1
ACTRL
Read/write
0x00
1 = Reset HDCP circuits
Automatically set to 0 upon completion
0 = Normal operation
D2 = START_AUTHENTICATION
1 = Start authentication
Automatically set to 0 once authentication starts
0 = Normal operation
D1 = VSYNC_DET
1 = Internal falling edge on VSYNC detected
0 = No falling edge detected
D0 = ENCRYPTION_ENABLE
1 = Enable encryption
0 = Disable encryption
46 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 18. Serializer HDCP Register Table (see Table 1) (continued)
REGISTER
ADDRESS
SIZE
(BYTES)
READ/
WRITE
DEFAULT VALUE
(hex)
NAME
FUNCTION
D[7:4] = Reserved
D3 = V_MATCHED
1 = V matches V’ (when EN_INT_COMP = 1)
0 = V does not match V’ or EN_INT_COMP = 0
D2 = PJ_MATCHED
1 = PJ matches PJ’ (when EN_INT_COMP = 1)
0 = PJ does not match PJ’ or EN_INT_COMP = 0
0x00
(read only)
0x96
1
ASTATUS
Read only
D1 = R0_RI_MATCHED
1 = RI matches RI’ (when EN_INT_COMP = 1)
0 = RI does not match RI’ or EN_INT_COMP = 0
D0 = BKSV_INVALID
1 = BKSV is not valid
0 = BKSV is valid
D[7:1] = RESERVED
D0 = REPEATER
1 = Set to 1 if device is a repeater
0 = Set to 0 if device is not a repeater
0x97
1
5
BCAPS
ASEED
Read/write
Read/write
0x00
Internal random number generator optional seed
value
0x98 to 0x9C
0x0000000000
Forced video data transmitted when
FORCE_VIDEO = 1
0x9D to 0x9F
0xA0 to 0xA3
0xA4 to 0xA7
0xA8 to 0xAB
3
4
4
4
DFORCE
Read/write R[7:0] = DFORCE[7:0]
G[7:0] = DFORCE[15:8]
0x000000
0x00000000
0x00000000
0x00000000
B[7:0] = DFORCE[23:16]
H0 part of SHA-1 hash value
V (read only) of the transmitter when
Read/write EN_INT_COMP = 0
V’ (read/write) of the receiver when
EN_INT_COMP = 1
V.H0,
V’.H0
H1 part of SHA-1 hash value
V (read only) of the transmitter when
Read/write EN_INT_COMP = 0
V’ (read/write) of the receiver when
EN_INT_COMP = 1
V.H1,
V’.H1
H2 part of SHA-1 hash value
V (read only) of the transmitter when
Read/write EN_INT_COMP = 0
V’ (read/write) of the receiver when
EN_INT_COMP = 1
V.H2,
V’.H2
______________________________________________________________________________________ 47
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Table 18. Serializer HDCP Register Table (see Table 1) (continued)
REGISTER
ADDRESS
SIZE
(BYTES)
READ/
WRITE
DEFAULT VALUE
(hex)
NAME
FUNCTION
H3 part of SHA-1 hash value
V (read only) of the transmitter when
Read/write EN_INT_COMP = 0
V’ (read/write) of the receiver when
V.H3,
V’.H3
0xAC to 0xAF
0xB0 to 0xB3
4
4
0x00000000
0x00000000
EN_INT_COMP = 1
H4 part of SHA-1 hash value
V (read only) of the transmitter when
Read/write EN_INT_COMP = 0
V.H4,
V’.H4
V’ (read/write) of the receiver when
EN_INT_COMP = 1
D[15:12] = Reserved
D11 = MAX_CASCADE_EXCEEDED
1 = Set to one if more than 7 cascaded devices
attached
0 = Set to zero if 7 or fewer cascaded devices
attached
0xB4 to 0xB5
2
BINFO
Read/write
0x0000
D[10:8] = DEPTH
Depth of cascaded devices
D7 = MAX_DEVS_EXCEEDED
1 = Set to one if more than 14 devices attached
0 = Set to zero if 14 or fewer devices attached
D[6:0] = DEVICE_COUNT
Number of devices attached
0xB6
1
3
GPMEM
—
Read/write General-purpose memory byte
0x00
0xB7 to 0xB9
Read only
Reserved
0x000000
List of KSV’s downstream repeaters and
receivers (maximum of 14 devices)
0xBA to 0xFF
70
KSV_LIST
Read/write
All zero
48 _____________________________________________________________________________________
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Typical Application Circuit
PCLK
RGB
HSYNC
VSYNC
DE
PCLKOUT
DOUT[17:0]
DOUT18/HS
DOUT19/VS
DOUT20
RXCLKIN+/-
TXCLK+/-
RXIN0+/- TO RXIN2+/-
TX0+/- TO TX2+/-
GPU
CDS
45kI
45kI
CDS
DISPLAY
AUTOS
LMN1
LMN0
ECU
MAX9264
5kI
5kI
MAX9265
TO PERIPHERALS
OUT+
INT
RX/SDA
TX/SCL
IN+
IN-
TX
RX/SDA
OUT-
UART
TX/SCL
RX
50kI
50kI
SCL
SDA
WS
LFLT
INT
LFLT
ADD0
INT
ADD1
MS
LOCK
WS
MS
SCK
SD
WS
WS
MAX9850
SCK
SD
SCK
AUDIO
SCK
SD/CNTL0
SD
MCLK
PLL
NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS.
VIDEO-DISPLAY APPLICATION
X1
OUT
Chip Information
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
48 TQFP-EP
C48E+8
21-0065
90-0138
______________________________________________________________________________________ 49
HDCP Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
12/10
Initial release
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
50
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
©
相关型号：
MAX9270GTN/V+
Gigabit Multimedia Deserializer with Spread Spectrum and Full-Duplex Control Channel
MAXIM
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