MAX9271GTJ/V+ [MAXIM]
16-Bit GMSL Serializer with Coax or STP Cable Drive; 16位GMSL串行器与同轴电缆或STP电缆驱动器
| 型号： | MAX9271GTJ/V+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 16-Bit GMSL Serializer with Coax or STP Cable Drive |
| 文件： | 总49页 (文件大小：3100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-6385; Rev 0; 7/12
E V A L U A T I O N K I T A V A I L A B L E
General Description
Benefits and Features
The MAX9271 compact serializer is designed to drive
50Icoax or 100Ishielded twisted-pair (STP) cable. The
device pairs with the MAX9272 deserializer.
S Ideal for Camera Applications
ꢀDrives Low-Cost 50I Coax Cable and FAKRA
Connectors or 100I STP
ꢀError Detection/Correction
The parallel input is programmable for single or double
input. Double input allows higher pixel clock input fre-
quency by registering two pixels of typical image-sensor
video data before serializing. This doubles the maximum
pixel clock frequency compared to single input.
ꢀ9.6kbps to 1Mbps Control Channel in I2C-to-I2C
Mode with Clock Stretch Capability
ꢀBest-in-Class Supply Current: 75mA (max)
ꢀDouble-Rate Clock for Megapixel Cameras
ꢀSerializer Pre/Deemphasis Allows 15m Cable at
Full Speed
The device features an embedded control channel that
operates at 9.6kbps to 1Mbps in UART and mixed UART/
I2C modes, and up to 400kbps in I2C mode. Using the
control channel, a microcontroller (FC) is capable of pro-
gramming serializer, deserializer, and camera (or any
peripheral) registers at any time, independent of video
timing. There is one dedicated GPIO, four optional
GPIOs, and a GPO output, allowing remote power-up of
a camera module, camera frame synchronization, and
other uses. Error-detection and correction coding are
programmable.
ꢀ32-Pin (5mm x 5mm) TQFN Package with 0.5mm
Lead Pitch
S High-Speed Data Serialization for Megapixel
Cameras
Up to 1.5Gbps Serial-Bit Rate with Single or
Double Input: 6.25MHz to 100MHz Clock
S Multiple Control-Channel Modes for System
Flexibility
9.6kbps to 1Mbps Control Channel in UART-to-
UART or UART-to-I2C Modes
For driving longer cables, the device has programmable
pre/deemphasis. Programmable spread spectrum is
available on the serial output. The serial output meets
ISO 10605 and IEC 61000-4-2 ESD standards. The core
supply range is 1.7V to 1.9V and the I/O supply range is
1.7V to 3.6V. The device is available in a 32-pin (5mm
x 5mm) TQFN-EP package with 0.5mm lead pitch and
operates over the -40NC to +105NC temperature range.
S Reduces EMI and Shielding Requirements
ꢀOutput Programmable for 100mV to 500mV
Single-Ended or 100mV to 400mV Differential
ꢀProgrammable Spread Spectrum on the Serial
Output Reduces EMI
ꢀBypassable Input PLL for Parallel Clock Jitter
Attenuation
ꢀTracks Spread Spectrum on Parallel Input
Applications
S Peripheral Features for Camera Power-Up and
Verification
Automotive Camera Systems
ꢀBuilt-In PRBS Generator for BER Testing of the
Serial Link
ꢀUp to Five GPIO Ports
ꢀDedicated “Up/Down” GPO for Camera Frame
Sync Trigger and Other Uses
ꢀRemote/Local Wake-Up from Sleep Mode
Ordering Information and Typical Application Circuit appear
at end of data sheet.
S Meets Rigorous Automotive and Industrial
Requirements
ꢀ-40NC to +105NC Operating Temperature
ꢀ10kV Contact and 15kV IEC 61000-4-2 ESD
Protection
ꢀ10kV Contact and 30kV Air ISO 10605 ESD
Protection
For related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX9271.related.
1
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input Bit Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Serial Link Signaling and Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Reverse Control Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Data-Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Control Channel and Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2
Interfacing Command-Byte-Only I C Devices with UART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
UART Bypass Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2
I C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
START and STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Bus Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Format for Writing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Format for Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2
I C Communication with Remote-Side Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2
I C Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2
I C Broadcast Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
GPO/GPI Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Pre/Deemphasis Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Manual Programming of the Spread-Spectrum Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Additional Error Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
TABLE OF CONTENTS (continued)
Hamming Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
HS/VS Encoding and/or Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Serial Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Coax-Mode Splitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Configuration Inputs (CONF1, CONF0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Configuration Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Link Startup Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PRBS Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Error Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Dual µC Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Jitter-Filtering PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PCLKIN Spread Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Changing the Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Providing a Frame Sync (Camera Applications) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Software Programming of the Device Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Three-Level Configuration Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Configuration Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Compatibility with Other GMSL Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Local Control-Channel Enable (LCCEN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Internal Input Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2
Choosing I C/UART Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
AC-Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Selection of AC-Coupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Power-Supply Circuits and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Power-Supply Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Cables and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Board Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Chip Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
LIST OF FIGURES
Figure 1. Serial-Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2. Output Waveforms at OUT+, OUT- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3. Single-Ended Output Template. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Worst-Case Pattern Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. Parallel Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2
Figure 6. I C Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Differential Output Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Input Setup and Hold Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. GPI-to-GPO Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Serializer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Link Startup Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. Power-Up Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Single-Input Waveform (Latch on Rising Edge of PCLKIN Selected). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14. Single-Input Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15. Double-Input Function Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16. Double-Input Waveform (Latch on Rising Edge of PCLKIN Selected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17. Serial-Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 18. GMSL UART Protocol for Base Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19. GMSL UART Data Format for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. SYNC Byte (0x79) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 21. ACK Byte (0xC3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 22. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0) . . . . . . . . 26
2
Figure 23. Format Conversion Between GMSL UART and I C with Register Address (I2CMETHOD = 1) . . . . . . . . 27
Figure 24. START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 25. Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 26. Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 27. Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2
Figure 28. Format for I C Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 29. Format for Write to Multiple Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2
Figure 30. Format for I C Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 31. 2:1 Coax-Mode Splitter Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 32. Coax-Mode Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 33. State Diagram, All Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 34. Human Body Model ESD Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 35. IEC 61000-4-2 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 36. ISO 10605 Contact Discharge ESD Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
LIST OF TABLES
Table 1. Power-Up Default Register Map (see Table 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 2. Input Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 3. Data-Rate Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2
Table 4. I C Bit-Rate Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5. TP/Coax Drive Current (CMLLVL = 1000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. Serial Output Spread . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 7. Spread Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8. Modulation Coefficients and Maximum SDIV Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 9. Configuration Input Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 10. Startup Procedure for Video-Display Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 11. Startup Procedure for Image-Sensing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 12. MAX9271 Feature Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 13. Double-Function Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 14. Typical Power-Supply Currents (Using Worst-Case Input Pattern). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 15. Suggested Connectors and Cables for GMSL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 16. Register Table (see Table 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
ABSOLUTE MAXIMUM RATINGS*
AVDD to EP ..........................................................-0.5V to +1.9V
DVDD to EP..........................................................-0.5V to +1.9V
IOVDD to EP.........................................................-0.5V to +3.9V
OUT+, OUT- to EP ...............................................-0.5V to +1.9V
Continuous Power Dissipation (T = +70NC)
A
TQFN (derate 34.5mW/NC above +70NC)...............2758.6mW
Junction Temperature .....................................................+150NC
Operating Temperature Range........................ -40NC to +105NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
All other pins to EP.............................. -0.5V to (V
+ 0.5V)
IOVDD
OUT+, OUT- short circuit to ground or supply ........Continuous
*EP connected to PCB ground.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (q ) ..........29°C/W
Junction-to-Case Thermal Resistance (q )..................1.7°C/W
JC
JA
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
DC ELECTRICAL CHARACTERISTICS
(V
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100I Q1% (differential), EP connected to PCB ground (GND),
AVDD
DVDD
IOVDD L
T
= -40NC to +105NC, unless otherwise noted. Typical values are at V
= V
= V
= 1.8V, T = +25NC.)
A
AVDD
DVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (LCCEN, DIN_, PCLKIN, HS, VS, MS/HVEN, PWDN)
0.65 x
High-Level Input Voltage
V
V
IH1
V
IOVDD
0.35 x
Low-Level Input Voltage
Input Current
V
V
IL1
V
IOVDD
I
V
= 0V to V
IOVDD
-10
20
FA
IN1
IN
THREE-LEVEL LOGIC INPUTS (CONF0, CONF1)
0.7 x
High-Level Input Voltage
Low-Level Input Voltage
V
V
V
IH
V
IOVDD
0.3 x
V
IL
V
IOVDD
Midlevel Input Current
Input Current
I
(Note 2)
-10
+10
FA
FA
INM
I
-150
+150
IN
SINGLE-ENDED OUTPUT (GPO)
V
IOVDD
- 0.2
High-Level Output Voltage
Low-Level Output Voltage
Output Short-Circuit Current
V
I
I
= -2mA
= 2mA
V
V
OH1
OUT
OUT
V
0.2
64
21
OL1
V
V
= 3.0V to 3.6V
= 1.7V to 1.9V
16
3
35
12
IOVDD
I
V
= 0V
O
mA
OS
IOVDD
6
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100I Q1% (differential), EP connected to PCB ground (GND),
AVDD
DVDD
IOVDD L
T
= -40NC to +105NC, unless otherwise noted. Typical values are at V
= V
= V
= 1.8V, T = +25NC.)
A
AVDD
DVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OPEN-DRAIN INPUTS/OUTPUTS (RX/SDA/EDC, TX/SCL/DBL, GPIO_)
0.7 x
High-Level Input Voltage
Low-Level Input Voltage
V
V
V
IH2
V
IOVDD
0.3 x
V
IL2
IN2
OL2
V
IOVDD
RX/SDA, TX/SCL
GPIO_
-110
-80
+1
Input Current
I
(Note 3)
+1
FA
EDC, DBL, BWS
-10
+20
0.4
V
V
= 1.7V to 1.9V
= 3.0V to 3.6V
IOVDD
Low-Level Output Voltage
V
I
= 3mA
V
OUT
0.3
IOVDD
DIFFERENTIAL SERIAL OUTPUTS (OUT+, OUT-)
Preemphasis off (Figure 1)
300
350
240
400
1.4
500
610
425
Differential Output Voltage
V
3.3dB preemphasis setting (Figure 2)
3.3dB deemphasis setting (Figure 2)
mV
OD
Change in V Between
Complementary Output States
OD
DV
25
1.56
25
mV
V
OD
Output Offset Voltage,
V
Preemphasis off
1.1
-62
OS
(V
+ V
)/2 = V
OUT+
OUT- OS
Change in V
Complementary Output States
between
OS
DV
mV
OS
V
V
or V
or V
= 0V
OUT+
OUT+
OUT-
Output Short-Circuit Current
I
mA
OS
= 1.9V
25
25
OUT-
Magnitude of Differential
Output Short-Circuit Current
I
V
= 0V
mA
OSD
OD
Output Termination Resistance
(Internal)
R
From V
, V
to V
AVDD
45
54
63
I
O
OUT+ OUT-
SINGLE-ENDED SERIAL OUTPUTS (OUT+, OUT-)
Preemphasis off, high drive (Figure 3)
375
435
500
625
765
3.3dB preemphasis setting, high drive
(Figure 2)
Single-Ended Output Voltage
V
mV
OUT
3.3dB deemphasis setting, high drive
(Figure 2)
300
-69
535
V
V
or V
or V
= 0V
OUT+
OUT-
Output Short-Circuit Current
I
mA
OS
= 1.9V
32
63
OUT+
OUT-
Output Termination Resistance
(Internal)
R
From V
, V
to V
AVDD
45
54
I
O
OUT+ OUT-
7
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100I Q1% (differential), EP connected to PCB ground (GND), T
=
AVDD
DVDD
IOVDD
L
A
-40NC to +105NC, unless otherwise noted. Typical values are at V
= V
= V
= 1.8V, T = +25NC.)
AVDD
DVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REVERSE CONTROL-CHANNEL RECEIVER OUTPUTS (OUT+, OUT-)
High Switching Threshold
Low Switching Threshold
POWER SUPPLY
V
27
mV
mV
CHR
V
-27
CLR
f
f
f
f
= 25MHz
= 50MHz
= 50MHz
= 100MHz
44
46
45
56
40
5
65
75
Single input,
BWS = 0
PCLKIN
PCLKIN
PCLKIN
PCLKIN
Worst-Case Supply Current
(Figure 4)
I
mA
WCS
65
Double input,
BWS = 0
75
Sleep Mode Supply Current
Power-Down Supply Current
ESD PROTECTION
I
Single wake-up receiver enabled
100
70
FA
FA
CCS
I
PWDN = EP
CCZ
Human Body Model, R = 1.5kI,
D
±8
C
= 100pF
S
IEC 61000-4-2,
Contact discharge
Air discharge
±10
±15
±10
±30
R
= 330I,
D
OUT+, OUT- (Note 4)
All Other Pins (Note 5)
V
V
kV
kV
ESD
C
= 150pF
S
ISO 10605,
Contact discharge
Air discharge
R
= 2kI,
D
C
= 330pF
S
Human Body Model, R = 1.5kI,
D
±4
ESD
C
= 100pF
S
AC ELECTRICAL CHARACTERISTICS
(V
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100IQ1% (differential), EP connected to PCB ground (GND),
DVDD
AVDD
IOVDD L
T
= -40NC to +105NC, unless otherwise noted. Typical values are at V
= V
= V
= 1.8V, T = +25NC)
A
DVDD
AVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK INPUT (PCLKIN)
BWS = 1, DRS = 1
6.25
8.33
12.5
16.66
25
12.5
16.66
37.5
50
BWS = 0, DRS = 1
BWS = 1, DRS = 0
BWS = 0, DRS = 0
Clock Frequency
f
MHz
PCLKIN
BWS = 1, DRS = 0, 15-bit double input
BWS = 0, DRS = 0, 11-bit double input
75
33.33
35
100
65
Clock Duty Cycle
DC
t
/t or t /t (Figure 5, Note 6)
LOW T
50
%
_
HIGH T
Clock Transition Time
t , t
(Figure 5, Note 6)
4
ns
R
F_
ps
(pk-pk)
Clock Jitter
t
1.5Gbps bit rate, 300kHz sinusoidal jitter
800
J
8
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
AC ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100I Q1% (differential), EP connected to PCB ground (GND),
DVDD
AVDD
IOVDD L
T
= -40NC to +105NC, unless otherwise noted. Typical values are at V
= V
= V
= 1.8V, T = +25NC)
A
DVDD
AVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I2C/UART AND GPIO PORT TIMING
I2C/UART Bit Rate
9.6
20
1000
120
kbps
ns
30% to 70%, C = 10pF to 100pF,
L
1kI pullup to IOVDD
Output Rise Time
Output Fall Time
t
R
70% to 30%, C = 10pF to 100pF,
L
1kI pullup to IOVDD.
t
20
120
ns
F
Input Setup Time
Input Hold Time
t
I2C only (Figure 6, Note 6)
I2C only (Figure 6, Note 6)
100
0
ns
ns
SET
t
HOLD
SWITCHING CHARACTERISTICS (Note 6)
Differential Output Rise/Fall
Time
20% to 80%, V
serial-bit rate = 1.5Gbps
R 400Mv, R = 100I,
OD L
t , t
250
ps
UI
R
F
1.5Gbps PRBS signal, measured at
Total Serial Output Jitter
(Differential Output)
t
V
= 0V differential, preemphasis
0.25
0.15
TSOJ1
OD
disabled (Figure 7)
1.5Gbps PRBS signal, measured at
Deterministic Serial Output Jitter
(Differential Output)
t
V
= 0V differential, preemphasis
UI
DSOJ2
OD
disabled (Figure 7)
Total Serial Output Jitter
(Single-Ended Output)
1.5Gbps PRBS signal, measured at V /2,
O
preemphasis disabled (Figure 3)
t
0.25
0.15
UI
UI
TSOJ1
Deterministic Serial Output Jitter
(Single-Ended Output)
1.5Gbps PRBS signal, measured at V /2,
O
preemphasis disabled (Figure 3)
t
DSOJ2
Parallel Data Input Setup Time
Parallel Data Input Hold Time
t
(Figure 8)
2
1
ns
ns
SET
t
(Figure 8)
HOLD
Deserializer GPI to serializer GPO
(Figure 9)
GPI-to-GPO Delay
t
350
Fs
GPIO
Spread spectrum enabled
(Figure 10)
6880
3040
2
Serializer Delay (Note 7)
t
Bits
SD
Spread spectrum disabled
Link Start Time
Power-Up Time
t
(Figure 11)
(Figure 12)
ms
ms
LOCK
t
7
PU
Note 2: To provide a midlevel, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current
must be less than Q10µA.
Note 3: I min due to voltage drop across the internal pullup resistor.
IN
Note 4: Specified pin to ground.
Note 5: Specified pin to all supply/ground.
Note 6: Guaranteed by design and not production tested.
Note 7: Measured in serial link bit times. Bit time = 1/(30 x f
for BWS = 0. Bit time = 1/(40 x f
) for BWS = 1.
PCLKIN)
PCLKIN
9
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Typical Operating Characteristics
(V
= V
= V
= 1.8V, DBL = low, T = +25NC, unless otherwise noted.)
AVDD
DVDD
IOVDD A
SUPPLY CURRENT vs.
PCLKIN FREQUENCY (BWS = 0)
SUPPLY CURRENT vs.
PCLKIN FREQUENCY (BWS = 1)
OUTPUT POWER SPECTRUM vs. PCLKIN
FREQUENCY (VARIOUS SPREAD)
70
65
60
55
50
45
40
35
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
70
65
60
55
50
45
40
35
PRBS ON,
COAX MODE
PRBS ON,
COAX MODE
f
= 20MHz
PCLKIN
PREEMPHASIS =
0x0B TO 0x0F
PREEMPHASIS =
0x0B TO 0x0F
0% SPREAD
0.5% SPREAD
1% SPREAD
PREEMPHASIS =
0x01 TO 0x04
PREEMPHASIS =
0x01 TO 0x04
4% SPREAD
2% SPREAD
PREEMPHASIS = 0x00
PREEMPHASIS = 0x00
5
10
15
20
25
30
35
40
18.5 19.0 19.5 20.0 20.5 21.0 21.5
PCLKIN FREQUENCY (MHz)
5
10 15 20 25 30 35 40 45 50
PCLKIN FREQUENCY (MHz)
PCLKIN FREQUENCY (MHz)
SERIAL LINK SWITCHING PATTERN
WITH 6dB PREEMPHASIS
SERIAL LINK SWITCHING PATTERN
WITH 6dB PREEMPHASIS
OUTPUT POWER SPECTRUM vs. PCLKIN
FREQUENCY (VARIOUS SPREAD)
(PARALLEL BIT RATE = 50MHz, 10m STP CABLE) (PARALLEL BIT RATE = 50MHz, 20m COAX CABLE)
MAX9271 toc05
MAX9271 toc06
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
= 50MHz
PCLKIN
0% SPREAD
0.5% SPREAD
1% SPREAD
4% SPREAD
2% SPREAD
49 50
PCLKIN FREQUENCY (MHz)
50mV/div
200ps/div
1.5Gbps
50mV/div
200ps/div
1.5Gbps
47
48
51
52
53
MAXIMUM PCLKIN FREQUENCY vs.
MAXIMUM PCLKIN FREQUENCY vs.
MAXIMUM PCLKIN FREQUENCY vs.
STP CABLE LENGTH (BER ≤ 10-10
)
COAX CABLE LENGTH (BER ≤ 10-10
)
ADDITIONAL DIFFERENTIAL C (BER < 10-10
)
L
60
40
20
0
60
40
20
0
60
OPTIMUM PE/EQ SETTINGS
OPTIMUM PE/EQ SETTINGS
10m STP CABLE
50
40
30
20
10
0
6dB PE, EQ OFF
6dB PE, EQ OFF
NO PE, 10.7dB EQ
NO PE, EQ OFF
6dB PE, EQ OFF
NO PE, 10.7dB EQ
NO PE, EQ OFF
NO PE, 10.7dB EQ
NO PE, EQ OFF
-12
-12
-12
BER CAN BE AS LOW AS 10 FOR CABLE
BER CAN BE AS LOW AS 10 FOR CABLE
BER CAN BE AS LOW AS 10 FOR C < 4pF
L
LENGTHS LESS THAN 10m
LENGTHS LESS THAN 10m
FOR OPTIMUM PE/EQ SETTINGS
0
5
10
15
20
0
5
10
15
20
25
0
2
4
6
8
10
STP CABLE LENGTH (m)
COAX CABLE LENGTH (m)
ADDITIONAL DIFFERENTIAL LOAD CAPACITANCE (pF)
10
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Pin Configuration
TOP VIEW
24 23 22 21 20 19 18 17
16
15
PCLKIN 25
DIN0 26
PWDN
MS/HVEN
14 GPIO1/BWS
27
28
29
30
31
32
DIN1
DIN2
DVDD
DIN3
DIN4
DIN5
GPO
13
12
MAX9271
IOVDD
11 DIN15/VS
EP*
10
9
DIN14/HS
+
DIN13/GPIO5
1
2
3
4
5
6
7
8
TQFN
(5mm x 5mm x 0.75mm)
*CONNECT EP TO GROUND PLANE
Pin Description
PIN
NAME
FUNCTION
Parallel Data Inputs with Internal Pulldown to EP
1–4, 26, 27, 28,
30, 31, 32
DIN0–DIN9
1.8V Analog Power Supply. Bypass AVDD to EP with 0.1FF and 0.001FF capacitors as
close as possible to the device with the smaller capacitor closest to AVDD.
5, 22
AVDD
Parallel Data Inputs/GPIO. Defaults to parallel data input on power-up.
Parallel data input has internal pulldown to EP.
GPIO_ has an open-drain output with internal 60kI pullup to IOVDD. See Table 1 for
programming details.
DIN10/
GPIO2–DIN13/
GPIO5
6–9
Parallel Data Input/Horizontal Sync with Internal Pulldown to EP. Defaults to parallel data
input on power-up.
Horizontal sync input when VS/HS encoding is enabled (Table 2).
10
11
12
DIN14/HS
DIN15/VS
IOVDD
Parallel Data Input/Vertical Sync with Internal Pulldown to EP. Defaults to parallel data
input on power-up.
Vertical sync input when VS/HS encoding is enabled (Table 2).
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to EP with
0.1FF and 0.001FF capacitors as close as possible to the device with the smallest value
capacitor closest to IOVDD.
11
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Pin Description (continued)
PIN
NAME
FUNCTION
General-Purpose Output. GPO follows the GMSL deserializer GPI (or INT) input.
GPO = low upon power-up and when PWDN = low.
13
GPO
GPIO/Bus Width Select Input. Function is determined by the state of LCCEN (Table 13).
GPIO1 (LCCEN = high): Open-drain, general-purpose input/output with internal 60kI
pullup to IOVDD.
BWS (LCCEN = low): Input with internal pulldown to EP. Set BWS = low for 22-bit input
latch. Set BWS = high for 30-bit input latch.
14
15
GPIO1/BWS
MS/HVEN
Mode Select/HS and VS Encoding Enable with Internal Pulldown to EP. Function is
determined by the state of LCCEN (Table 13).
MS (LCCEN = high): Set MS = low to select base mode. Set MS = high to select the
bypass mode.
HVEN (LCCEN = low): Set HVEN = high to enable HS/VS encoding on DIN14/HS and
DIN15/VS. Set HVEN = low to use DIN14/HS and DIN15/VS as parallel data inputs.
Active-Low, Power-Down Input with Internal Pulldown to EP. Set PWDN low to enter
power-down mode to reduce power consumption.
16
17
PWDN
Local Control-Channel Enable Input with Internal Pulldown to EP. LCCEN = high enables
the control-channel interface pins. LCCEN = low disables the control-channel interface
pins and selects an alternate function on the indicated pins (Table 13).
LCCEN
18
19
20
21
CONF0
CONF1
OUT-
Configuration 0. Three-level configuration input (Table 9).
Configuration 1. Three-level configuration input (Table 9).
Inverting Coax/Twisted-Pair Serial Output
OUT+
Noninverting Coax/Twisted-Pair Serial Output
Receive/Serial Data/Error-Detection/Correction. Function is determined by the state of
LCCEN (Table 13).
RX/SDA (LCCEN = high): Input/output with internal 30kI pullup to IOVDD. In UART
mode, RX/SDA is the Rx input of the serializer’s UART. In I2C mode, RX/SDA is the
SDA input/output of the serializer’s I2C master/slave. RX/SDA has an open-drain driver
and requires a pullup resistor.
EDC (LCCEN = low): Input with internal pulldown to EP. Set EDC = high to enable
error-detection correction. Set EDC = low to disable error-detection correction.
23
24
RX/SDA/EDC
Transmit/Serial Clock/Double Mode. Function is determined by the state of LCCEN
(Table 13).
TX/SCL (LCCEN = high): Input/output with internal 30kI pullup to IOVDD. In UART
mode, TX/SCL is the Tx output of the serializer’s UART. In the I2C mode, TX/SCL is
the SCL input/output of the serializer’s I2C master/slave. TX/SCL has an open-drain
driver and requires a pullup resistor.
TX/SCL/DBL
DBL (LCCEN = low): Input with internal pulldown to EP. Set DBL = high to use double-
input mode. Set DBL = low to use single-input mode.
Parallel Clock Input with Internal Pulldown to EP. Latches parallel data inputs and
provides the PLL reference clock.
25
29
—
PCLKIN
DVDD
EP
1.8V Digital Power Supply. Bypass DVDD to EP with 0.1FF and 0.001FF capacitors as
close as possible to the device with the smaller value capacitor closest to DVDD.
Exposed Pad. EP is internally connected to device ground. MUST connect EP to the PCB
ground plane through an array of vias for proper thermal and electrical performance.
12
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Functional Diagram
SSPLL
FILTER
PCLKIN
PLL
MAX9271
CLKDIV
DIN0–DIN9
OUT+
DIN10/GPIO2
DIN11/GPIO3
DIN12/GPIO4
DIN13/GPIO5
PARALLEL
TO SERIAL
OUT-
CML TX
RX
SCRAMBLE/
CRC/
HAMMING/
8b/10b
SINGLE-/
DOUBLE-
INPUT
FIFO
ENCODE
GPO
LATCH
REVERSE
CONTROL
CHANNEL
GPIO1/BWS
FCC
GPIO
DIN14/HS
DIN15/VS
2
UART/I C
TX/SCL/ RX/SDA/
DBL EDC
13
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
R /2
L
OUT+
V
OD
V
OS
OUT-
R /2
L
GND
((OUT+) + (OUT-))/2
OUT-
OUT+
V
V
OS(+)
V
OS(-)
OS(-)
DV = |V
- V
|
OS(+) OS(-)
OS
V
(+)
OD
V
= 0V
OD
V
OD(-)
V
OD(-)
DV = |V
- V
|
OD(+) OD(-)
OD
(OUT+) - (OUT-)
Figure 1. Serial-Output Parameters
OUT+
OUT+
OR
V /2
O
V
V /2
O
V
O
O
V
V
OD(D)
OD(P)
V
OS
OUT-
OUT-
Figure 3. Single-Ended Output Template
SERIAL-BIT
TIME
PCLKIN
DIN_
Figure 2. Output Waveforms at OUT+, OUT-
NOTE: PCLKIN PROGRAMMED FOR RISING LATCH EDGE.
Figure 4. Worst-Case Pattern Input
14
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
t
T
V
IH MIN
t
HIGH
PCLKIN
V
IL MAX
t
R
t
F
t
LOW
Figure 5. Parallel Clock Input Requirements
START
CONDITION
BIT 7
MSB
(A7)
STOP
CONDITION
(P)
BIT 6
(A6)
BIT 0
(R/W)
ACKNOWLEDGE
(A)
PROTOCOL
(S)
t
t
t
SU;STA
LOW
HIGH
1/f
SCL
SCL
SDA
t
SP
t
BUF
t
r
t
f
t
t
t
t
t
SU;STO
HD;STA
t
HD;DAT
VD;DAT
VD;ACK
SU;DAT
2
Figure 6. I C Timing Parameters
800mV
P-P
t
t
TSOJ1
2
TSOJ1
2
Figure 7. Differential Output Template
15
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
V
IH MIN
PCLKIN
V
IL MAX
t
t
HOLD
SET
V
V
V
V
IH MIN
IH MIN
IL MAX
DIN_
IL MAX
NOTE: PCLKIN PROGRAMMED FOR RISING LATCHING EDGE.
Figure 8. Input Setup and Hold Times
V
IH_MIN
DESERIALIZER
GPI
V
IL_MAX
t
GPIO
t
GPIO
V
OH_MIN
SERIALIZER
GPO
V
OL_MAX
Figure 9. GPI-to-GPO Delay
16
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
EXPANDED TIME SCALE
DIN_
N
N+2
N+3
N+4
N+1
PCLKIN
N-1
N
OUT+/-
t
SD
FIRST BIT
LAST BIT
Figure 10. Serializer Delay
PCLKIN
t
LOCK
350Fs
SERIAL LINK INACTIVE
SERIAL LINK ACTIVE
REVERSE CONTROL CHANNEL
DISABLED
CHANNEL
DISABLED
REVERSE CONTROL CHANNEL
AVAILABLE
PWDN MUST BE HIGH
Figure 11. Link Startup Time
17
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
PCLKIN
V
IH1
PWDN
t
PU
POWERED UP,
SERIAL LINK INACTIVE
POWERED DOWN
POWERED UP, SERIAL LINK ACTIVE
350µs
REVERSE CONTROL
CHANNEL DISABLED
REVERSE CONTROL
CHANNEL ENABLED
REVERSE CONTROL
CHANNEL DISABLED
REVERSE CONTROL
CHANNEL ENABLED
Figure 12. Power-Up Delay
Register Mapping
Detailed Description
Registers set the operating conditions of the serializer
and are programmed using the control channel in base
mode. The serializer holds its device address and the
device address of the deserializer it is driving. Similarly,
the driven deserializer holds its device address and the
address of the serializer by which it is driven. Whenever a
device address is changed, the new address should be
written to both devices. The default device address of the
MAX9271 serializer (or any GMSL serializer) is 0x80 and
the default device address of any GMSL deserializer is
0x90 (Table 1). Registers 0x00 and 0x01 in both devices
hold the device addresses.
The MAX9271 serializer, when paired with the MAX9272
deserializer, provides the full set of operating features,
but offers basic functionality when paired with any GMSL
deserializer.
The serializer has a maximum serial-bit rate of 1.5Gbps
for 15m or more of cable and operates up to a maximum
input clock of 50MHz in 16-bit, single-input mode, or
75MHz/100MHz in 15-bit/11-bit, double-input mode,
respectively. Pre/deemphasis, along with the GMSL
deserializer channel equalizer, extends the link length
and enhances link reliability.
Input Bit Map
The parallel input functioning and width depends on
settings of the double-/single-input mode (DBL), HS/VS
encoding (HVEN), error correction (EDC), and bus width
(BWS) pins. DINA is the input latched by the pixel clock
in single-input mode, or the inputs latched on the first
pixel clock in double-input mode. DINB are the inputs
latched on the second pixel clock in double-input mode.
Table 2 lists the bit map for the control pin settings.
The control channel enables a FC to program serial-
izer and deserializer registers and program registers
on peripherals. The FC can be located at either end of
the link or at both ends. Two modes of control-channel
operation are available with associated protocols and
data formats. Base mode uses either I2C or GMSL UART
protocol, while bypass mode uses a user-defined UART
protocol.
Spread spectrum is available to reduce EMI on the serial
output. The serial output complies with ISO 10605 and
IEC 61000-4-2 ESD protection standards.
18
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Table 1. Power-Up Default Register Map (see Table 16)
REGISTER
ADDRESS (hex)
POWER-UP
DEFAULT (hex)
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
SERID = 1000000, serializer device address
CFGBLOCK = 0, registers 0x00 to 0x1F are read/write
0x00
0x01
0x80
0x90
DESID = 1001000, deserializer device address
RESERVED = 0
SS = 000 no spread spectrum
RESERVED = 1
PRNG = 11, automatically detect the pixel clock range
SRNG = 11, automatically detect serial-data rate
0x02
0x03
0x1F
0x00
AUTOFM = 00, calibrate spread-modulation rate only once after locking
SDIV = 000000, autocalibrate sawtooth divider
SEREN = 1, serial link enabled
CLINKEN = 0, configuration link disabled
PRBSEN = 0, PRBS test disabled
0x04
0x87
SLEEP = 0, sleep mode disabled (see the Link Startup Procedure section)
INTTYPE = 01, local control channel uses UART
REVCCEN = 1, reverse control channel active (receiving)
FWDCCEN = 1, forward control channel active (sending)
I2CMETHOD = 0, I2C packets include register address
ENJITFILT = 0, jitter filter disabled
PRBSLEN = 00, continuous PRBS length
RESERVED = 00
ENWAKEN = 0, OUT- wake-up receiver disabled
ENWAKEP = 1, OUT+ wake-up receiver enabled
0x05
0x06
0x00
CMLLVL = 1000 or 1010, output level determined by the state of CONF1 and CONF0
at power-up
0x80, 0xA0
PREEMP = 0000, preemphasis disabled
DBL = 0 or 1, single-/double-input mode setting determined by the state of LCCEN
and TX/SCL/DBL at startup
DRS = 0, high data-rate mode
BWS = 0 or 1, bit width setting determined by the state of LCCEN and GPIO1/BWS
at startup
ES = 0 or 1, edge-select input setting determined by the state of LCCEN and
TX/SCL/ES at startup
RESERVED = 0
HVEN = 0 or 1, HS/VS tracking encoding setting determined by the state of LCCEN
and MS/HVEN at startup
EDC = 00 or 10, error-detection/correction setting determined by the state of LCCEN
and RX/SDA/EDC at startup
0x07
0x08
0xXX
0x00
INVVS = 0, serializer does not invert VSYNC
INVHS = 0, serializer does not invert HSYNC
RESERVED = 000000
19
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Table 1. Power-Up Default Register Map (see Table 16) (continued)
REGISTER
ADDRESS (hex)
POWER-UP
DEFAULT (hex)
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
I2CSRCA = 0000000, I2C address translator source A is 0x00
RESERVED = 0
0x09
0x0A
0x0B
0x0C
0x00
0x00
0x00
0x00
I2CDSTA = 0000000, I2C address translator destination A is 0x00
RESERVED = 0
I2CSRCB = 0000000, I2C address translator source B is 0x00
RESERVED = 0
I2CDSTB = 0000000, I2C address translator destination B is 0x00
RESERVED = 0
I2CLOCACK = 1, acknowledge generated when forward channel is not available
I2CSLVSH = 01, 469ns/234ns I2C setup/hold time
I2CMSTBT = 101, 339kbps (typ) I2C-to-I2C master bit-rate setting
I2CSLVTO = 10, 1024Fs (typ) I2C-to-I2C slave remote timeout
0x0D
0xB6
DIS_REV_P = 0, OUT+ reverse channel receiver enabled
DIS_REV_N = 1, OUT- reverse channel receiver disabled
GPIO5EN = 0, GPIO5 disabled
GPIO4EN = 0, GPIO4 disabled
GPIO3EN = 0, GPIO3 disabled
0x0E
0x42
GPIO2EN = 0, GPIO2 disabled
GPIO1EN = 1, GPIO1 enabled
RESERVED = 0
RESERVED = 11
GPIO5OUT = 1, GPIO5 set high
GPIO4OUT = 1, GPIO4 set high
GPIO3OUT = 1, GPIO3 set high
GPIO2OUT = 1, GPIO2 set high
GPIO1OUT = 1, GPIO1 set high
SETGPO = 0, GPO set low
0x0F
0xFE
RESERVED = 00
GPIO5IN = 1, GPIO5 is input high
GPIO4IN = 1, GPIO4 is input high
GPIO3IN = 1, GPIO3 is input high
GPIO2IN = 1, GPIO2 is input high
GPIO1IN = 1, GPIO1 is input high
GPO_L = 0, GPO is set low
0x10
0x11
0x3E
0x00
ERRGRATE = 00, generate an error every 2560 bits
ERRGTYPE = 0, generate single-bit errors
ERRGCNT = 00, continuously generate errors
ERRGPER = 0, disable periodic error generation
ERRGEN = 0, disable error generation
20
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Table 1. Power-Up Default Register Map (see Table 16) (continued)
REGISTER
ADDRESS (hex)
POWER-UP
DEFAULT (hex)
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
0x12
0x13
0x14
0x40
0x22
0xXX
RESERVED = 01000000
RESERVED = 00100010
RESERVED = XXXXXXXX
CXTP = 0, CXTP is low
I2CSEL = 0, input is low
LCCEN = 0, local control channel disabled
RESERVED = 000
0x15
0x00
OUTPUTEN = 0, output disabled
PCLKDET = 0, no valid PCLKIN detected
0xXX
(read only)
0x16
0x17
0x1E
RESERVED = XXXXXXXX
0xXX
(read only)
RESERVED = XXXXXXXX
0x09
(read only)
ID = 00001001, device ID is 0x09
RESERVED = 000
CAPS = 0, serializer is not HDCP capable
REVISION = XXXX, revision number
0x0X
(read only)
0x1F
X = Don’t care.
Table 2. Input Map
EDC
0
BWS
0
DBL
0
HVEN
DINA
0:15
DINB*
SERIAL LINK WORD BITS
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
—
0:15
0:13
0
0
0
0:13, HS, VS
0:10
—
0
0
1
0:10
0:21
0
0
1
0:10, HS, VS
0:15
0:10, HS, VS
0:21
0
1
0
—
0:15
0
1
0
0:13, HS, VS
0:14
—
0:13
0
1
1
0:14
0:29
0
1
1
0:13, HS, VS
0:15
0:13, HS, VS
0:13, 15:28
0:15
1
0
0
—
1
0
0
0:13, HS, VS
0:7
—
0:7
0:13
1
0
1
0:15
1
0
1
0:7, HS, VS
0:15
0:7, HS, VS
—
0:13
1
1
0
0:15
1
1
0
0:13, HS, VS
0:11
—
0:13
1
1
1
0:11
0:23
1
1
1
0:11, HS, VS
0:11, HS, VS
0:23
*In double-input mode (DBL = 1), DINA is latched on the first cycle of PCLKIN and DINB is latched on the second cycle of PCLKIN.
21
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
The parallel input has two input modes: single- and
In double-input mode, LATCH B stores two input words
(Figure 15). Data from LATCH B is sent to the scrambler
as a combined word. The MAX9272 deserializer outputs
the combined word (single-output mode) or two half-sized
words (double-output mode). The serializer/deserializer
use pixel clock rates from 33.3MHz to 100MHz for 11-bit,
double-input mode and 25MHz to 75MHz for 15-bit,
double-input mode. See Figure 16 for timing details.
double-rate input. In single-input mode, LATCH A stores
data from DIN_ every PCLKIN cycle (Figure 13). Parallel
data from LATCH A is then sent to the scrambler for
serialization (Figure 14). The device accepts pixel clocks
from 6.25MHz to 50MHz.
PCLKIN
DIN0–DIN15
LATCH A
FIRST WORD
SECOND WORD
THIRD WORD
FOURTH WORD
FIRST WORD
SECOND WORD
THIRD WORD
FOURTH WORD
Figure 13. Single-Input Waveform (Latch on Rising Edge of PCLKIN Selected)
MAX9271
DIN0–DIN14
INPUT
LATCH A
DIN0–DIN15
OR
DIN0–DIN10
INPUT
LATCH B
INPUT
LATCH A
MAX9271
÷ 2
PCLKIN
PCLKIN
Figure 14. Single-Input Function Block
Figure 15. Double-Input Function Block
22
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
PCLKIN
÷ 2
DIN0–DIN14
OR
FIRST WORD
SECOND WORD
THIRD WORD
FOURTH WORD
DIN0–DIN10
LATCH A
LATCH B
FIRST WORD
THIRD WORD
THIRD AND FOURTH WORD
FIRST AND SECOND WORD
Figure 16. Double-Input Waveform (Latch on Rising Edge of PCLKIN Selected)
Serial Link Signaling and Data Format
The serializer uses differential CML signaling to drive
Control Channel and Register
Programming
twisted-pair cable and single-ended CML to drive coax
cable. The output amplitude is programmable.
The control channel is available for the FC to send and
receive control data over the serial link simultaneously
with the high-speed data. The FC controls the link from
either the serializer or the deserializer side. The control
channel between the FC and serializer or deserializer
runs in base mode or bypass mode, according to the
mode selection (MS/HVEN) input of the device connected
to the FC. Base mode is a half-duplex control channel and
bypass mode is a full-duplex control channel.
Input data is scrambled and then 8b/10b coded. The
deserializer recovers the embedded serial clock, then
samples, decodes, and descrambles the data. In 24-bit
or 32-bit mode, 22 or 30 bits contain the video data
and/or error-correction bits, if used. The 23rd or 31st bit
carries the forward control-channel data. The last bit is
the parity bit of the previous 23 or 31 bits. (Figure 17).
UART Interface
In base mode, the FC is the host and can access the
registers of both the serializer and deserializer from
either side of the link using the GMSL UART protocol.
The FC can also program the peripherals on the remote
side by sending the UART packets to the serializer or
deserializer, with the UART packets converted to I2C
by the device on the remote side of the link. The FC
communicates with a UART peripheral in base mode
(through INTTYPE register settings), using the half-duplex
default GMSL UART protocol of the serializer/deserial-
izer. The device addresses of the serializer/deserializer in
base mode are programmable. The default value is 0x80
for the serializer and 0x90 for the deserializer.
Reverse Control Channel
The serializer uses the reverse control channel to receive
I2C/UART and GPO signals from the deserializer in the
opposite direction of the video stream. The reverse
control channel and forward video data coexist on the
same serial cable, forming a bidirectional link. The
reverse control channel operates independently from the
forward control channel. The reverse control channel is
available 2ms after power-up. The serializer temporarily
disables the reverse control channel for 350Fs after start-
ing/stopping the forward serial link.
Data-Rate Selection
The serializer/deserializer use DRS, DBL, and BWS to set
the PCLKIN frequency range (Table 3). Set DRS = 1 for
a PCLKIN frequency range of 6.25MHz to 12.5MHz (32-
bit, single-input mode) or 8.33MHz to 16.66MHz (24-bit,
single-input mode). Set DRS = 0 for normal operation.
It is not recommended to use double-input mode when
DRS = 1.
When the peripheral interface is I2C, the serializer/
deserializer convert UART packets to I2C that have
device addresses different from those of the serializer or
deserializer. The converted I2C bit rate is the same as the
original UART bit rate.
23
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
24 BITS
32 BITS
D0
D1
D21
FCC
PCB
D0
D1
D29
FCC
PCB
FORWARD
CONTROL-
CHANNEL BIT
FORWARD
CONTROL-
CHANNEL BIT
VIDEO AND ERROR-
CORRECTION DATA
VIDEO AND ERROR-
CORRECTION DATA
PACKET
PARITY
PACKET
PARITY
CHECK BIT
CHECK BIT
NOTE: SERIAL DATA SHOWN BEFORE SCRAMBLING AND 8b/10b ENCODING
Figure 17. Serial-Data Format
Table 3. Data-Rate Selection Table
DRS SETTING
DBL SETTING
BWS SETTING
PCLKIN RANGE (MHz)
16.66 to 50
12.5 to 35
0
0
0
0
1
1
1
1
0 (single input)
0 (24-bit mode)
0
1 (32-bit mode)
1 (double input)
0
1
0
1
0
1
33.3 to 100
25 to 75
1
0
0
1
1
8.33 to 16.66
6.25 to 12.5
Do not use
Do not use
The deserializer uses differential line coding to send
signals over the reverse channel to the serializer. The
bit rate of the control channel is 9.6kbps to 1Mbps in
both directions. The serializer/deserializer automatically
detect the control-channel bit rate in base mode. Packet
bit-rate changes can be made in steps of up to 3.5
times higher or lower than the previous bit rate. See the
Changing the Clock Frequency section for more informa-
tion on changing the control-channel bit rate.
generate transitions on the control channel that can be
ignored by the FC. Data written to the serializer/deserial-
izer registers do not take effect until after the ACK byte
is sent. This allows the FC to verify that write commands
are received without error, even if the result of the write
command directly affects the serial link. The slave uses
the SYNC byte to synchronize with the host UART’s data
rate. If the GPI or MS/HVEN inputs of the deserializer tog-
gle while there is control-channel communication, or if a
line fault occurs, the control-channel communication is
corrupted. In the event of a missed or delayed acknowl-
edge (~1ms due to control-channel timeout), the FC
should assume there was an error in the packet when the
slave device received it, or that an error occurred during
the response from the slave device. In base mode, the
FC must keep the UART Tx/Rx lines high for 16 bit times
before starting to send a new packet.
Figure 18 shows the UART protocol for writing and read-
ing in base mode between the FC and the serializer/
deserializer.
Figure 19 shows the UART data format. Figure 20 and
Figure 21 detail the formats of the SYNC byte (0x79)
and the ACK byte (0xC3). The FC and the connected
slave chip generate the SYNC byte and ACK byte,
respectively. Events such as device wake-up and GPI
24
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
WRITE DATA FORMAT
SYNC
DEV ADDR + R/W
REG ADDR
NUMBER OF BYTES
BYTE 1
BYTE N
ACK
MASTER WRITES TO SLAVE
MASTER READS FROM SLAVE
READ DATA FORMAT
NUMBER OF BYTES
SYNC
DEV ADDR + R/W
REG ADDR
MASTER WRITES TO SLAVE
ACK
BYTE 1
BYTE N
MASTER READS FROM SLAVE
Figure 18. GMSL UART Protocol for Base Mode
1 UART FRAME
D4
START
D0
D1
D2
D3
D5
D6
D7
PARITY
STOP
FRAME 1
FRAME 2
FRAME 3
STOP
START
STOP
START
Figure 19. GMSL UART Data Format for Base Mode
D0
1
D1
0
D2
0
D3
1
D4
1
D5
1
D6
1
D7
0
D0
1
D1
D2
0
D3
0
D4
0
D5
0
D6
1
D7
1
START
1
PARITY STOP
START
PARITY STOP
Figure 20. SYNC Byte (0x79)
Figure 21. ACK Byte (0xC3)
25
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
UART Bypass Mode
In bypass mode, the serializer/deserializer ignore UART
commands from the FC and the FC communicates with
the peripherals directly using its own defined UART pro-
tocol. The FC cannot access the serializer/deserializer
registers in this mode. Peripherals accessed through the
forward control channel using the UART interface need
to handle at least one PCLKIN period Q10ns of jitter due
to the asynchronous sampling of the UART signal by
PCLKIN. Set MS/HVEN = high to put the control channel
into bypass mode. For applications with the FC connect-
ed to the deserializer, there is a 1ms wait time between
setting MS/HVEN high and the bypass control channel
being active. There is no delay time when switching to
bypass mode when the FC is connected to the serial-
izer. Do not send a logic-low value longer than 100Fs to
ensure proper GPO functionality. Bypass mode accepts
bit rates down to 10kbps in either direction. See the GPO/
GPI Control section for GPO functionality limitations. The
control-channel data pattern should not be held low
longer than 100Fs if GPO control is used.
As shown in Figure 22, the remote-side device converts
packets going to or coming from the peripherals from
UART format to I2C format and vice versa. The remote
device removes the byte number count and adds or
receives the ACK between the data bytes of I2C. The I2C
bit rate is the same as the UART bit rate.
2
Interfacing Command-Byte-Only I C
Devices with UART
The serializer/deserializer UART-to-I2C conversion can
interface with devices that do not require register address-
es, such as the MAX7324 GPIO expander. In this mode,
the I2C master ignores the register address byte and
directly reads/writes the subsequent data bytes (Figure
23). Change the communication method of the I2C mas-
ter using the I2CMETHOD bit. I2CMETHOD = 1 sets
command-byte-only mode, while I2CMETHOD = 0 sets
normal mode where the first byte in the data stream is
the register address.
2
UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)
SERIALIZER/DESERIALIZER
11
FC
11
11
11
11
11
11
SYNC FRAME
DEVICE ID + WR
REGISTER ADDRESS NUMBER OF BYTES
DATA 0
DATA N
ACK FRAME
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
8
1
1
S
DEV ID W A REG ADDR
A
DATA 0
A
DATA N
A
P
2
UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 0)
SERIALIZER/DESERIALIZER
11
FC
11
11
11
11
ACK FRAME
11
DATA 0
11
DATA N
SYNC FRAME
DEVICE ID + RD
REGISTER ADDRESS NUMBER OF BYTES
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
DEV ID W A REG ADDR
A
S
DEV ID
R
A
DATA 0
A
DATA N
A
P
S: START
P: STOP
A: ACKNOWLEDGE
: MASTER TO SLAVE
: SLAVE TO MASTER
Figure 22. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0)
26
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
2
UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)
FC
SERIALIZER/DESERIALIZER
11
11
11
11
11
11
11
SYNC FRAME
DEVICE ID + WR
REGISTER ADDRESS NUMBER OF BYTES
DATA 0
DATA N
ACK FRAME
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
1
S
DEV ID
W
A
DATA 0
A
DATA N
A
P
2
UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 1)
FC
SERIALIZER/DESERIALIZER
11
11
11
11
11
11
DATA 0
11
DATA N
SYNC FRAME
DEVICE ID + RD
REGISTER ADDRESS NUMBER OF BYTES
ACK FRAME
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
1
S
DEV ID
R
A
DATA 0
A
DATA N
A
P
: MASTER TO SLAVE
: SLAVE TO MASTER S: START
P: STOP A: ACKNOWLEDGE
2
Figure 23. Format Conversion Between GMSL UART and I C with Register Address (I2CMETHOD = 1)
I2C Interface
In I2C-to-I2C mode the serializer’s control-channel inter-
face sends and receives data through an I2C-compatible
2-wire interface. The interface uses a serial-data line
(SDA) and a serial-clock line (SCL) to achieve bidirec-
tional communication between master and slave(s). A
FC master initiates all data transfers to and from the
device and generates the SCL clock that synchronizes
the data transfer. When an I2C transaction starts on the
local-side device’s control-channel port, the remote-side
device’s control-channel port becomes an I2C master
that interfaces with remote-side I2C perhipherals. The I2C
master must accept clock stretching, which is imposed
by the serializer (holding SCL low). The SDA and SCL
lines operate as both an input and an open-drain output.
Pullup resistors are required on SDA and SCL. Each
transmission consists of a START condition (Figure 6)
sent by a master, followed by the device’s 7-bit slave
address plus a R/W bit, a register address byte, one or
more data bytes, and finally a STOP condition.
master has finished communicating with the slave, it
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission.
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 25). The data on SDA must remain stable while
SCL is high.
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipient
uses to handshake receipt of each byte of data (Figure 26).
Thus, each byte transferred effectively requires 9 bits.
The master generates the 9th clock pulse, and the recipi-
ent pulls down SDA during the acknowledge clock pulse.
The SDA line is stable low during the high period of the
clock pulse. When the master is transmitting to the slave
device, the slave device generates the acknowledge bit
because the slave device is the recipient. When the slave
device is transmitting to the master, the master generates
the acknowledge bit because the master is the recipient.
The device generates an acknowledge even when the
forward control channel is not active (not locked). To pre-
vent acknowledge generation when the forward control
channel is not active, set the I2CLOCACK.
START and STOP Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from
high to low while SCL is high (see Figure 24). When the
27
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
SDA
SCL
P
S
STOP
CONDITION
START
CONDITION
Figure 24. START and STOP Conditions
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 25. Bit Transfer
START
CONDITION
CLOCK PULSE FOR
ACKNOWLEDGE
1
2
8
9
SCL
SDA
BY
TRANSMITTER
SDA
BY
RECEIVER
S
Figure 26. Acknowledge
28
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Slave Address
The serializer/deserializer have a 7-bit-long slave address.
The bit following a 7-bit slave address is the R/W bit,
which is low for a write command and high for a read
command. The slave address is 10000001 for read com-
mands and 10000000 for write commands. See Figure 27.
followed by at least one byte of information. The first
byte of information is the register address or command
byte. The register address determines which register of
the device is to be written by the next byte, if received.
If a STOP (P) condition is detected after the register
address is received, the device takes no further action
beyond storing the register address (Figure 28). Any
bytes received after the register address are data bytes.
The first data byte goes into the register selected by the
register address, and subsequent data bytes go into
subsequent registers (Figure 29). If multiple data bytes
are transmitted before a STOP condition, these bytes
are stored in subsequent registers because the register
addresses autoincrement.
Bus Reset
The device resets the bus with the I2C START condition
for reads. When the R/W bit is set to 1, the serializer/
deserializer transmit data to the master, thus the master
is reading from the device.
Format for Writing
A write to the serializer/deserializer comprises the trans-
mission of the slave address with the R/W bit set to zero,
0
0
0
0
0
0
R/W
LSB
SDA
SCL
1
ACK
MSB
Figure 27. Slave Address
0 = WRITE
ADDRESS = 0x80
REGISTER ADDRESS = 0x00
REGISTER 0x00 WRITE DATA
S
1
0
0
0
0
0
0
0
A
0
0
0
0
0
0
0
0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
S = START BIT
P = STOP BIT
A = ACK
D_ = DATA BIT
2
Figure 28. Format for I C Write
0 = WRITE
ADDRESS = 0x80
REGISTER ADDRESS = 0x00
S
1
0
0
0
0
0
0
0
A
0
0
0
0
0
0
0
0
A
S = START BIT
P = STOP BIT
A = ACK
REGISTER 0x00 WRITE DATA
REGISTER 0x01 WRITE DATA
N = NACK
D_ = DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
A
D7
D6
D5
D4
D3
D2
D1
D0
N
P
Figure 29. Format for Write to Multiple Registers
29
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Format for Reading
The serializer/deserializer are read using the internally
stored register address as an address pointer, the same
way the stored register address is used as an address
pointer for a write. The pointer autoincrements after each
data byte is read using the same rules as for a write. Thus,
a read is initiated by first configuring the register address
by performing a write (Figure 30). The master can now
read consecutive bytes from the device, with the first data
byte being read from the register address pointed by
the previously written register address. Once the master
sends a NACK, the device stops sending valid data.
bit rate different than 400kbps, local- and remote-side
I2C setup and hold times should be adjusted by setting
the SLV_SH register settings on both sides.
2
I C Address Translation
The serializer supports I2C address translation for up to
two device addresses. Use address translation to assign
unique device addresses to peripherals with limited
I2C addresses. Source addresses (address to translate
from) are stored in registers 0x09 and 0x0B. Destination
addresses (address to translate to) are stored in registers
0x0A and 0x0C.
2
I C Broadcast Mode
2
I C Communication with Remote-Side Devices
The serializer supports broadcast commands to control
multiple peripheral devices. Select an unused device
address to use as a broadcast device address. Program
the remote-side GMSL device to translate the broadcast
device address (source address stored in registers 0x09,
0x0B) to the peripheral device address (destination
address stored in registers 0x0A, 0x0C). Any commands
sent to the broadcast address are sent to all designated
peripherals, while commands sent to a peripheral’s unique
device address are sent to that particular device only.
The serializer supports I2C communication with a periph-
eral on the remote side of the communication link using
SCL clock stretching. While multiple masters can reside
on either side of the communication link, arbitration is
not provided. The connected masters need to support
SCL clock stretching and provide contention detection.
The remote side I2C bit-rate range must be set accord-
ing to the local-side I2C bit rate. Supported remote-side
bit rates can be found in Table 4. Set the I2CMSTBT
(register 0x0D) to set the remote I2C bit rate. If using a
0 = WRITE
ADDRESS = 0x80
REGISTER ADDRESS = 0x00
S
1
1
0
0
0
0
0
0
0
0
0
0
A
A
0
0
0
0
0
0
0
0
A
S = START BIT
P = STOP BIT
A = ACK
N = NACK
D_ = DATA BIT
1 = READ
ADDRESS = 0x81
REGISTER 0x00 READ DATA
REPEATED START
S
0
0
0
1
D7
D6
D5
D4
D3
D2
D1
D0
N
P
2
Figure 30. Format for I C Read
2
Table 4. I C Bit-Rate Ranges
LOCAL BIT RATE
f > 50kbps
REMOTE BIT-RATE RANGE
Up to 1Mbps
I2CMSTBT SETTING
Any
Up to 110
000
20kbps > f > 50kbps
f < 20kbps
Up to 400kbps
Up to 10kbps
30
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
compensates the high-frequency loss of the cable and
enables reliable transmission over longer link distances.
Current drive for both TP and coax modes is program-
mable. CMLLVL bits (0x06, D[7:4]) program drive current
in TP and coax modes for a single-ended voltage swing
from 100mV to 500mV.
GPO/GPI Control
GPO on the serializer follows GPI transitions on the dese-
rializer. This GPO/GPI function can be used to transmit
signals such as frame sync in a surround-view camera
system. The GPI-to-GPO delay is 0.35ms (max). Keep
the time between GPI transitions to a minimum 0.35ms.
This includes transitions from the other deserializer in the
coax-mode splitter. Bit D4 of register 0x0E in the deserial-
izer stores the GPI input state. GPO is low after power-up.
The FC can set GPO by writing to the SET_GPO register
bit. Do not send a logic-low value on the deserializer RX/
SDA input (UART mode) longer than 100Fs in either base
or bypass mode to ensure proper GPO/GPI functionality.
Spread Spectrum
To reduce the EMI generated by the transitions on the
serial link, the serializer output is programmable for
spread spectrum. If the deserializer driven by the serial-
izer has programmable spread spectrum, do not enable
spread for both at the same time or their interaction will
cancel benefits. The deserializer tracks the serializer’s
spread and passes the spread to the deserializer output.
The programmable spread-spectrum amplitudes are
Q0.5%, Q1%, Q1.5%, Q2%, Q3%, and Q4% (Table 6).
Some spread-spectrum amplitudes can only be used at
lower PCLKIN frequencies (Table 7). There is no PCLKIN
frequency limit for the Q0.5% spread rate.
Pre/Deemphasis Driver
The serial line driver employs current-mode logic (CML)
signaling. The driver is differential when programmed
for twisted-pair (TP). When programmed for coax, one
side of the CML driver is used. The line driver has pro-
grammable pre/deemphasis that modifies the output to
compensate for cable length. There are 13 preemphasis
settings, as shown in Table 5. Negative preemphasis
levels are deemphasis levels in which the preempha-
sized swing level is the same as normal swing, but the
no-transition data (e.g., a 1 followed by a 1) is deempha-
sized. Program the preemphasis levels through register
0x06 D[3:0] of the serializer. This preemphasis function
When the spread spectrum is turned on or off, the serial
link stops for several microseconds and then restarts in
order for the deserializer to lose and relock to the new
serial-data stream.
The serializer includes a sawtooth divider to control the
spread-modulation rate. Autodetection of the PCLKIN
Table 5. TP/Coax Drive Current (CMLLVL = 1000)
SINGLE-ENDED VOLTAGE SWING
PREEMPHASIS
LEVEL (dB)*
PREEMP SETTING
(0x06, D[3:0])
I
I
PRE
(mA)
CML
(mA)
MAX (mV)
400
MIN (mV)
200
-6.0
-4.1
-2.5
-1.2
0100
0011
0010
0001
12
4
3
2
1
13
400
250
14
400
300
15
400
350
0
0000
16
0
400
400
(power-on default)
1.1
2.2
1000
1001
1010
1011
1100
1101
1110
1111
16
16
16
16
15
14
13
12
1
2
3
4
5
6
7
8
425
450
475
500
500
500
500
500
375
350
325
300
250
200
150
100
3.3
4.4
6.0
8.0
10.5
14.0
*Negative preemphasis levels denote deemphasis.
31
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Table 6. Serial Output Spread
SS
000
001
010
011
100
101
110
111
SPREAD (%)
No spread spectrum. Power-up default.
0.5% spread spectrum.
1.5% spread spectrum.
2% spread spectrum.
No spread spectrum.
1% spread spectrum.
3% spread spectrum.
4% spread spectrum.
Table 7. Spread Limitations
BWS = 0 MODE, PCLKIN
FREQUENCY (MHz)
BWS = 1 MODE, PCLKIN
FREQUENCY (MHz)
SERIAL LINK BIT
RATE (Mbps)
AVAILABLE
SPREAD RATES
< 33.3
< 25
(DBL = 0)
(DBL = 0)
< 1000
All rates available
1.5%, 1.0%, 0.5%
< 66.6
(DBL = 1)
< 50
(DBL = 1)
33.3 to 50
(DBL = 0)
25 to 37.5
(DBL = 0)
R 1000
66.6 to 100
(DBL = 1)
50 to 75
(DBL = 1)
operation range guarantees a spread-spectrum modu-
lation frequency within 20kHz to 40kHz. Additionally,
manual configuration of the sawtooth divider (SDIV: 0x03,
D[5:0]) allows the user to set a modulation frequency
according to the PCLKIN frequency. When ranges are
manually selected, program the SDIV value for a fixed
modulation frequency around 20kHz.
spread-spectrum settings. Solve the above equation for
SDIV using the desired pixel clock and modulation fre-
quencies. If the calculated SDIV value is larger than the
maximum allowed SDIV value in Table 8, set SDIV to the
maximum value.
Additional Error Detection and Correction
In default mode (additional error detection and correc-
tion disabled), data encoding/decoding is the same as in
previous GMSL serializers/deserializers (parity only). At
the serializer, the parallel input word is scrambled and a
parity bit is added. The scrambled word is divided into
3 or 4 bytes (depending on the BWS setting), 8b/10b
encoded, and then transmitted serially. At the deserial-
izer, the same operations are performed in reverse order.
The parity bit is used by the deserializer to find the word
boundary and for error detection. Errors are counted in
an error counter register and an error pin indicates errors.
The serializer can use one of two additional error-
detection/correction methods (selectable by register
setting):
Manual Programming of the
Spread-Spectrum Divider
The modulation rate relates to the PCLKIN frequency as
follows:
f
PCLKIN
MOD x SDIV
f
= (1+ DRS)
M
where:
fM = Modulation frequency
DRS = DRS value (0 or 1)
fPCLKIN = PCLKIN frequency
MOD = Modulation coefficient given in Table 8
SDIV = 6-bit SDIV setting, manually programmed by the FC
1) 6-bit cyclic redundancy check
To program the SDIV setting, first look up the modula-
tion coefficient according to the desired bus-width and
2) 6-bit hamming code with 16-word interleaving
32
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
The serializer uses data interleaving for burst error toler-
Table 8. Modulation Coefficients and
Maximum SDIV Settings
ance. Burst errors up to 11 consecutive bits on the serial
link are corrected, and burst errors up to 31 consecutive
bits are detected.
SPREAD-
SPECTRUM
SETTING (%)
MODULATION
COEFFICIENT
(dec)
SDIV UPPER
LIMIT (dec)
BWS
Hamming code adds overhead similar to CRC. See Table 2
for details regarding the available input word size.
1
0.5
3
104
104
152
152
204
204
80
40
63
27
54
15
30
52
63
37
63
21
42
HS/VS Encoding and/or Tracking
HS/VS encoding by a GMSL serializer allows horizontal
and vertical synchronization signals to be transmitted
while conserving pixel data bandwidth. With HS/VS
encoding enabled, 10-bit pixel data with a clock up to
100MHz can be transmitted using one video pixel of
data per HS/VS transition, versus 8-bit data with a clock
up to 100MHz without HS/VS encoding. The deserializer
performs HS/VS decoding, tracks the period of the HS/
VS signals, and uses voting to filter HS/VS bit errors.
When using HS/VS encoding, use a minimum HS/VS low-
pulse duration of two PCLKIN cycles when DBL = 0 on
the MAX9271/MAX9273. When DBL = 1, use a minimum
low-pulse duration of five PCLKIN cycles and a minimum
high-pulse duration of two PCLKIN cycles. When using
hamming code with HS/VS encoding, do not send more
than two transitions every 16 PCLKIN cycles.
1
1.5
4
2
1
0.5
3
80
112
112
152
152
0
1.5
4
2
Cyclic Redundancy Check (CRC)
When CRC is enabled, the serializer adds 6 bits of CRC
to the input data. This reduces the available bits in the
input data word by 6, compared to the non-CRC case
(see Table 2 for details). For example, 16 bits are avail-
able for input data instead of 22 bits when BWS = 0, and
24 bits instead of 30 bits when BWS = 1.
When the serializer uses double-input mode (DBL = 1)
the active duration, plus the blanking duration of HS or
VS signals, should be an even number of PCLKIN cycles.
If HS/VS tracking is used without HS/VS encoding, use
DIN0 for HSYNC and DIN1 for VSYNC. In this case, if
DBL values on the serializer and the deserializer are dif-
ferent, set the deserializer’s UNEQDBL register bit to 1.
If the serializer and deserializer have unequal DBL set-
tings and HVEN = 0, then HS/VS inversion should only
be used on the side that has DBL = 1. HS/VS encoding
sends packets when HSYNC or VSYNC is low, use H/V
inversion register bits if input HSYNC and VSYNC signals
use an active-low convention to send data packets dur-
ing the inactive pixel clock periods.
The CRC generator polynomial is x6 + x + 1 (as used in
the ITU-T G704 telecommunication standard).
The parity bit is still added when CRC is enabled,
because it is used for word-boundary detection. When
CRC is enabled, each data word is scrambled and then
the 6-bit CRC and 1-bit parity are added before the
8b/10b encoding.
At the deserializer, the CRC code is recalculated. If the
recalculated CRC code does not match the received
CRC code, an error is flagged. This CRC error is reported
to the error counter.
Serial Output
The driver output is programmable for two types of cable:
100I twisted pair and 50I coax (contact the factory for
serializers with 75I cable drive).
Hamming Code
Hamming code is a simple and effective error-correction
code to detect and/or correct errors. The MAX9271 seri-
alizer (when used with the MAX9272 GMSL deserializer)
uses a single-error correction, double-error detection per
pixel hamming-code scheme.
33
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Coax-Mode Splitter
In coax mode, OUT+ and OUT- are active. This enables
use as a 1:2 splitter (Figure 31). In coax mode, connect
OUT+ to IN+ of the deserializer. Connect OUT- to IN- of
the second deserializer. Control-channel data is broad-
cast from the serializer to both deserializers and their
attached peripherals. Assign a unique device address to
send control data to one deserializer. Leave all unused
IN_ pins unconnected, or connect them to ground
through 50Iand a capacitor for increased power-supply
rejection. If OUT- is not used, connect OUT- to AVDD
through a 50I resistor (Figure 32). When there are FCs
at the serializer, and at each deserializer, only one FC
can communicate at a time. Disable one splitter control-
channel link to prevent contention. Use the DIS_REV_P or
DIS_REV_N register bits to disable a control-channel link.
Configuration Inputs (CONF1, CONF0)
CONF1 and CONF0 determine the power-up values
of the serial output type, the input data latch, and the
control-channel interface type (Table 9). These functions
can be changed after power-up by writing to the appro-
priate register bits.
Sleep Mode
The serializer includes a sleep mode to reduce power
consumption. The device enters or exits sleep mode by
a command from a local FC or a remote FC using the
control channel. Set the SLEEP bit to 1 to initiate sleep
mode. The serializer sleeps immediately after setting
its SLEEP = 1. The OUT+ and OUT- serial outputs each
have a wake-up receiver to accept wake-up commands
from the attached deserializers. On power-up, the OUT+
GMSL
DESERIALIZER
MAX9271
GMSL
MAX9271
DESERIALIZER
OUT+
OUT-
IN+
IN-
OUT+
OUT-
IN+
IN-
AVDD
GMSL
DESERIALIZER
50I
IN+
IN-
Figure 31. 2:1 Coax-Mode Splitter Connection Diagram
Figure 32. Coax-Mode Connection Diagram
Table 9. Configuration Input Map
CXTP
ES
I2CSEL
(CONTROL-CHANNEL TYPE)
CONF1
CONF0
(OUT+/OUT- OUTPUT TYPE)
(PCLKIN LATCH EDGE)
Low
Low
Low
Mid
Low
Mid
1 (coax)
1 (falling)
1 (falling)
0 (rising)
0 (rising)
1 (falling)
1 (falling)
0 (rising)
0 (rising)
Do not use
1 (I2C-to-I2C)
0 (UART-to-I2C/UART)
1 (I2C-to-I2C)
0 (UART-to-I2C/UART)
1 (I2C-to-I2C)
0 (UART-to-I2C/UART)
1 (I2C-to-I2C)
0 (UART-to-I2C/UART)
1 (coax)
High
Low
Mid
1 (coax)
1 (coax)
Mid
0 (STP)
Mid
High
Low
Mid
0 (STP)
High
High
High
0 (STP)
0 (STP)
High
Do not use
Do not use
34
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
wake-up receiver is enabled and the OUT- wake-up
Configuration Link
The control channel can operate in a low-speed mode
called configuration link in the absence of a clock input.
This allows a microprocessor to program configuration
registers before starting the video link. An internal oscil-
lator provides the clock for the configuration link. Set
CLINKEN = 1 on the serializer to enable the configuration
link. The configuration link is active until the video link is
enabled. The video link overrides the configuration link
and attempts to lock when SEREN = 1.
receiver is disabled. Disable the wake-up receivers
(through ENWAKEP or ENWAKEN) if the devices are
disconnected or wake-up is not used in order to reduce
sleep mode current. If both wake-up receivers are disa-
bled, the device can only be woken up from the local
control channel. To wake up the device, send an arbitrary
control-channel command to the serializer. Wait 5ms for
the chip to power up and then write 0 to the SLEEP reg-
ister bit to make the wake-up permanent.
Power-Down Mode
The serializer has a power-down mode that further
reduces power consumption compared to sleep mode.
Set PWDN low to enter power-down mode. In power-
down mode, the serial outputs are in high impedance.
Entering power-down resets the device’s registers.
Upon exiting power-down, the state of the GPIO1/BWS,
MS/HVEN, LCCEN, CONF0, CONF1, RX/SDA/EDC, and
TX/SCL/DBL pins are latched.
Link Startup Procedure
Table 10 lists the startup procedure for video-display
applications. Table 11 lists the startup procedure for
image-sensing applications. The control channel is avail-
able after the video link or the configuration link is estab-
lished. If the deserializer powers up after the serializer,
the control channel becomes unavailable until 2ms after
power-up.
Table 10. Startup Procedure for Video-Display Applications
NO.
µC
FC connected to serializer.
Powers up.
SERIALIZER
DESERIALIZER
Sets all configuration inputs. If any
configuration inputs are available
on one end of the link but not on
the other, always connects that
configuration input low.
Sets all configuration inputs. If any
configuration inputs are available
on one end of the link but not on
the other, always connects that
configuration input low.
—
1
2
Powers up and loads default settings.
Powers up and loads default settings.
Enables configuration link by
setting CLINKEN = 1 (if not enabled
automatically) and gets an acknowledge.
Waits for link to be established (~3ms).
Establishes configuration link.
Locks to configuration link signal.
Writes one link configuration bit (DRS,
BWS, or EDC) in the deserializer and
gets an acknowledge.
Configuration changed from default
settings (loss-of-lock occurs if BWS or
EDC changes).
3
4
5
6
7
—
Writes corresponding serializer
link configuration bit and gets an
acknowledge.
Configuration changed from default
settings.
Relocks to configuration link signal.
—
Waits for link to be established (~3ms)
and then repeats steps 3 through 4 until
all serial link bits are configured.
—
Writes remaining configuration bits in
the serializer/deserializer and gets an
acknowledge.
Configuration changed from default
settings.
Configuration changed from default
settings.
Enables video link by setting SEREN = 1
and gets an acknowledge. Waits for link
to be established (~3ms).
Locks to serial link signal and begins
deserializing data.
Begins serializing data.
35
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Table 11. Startup Procedure for Image-Sensing Applications
NO.
µC
SERIALIZER
DESERIALIZER
Sets all configuration inputs. If any
configuration inputs are available
on one end of the link but not on
the other, always connects that
configuration input low.
Sets all configuration inputs. If any
configuration inputs are available
on one end of the link but not on
the other, always connects that
configuration input low.
—
FC connected to deserializer.
Powers up and loads default settings. Powers up and loads default settings.
1
3
Powers up.
Establishes serial link.
Locks to serial link signal.
Configuration changed from default
settings (loss-of-lock occurs if BWS or
EDC changes).
Writes deserializer configuration bits
and gets an acknowledge.
—
Writes serializer configuration bits.
Does not get an acknowledge (or
gets a dummy acknowledge) if loss-
of-lock occurred.
Configuration changed from default
settings.
4
5
Relocks to serial link signal.
Enables video link by setting SEREN
= 1 (if not enabled automatically).
Cannot get an acknowledge (or gets
a dummy acknowledge) if loss-of-
lock occurred. Waits for link to be
established (~3ms).
Locks to serial link signal and begins
deserializing data.
Begins serializing data.
CLINKEN = 0 OR
SEREN = 1
CLINKEN = 0 OR
SLEEP = 1
FOR > 8ms
SEREN = 1
CONFIG LINK
CONFIG LINK
UNLOCKED
SLEEP = 0,
SEREN = 0
OPERATING
POWER-ON
IDLE
CONFIG
LINK STARTED
SLEEP
WAKE-UP
PROGRAM
REGISTERS
WAKE-UP SIGNAL
CLINKEN = 1
CONFIG LINK
LOCKED
SEREN = 1,
PCLKIN RUNNING
SEREN = 0 OR
NO PCLKIN
SLEEP = 0,
SEREN = 1
SLEEP = 1
SEREN = 0 OR
NO PCLKIN
PRBSEN = 0
PRBSEN = 1
POWER-DOWN
OR
POWER-OFF
VIDEO LINK
LOCKED
PWDN = LOW OR
POWER-OFF
PWDN = HIGH,
POWER-ON
VIDEO
LINK LOCKING
VIDEO LINK
OPERATING
VIDEO LINK
PRBS TEST
ALL STATES
VIDEO LINK
UNLOCKED
Figure 33. State Diagram, All Applications
36
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
PCLKIN Spread Tracking
Applications Information
The serializer can operate with a spread PCLKIN
signal. When using a spread PCLKIN signal, disable the
jitter filter by setting ENJITFILT = 0 (0x05, D6). Do not
exceed the spread limitations listed in Table 7 and keep
modulation less than 40kHz. In addition, turn off spread
spectrum in the serializer/deserializer. The serializer/
deserializer track the spread on PCLKIN.
PRBS Test
The serializer includes a PRBS pattern generator that
works with bit-error verification in the deserializer. To run
the PRBS test, set PRBSEN = 1 (0x04, D5) in the deserial-
izer and then in the serializer. To exit the PRBS test, set
PRBSEN = 0 (0x04, D5) in the serializer.
Changing the Clock Frequency
It is recommended that the serial link be enabled after
the video clock (fPCLKIN) and the control-channel clock
(fUART/fI2C) are stable. When changing clock frequency,
stop the video clock for 5Fs, apply the clock at the new
frequency, then restart the serial link or toggle SEREN.
On-the-fly changes in clock frequency are possible if
the new frequency is immediately stable and without
glitches. The reverse control channel remains unavail-
able for 350Fs after serial link start or stop. When using
the UART interface, limit on-the-fly changes in fUART to
factors of less than 3.5 at a time to ensure that the device
recognizes the UART sync pattern. For example, when
lowering the UART frequency from 1Mbps to 100kbps,
first send data at 333kbps, then at 100kbps for reduction
ratios of 3 and 3.333, respectively.
Error Generator
The serializer contains an error generator that enables
repeatable testing of the error-detection/correction fea-
tures of the GMSL link. Register 0x11 stores the configu-
ration bits for the error generator. A FC sets the error-
generation rate, type of errors, and the total number of
errors. The error generator is off by default.
Dual µC Control
Usually systems have one FC to run the control channel,
located on the serializer side for video-display appli-
cations or on the deserializer side for image-sensing
applications. However, a FC can reside on each side
simultaneously and trade off running the control channel.
In this case, each FC can communicate with the serializer
and deserializer and any peripheral devices.
Contention occurs if both FC s attempt to use the control
channel at the same time. It is up to the user to prevent
this contention by implementing a higher-level protocol.
In addition, the control channel does not provide arbitra-
tion between I2C masters on both sides of the link. An
acknowledge frame is not generated when communica-
tion fails due to contention. If communication across the
serial link is not required, the FC s can disable the for-
ward and reverse control channel using the FWDCCEN
and REVCCEN bits (0x04, D[1:0]) in the serializer/dese-
rializer. Communication across the serial link is stopped
and contention between FC s cannot occur.
Providing a Frame Sync
(Camera Applications)
The GPI and GPO provide a simple solution for camera
applications that require a frame sync signal from the
ECU (e.g., surround-view systems). Connect the ECU
frame sync signal to the GPI input and connect the GPO
output to the camera frame sync input. GPI/GPO have
a typical delay of 275Fs. Skew between multiple GPI/
GPO channels is 115Fs (max). If a lower skew signal is
required, connect the camera’s frame sync input to one
of the serializer’s GPIOs and use an I2C broadcast write
command to change the GPIO output state. This has a
maximum skew of 1.5Fs, independent from the used I2C
bit rate.
As an example of dual FC use in an image-sensing appli-
cation, the serializer can be in sleep mode, waiting for
wake-up by the FC on the deserializer side. After wake-
up, the serializer-side FC assumes master control of the
serializer’s registers.
Software Programming of the
Device Addresses
Jitter-Filtering PLL
In some applications, the clock input (PCLKIN) includes
noise, which reduces link reliability. The clock input has a
programmable narrowband jitter-filter PLL that attenuates
frequencies higher than 100kHz (typ). Enable the jitter
filter by setting ENJITFILT = 1 (0x05, D6).
The serializer and deserializer have programmable device
addresses. This allows multiple GMSL devices, along with
I2C peripherals, to coexist on the same control channel.
The serializer device address is in register 0x00 of each
device, while the deserializer device address is in register
0x01 of each device. To change a device address, first
37
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
write to the device whose address changes (register 0x00
Compatibility with Other GMSL Devices
The MAX9271 serializer is designed to pair with the
MAX9272 deserializer, but interoperates with any GMSL
deserializer. See Table 12 for operating limitations.
of the serializer for serializer device address change, or
register 0x01 of the deserializer for deserializer device
address change). Then write the same address into the
corresponding register on the other device (register 0x00
of the deserializer for serializer device address change,
or register 0x01 of the serializer for deserializer device
address change).
GPIOs
The serializer has five open-drain GPIOs available when
not used as data or configuration inputs. Setting the
GPIO enable bits (register 0x0E) to 1 enables the GPIOs
and internally connects the respective data or configura-
tion input low. Setting the GPIO output bits to 0 pulls the
output low, while setting the bits to 1 leaves the output
undriven, and pulled high through internal/external pullup
resistors. The GPIO input buffers are enabled when the
GPIO is enabled. The input states are stored in register
0x10 (read only). Set GPIO_OUT to 1 when using a GPIO_
as an input.
Three-Level Configuration Inputs
CONF1 and CONF0 are three-level inputs that control
the serial interface configuration and power-up defaults.
Connect CONF1or CONF0 through a pullup resistor to
IOVDD to set a high level, a pulldown resistor to GND to
set a low level, or IOVDD/2 or open to set a midlevel. For
digital control, use three-state logic to drive the three-
level logic inputs.
Local Control-Channel Enable (LCCEN)
The serializer provides inputs for limited configuration of
the device when a FC is not connected. Connect LCCEN
= low upon power-up to disable the local control chan-
nel, and enable the double-function configuration inputs
(Table 13). All input configuration states are latched at
power-up.
Configuration Blocking
The serializer can block changes to registers. Set
CFGBLOCK to make all registers read only. Once set, the
registers remain blocked until the supplies are removed
or until PWDN is low.
Table 12. MAX9271 Feature Compatibility
MAX9271 FEATURE
GMSL Deserializer
HSYNC/VSYNC encoding
Hamming-code error correction
I2C-to-I2C
If feature not supported in the deserializer, must be turned off in the serializer.
If feature not supported in the deserializer, must be turned off in the serializer.
If feature not supported in the deserializer, must use UART-to-I2C or UART-to-UART.
If feature not supported in the deserializer, must be turned off in the serializer.
CRC error detection
If feature not supported in the deserializer, data is output as a single word at half the
input frequency.
Double input
If feature not supported in the deserializer, Must connect unused serial input through 200nF
and 50I in series to AVDD, and set the reverse control-channel amplitude to 100mV.
Coax
I2S encoding
If supported in the deserializer, disable I2S in the deserializer.
Table 13. Double-Function Configuration
GPIO1/BWS
FUNCTION
LCCEN
MS/HVEN FUNCTION
RX/SDA/EDC FUNCTION
TX/SCL/DBL FUNCTION
MS input
(low = base mode
high = bypass mode)
High
Functions as GPIO
UART/I2C input/output
UART/I2C input/output
HVEN input
EDC input
BWS input
(low = 24-bit mode,
high = 32-bit mode)
DBL input
(low = single input,
high = double input)
(low = HS/VS encoding
disabled, high = HS/VS
encoding enabled)
(low = error detection/correction
disabled, high = error detection/
correction enabled
Low
38
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Internal Input Pulldowns
Selection of AC-Coupling Capacitors
Voltage droop and the digital sum variation (DSV) of trans-
mitted symbols cause signal transitions to start from dif-
ferent voltage levels. Because the transition time is fixed,
starting the signal transition from different voltage levels
causes timing jitter. The time constant for an AC-coupled
link needs to be chosen to reduce droop and jitter to an
acceptable level. The RC network for an AC-coupled link
consists of the CML/coax receiver termination resistor
(RTR), the CML/coax driver termination resistor (RTD),
and the series AC-coupling capacitors (C). The RC time
constant for four equal-value series capacitors is (C x
(RTD + RTR))/4. RTD and RTR are required to match the
transmission line impedance (usually 100I differential,
50I single-ended). This leaves the capacitor selection
to change the system time constant. Use 0.2FF or larger
high-frequency surface-mount ceramic capacitors, with
sufficient voltage rating to withstand a short to battery, to
pass the lower speed reverse control-channel signal. Use
capacitors with a case size less than 3.2mm x 1.6mm to
have lower parasitic effects to the high-speed signal.
The control and configuration inputs (except three-level
inputs) include a pulldown resistor to GND. External pull-
down resistors are not needed.
Choosing I2C/UART Pullup Resistors
The I2C and UART open-drain lines require a pullup
resistor to provide a logic-high level. There are tradeoffs
between power dissipation and speed, and a compro-
mise may be required when choosing pullup resistor
values. Every device connected to the bus introduces
some capacitance even when the device is not in opera-
tion. I2C specifies 300ns rise times (30% to 70%) for fast
mode, which is defined for data rates up to 400kbps (see
the I2C specifications in the AC Electrical Characteristics
table for details). To meet the fast-mode rise-time require-
ment, choose the pullup resistors so that rise time tR
=
0.85 x RPULLUP x CBUS < 300ns. The waveforms are not
recognized if the transition time becomes too slow. The
serializer supports I2C/UART rates up to 1Mbps (UART-
to-I2C mode) and 400kbps (I2C-to-I2C mode).
AC-Coupling
AC-coupling isolates the receiver from DC voltages up to
the voltage rating of the capacitor. Capacitors at the seri-
alizer output and at the deserializer input are needed for
proper link operation and to provide protection if either
end of the cable is shorted to a battery. AC-coupling
blocks low-frequency ground shifts and low-frequency
common-mode noise.
Power-Supply Circuits and Bypassing
The serializer uses an AVDD and DVDD of 1.7V to 1.9V.
All inputs and outputs, except for the serial output, derive
power from an IOVDD of 1.7V to 3.6V that scales with
IOVDD. Proper voltage-supply bypassing is essential for
high-frequency circuit stability.
Power-Supply Table
Power-supply currents shown in the Electrical
Characteristics table are the sum of the currents from
AVDD, DVDD, and IOVDD. Typical currents from the
individual power supplies are shown in Table 14.
Table 14. Typical Power-Supply Currents
(Using Worst-Case Input Pattern)
Cables and Connectors
Interconnect for CML typically has a differential imped-
ance of 100I. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Coax cables typically have a characteris-
tic impedance of 50I contact the factory for 75I opera-
tion). Table 15 lists the suggested cables and connectors
used in the GMSL link.
PCLK
(MHz)
AVDD
(mA)
DVDD
(mA)
IOVDD
(mA)
25
50
36.8
42.1
9.0
0.32
0.34
13.7
Table 15. Suggested Connectors and Cables for GMSL
SUPPLIER
Rosenberger
CONNECTOR
59S2AX-400A5-Y
MX38-FF
CABLE
RG174
TYPE
Coax
STP
JAE
A-BW-Lxxxxx
F-2WME AWG28
Dacar 538
Nissei
GT11L-2S
STP
Rosenberger
D4S10A-40ML5-Z
STP
39
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
do not have 100I differential impedance when brought
close together—the impedance goes down when the
traces are brought closer. Use a 50Itrace for the single-
ended output when driving coax.
Board Layout
Separate the LVCMOS logic signals and CML/coax high-
speed signals to prevent crosstalk. Use a four-layer PCB
with separate layers for power, ground, CML/coax, and
LVCMOS logic signals. Layout PCB traces close to each
other for a 100I differential characteristic impedance.
The trace dimensions depend on the type of trace used
(microstrip or stripline). Note that two 50I PCB traces
Route the PCB traces for differential CML in parallel to
maintain the differential characteristic impedance. Avoid
vias. Keep PCB traces that make up a differential pair
equal in length to avoid skew within the differential pair.
ESD Protection
ESD tolerance is rated for Human Body Model, IEC
61000-4-2, and ISO 10605. The ISO 10605 and IEC
61000-4-2 standards specify ESD tolerance for electronic
systems. The serial outputs are rated for ISO 10605 ESD
protection and IEC 61000-4-2 ESD protection. All pins
are tested for the Human Body Model. The Human Body
Model discharge components are CS = 100pF and RD =
1.5kI(Figure 34). The IEC 61000-4-2 discharge compo-
nents are CS = 150pF and RD = 330I (Figure 35). The
ISO 10605 discharge components are CS = 330pF and
RD = 2kI (Figure 36).
R
D
1MI
1.5kI
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
100pF
S
STORAGE
CAPACITOR
SOURCE
Figure 34. Human Body Model ESD Test Circuit
R
R
D
D
330I
2kI
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
C
S
C
S
330pF
STORAGE
CAPACITOR
STORAGE
CAPACITOR
150pF
SOURCE
SOURCE
Figure 35. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Figure 36. ISO 10605 Contact Discharge ESD Test Circuit
40
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Table 16. Register Table (see Table 1)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
D[7:1]
D0
NAME
SERID
VALUE
FUNCTION
Serializer device address.
XXXXXXX
0
1000000
0x00
0x01
Normal operation.
CFGBLOCK
0
1
Registers 0x00 to 0x1F are read only.
Deserializer device address.
Reserved.
D[7:1]
D0
DESID
—
XXXXXXX
0
1001000
0
000
001
010
011
100
101
110
111
1
No spread spectrum.
0.5% spread spectrum.
1.5% spread spectrum.
2% spread spectrum.
D[7:5]
SS
000
No spread spectrum.
1% spread spectrum.
3% spread spectrum.
4% spread spectrum.
0x02
D4
—
Reserved.
1
00
12.5MHz to 25MHz pixel clock.
25MHz to 50MHz pixel clock.
Automatically detect the pixel clock range.
Automatically detect the pixel clock range.
0.5 to 1Gbps serial-bit rate.
1 to 2Gps serial-bit rate.
Automatically detect serial-bit rate.
Automatically detect serial-bit rate.
01
D[3:2]
PRNG
11
10
11
00
01
D[1:0]
SRNG
11
10
11
Calibrate spread-modulation rate only once
after locking.
00
01
10
Calibrate spread-modulation rate every 2ms
after locking.
D[7:6]
D[5:0]
AUTOFM
00
Calibrate spread-modulation rate every 16ms
after locking.
0x03
Calibrate spread-modulation rate every 256ms
after locking.
11
000000
XXXXXX
Autocalibrate sawtooth divider.
SDIV
000000
Manual SDIV setting. See the Manual Programming
of the Spread-Spectrum Divider section.
41
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Table 16. Register Table (see Table 1) (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
Disable serial link. Reverse control-channel
communication remains unavailable for 350Fs after
the serializer starts/stops the serial link.
0
D7
SEREN
1
Enable serial link. Reverse control-channel
communication remains unavailable for 350Fs after
the serializer starts/stops the serial link.
1
0
Disable configuration link.
D6
D5
D4
CLINKEN
PRBSEN
SLEEP
0
0
0
1
Enable configuration link.
0
1
Disable PRBS test.
Enable PRBS test.
0
Normal mode.
1
Activate sleep mode.
0x04
00
01
10, 11
Local control channel uses I2C when I2CSEL = 0.
Local control channel uses UART when I2CSEL = 0.
Local control channel disabled.
D[3:2]
D1
INTTYPE
01
1
Disable reverse control channel from deserializer
(receiving).
0
1
0
1
0
1
REVCCEN
Enable reverse control channel from deserializer
(receiving).
Disable forward control channel to deserializer
(sending).
D0
FWDCCEN
1
Enable forward control channel to deserializer
(sending).
I2C conversion sends the register address when
converting UART to I2C.
D7
D6
I2CMETHOD
ENJITFILT
PRBSLEN
0
0
Disable sending of I2C register address when
converting UART to I2C (command-byte-only mode).
0
Jitter filter disabled.
Jitter filter active.
1
00
01
10
11
00
0
Continuous PRBS length.
9.83Mbit PRBS length.
167.1Mbit PRBS length.
1341.5Mbit PRBS length.
Reserved.
D[5:4]
00
0x05
D[3:2]
D1
—
00
0
Disable wake-up receiver.
ENWAKEN
Enable OUT- wake-up receiver during
sleep mode.
1
0
1
Disable wake-up receiver.
D0
ENWAKEP
1
Enable OUT- wake-up receiver during
sleep mode.
42
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Table 16. Register Table (see Table 1) (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
0000
0001
0010
0011
0100
0101
0110
0111
Do not use.
Do not use.
100mV output level.
150mV output level.
200mV output level.
250mV output level.
300mV output level.
350mV output level.
400mV output level. Power-up default when
twisted-pair output is selected (Table 9).
D[7:4]
CMLLVL
1000
1001
1010
1000, 1010
450mV output level.
500mV output level. Power-up default when coax
output is selected (Table 9).
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Do not use.
Do not use.
Do not use.
Do not use.
0x06
Do not use.
Preemphasis off.
-1.2dB preemphasis.
-2.5dB preemphasis.
-4.1dB preemphasis.
-6.0dB preemphasis.
Do not use.
Do not use.
Do not use.
D[3:0]
PREEMP
0000
1.1dB preemphasis.
2.2dB preemphasis.
3.3dB preemphasis.
4.4dB preemphasis.
6.0dB preemphasis.
8.0dB preemphasis.
10.5dB preemphasis.
14.0dB preemphasis.
43
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Table 16. Register Table (see Table 1) (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
Single-input mode. Power-up default when
LCCEN = high or TX/SCL/DBL = low.
0
1
D7
DBL
0, 1
0
Double-input mode. Power-up default when
LCCEN = low and TX/SCL/DBL = high.
0
1
High data-rate mode.
Low data-rate mode.
D6
DRS
24-bit mode. Power-up default when
LCCEN = high or GPIO1/BWS = low.
0
1
D5
BWS
0, 1
32-bit mode. Power-up default when
LCCEN = low and GPIO1/BWS = high.
Input data latched on rising edge of PCLKIN.
Power-up default determined by CONF1 and
CONF0 (Table 9). Do not change this value while the
0
1
pixel clock is runnin
g.
D4
ES
0, 1
Input data latched on falling edge of PCLKIN.
Power-up default determined by CONF1 and
CONF0 (Table 9). Do not change this value while the
pixel clock is running.
0x07
D3
D2
—
0
Reserved.
0
HS/VS encoding disabled. Power-up default when
LCCEN = high or MS/HVEN = low.
0
HVEN
0, 1
HS/VS encoding enabled. Power-up default when
LCCEN = low and MS/HVEN = high.
1
1-bit parity error detection (GMSL compatible).
Power-up default when LCCEN = high or
RX/SDA/EDC = low.
00
01
6-bit CRC error detection.
D[1:0]
EDC
00, 10
6-bit hamming code (single-bit error correct,
double-bit error detect) and 16 word interleaving.
Power-up default when LCCEN = low and
RX/SDA/EDC = high.
10
11
0
Do not use.
No VS or DIN0 inversion.
Invert VS when HVEN = 1.
D7
INVVS
0
Invert DIN0 when HVEN = 0.
Do not use if DBL = 0 in the serializer and
DBL = 1 in the deserializer.
1
0x08
0
1
No HS or DIN1 inversion.
Invert HS when HVEN = 1.
D6
INVHS
—
0
Invert DIN1 when HVEN = 0.
Do not use if DBL = 0 in the serializer and
DBL = 1 in the deserializer.
D[5:0]
000000
Reserved.
000000
44
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Table 16. Register Table (see Table 1) (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
D[7:1]
D0
I2CSRCA
—
XXXXXXX
I2C address translator source A.
Reserved.
I2C address translator destination A.
0000000
0x09
0x0A
0x0B
0x0C
0
0
D[7:1]
D0
I2CDSTA
—
XXXXXXX
0000000
0
Reserved.
I2C address translator source B.
Reserved.
0
D[7:1]
D0
I2CSRCB
—
XXXXXXX
0000000
0
XXXXXXX
0
0
0000000
0
D[7:1]
D0
I2CDSTB
—
I2C address translator destination B.
Reserved.
Acknowledge not generated when forward channel
is not available.
0
1
D7
I2CLOCACK
I2CSLVSH
1
I2C-to-I2C slave generates local acknowledge when
forward channel is not available.
352ns/117ns I2C setup/hold time.
469ns/234ns I2C setup/hold time.
938ns/352ns I2C setup/hold time.
00
01
D[6:5]
01
10
11
1046ns/469ns I2C setup/hold time.
000
001
010
011
100
101
110
111
00
8.47kbps (typ) I2C-to-I2C master bit-rate setting.
28.3kbps (typ) I2C-to-I2C master bit-rate setting.
84.7kbps (typ) I2C-to-I2C master bit-rate setting.
105kbps (typ) I2C-to-I2C master bit-rate setting.
173kbps (typ) I2C-to-I2C master bit-rate setting.
339kbps (typ) I2C-to-I2C master bit-rate setting.
533kbps (typ) I2C-to-I2C master bit-rate setting.
837kbps (typ) I2C-to-I2C master bit-rate setting.
64Fs (typ) I2C-to-I2C slave remote timeout.
256Fs (typ) I2C-to-I2C slave remote timeout.
1024Fs (typ) I2C-to-I2C slave remote timeout.
No I2C-to-I2C slave remote timeout.
0x0D
D[4:2]
D[1:0]
I2CMSTBT
I2CSLVTO
101
01
10
10
11
45
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Table 16. Register Table (see Table 1) (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
D7
D6
D5
D4
D3
D2
D1
NAME
VALUE
FUNCTION
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
11
0
1
0
1
0
1
0
1
0
1
0
1
00
0
1
0
1
0
1
0
1
0
1
0
1
OUT+ reverse channel receiver enabled.
OUT+ reverse channel receiver disabled.
OUT- reverse channel receiver enabled.
OUT- reverse channel receiver disabled.
Disable GPIO5.
DIS_REV_P
DIS_REV_N
GPIO5EN
GPIO4EN
GPIO3EN
GPIO2EN
GPIO1EN
0
1
0
0
0
0
1
Enable GPIO5.
Disable GPIO4.
0x0E
Enable GPIO4.
Disable GPIO3.
Enable GPIO3.
Disable GPIO2.
Enable GPIO2.
Disable GPIO1.
Enable GPIO1.
D0
—
—
Reserved.
0
D[7:6]
Reserved.
11
Set GPIO5 low.
D5
D4
D3
D2
D1
GPIO5OUT
GPIO4OUT
GPIO3OUT
GPIO2OUT
GPIO1OUT
1
1
1
1
1
Set GPIO5 high.
Set GPIO4 low.
Set GPIO4 high.
Set GPIO3 low.
0x0F
Set GPIO3 high.
Set GPIO2 low.
Set GPIO2 high.
Set GPIO1 low.
Set GPIO1 high.
Set GPO low.
D0
D[7:6]
D5
SETGPO
—
0
Set GPO high.
Reserved.
00
GPIO5 is low
1
GPIO5IN
(read only)
GPIO5 is high.
GPIO4 is low.
1
D4
D3
D2
D1
D0
GPIO4IN
GPIO3IN
GPIO2IN
GPIO1IN
GPO_L
(read only)
GPIO4 is high.
GPIO3 is low.
1
(read only)
0x10
GPIO3 is high.
GPIO2 is low.
1
(read only)
GPIO2 is high.
GPIO1 is low.
1
(read only)
GPIO1 is high.
GPO is set low.
0
(read only)
GPO is set high.
46
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Table 16. Register Table (see Table 1) (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
00
Generate an error every 2560 bits.
Generate an error every 40,960 bits.
Generate an error every 655,360 bits.
Generate an error every 10,485,760 bits.
Generate single-bit errors.
Generate 2 (8b/10b) symbol errors.
Generate 3 (8b/10b) symbol errors.
Generate 4 (8b/10b) symbol errors.
Continuously generate errors.
16 generated errors.
01
D[7:6]
ERRGRATE
00
00
00
10
11
00
01
D[5:4]
D[3:2]
ERRGTYPE
ERRGCNT
10
11
0x11
00
01
10
128 generated errors.
11
1024 generated errors.
0
Disable periodic error generation.
Enable periodic error generation.
Disable error generator.
D1
D0
ERRGPER
ERRGEN
0
0
1
0
1
Enable error generator.
0x12
0x13
D[7:0]
D[7:0]
—
—
01000000
00100010
Reserved.
01000000
00100010
Reserved.
00000000
(read only)
0x14
D[7:0]
D7
—
XXXXXXXX Reserved.
0
1
CXTP is low.
0
CXTP
I2CSEL
(read only)
CXTP is high.
0
Input is high.
0
D6
(read only)
1
Input is low.
0
Input is high.
0
D5
D[4:2]
D1
LCCEN
—
(read only)
0x15
1
Input is low.
000
0
Reserved.
000 (read only)
Output disabled.
Output enabled.
Valid PCLKIN detected.
Valid PCLKIN not detected.
0
OUTPUTEN
(read only)
1
0
0
D0
PCLKDET
(read only)
1
00000000
(read only)
0x16
0x17
0x1E
D[7:0]
D[7:0]
D[7:0]
D[7:5]
—
—
ID
—
XXXXXXXX Reserved.
XXXXXXXX Reserved.
00000000
(read only)
00001001
(read only)
00001001
000
Device identifier (MAX9271 = 0x09).
000
(read only)
Reserved.
0
1
Not HDCP capable.
HDCP capable.
Device revision.
0x1F
0
D4
CAPS
(read only)
D[3:0]
REVISION
XXXX
(read only)
47
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Typical Application Circuit
CAMERA APPLICATION
PCLK
RGBHV
SHDN
PCLKIN
DIN0–DIN15
GPO
PCLKOUT
PCLK
DOUT0–DOUT15
RGBHV
CONF1
CONF0
CAMERA
GPU
MAX9271
MAX9272
RX/SDA/EDC
TX/SCL/ES
TX
RX
UART
TO PERIPHERALS
GPI
LOCK
RX/SDA/EDC
TX/SCL/DBL
LCCEN
OUT+
OUT-
IN+
IN-
CX/TP
ECU
NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS.
Ordering Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PART
TEMP RANGE
PIN-PACKAGE
MAX9271GTJ/V+
-40NC to +105NC
32 TQFN-EP*
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
Chip Information
32 TQFN-EP
T3255+5
21-0140
90-0013
PROCESS: CMOS
48
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
7/12
Initial release
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
49
©
2012 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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