MAX9280GTN/V+ [MAXIM]
3.12Gbps GMSL Deserializers for Coax or STP Input and Parallel Output;
| 型号： | MAX9280GTN/V+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 3.12Gbps GMSL Deserializers for Coax or STP Input and Parallel Output |
| 文件： | 总70页 (文件大小：2183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
General Description
Benefits and Features
● Ideal for High-Definition Video Applications
• Works with Low-Cost 50Ω Coax Cable and FAKRA
Connectors or 100Ω STP
The MAX9276/MAX9280 gigabit multimedia serial link
(GMSL) deserializers receive data from a GMSL serializer
over 50Ω coax or 100Ω shielded twisted pair (STP) cable
and output deserialized data on the LVCMOS outputs.
• 104MHz High-Bandwidth Mode Supports
1920x720p/60Hz Display With 24-Bit Color
• Equalization Allows 15m Cable at Full Speed
• Up to 192kHz Sample Rate And 32-Bit Sample
Depth For 7.1 Channel HD Audio
• Audio Clock from Audio Source or Audio Sink
• Color Lookup-Table for Gamma Correction
• CNTL[3:0] Control Outputs
The MAX9280 has HDCP content protection but other-
wise is the same as the MAX9276. The deserializers pair
with any GMSL serializer capable of coax output including
the MAX9293 HDMI/MHL serializer. When programmed
for STP input they are backward compatible with any
GMSL serializer.
2
The audio channel supports L-PCM I S stereo and up to
● Multiple Data Rates for System Flexibility
• Up to 3.12Gbps Serial-Bit Rate
eight channels of L-PCM in TDM mode. Sample rates of
32kHz to 192kHz are supported with sample depth up to
32 bits.
• 6.25MHz to 104MHz Pixel Clock
• 9.6kbps to 1Mbps Control Channel in UART, Mixed
The embedded control channel operates at 9.6kbps to
2
2
UART/I C, or I C Mode with Clock Stretch
Capability
2
1Mbps in UART-UART and UART-I C modes, and up to
2
2
1Mbps in I C-I C mode. Using the control channel, a µC
can program serializer, deserializer, and peripheral device
registers at any time, independent of video timing, and
manage HDCP operation (MAX9280). Two GPIO ports
are included, allowing display power-up and switching of
the backlight among other uses. A continuously-sampled
GPI input supports touch-screen controller interrupt
requests in display applications.
● Reduces EMI and Shielding Requirements
• Programmable Spread Spectrum Reduces EMI
• Tracks Spread Spectrum on Input
• High-Immunity Mode for Maximum Control-
Channel Noise Rejection
● Peripheral Features for System Power-Up and
Verification
• Built-In PRBS Tester for BER Testing of the Serial
Link
• Programmable Choice of 8 Default Device
Addresses
• Two Dedicated GPIO Ports
• Dedicated “Up/Down” GPI for Touch-Screen
Interrupt and Other Uses
For use with longer cables, the deserializers have a pro-
grammable cable equalizer. Programmable spread spec-
trum is available on the parallel output. The serial input
meets ISO 10605 and IEC 61000-4-2 ESD standards.
The core supply is 3.0V to 3.6V and the I/O supply is
1.7V to 3.6V.
The devices are in lead-free, 56-lead, 8mm x 8mm TQFN
and QFND packages with exposed pad and 0.5mm lead
pitch.
• Remote/Local Wake-Up from Sleep Mode
● Meets Rigorous Automotive and Industrial
Requirements
• -40°C to +105°C Operating Temperature
• ±8kV Contact and 15kV Air ISO 10605 and
IEC 61000-4-2 ESD Protection
Applications
● High-Resolution Automotive Navigation
● Rear-Seat Infotainment
● Megapixel Camera Systems
Ordering Information appears at end of data sheet.
VIDEO/AUDIO
VIDEO/AUDIO
GMSL
SERIALIZER
720p
DISPLAY
MAX9276
MAX9280
µC
2
2
I C
I C
19-6623; Rev 1; 11/15
MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Output Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Serial Link Signaling and Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
High-Bandwidth Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Audio Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Audio Channel Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Audio Channel Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Additional MCLK Output for Audio Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Audio Output Timing Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Reverse Control Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Control Channel and Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2
Interfacing Command-Byte-Only I C Devices with UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
UART Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2
I C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Bus Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Format for Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Format for Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2
I C Communication with Remote Side Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2
I C Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
GPO/GPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Line Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Maxim Integrated
│ 2
www.maximintegrated.com
MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
TABLE OF CONTENTS (continued)
Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Manual Programming of the Spread-Spectrum Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
HS/VS/DE Tracking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Serial Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Coax Splitter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Cable Type Configuration Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Color Lookup Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Programming and Verifying LUT Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
LUT Color Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
LUT Bit Width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Recommended LUT Program Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
High-Immunity Reverse Control Channel Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Configuration Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Link Startup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
High-Bandwidth Digital Content Protection (HDCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Encryption Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Synchronization of Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Repeater Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
HDCP Authentication Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
HDCP Protocol Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Example Repeater Network—Two µCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Detection and Action Upon New Device Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Notification of Start of Authentication and Enable of Encryption to Downstream Links . . . . . . . . . . . . . . . . . . . . . 55
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Self PRBS Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Error Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
ERR Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Auto Error Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Dual µC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Changing the Clock Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Fast Detection of Loss of Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Providing a Frame Sync (Camera Applications). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Software Programming of the Device Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3-Level Configuration Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Configuration Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Maxim Integrated
│ 3
www.maximintegrated.com
MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
TABLE OF CONTENTS (continued)
Compatibility with Other GMSL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Key Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
HS/VS/DE Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
WS/SCK Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Staggered Parallel Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Internal Input Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2
Choosing I C/UART Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
AC-Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Selection of AC-Coupling Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Power-Supply Circuits and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Power-Supply Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Cables and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Board Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Chip Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Maxim Integrated
│ 4
www.maximintegrated.com
MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
LIST OF FIGURES
Figure 1. Reverse Control Channel Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 2a. Test Circuit for Single-Ended Input Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 2. Test Circuit for Differential Input Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3. Worst-Case Pattern Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 4. I2C Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 5. Parallel Clock Output Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 6. Output Rise-and-Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 7. Deserializer Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. GPI-to-GPO Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10. Power-Up Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. Output I2S Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. 24-Bit Mode Serial Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. 32-Bit Mode Serial Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. High-Bandwidth Mode Serial Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Audio Channel Input Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. 8-Channel TDM (24-Bit Samples, Padded With Zeros) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17. 6-Channel TDM (24-Bit Samples, No Padding) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 18. Stereo I2S (24-Bit Samples, Padded With Zeros) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 19. Stereo I2S (16-Bit Samples, No Padding). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 20. Audio Channel Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 21. GMSL UART Protocol for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 22. GMSL UART Data Format for Base Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 23. Sync Byte (0x79). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 24. ACK Byte (0xC3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 25. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0) . . . . . . . . 34
2
Figure 26. Format Conversion Between GMSL UART and I C with Register Address (I2CMETHOD = 1). . . . . . . . 35
Figure 27. START and STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 28. Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 29. Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 30. Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 31. Format for I2C Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 32. Format for Write to Multiple Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 33. Format for I2C Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 34. 2:1 Coax Splitter Connection Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 35. Coax Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 36. LUT Dataflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 37. State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Maxim Integrated
│ 5
www.maximintegrated.com
MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
LIST OF FIGURES (continued)
Figure 38. Example Network with One Repeater and Two µCs (Tx = GMSL Serializer’s, Rx = Deserializer’s). . . . . 52
Figure 39. Human Body Model ESD Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 40. IEC 61000-4-2 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 41. ISO 10605 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
LIST OF TABLES
Table 1. Device Address Defaults (Register 0x00, 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 2. Output Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 3. Data-Rate Selection Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 4. Maximum Audio WS Frequency (kHz) for Various PCLKOUT Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 5. f
Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SRC
2
Table 6. I C Bit Rate Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 7. Cable Equalizer Boost Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 8. Output Spread . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 9. Modulation Coefficients and Maximum SDIV Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 10. Configuration Input Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 11. Pixel Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 12. Reverse Control Channel Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 13. Fast High-Immunity Mode Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 14. Startup Procedure for Video-Display Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 15. Startup Procedure for Image-Sensing Applications (CDS = High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 16. Startup, HDCP Authentication, and Normal Operation (Deserializer is Not a Repeater)—First Part of the
HDCP Authentication Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 17. Link Integrity Check (Normal)—Performed Every 128 Frames After Encryption is Enabled . . . . . . . . . . . 50
Table 18. Optional Enhanced Link Integrity Check—Performed Every 16 Frames After Encryption is Enabled . . . . 51
Table 19. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First and Second Parts of the
HDCP Authentication Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 20. MAX9276/MAX9280 Feature Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 21. Staggered Output Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 22. IOVDD Current Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 23. Additional Supply Current from HDCP (MAX9280 Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 24. Suggested Connectors and Cables for GMSL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 25. Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 26. HDCP Register Table (MAX9280 Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Maxim Integrated
│ 6
www.maximintegrated.com
MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
(Note 1)
Absolute Maximum Ratings
AVDD to EP..........................................................-0.5V to +3.9V
DVDD to EP .........................................................-0.5V to +3.9V
IOVDD to EP........................................................-0.5V to +3.9V
IN+, IN- to EP.......................................................-0.5V to +1.9V
Continuous Power Dissipation (T = +70°C)
A
TQFN (derate 47.6mW/°C above +70°C)...............3809.5mW
QFND (derate 42.7mW/°C above +70°C) .................3418mW
Junction Temperature......................................................+150°C
Storage Temperature........................................ -65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
All Other Pins to EP ............................-0.5V to (V
+ 0.5V)
IOVDD
IN+, IN- Short Circuit to Ground or Supply ...............Continuous
Note 1: EP connected to PCB ground.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Note 2)
Package Thermal Characteristics
TQFN
QFND
Junction-to-Case Thermal Resistance (θ )...............1.6°C/W
Junction-to-Case Thermal Resistance (θ ).................1°C/W
JC
JC
Junction-to-Ambient Thermal Resistance (θ ) ..........21°C/W
Junction-to-Ambient Thermal Resistance (θ ) .......23.4°C/W
JA
JA
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
DC Electrical Characteristics
(V
= V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground (GND), T = -40°C
AVDD
DVDD
IOVDD L A
to +105°C, unless otherwise noted. Typical values are at V
= V
= V
= 3.3V, T = +25°C.)(Note 3)
AVDD
DVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (ADD_, HIM, I2CSEL, GPI, PWDN, MS)
0.65 x
High-Level Input Voltage
V
V
IH1
V
IOVDD
0.35 x
Low-Level Input Voltage
Input Current
V
V
IL1
V
IOVDD
+20
I
V
= 0V to V
IOVDD
-10
µA
IN1
IN
THREE-LEVEL LOGIC INPUTS (BWS, CX/TP)
0.7 x
High-Level Input Voltage
Low-Level Input Voltage
V
V
V
IH
V
IOVDD
0.3 x
IOVDD
10
V
IL
V
Mid-Level Input Current
Input Current
I
(Note 4)
-10
µA
µA
INM
I
-150
150
IN
SINGLE-ENDED OUTPUTS (WS, SCK, SD, DOUT_, CNTL_, INTOUT, PCLKOUT)
V
V
IOVDD
- 0.3
DCS = ‘0’
High-Level Output Voltage
Low-Level Output Voltage
V
I
= -2mA
= 2mA
V
V
OH1
OUT
OUT
IOVDD
- 0.2
DCS = ‘1’
DCS = ‘0’
DCS = ‘1’
0.3
0.2
V
I
OL1
Maxim Integrated
│ 7
www.maximintegrated.com
MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
DC Electrical Characteristics (continued)
(V
= V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground (GND), T = -40°C
AVDD
DVDD
IOVDD L A
to +105°C, unless otherwise noted. Typical values are at V
= V
= V
= 3.3V, T = +25°C.) (Note 3)
AVDD
DVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
=
IOVDD
15
25
39
3.0V to 3.6V
V
= 0V,
O
DCS = ‘0’
V
=
IOVDD
3
20
5
7
13
63
21
50
17
97
32
1.7V to 1.9V
DOUT_
V
=
IOVDD
35
10
33
10
54
16
3.0V to 3.6V
V
= 0V,
O
DCS = ‘1’
V
=
IOVDD
1.7V to 1.9V
OUTPUT Short-Circuit Current
I
mA
OS
V
=
IOVDD
15
5
3.0V to 3.6V
V
= 0V,
O
DCS = ‘0’
V
=
IOVDD
1.7V to 1.9V
PCLKOUT
V
=
IOVDD
30
9
3.0V to 3.6V
V
= 0V,
O
DCS = ‘1’
V
=
IOVDD
1.7V to 1.9V
OPEN-DRAIN INPUT/OUTPUT (GPIO0, GPIO1, RX/SDA, TX/SCL, ERR, LOCK)
0.7 x
High-Level Input Voltage
Low-Level Input Voltage
V
V
V
IH2
V
IOVDD
0.3 x
V
IL2
V
IOVDD
+5
RX/SDA, TX/SCL
-100
Input Current
I
(Note 5)
µA
IN2
LOCK, ERR, GPIO_
-80
+5
0.4
0.3
10
V
= 1.7V to 1.9V
= 3.0V to 3.6V
IOVDD
IOVDD
Low-Level Output Voltage
Input Capacitance
V
I
= 3mA
V
OL2
OUT
V
C
Each pin (Note 6)
pF
IN
OUTPUT FOR REVERSE CONTROL CHANNEL (IN+, IN-)
Legacy reverse control
Forward channel
disabled,
Figure 1
30
50
60
Differential High Output Peak
Voltage (V +) - (V -)
channel mo
V
mV
mV
de
RODH
IN
IN
High immunity mode
100
Legacy reverse control
channel mode
Forward channel
disabled,
Figure 1
-60
-30
Differential Low Output Peak
Voltage (V +) - (V -)
V
RODL
ROSH
IN
IN
High immunity mode
-100
30
-50
60
Legacy reverse control
channel mode
Single-Ended High Output Peak
Voltage
Forward channel
disabled
V
mV
mV
High immunity mode
50
100
-30
-50
Legacy reverse control
channel mode
-60
-100
Single-Ended Low Output Peak
Voltage
Forward channel
disabled
V
ROSL
High immunity mode
Maxim Integrated
│ 8
www.maximintegrated.com
MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
DC Electrical Characteristics (continued)
(V
= V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground (GND), T = -40°C
AVDD
DVDD
IOVDD L A
to +105°C, unless otherwise noted. Typical values are at V
= V
= V
= 3.3V, T = +25°C.) (Note 3)
AVDD
DVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIFFERENTIAL INPUTS (IN+, IN-)
Activity detector medium
Threshold, (0x0B D[6:5] = 01)
60
Differential High Input Threshold
V
Figure 2
Figure 2
mV
mV
IDH(P)
(Peak) Voltage (V +) - (V -)
IN
IN
Activity detector low
Threshold, (0x0B D[6:5] = 00)
47.5
Activity detector medium
Threshold, (0x0B D[6:5] = 01)
-60
-47.5
1
Differential Low Input Threshold
(Peak) Voltage (V +) - (V -)
V
IDL(P)
IN
IN
Activity detector medium
Threshold, (0x0B D[6:5] = 00)
Input Common-Mode Voltage
((V +) + (V -))/2
V
1.3
1.6
V
CMR
IN
IN
Differential Input Resistance
(Internal)
R
80
100
130
Ω
IN
SINGLE-ENDED INPUTS (IN+, IN-)
Activity detector medium
threshold, (0x0B D[6:5] = 01)
43
Single-Ended High Input
Threshold (Peak) Voltage
V
Figure 2a
Figure 2a
mV
ISH(P)
Activity detector low threshold,
(0x0B D[6:5] = 00)
33
Activity detector medium
threshold, (0x0B D[6:5] = 01)
-43
Single-Ended Low Input
Threshold (Peak) Voltage
V
mV
Ω
ISL(P)
Activity detector medium
threshold, (0x0B D[6:5] = 00)
-33
Input Resistance (Internal)
R
40
50
65
I
POWER SUPPLY
C = 5pF
131
136
164
169
2% spread
active
L
C = 10pF
BWS = low,
L
f
=
PCLKOUT
Spread
C = 5pF
122
127
153
158
L
16.6MHz
spectrum
disabled
C = 10pF
L
C = 5pF
144
153
179
189
2% spread
active
L
Total Supply Current (AVDD
+ DVDD + IOVDD) (Note 7)
(Worst-Case-Pattern, Figure 3)
BWS = low,
C = 10pF
L
I
mA
f
=
WCS
PCLKOUT
Spread
C = 5pF
133
142
167
177
L
33.3MHz
spectrum
disabled
C = 10pF
L
C = 5pF
175
190
159
216
233
197
2% spread
active
L
BWS = low,
C = 10pF
L
f
=
PCLKOUT
Spread
C = 5pF
L
66.6MHz
spectrum
disabled
C = 10pF
174
214
L
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
DC Electrical Characteristics (continued)
(V
= V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground (GND), T = -40°C
AVDD
DVDD
IOVDD L A
to +105°C, unless otherwise noted. Typical values are at V
= V
= V
= 3.3V, T = +25°C.) (Note 3)
AVDD
DVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
C = 5pF
212
255
2% spread
L
active
BWS = low,
C = 10pF
234
190
278
228
L
f
=
PCLKOUT
Spread
C = 5pF
104MHz
L
spectrum
disabled
C = 10pF
212
251
L
C = 5pF
154
164
191
2% spread
active
L
Total Supply Current (AVDD
+ DVDD + IOVDD) (Note 7)
(Worst-Case-Pattern, Figure 3)
BWS = mid,
C = 10pF
203
L
I
mA
f
=
WCS
PCLKOUT
Spread
C = 5pF
143
154
177
189
L
36.6MHz
spectrum
disabled
C = 10pF
L
C = 5pF
231
277
305
2% spread
active
L
C = 10pF
257
L
BWS = mid,
f
=
PCLKOUT
Spread
C = 5pF
209
249
L
104MHz
spectrum
disabled
C = 10pF
234
277
L
Sleep Mode Supply Current
Power-Down Current
ESD PROTECTION
I
70
20
265
µA
µA
CCS
I
PWDN = GND
Human body model, R = 1.5kΩ,
195
CCZ
D
±8
C
= 100pF
S
Contact discharge
Air discharge
±10
±12
±10
±20
IEC 61000-4-2, R
=
D
IN+, IN- (Note 8)
V
V
kV
kV
ESD
330Ω, C = 150pF
S
Contact discharge
Air discharge
ISO 10605, R = 2kΩ,
D
C
S
= 330pF
Human body model, R = 1.5kΩ,
D
All Other Pins (Note 9)
±4
ESD
C
= 100pF
S
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
AC Electrical Characteristics
(V
= V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground (GND), T = -40°C
AVDD
DVDD
IOVDD L A
to +105°C, unless otherwise noted. Typical values are at V
= V
= V
= 3.3V, T = +25°C.) (Note 10)
AVDD
DVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PARALLEL CLOCK OUTPUT (PCLKOUT)
BWS = low, DRS = ‘1’
BWS = low, DRS = ‘0’
BWS = mid, DRS = ‘1’
BWS = mid, DRS = ‘0’
BWS = high, DRS = ‘1’
BWS = high, DRS = ‘0’
8.33
16.66
18.33
36.66
6.25
12.5
40
16.66
104
36.66
104
12.5
78
Clock Frequency
f
MHz
PCLKOUT
Clock Duty Cycle
Clock Jitter
DC
t
/t or t
/t (Note 6)
50
60
%
HIGH T
LOW T
Period jitter, peak-to-peak, spread off,
3.12Gbps, PRBS pattern, UI = 1/f
(Note 6)
t
0.05
UI
J
PCLKOUT
2
I C/UART PORT TIMING
2
I C/UART Bit Rate
9.6
1000
150
kbps
30% to 70%, C = 10pF to 100pF, 1kΩ
L
Output Rise Time
Output Fall Time
t
20
ns
R
pullup to V
IOVDD
70% to 30%, C = 10pF to 100pF, 1kΩ
L
t
20
150
ns
F
pullup to V
IOVDD
2
I C TIMING (Figure 4)
Low f
range:
SCL
9.6
100
400
(I2CMSTBT = 010, I2CSLVSH = 10)
Mid f range:
SCL
SCL Clock Frequency
f
> 100
> 400
kHz
µs
SCL
(I2CMSTBT 101, I2CSLVSH = 01)
High f range:
(I2CMSTBT = 111, I2CSLVSH = 00)
SCL
1000
Low
4.0
0.6
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
t
f
f
range
range
Mid
HD:STA
SCL
High
Low
Mid
0.26
4.7
1.3
V
= 1.7V to
IOVDD
t
0.6
0.5
µs
LOW
SCL
< 3V (Note 11)
High
V
= 3.0V to
IOVDD
3.6V
Low
Mid
4.0
0.6
t
f
f
range
range
µs
µs
HIGH
SCL
High
Low
Mid
0.26
4.7
Repeated START Condition
Setup Time
t
0.6
SU:STA
SCL
High
0.26
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
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AC Electrical Characteristics (continued)
(V
= V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground (GND), T = -40°C
AVDD
DVDD
IOVDD L A
to +105°C, unless otherwise noted. Typical values are at V
= V
= V
= 3.3V, T = +25°C.) (Note 10)
AVDD
DVDD
IOVDD A
PARAMETER
Data Hold Time
SYMBOL
CONDITIONS
Low
MIN
0
TYP
MAX
UNITS
t
f
f
f
f
range
Mid
0
µs
µs
µs
µs
HD:DAT
SCL
SCL
SCL
SCL
High
Low
0
250
100
50
Data Setup Time
t
range
range
range
Mid
SU:DAT
SU:STO
High
Low
4.0
0.6
0.26
4.7
1.3
0.5
Setup Time for STOP Condition
Bus Free Time
t
Mid
High
Low
t
Mid
BUF
High
Low
3.45
0.9
Mid
V
= 1.7V to
IOVDD
Data Valid Time
t
f
range
0.55
0.45
µs
µs
VD:DAT
SCL
< 3V (Note 12)
High
V
= 3.0V to
IOVDD
3.6V
Low
3.45
0.9
Mid
V
= 1.7V to
IOVDD
Data Valid Acknowledge Time
t
f
f
range
range
0.55
0.45
VD:ACK
SCL
< 3V (Note 13)
High
V
= 3.0V to
IOVDD
3.6V
Low
Mid
50
50
Pulse Width of Spikes
Suppressed
t
ns
SP
SCL
High
50
Capacitive Load Each Bus Line
C
100
pF
b
SWITCHING CHARACTERISTICS
20% to 80%,
= 1.7V to
1.9V (Note 6)
DCS = ‘1’, C = 10pF
0.4
0.5
0.25
0.3
0.5
0.6
0.3
0.4
2.2
2.8
1.8
2.0
3.1
3.8
2.2
2.4
L
V
IOVDD
DCS = ‘0’, C = 5pF
L
PCLKOUT Rise-and-Fall Time,
Figure 5
t , t
ns
ns
R
F
20% to 80%,
DCS = ‘1’, C = 10pF
L
V
= 3.0V to
IOVDD
DCS = ‘0’, C = 5pF
3.6V (Note 1)
L
20% to 80%,
DCS = ‘1’, C = 10pF
L
V
= 1.7V to
IOVDD
DCS = ‘0’, C = 5pF
1.9V (Note 1)
L
Parallel Data Rise-and-Fall Time,
Figure 6
t , t
R
F
20% to 80%,
DCS = ‘1’, C = 10pF
L
V
= 3.0V to
IOVDD
DCS = ‘0’, C = 5pF
3.6V (Note 6)
L
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
AC Electrical Characteristics (continued)
(V
= V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground (GND), T = -40°C
AVDD
DVDD
IOVDD L A
to +105°C, unless otherwise noted. Typical values are at V
= V
= V
= 3.3V, T = +25°C.) (Note 10)
AVDD
DVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
Spread spectrum
MIN
TYP
MAX
UNITS
6960
enabled
Deserializer Delay
t
(Note 14) Figure 7
Bits
SD
Spread spectrum
2160
400
400
350
3
disabled
Reverse Control Channel Output
Rise Time
No forward channel data transmission,
Figure 1
t
180
180
ns
ns
µs
R
Reverse Control Channel Output
Fall Time
No forward channel data transmission,
Figure 1
t
F
Deserializer GPI to serializer GPO (cable
delay not included), Figure 8
GPI to GPO Delay
t
GPIO
Spread spectrum
enabled
Figure 9
Lock Time
t
ms
ms
LOCK
Spread spectrum
disabled
2
8
Power-Up Time
t
Figure 10
PU
2
I S/TDM OUTPUT TIMING (Note 6)
f
= 48kHz or
1.2e-3 1.5e-3
x t x t
WS
t
= 1/f
,
44.1kHz
WS
WS
WS
WS
(cycle-to-cycle),
rising-to-falling
edge or falling-to-
rising edge
1.6e-3 2e-3 x
x t
WS Jitter
tj
f
= 96kHz
ns
ns
WS
WS
WS
t
WS
WS
1.6e-3 2e-3 x
x t
f
= 192kHz
t
WS
WS
n
f
= 16 bits,
SCK
13e-3 x 16e-3 x
= 48kHz or
SCK
t
t
SCK
SCK
t
= 1/f
,
44.1kHz
SCK
SCK
(cycle-to-cycle),
rising-to-rising
edge
2
SCK Jitter (2-Channel I S)
tj
SCK1
n
= 24 bits,
39e-3 x 48e-3 x
SCK
f
= 96kHz
t
t
SCK
WS
SCK
n
= 32 bits,
0.1 x
0.13 x
SCK
f
= 192kHz
t
t
SCK
WS
SCK
n
= 16 bits,
= 48kHz or
SCK
52e-3 x 64e-3 x
f
WS
t
t
SCK
SCK
44.1kHz
t
= 1/f
,
SCK
SCK
(cycle-to-cycle),
rising-to-rising
edge
n
= 24 bits,
= 96kHz
156e-3 192e-3
x t x t
SCK Jitter (8-Channel TDM)
tj
ns
SCK
SCK2
f
WS
SCK
SCK
n
= 32 bits,
0.4 x
0.52 x
SCK
f
= 192kHz
t
t
SCK
WS
SCK
Audio Skew Relative to Video
t
Video and audio synchronized
C = 10pF, DCS = 1
3 x t
4 x t
WS
µs
ASK
WS
0.3
0.4
3.1
3.8
L
SCK, SD, WS Rise-and-Fall Time
t , t
20% to 80%
ns
R
F
C = 5pF, DCS = 0
L
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
AC Electrical Characteristics (continued)
(V
= V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground (GND), T = -40°C
AVDD
DVDD
IOVDD L A
to +105°C, unless otherwise noted. Typical values are at V
= V
= V
= 3.3V, T = +25°C.) (Note 10)
AVDD
DVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SD, WS Valid Time Before SCK
(2-Channel I S)
0.20 x
0.5 x
t
SCK
t
t
t
t
t
= 1/f
= 1/f
= 1/f
= 1/f
, Figure 11
, Figure 11
, Figure 11
, Figure 11
ns
ns
ns
ns
DVB1
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
2
t
SCK
SD, WS Valid Time After SCK
0.20 x
0.5 x
t
SCK
t
DVA1
DVB2
2
(2-Channel I S)
t
SCK
SD, WS Valid Time Before SCK
(8-Channel TDM)
0.20 x
0.5 x
t
SCK
t
t
SCK
SD, WS Valid Time After SCK
(8-Channel TDM)
0.20 x
0.5 x
t
SCK
t
DVA2
t
SCK
Note 3: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed by design
A
and characterization, unless otherwise noted.
Note 4: To provide a mid level, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current
must be less than ±10µA.
Note 5:
I
MIN due to voltage drop across the internal pullup resistor.
IN
Note 6: Not production tested. Guaranteed by design.
Note 7: HDCP not enabled (MAX9280 only). IOVDD current is not production tested. See Table 23 for additional supply current
when HDCP is enabled
Note 8: Specified pin to ground.
Note 9: Specified pin to all supply/ground.
Note 10: Not production tested, guaranteed by bench characterization.
2
2
2
Note 11: The I C bus standard t
(min) = 0.5µs.
LOW
Note 12: The I C bus standard t
(max) = 0.45µs.
(max) = 0.45µs.
VD:DAT
VD:ACK
Note 13:.The I C bus standard t
Note 14: Measured in serial link bit times. Bit time = 1/(30 x f
) for BWS = ‘0’ or open. Bit time = 1/(40 x f
)
PCLKIN
PCLKIN
for BWS = ‘1’.
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
Typical Operating Characteristics
(V
= V
= V
= 3.3V, T = +25°C, unless otherwise noted.)
AVDD
DVDD
IOVDD
A
SUPPLY CURRENT
SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (BWS = 1)
vs. PCLKOUT FREQUENCY (BWS = 0)
190
180
170
160
150
140
200
PRBS ON, SS OFF,
COAX MODE
PRBS ON, SS OFF,
COAX MODE
190
180
170
EQ ON
EQ ON
160
150
140
EQ OFF
130
120
130
120
EQ OFF
5
20
35
50
65
80
5
15 25 35 45 55 65 75 85 95 105
PCLKOUT FREQUENCY (MHz)
PCLKOUT FREQUENCY (MHz)
SUPPLY CURRENT
SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (BWS = OPEN)
vs. PCLKOUT FREQUENCY (BWS = 0)
210
200
190
180
170
160
150
140
130
220
210
200
PRBS ON, SS OFF,
COAX MODE
PRBS ON, EQ ON,
COAX MODE
190
180
170
EQ ON
SS ON
160
150
140
130
120
EQ OFF
SS OFF
15
30
45
60
75
95
105
5
15 25 35 45 55 65 75 85 95 105
PCLKOUT FREQUENCY (MHz)
PCLKOUT FREQUENCY (MHz)
SUPPLY CURRENT
SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (BWS = 1)
vs. PCLKOUT FREQUENCY (BWS = OPEN)
210
200
190
180
170
160
150
140
130
240
230
220
PRBS ON, EQ ON,
COAX MODE
PRBS ON, EQ ON,
COAX MODE
210
200
190
SS ON
SS ON
180
170
160
150
140
SS OFF
SS OFF
5
20
35
50
65
80
15
30
45
60
75
90
105
PCLKOUT FREQUENCY (MHz)
PCLKOUT FREQUENCY (MHz)
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
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Typical Operating Characteristics (continued)
(V
= V
= V
= 3.3V, T = +25°C, unless otherwise noted.)
AVDD
DVDD
IOVDD
A
OUTPUT POWER SPECTRUM
OUTPUT POWER SPECTRUM
vs. PCLKOUT FREQUENCY (VARIOUS SPREAD)
vs. PCLKOUT FREQUENCY (VARIOUS SPREAD)
10
10
f
= 33.3MHz
f
= 66.7MHz
PCLKOUT
PCLKOUT
0
0
0% SPREAD
-10
-10
0% SPREAD
-20
-30
-40
-20
-30
-40
-50
-60
-50
-60
-70
-80
-90
-70
-80
-90
2% SPREAD 4% SPREAD
2% SPREAD
4% SPREAD
31.0 31.5 32.0 32.5 33.0 33.5 34.0 34.5 35.0 35.5
PCLKOUT FREQUENCY (MHz)
62 63 64 65 66 67 68 69 70 71
PCLKOUT FREQUENCY (MHz)
MAXIMUM PCLKOUT FREQUENCY
vs. COAX CABLE LENGTH (BER ≤ 10-10
)
10
-10
-20
OPTIMUM PE/EQ
NO PE, 10.7dB EQ
-40
-60
-70
-90
BER CAN BE AS LOW AS 10-12 FOR
CABLE LENGTHS LESS THAN 15m
0
5
10
15
20
25
CABLE LENGTH (m)
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
Pin Configuration
TOP VIEW
42 41 40 39 38 37 36 35 34 33 32 31 30 29
DOUT10
28 DOUT24
43
44
45
27
26
IOVDD
DOUT9
IOVDD
DOUT25
25 DOUT26
DOUT8 46
DOUT7 47
DOUT6 48
24 DOUT27/CNTL1
23
22
21
20
DOUT28/CNTL2
SD/HIM
SCK
49
DOUT5
MAX9276
MAX9280
DOUT4 50
DOUT3 51
WS
DOUT2
19 LOCK
18
52
DOUT1 53
54
ERR
17 PWDN
DOUT0
AVDD 55
56
EP
+
16 TX/SCL
RX/SDA
15
CX/TP
2
3
4
5
6
7
8
9
10
1
11
12 13 14
TQFN/QFND
*CONNECT EP TO GROUND PLANE
Pin Description
PIN
NAME
FUNCTION
Active-Low Parallel Output-Enable Input With Internal Pulldown to EP. Set ENABLE = low to enable
PCLKOUT DOUT_ and CNTL_ outputs. Set ENABLE = high to put PCLKOUT, DOUT_ and CNTL_ into
high impedance.
1
ENABLE
A/V Status Register Interrupt Output/Address Selection Input With Internal Pulldown to EP. Functions
as ADD2 input at power-up or when resuming from power-down mode (PWDN = low), and switches to
INTOUT output automatically after power-up.
2
INTOUT/ADD2 ADD2: Bit value is latched at power-up or when resuming from power-down mode (PWDN = low). See
Table 1. Connect INTOUT/ADD2 to IOVDD with a 30kΩ resistor to set high or leave open to set low.
INTOUT: Indicates new data in the A/V status registers. INTOUT is reset when the A/V status registers
are read.
3
4
5
GPI
General-Purpose Input With Internal Pulldown to EP. The serializer GPO (or INT) output follows GPI.
2
I C Select. Control channel interface protocol select input with internal pulldown to EP. Set I2CSEL =
I2CSEL
GPIO0
2
high to select I C interface. Set I2CSEL = low to select UART interface.
Open-Drain, General-Purpose Input/Output with Internal 60kΩ Pullup to IOVDD
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
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Pin Description (continued)
PIN
NAME
FUNCTION
Three-Level Bus Width Select Input. Set BWS to the same level on both sides of the serial link. Set
BWS = low for 24 bit mode. Set BWS = high for 32-bit mode. Set BWS = open for high-bandwidth
mode.
6
BWS
3.3V Analog Power Supply. Bypass AVDD to EP with 0.1µF and 0.001µF capacitors as close as
possible to the device with the smaller capacitor closest to AVDD.
7, 55
AVDD
8
9
IN+
IN-
Noninverting Coax/Twisted-Pair Serial Input
Inverting Coax/Twisted-Pair Serial Input
Mode Select with Internal Pulldown to EP. Set MS = low, to select base mode. Set MS = high to select
the bypass mode.
10
11
MS
Auxiliary Control Signal Output/Address Selection Input With Internal Pulldown to EP. Functions as
ADD1 input at power-up or when resuming from power-down mode (PWDN = low), and switches to
CNTL3 output automatically after power-up.
CNTL3/ADD1 ADD1: Bit value is latched at power-up or when resuming from power-down mode (PWDN = low). See
Table 1. Connect CNTL3/ADD1 to IOVDD with a 30kΩ resistor to set high or leave open to set low.
CNTL3: Used only in high-bandwidth mode (BWS = open). CNTL3 not encrypted when HDCP is
enabled (MAX9280 only).
12
13
GPIO1
DVDD
Open-Drain, General-Purpose Input/Output With Internal 60kΩ Pullup to IOVDD
3.3V Digital Power Supply. Bypass DVDD to EP with 0.1µF and 0.001µF capacitors as close as
possible to the device with the smaller value capacitor closest to DVDD.
Auxiliary Control Signal Output/Address Selection Input With Internal Pulldown to EP. Functions as
ADD0 input at power-up or when resuming from power-down mode (PWDN = low), and switches to
CNTL0 output automatically after power-up.
14
CNTL0/ADD0 ADD0: Bit value is latched at power-up or when resuming from power-down mode (PWDN = low). See
Table 1. Connect CNTL0/ADD0 to IOVDD with a 30kΩ resistor to set high or leave open to set low.
CNTL0: Used only in high-bandwidth mode (BWS = open). CNTL0 not encrypted when HDCP is
enabled (MAX9280 only
).
2
UART Receive/I C Serial Data Input/Output with Internal 30kΩ Pullup to IOVDD. Function is
determined by the state of I2CSEL at power-up. RX/SDA has an open-drain driver and requires a
15
16
RX/SDA
TX/SCL
pullup resistor.
RX: Input of the serializer’s UART.
SDA: Data input/output of the serializer’s I C Master/Slave.
2
2
UART Transmit/I C Serial Clock Input/Output with Internal 30kΩ Pullup to IOVDD. Function is
determined by the state of I2CSEL at power-up. TX/SCL has an open-drain driver and requires a pullup
resistor.
TX: Output of the serializer’s UART.
SCL: Clock input/output of the serializer’s I C Master/Slave.
2
Active-Low, Power-Down Input with Internal Pulldown to EP. Set PWDN low to enter power-down mode
to reduce power consumption.
17
18
PWDN
ERR
Error Output. Open-drain data error detection and/or correction indication output with internal 30kΩ
pullup to IOVDD. ERR is high when PWDN is low
Open-Drain Lock Output with Internal 30kΩ Pullup to IOVDD. LOCK = high indicates that PLLs are
locked with correct serial-word-boundary alignment. LOCK = low indicates that PLLs are not locked or
an incorrect serial-word-boundary alignment. LOCK is high when PWDN = low.
19
LOCK
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
Pin Description (continued)
PIN
NAME
FUNCTION
2
2
I S/TDM Word-Select Input/Output. Powers up as an I S output (deserializer provided clock). Set
AUDIOMODE bit = ‘1’ to change WS to an input with internal pulldown to GND and supply WS
externally (system provided clock).
20
WS
2
2
I S/TDM Serial-Clock Input/Output. Powers up as an I S output (deserializer provided clock). Set
AUDIOMODE bit = ‘1’ to change SCK to an input with internal pulldown to GND and supply WS
externally (system provided clock).
21
SCK
2
I S/TDM Serial-Data Output/High-Immunity Mode Input.
Functions as HIM input with internal pulldown to EP at power-up or when resuming from power-down
mode (PWDN = low), and switches to SD output automatically after power-up.
HIM: Default HIGHIMM bit value is latched at power-up or when resuming from power-down mode
(PWDN = low) and is active-high. Connect SD/HIM to IOVDD with a 30kΩ resistor to set high or leave
open to set low. HIGHIMM can be programmed to a different value after power-up. HIGHIMM in the
serializer must be set to the same value.
22
SD/HIM
2
SD: Disable I S/TDM encoding to serial data to use SD as an additional control/data output valid on the
selected edge of PCLKOUT. Encrypted when HDCP is enabled (MAX9280 only).
Parallel Data/Auxiliary Control Signal Output Valid on the Selected Edge of PCLKOUT.
DOUT28/CNTL2 remains high impedance in 24-bit mode (BWS = low)
DOUT28 used only in 32-bit mode (BWS = high). DOUT28 not encrypted when HDCP is enabled
(MAX9280 only).
CNTL2 used only in high-bandwidth mode (BWS = open). CNTL2 not encrypted when HDCP is
enabled (MAX9280 only).
23
DOUT28/CNTL2
DOUT27/CNTL1
Parallel Data/Auxiliary Control Signal Output Valid on the Selected Edge of PCLKOUT.
DOUT27/CNTL1 remains high impedance in 24-bit mode (BWS = low)
DOUT27 used only in 32-bit mode (BWS = high). DOUT27 not encrypted when HDCP is enabled
(MAX9280 only).
24
CNTL1 used only in high-bandwidth mode (BWS = open). CNTL1 not encrypted when HDCP is
enabled (MAX9280 only)
Parallel Data Outputs Valid on the Selected Edge of PCLKOUT. Encrypted when HDCP is enabled
(MAX9280 only). DOUT[26:21] used only in 32-bit and high-bandwidth modes (BWS = high or open).
DOUT[26:21] remains high-impedance in 24-bit mode.
25, 26,
28–31
DOUT[26:21]
IOVDD
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to EP with 0.1µF and 0.001µF
capacitors as close as possible to the device with the smallest value capacitor closest to IOVDD.
27, 44
Parallel Data/Device Enable Output Valid on the Selected Edge of PCLKOUT. Defaults to parallel data
output on power-up.
32
DOUT20/DE
DOUT19/VS
DOUT18/HS
Device enable output when HDCP is enabled (MAX9280 only) or when in high-bandwidth mode (BWS
= open).
Parallel Data/Vertical Sync Output Valid on the Selected Edge of PCLKOUT. Defaults to parallel data
output on power-up.
Vertical sync output when HDCP is enabled (MAX9280 only) or when in high-bandwidth mode (BWS =
open).
33
Parallel Data/Horizontal Sync Output Valid on the Selected Edge of PCLKOUT. Defaults to parallel data
output on power-up.
Horizontal sync output when HDCP is enabled (MAX9280 only) or when in high-bandwidth mode (BWS
= open).
34
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
Pin Description (continued)
PIN
NAME
FUNCTION
35, 36,
38–43,
45–54
Parallel Data Outputs Valid on the Selected Edge of PCLKOUT. Encrypted when HDCP is enabled
(MAX9280 only)
DOUT[17:0]
37
56
PCLKOUT
CX/TP
Parallel Clock Output Used for DOUT[28:0]. Latches parallel data into the input of another device.
Three-Level Coax/Twisted Pair Select Input. See Table 10 for function.
Exposed Pad. EP is internally connected to device ground. MUST connect EP to the PCB ground plane
through an array of vias for proper thermal and electrical performance.
—
EP
Functional Diagram
PCLKOUT
SSPLL
RGB
CLKDIV
CDRPLL
MAX9276
MAX9280
ENABLE
(MAX9280
ONLY)
DOUT[17:0]
RGB[17:0]
CX/
TP
HDCP
DECRYPT
RGB[23:18]
(30-BIT OR 9b10b)
DOUT[26:21]
VIDEO
SYNC
IN+
IN-
DOUT18/HS
DOUT19/VS
DOUT20/DE
HS
VS
DE
HS
VS
DE
SERIAL
TO
PARALLEL
CML RX
AND EQ
8b/10b OR
9b10b
DOUT[28:27]
(30-BIT)
HDCP
KEYS CONTROL
HDCP
DOUT[28:27]
(30-BIT)
DOUT27/CNTL1
DOUT28/CNTL2
FIFO
DECODE
DESCRAMBLE
CNTL[2:1]
(9b10b)
CNTL[3:0]
(9b10b)
CNTL0/ADD0
CNTL3/ADD1
CONTROL
(9b10b)
TX
CNTL0, CNTL3
(9b10b)
ACB
FCC
REVERSE
CONTROL
CHANNEL
HDCP
DECRYPT
2
I S/TDM
ADD[2:0]
DATA
DESCRIPTION
REGISTERS
ADD[2:0]
CONTROL
2
UART/I C
INTOUT/
ADD2
SD/HIM SCK
WS
GPI
GPIO_ TX/
RX/
I2CSEL
PWDN MS BWS
SCL SDA
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
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R /2
L
IN+
IN-
MAX9276
MAX9280
V
OD
REVERSE
CONTROL-CHANNEL
TRANSMITTER
V
CMR
R /2
L
IN+
IN-
V
CMR
IN-
IN+
V
ROH
0.9 x V
ROH
0.1 x V
ROH
(IN+) - (IN-)
0.1 x V
ROL
ROL
t
R
0.9 x V
V
ROL
t
F
Figure 1. Reverse Control Channel Output Parameters
R /2
L
IN+
IN-
V
IS(P)
0.22µF
49.9Ω
V
ID(P)
IN_
R /2
L
_
V
IN+
+
_
+
C
C
IN
IN
V
IN_
-
C
IN
+
_
V
IN-
V | V - V
ID(P) = IN+ IN-
|
V
(V + V )/2
CMR = IN+ IN-
Figure 2. Test Circuit for Differential Input Measurement
Figure 2a. Test Circuit for Single-Ended Input Measurement
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3.12Gbps GMSL Deserializers
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PCLKOUT
DOUT_
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCH EDGE.
Figure 3. Worst-Case Pattern Output
START
CONDITION
BIT 7
MSB
(A7)
STOP
CONDITION
(P)
BIT 6
(A6)
BIT 0
(R/W)
ACKNOWLEDGE
(A)
PROTOCOL
(S)
t
t
t
HIGH
SU;STA
LOW
1/f
SCL
V
V
x 0.7
x 0.3
IOVDD
IOVDD
SCL
t
SP
t
t
f
BUF
t
r
V
x 0.7
x 0.3
IOVDD
SDA
V
IOVDD
t
t
t
t
t
SU;STO
HD;STA
t
HD;DAT
VD;DAT
VD;ACK
SU;DAT
2
Figure 4. I C Timing Parameters
t
T
V
OH MIN
t
HIGH
PCLKOUT
V
OL MAX
t
LOW
Figure 5. Parallel Clock Output Requirements
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
C
L
SINGLE-ENDED OUTPUT LOAD
0.8 x V
I0VDD
0.2 x V
I0VDD
t
t
R
F
Figure 6. Output Rise-and-Fall Times
SERIAL-WORD LENGTH
SERIAL WORD N
SERIAL WORD N+1
SERIAL WORD N+2
IN+/-
FIRST BIT
LAST BIT
DOUT_
PARALLEL WORD N-1
PARALLEL WORD N
PARALLEL WORD N-2
PCLKOUT
t
SD
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCHING EDGE.
Figure 7. Deserializer Delay
V
IH_MIN
DESERIALIZER
GPI
V
IL_MAX
t
GPIO
t
GPIO
V
OH_MIN
SERIALIZER
GPO
V
OL_MAX
Figure 8. GPI-to-GPO Delay
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
Detailed Description
The MAX9276/MAX9280 deserializers, when paired with
the MAX9275/MAX9277/MAX9279/MAX9281 serializers,
provides the full set of operating features, but is back-
ward-compatible with the MAX9249–MAX9270 family of
gigabit multimedia serial link (GMSL) devices, and have
basic functionality when paired with any GMSL device.
The MAX9280 has high-bandwidth digital content protec-
tion (HDCP) while the MAX9276 does not.
IN+ - IN-
t
LOCK
LOCK
V
OH
The deserializer has a maximum serial-bit rate of 3.12Gbps
for up to 15m of cable and operates up to a maximum out-
put clock of 104MHz in 24-bit mode and 27-bit high-band-
width mode, or 78MHz in 32-bit mode. This bit rate and
output flexibility support a wide range of displays, from
QVGA (320 x 240) to 1920 x 720 and higher with 24-bit
color, as well as megapixel image sensors. An encoded
PWDN MUST BE HIGH
Figure 9. Lock Time
2
audio channel supports L-PCM I S stereo and up to eight
IN+/-
channels of L-PCM in TDM mode. Sample rates of 32kHz
to 192kHz are supported with sample depth from 8 to 32
bits. Input equalization, combined with GMSL serializer
pre/deemphasis, extends the cable length and enhances
link reliability
V
IH1
PWDN
The control channel enables a µC to program the serial-
izer and deserializer registers and program registers on
peripherals. The control channel is also used to perform
HDCP functions (MAX9280 only). The µC can be located
at either end of the link, or when using two µCs, at both
ends. Two modes of control-channel operation are avail-
t
PU
LOCK
V
OH
2
able. Base mode uses either I C or GMSL UART protocol,
Figure 10. Power-Up Delay
while bypass mode uses a user-defined UART protocol.
UART protocol allows full-duplex communication, while
2
I C allows half-duplex communication.
WS
Spread spectrum is available to reduce EMI on the paral-
lel output. The serial input complies with ISO 10605 and
IEC 61000-4-2 ESD protection standards.
t
t
DVB
DVA
t
R
Register Mapping
SCK
SD
Registers set the operating conditions of the deserializers
and are programmed using the control channel in base
mode. The MAX9276/MAX9280 holds its own device
address and the device address of the serializer it is
paired with. Similarly, the serializer holds its own device
address and the address of the MAX9276/MAX9280.
Whenever a device address is changed be sure to write
the new address to both devices. The default device
address of the deserializer is set by the ADD[2:0] and
CX/TP inputs (see Table 1). Registers 0x00 and 0x01 in
both devices hold the device addresses.
t
t
DVA
DVB
t
F
2
Figure 11. Output I S Timing Parameters
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
Table 1. Device Address Defaults (Register 0x00, 0x01)
SERIALIZER
DEVICE
DESERIALIZER
DEVICE
DEVICE ADDRESS
PIN
(BIN)
ADDRESS
(hex)
ADDRESS
(hex)
CX/TP**
ADD2
ADD1
ADD0
D7 D6 D5 D4 D3 D2 D1
D0
High/Low
High/Low
High/Low
High/Low
High/Low
High/Low
High/Low
High/Low
Open
Low
Low
Low
Low
High
High
High
High
Low
Low
Low
Low
High
High
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
High
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X*
X*
X*
X*
X*
X*
X*
X*
X*
X*
X*
X*
X*
X*
X*
X*
0
0
1
0
0
0
1
1
0
0
1
0
0
0
1
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
0
RW
80
84
88
44
C0
C4
C8
48
80
84
88
44
C0
C4
C8
48
90
94
98
54
D0
D4
D8
58
92
96
9A
56
D2
D6
DA
5A
R//W
R//W
R//W
R//W
R//W
R//W
R//W
R//W
R//W
R//W
R//W
R//W
R//W
R//W
R//W
0
0
0
0
0
0
X*
X*
X*
X*
X*
X*
X*
X*
Open
Open
Open
Open
Open
Open
Open
*X = 0 for the serializer address, X = 1 for the deserializer address
**CX/TP determine the serial cable type CX/TP = open addresses only for coax mode.
Input data is scrambled and then 8b/10b coded (9b10b
in high-bandwidth mode). The deserializer recovers the
embedded serial clock, then samples, decodes, and
descrambles the data. In 24-bit mode, the first 21 bits
contain video data. In 32-bit mode, the first 29 bits contain
video data. In high-bandwidth mode, the first 24 bits con-
tain video data, or special control signal packets. The last
3 bits contain the embedded audio channel, the embed-
ded forward control channel, the parity bit of the serial
word (Figure 12, Figure 13).
Output Bit Map
The output bit width depends on settings of the bus width
(BWS) pin. Table 2 lists the bit map. Unused output bits
are pulled low.
Serial Link Signaling and Data Format
The serializer uses differential CMLsignaling to drive twist-
ed-pair cable and single-ended CML to drive coaxial cable
with programmable pre/deemphasis and AC-coupling.
The deserializer uses AC-coupling and programmable
channel equalization.
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
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Table 2. Output Map
MODE
SIGNAL
OUTPUT PIN
24-BIT MODE
(BWS = LOW)
HIGH-BANDWIDTH
MODE (BWS = MID
32-BIT MODE
(BWS = HIGH)
R[5:0]
G[5:0]
B[5:0]
DOUT[5:0]
DOUT [11:6]
DOUT [17:12]
Used
Used
Used
Used
Used
Used
Used
Used
Used
DOUT18/HS, DOUT19/VS,
DOUT20/DE
HS, VS, DE
Used**
Used**
Used**
R[7:6]
G[7:6]
DOUT [22:21]
DOUT [24:23]
Used+
Used+
Used+
Not used
Not used
Used
Used
Used
Used
Used
B[7:6]
DOUT [26:25]
Used
Used
CNTL[2:1]
CNTL3, CNTL0
DOUT [28:27]/CNTL[2:1]
CNTL3/ADD1, CNTL0/ADD0
Used*,**
Used*,**
Used
Used**
Not used
Used
2
I S/TDM
WS, SCK, SD/HIM
AUX SIGNAL
Used
Used
Used
*See the High-Bandwidth Mode section for details on timing requirements.
+Outputs used only when the respective color lookup tables are enabled.
**Not encrypted when HDCP is enabled (MAX9280 only).
24 BITS
SERIAL DATA
D0
D1
D17
D18
D19
D20
ACB
FCC
AUDIO DECODE
SCK
PCB
FORWARD
CONTROL
PACKET
PARITY
CHANNEL BIT
CHECK BIT
DOUT
0
DOUT
1
DOUT
17
DOUT
18/HS
DOUT
19/VS
DOUT
20/DE
RX/
TX/
OUTPUT PIN
WS
SD
SDA
SCL
OUTPUT
SIGNAL
R0
R1
B5
HS
VS
DE
RGB DATA
CONTROL BITS
2
2
UART/I C
I S/TDM
AUDIO
MAX9280 NOTE: VS/HS MUST BE SET AT DOUT[19:18] FOR HDCP
FUNCTIONALITY.
ONLY DOUT[17:0] AND ACB HAVE HDCP DECRYPTION.
Figure 12. 24-Bit Mode Serial Data Format
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3.12Gbps GMSL Deserializers
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32 BITS
D22
SERIAL DATA
D0
D1
D17
D18
D19
D20
D21
D23
D24
D25
D26
D27
D28
ACB
FCC
AUDIO DECODE
SCK
PCB
FORWARD
CONTROL
PACKET
PARITY
CHANNEL BIT
CHECK BIT
DOUT
0
DOUT
1
DOUT
17
DOUT
18/HS
DOUT
19/VS
DOUT
20/DE
DOUT
21
DOUT DOUT
22
DOUT DOUT
24
DOUT DOUT27/ DOUT28/
26
RX/
TX/
OUTPUT PIN
WS
SD
23
25
CNTL1 CNTL2
SDA
SCL
OUTPUT
SIGNAL
R0
R1
B5
HS
VS
DE
R6
R7
G6
G7
B6
B7
2
2
UART/I C
AUX
CONTROL
BITS
I S/TDM
RGB DATA
CONTROL BITS
RGB DATA
AUDIO
MAX9280 NOTE: VS/HS MUST BE SET AT DOUT[19:18] FOR HDCP
FUNCTIONALITY.
ONLY DOUT[17:0], DOUT[26:21] AND ACB HAVE HDCP ENCRYPTION.
Figure 13. 32-Bit Mode Serial Data Format
27 BITS
27 BITS
SERIAL DATA
D0
D1
D17
D18
D19
D20
D21
D22
D23
ACB
FCC
PCB
SPECIAL SERIAL DATA PACKET
CONTROL SIGNAL DECODING
FORWARD
CONTROL
PACKET
PARITY
AUDIO DECODE
CHANNEL BIT
CHECK BIT
DOUT
0
DOUT
1
DOUT
17
DOUT
21
DOUT
22
DOUT
23
DOUT
24
DOUT
25
DOUT
26
RX/
SDA
TX/
SCL
CNTL0/ DOUT27/ DOUT28/ CNTL3
DOUT
18/HS
DOUT
19/VS
DOUT
20/DE
INPUT PIN
WS
SCK
SD
ADD0
CNTL1 CNTL2
ADD1
INPUT
SIGNAL
R0
R1
B5
R6
R7
G6
G7
B6
B7
HS
VS
DE
2
2
I S/TDM
UART/I C
AUX
CONTROL
BITS
CONTROL BITS
RGB DATA
RGB DATA
AUDIO
MAX9280 NOTE: VS/HS MUST BE SET AT DOUT[20:18].
ONLY DOUT[17:0], DOUT[26:21] AND ACB HAVE HDCP ENCRYPTION.
Figure 14. High-Bandwidth Mode Serial Data Format
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3.12Gbps GMSL Deserializers
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Table 3. Data-Rate Selection Table
DRS BIT SETTING
BWS PIN SETTING
Low (24-bit mode)
PCLKOUT RANGE (MHz)
16.66 to 104
36.66 to 104
12.5 to 78
0 (high data rate)
Mid (high bandwidth mode)
High (32-bit mode)
Low
Mid
8.33 to 16.66
18.33 to 36.66
6.25 to 12.5
1 (low data rate)
High
The deserializer uses the DRS bit and the BWS input to
set the PCLKOUT frequency range (Table 3). Set DRS = 1
for low data rate PCLKOUT frequency range of 6.25MHz
to 16.66MHz. Set DRS = 0 for high data rate PCLKOUT
frequency range of 12.5MHz to 104MHz.
stream and stores audio words in a FIFO. Audio rate
detection uses an internal oscillator to continuously
determine the audio data rate and output the audio in I S
format. The audio channel is enabled by default. When
the audio channel is disabled, the SD/HIM is treated as
an auxiliary control signal.
2
High-Bandwidth Mode
Since the audio data sent through the serial link is syn-
chronized with PCLKOUT, low PCLKOUT frequencies
limit the maximum audio sampling rate. Table 3 lists the
maximum audio sampling rate for various PCLKOUT fre-
The deserializer uses a 27-bit high-bandwidth mode to
support 24-bit RGB at 104MHz pixel clock. Set BWS =
open in both the serializer and deserializer to use high-
bandwidth mode. In high-bandwidth mode, the deserial-
izer decodes HS, VS, DE and CNTL[3:0] from special
packets. Packets are sent by replacing a pixel before
the rising edge and after the falling edge of the HS, VS,
and DE signals. However, for CNTL[3:0], packets always
replace a pixel before the transition of CNTL[3:0]. Keep
HS, VS, and DE low pulse widths at least 2 pixel clock
cycles. By default, CNTL[3:0] are sampled continuously
when DE is low. CNTL[3:0] are sampled only on HS/VS
transitions when DE is high. If DE triggering of encoded
packets is not desired, set the serializer’s DISDETRIG
= 0 and the CNTLTRIG bits to their desired value (reg-
ister 0x15) to change the CNTL triggering behavior. Set
DETREN = 0 on the deserializer when DE is not periodic.
2
quencies. Spread-spectrum settings do not affect the I S/
TDM data rate or WS clock frequency.
Audio Channel Input
The audio channel input works with 8-channel TDM and
2
stereo I S, as well as non-standard formats. The input
format is shown in Figure 15.
FRAME
WS
SCK
Audio Channel
The audio channel supports 8kHz to 192kHz audio
sampling rates and audio word lengths from 8 bits to
32 bits (2 channel I S) or 64 to 256 bits (TDM64 to
TDM256). The audio bit clock (SCK) does not have to be
synchronized with PCLKOUT. The serializer automatically
encodes audio data into a single-bit stream synchronous
with PCLKOUT. The deserializer decodes the audio
SD
0
1
2
N
2
16 TO 256 BITS
Figure 15. Audio Channel Input Format
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Table 4. Maximum Audio WS Frequency (kHz) for Various PCLKOUT Frequencies
PCLKOUT FREQUENCY
(DRS = 0*)
(MHz)
BITS PER
CHANNEL
12.5
15.0
16.6
20.0
25.0
30.0
35.0
40.0
45.0
50.0
100
8
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
16
18
20
24
32
+
+
185.5
174.6
152.2
123.7
+
+
+
2
4
6
8
+
182.7
148.4
+
164.3
8
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
16
18
20
24
32
123.7
112.0
104.2
88.6
148.4
134.4
125.0
106.3
83.8
164.3
148.8
138.3
117.7
92.8
+
+
179.2
166.7
141.8
111.8
+
+
+
+
177.2
139.7
+
69.9
167.6
8
152.2
88.6
80.2
73.3
62.5
48.3
182.7
106.3
93.3
88.0
75.0
57.9
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
16
18
20
24
32
117.7
106.6
97.3
83.0
64.1
141.8
128.4
117.3
100
177.2
160.5
146.6
125
+
+
+
+
+
+
+
+
175.9
150
115.9
+
175
135.2
+
+
77.2
96.5
154.5
173.8
8
123.7
69.9
62.5
57.1
48.3
37.1
148.4
83.8
75.0
68.5
57.9
44.5
164.3
92.8
83.0
75.8
64.1
49.3
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
16
18
20
24
32
111.8
100.0
91.3
77.2
59.4
139.7
125.0
114.2
96.5
167.6
150.0
137.0
115.9
89.1
+
+
175.0
159.9
135.2
103.9
+
+
+
+
182.7
154.5
118.8
+
173.8
133.6
+
74.2
148.4
COLOR CODING
< 48kHz
48kHz to 96kHz
96kHz to 192kHz
> 192kHz
+Max WS rate is greater than 192kHz.
*DRS = 0 PCLKOUT frequency is equal to 2x the DRS = 1 PCLKOUT frequency.
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The period of the WS can be 8 to 256 SCK periods. The
WS frame starts with the falling edge and can be low for
1 to 255 SCK periods. SD is one SCK period, sampled
on the rising edge. MSB/LSB order, zero padding or any
other significance assigned to the serial data does not
affect operation of the audio channel. The polarity for WS
and SCK edges is programmable.
Figure 16, Figure 17, Figure 18, and Figure 19 are exam-
ples of acceptable input formats.
256 SCK
WS
SCK
SD
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
32 SCK
MSB 24-BIT DATA
LSB 8 BITS ZERO
Figure 16. 8-Channel TDM (24-Bit Samples, Padded With Zeros)
144 SCK
WS
SCK
SD
CH1
CH2
CH3
CH4
CH5
CH6
24 SCK
24-BIT DATA
Figure 17. 6-Channel TDM (24-Bit Samples, No Padding)
64 SCK
WS
SCK
SD
LEFT CHANNEL
32 SCK
RIGHT CHANNEL
MSB 24-BIT DATA
LSB 8 BITS ZERO
2
Figure 18. Stereo I S (24-Bit Samples, Padded With Zeros)
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32 SCK
WS
SCK
SD
LEFT CHANNEL
16 SCK
RIGHT CHANNEL
16-BIT DATA
2
Figure 19. Stereo I S (16-Bit Samples, No Padding)
WS and SCK can be driven by the audio source (clock
master) or the audio sink (clock slave). Buffer underflow
and overflow flags are available to the sink as clock slave
via I C for clock frequency adjustment. Data are sampled
on the rising edge. WS and SCK polarity is programmable.
Audio Channel Output
WS, SCK, and SD are output with the same timing rela-
tionship they had at the audio input, except that WS is
always 50% duty cycle (regardless of the duty cycle of
WS at the input).
2
The output format is shown in Figure 20.
2
I S
TDM 256
WS
SCK
WS
SCK
SD/HIM
SD/HIM
8 TO 32 BITS
256 BITS
Figure 20. Audio Channel Output Format
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Additional MCLK Output for Audio Applications
Audio Output Timing Sources
Some audio DACs, such as the MAX9850, do not
require a synchronous main clock (MCLK), while other
DACs require a separate MCLK for operation. For audio
applications that cannot use WS or PCLKOUT directly,
the deserializer provides a divided MCLK output at
either DOUT28/CNTL2 or CNTL0/ADD0 (determined by
MCLKPIN bit setting) at the expense of one less control
line. By default, MCLK is turned off. Set MCLKDIV (dese-
rializer register 0x12, D[6:0]) to a nonzero value to enable
the MCLK output. Set MCLKDIV to 0x00 to disable MCLK
and set DOUT28/CNTL2 or CNTL0/ADD0 as a control
output.
The deserializer has multiple options for audio data output
timing. By default, the deserializer provides the output
timing based on the incoming data rate (through a FIFO)
and an internal oscillator.
To use a system sourced clock, set the AUDIOMODE bit
to 1 (D5 of register 0x02) to set WS and SCK as inputs
on the deserializer side. The deserializer uses a FIFO to
smooth out the differences in input and output audio tim-
ing. Registers 0x78 and 0x79 store the FIFO overflow/
underflow information for use with external WS/SCK tim-
ing. The FIFO drops data packets during FIFO overflow.
By default, the FIFO repeats the last audio packet during
FIFO underflow when no audio data is available. Set the
AUDUFBEH bit (D2 of register 0x01D) to 1 to output all
zeroes during underflow.
The output MCLK frequency is:
f
SRC
f
=
MCLK
MCLKDIV
Reverse Control Channel
where:
The serializer uses the reverse control channel to receive
I C/UART and GPO signals from the deserializer in
f
is the MCLK source frequency (see Table 5)
SRC
2
MCLKDIV is the divider ratio from 1 to 127
the opposite direction of the video stream. The reverse
control channel and forward video data coexist on the
same serial cable forming a bidirectional link. The reverse
control channel operates independently from the forward
control channel. The reverse control channel is available
2ms after power-up. The serializer temporarily disables
the reverse control channel for 500µs after starting/
stopping the forward serial link.
Choose MCLKDIV values so that f
is not greater
MCLK
than 60MHz. MCLK frequencies derived from PCLKOUT
(MCLKSRC = 0) are not affected by spread-spectrum
settings in the deserializer. Enabling spread spectrum
in the serializer, however, introduces spread spectrum
into MCLK. Spread-spectrum settings of either device
do not affect MCLK frequencies derived from the internal
oscillator. The internal oscillator frequency ranges
from 100MHz to 150MHz over all process corners and
operating conditions. Alternatively, set MCLKWS = 1
(0x15 D1) to output WS from MCLK.
Table 5. f
Settings
SRC
MCLKWS SETTING
(REGISTER 0x15, D1)
MCLKSRC SETTING
(REGISTER 0x12, D7)
DATA RATE
SETTING
MCLK SOURCE
BIT-WIDTH SETTING
FREQUENCY (f
)
SRC
24-bit or high-bandwidth mode
32-bit mode
3 x f
High speed
(DRS = 0)
CLKOUT
CLKOUT
CLKOUT
CLKOUT
4 x f
6 x f
8 x f
0
24-bit or high-bandwidth mode
32-bit mode
Low speed
(DRS = 1)
0
Internal oscillator
(120MHz typ)
1
—
—
—
1
—
—
WS*
*MCLK is not divided when using WS as the MCLK source. MCLK divider must still be set to a nonzero number for MCLK to be
enabled.
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The deserializer uses differential line coding to send sig-
nals over the reverse channel to the serializer. The bit rate
of the control channel is 9.6kbps to 1Mbps in both direc-
tions. The serializer and deserializer automatically detect
the control-channel bit rate in base mode. Packet bit rate
changes can be made in steps of up to 3.5 times higher
or lower than the previous bit rate. See the Changing the
Clock Frequency section for more information.
Control Channel and Register Programming
The control channel is available for the µC to send and
receive control data over the serial link simultaneously
with the high-speed data. The µC controls the link from
either the serializer or the deserializer side to support
video-display or image-sensing applications. The control
channel between the µC and serializer or deserializer
runs in base mode or bypass mode according to the
mode selection (MS) input of the device connected to the
µC. Base mode is a half-duplex control channel and the
bypass mode is a full-duplex control channel. The total
maximum forward or reverse control channel delay is 2µs
Figure 21 shows the UART protocol for writing and read-
ing in base mode between the µC and the serializer/
deserializer.
Figure 22 shows the UART data format. Even parity is
used. Figure 23 and Figure 24 detail the formats of the
SYNC byte (0x79) and the ACK byte (0xC3). The µC and
the connected slave chip generate the SYNC byte and
ACK byte, respectively. Events such as device wake-up
and GPI generate transitions on the control channel that
can be ignored by the µC. Data written to the deserial-
izer registers do not take effect until after the acknowl-
edge byte is sent. This allows the µC to verify that write
commands are received without error, even if the result
of the write command directly affects the serial link. The
slave uses the SYNC byte to synchronize with the host
UART’s data rate. If the GPI or MS inputs of the deserial-
izer toggle while there is control-channel communication,
or if a line fault occurs, the control-channel communica-
tion will be corrupted. In the event of a missed or delayed
acknowledge (~1ms due to control channel timeout), the
µC should assume there was an error in the packet. In
base mode, the µC must keep the UART Tx/Rx lines high
no more than 4 bit times between bytes in a packet. Keep
the UART Rx/Tx lines high for at least 16 bit times before
starting to send a new packet.
2
(UART) or 2-bit times (I C) from the input of one device
2
to the output of the other. I C delay is measured from a
START condition to START condition.
UART Interface
In base mode, the µC is the host and can access the
registers of both the serializer and deserializer from either
side of the link using the GMSL UART protocol. The µC
can also program the peripherals on the remote side by
sending the UART packets to the serializer or deserializer,
2
with the UART packets converted to I C by the device
on the remote side of the link. The µC communicates
with a UART peripheral in base mode (through INTTYPE
register settings), using the half-duplex default GMSL
UART protocol of the serializer/deserializer. The device
addresses of the serializer and deserializer in base mode
are programmable.
2
When the peripheral interface is I C, the serializer/
2
deserializer converts UART packets to I C that have
device addresses different from those of the serializer or
2
deserializer. The converted I C bit rate is the same as the
original UART bit rate.
WRITE DATA FORMAT
DEV ADDR + R/W REG ADDR NUMBER OF BYTES BYTE 1
SYNC
BYTE N
ACK
MASTER READS FROM SLAVE
MASTER WRITES TO SLAVE
READ DATA FORMAT
SYNC
DEV ADDR + R/W REG ADDR NUMBER OF BYTES
MASTER WRITES TO SLAVE
ACK
BYTE 1
BYTE N
MASTER READS FROM SLAVE
Figure 21. GMSL UART Protocol for Base Mode
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1 UART FRAME
START
D0
D1
D2
D3
D4
D5
D6
D7
PARITY
STOP
FRAME 1
FRAME 2
FRAME 3
BASE MODE USES EVEN PARITY
STOP
START
STOP
START
Figure 22. GMSL UART Data Format for Base Mode
D0
1
D1
0
D2
0
D3
1
D4
1
D5
1
D6
1
D7
0
D0
1
D1
1
D2
0
D3
0
D4
0
D5
0
D6
1
D7
1
START
PARITYSTOP
START
PARITY STOP
Figure 23. Sync Byte (0x79)
Figure 24. ACK Byte (0xC3)
2
UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)
SERIALIZER/DESERIALIZER
11
µC
11
11
11
11
11
11
ACK FRAME
SYNC FRAME
DEVICE ID + WR
REGISTER ADDRESS NUMBER OF BYTES
DATA 0
DATA N
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
8
1
1
S
DEV ID W A REG ADDR
A
DATA 0
A
DATA N
A
P
2
UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 0)
SERIALIZER/DESERIALIZER
11
µC
11
11
11
11
ACK FRAME
11
DATA 0
11
DATA N
SYNC FRAME
DEVICE ID + RD
REGISTER ADDRESS NUMBER OF BYTES
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
DEV ID W A REG ADDR
A
S
DEV ID
R
A
DATA 0
A
DATA N
A
P
S: START
P: STOP
A: ACKNOWLEDGE
: MASTER TO SLAVE
: SLAVE TO MASTER
2
Figure 25. Format Conversion Between GMSL UART and I C with Register Address (I2CMETHOD = 0)
As shown in Figure 25, the remote-side device converts
device removes the byte number count and adds or
receives the ACK between the data bytes of I C. The I C
bit rate is the same as the UART bit rate.
2
2
packets going to or coming from the peripherals from
2
UART format to I C format and vice versa. The remote
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2
The µC cannot access the serializer/deserializer’s reg-
isters in this mode. Peripherals accessed through the
forward control channel using the UART interface need
to handle at least one PCLKOUT period 10ns of jitter
due to the asynchronous sampling of the UART signal
by PCLKOUT. Set MS/HVEN = high to put the control
channel into bypass mode. For applications with the µC
connected to the deserializer, there is a 1ms wait time
between setting MS high and the bypass control channel
being active. There is no delay time when switching to
bypass mode when the µC is connected to the serial-
izer. Do not send a logic-low value longer than 100µs to
ensure proper GPO functionality. Bypass mode accepts
bit rates down to 10kbps in either direction. See the
GPO/GPI Control section for GPI functionality limitations.
The control-channel data pattern should not be held low
longer than 100µs if GPI control is used.
Interfacing Command-Byte-Only I C Devices with
UART
2
The deserializers’ UART-to-I C conversion can interface
with devices that do not require register addresses, such
as the MAX7324 GPIO expander. In this mode, the I C
master ignores the register address byte and directly reads/
writes the subsequent data bytes (Figure 26). Change
the communication method of the I C master using the
I2CMETHOD bit. I2CMETHOD = 1 sets command-byte-
only mode, while I2CMETHOD = 0 sets normal mode
where the first byte in the data stream is the register
address.
2
2
UART Bypass Mode
In bypass mode, the deserializers ignore UART com-
mands from the µC and the µC communicates with the
peripherals directly using its own defined UART protocol.
2
UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)
µC
SERIALIZER/DESERIALIZER
11
SYNC FRAME
11
11
11
11
DATA 0
11
DATA N
11
DEVICE ID + WR
REGISTER ADDRESS NUMBER OF BYTES
ACK FRAME
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
1
S
DEV ID
W
A
DATA 0
A
DATA N
A
P
2
UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 1)
µC
SERIALIZER/DESERIALIZER
11
11
11
11
11
11
DATA 0
11
DATA N
SYNC FRAME
DEVICE ID + RD
REGISTER ADDRESS NUMBER OF BYTES
ACK FRAME
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
1
S
DEV ID
R
A
DATA 0
A
DATA N
A
P
: MASTER TO SLAVE
: SLAVE TO MASTER S: START
P: STOP A: ACKNOWLEDGE
2
Figure 26. Format Conversion Between GMSL UART and I C with Register Address (I2CMETHOD = 1)
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2
sent by a master, followed by the device’s 7-bit slave
address plus a R/W bit, a register address byte, one or
more data bytes, and finally a STOP condition.
I C Interface
2
2
In I C to I C mode, the deserializer’s control channel
interface sends and receives data through an I C-
2
compatible 2-wire interface. The interface uses a serial-
data line (SDA) and a serial-clock line (SCL) to achieve
bidirectional communication between master and slave(s).
A µC master initiates all data transfers to and from the
device and generates the SCL clock that synchronizes
START and STOP Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from high
to low while SCL is high (see Figure 27). When the mas-
ter has finished communicating with the slave, it issues
a STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission.
2
the data transfer. When an I C transaction starts on the
local side device’s control channel port, the remote side
2
device’s control channel port becomes an I C master
2
2
that interfaces with remote side I C peripherals. The I C
master must accept clock-stretching which is imposed by
the deserializer (holding SCL LOW) The SDA and SCL
lines operate as both an input and an open-drain output.
Pullup resistors are required on SDA and SCL. Each
transmission consists of a START condition (Figure 4)
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 28). The data on SDA must remain stable while
SCL is high.
SDA
SCL
P
S
STOP
CONDITION
START
CONDITION
Figure 27. START and STOP Conditions
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 28. Bit Transfer
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Acknowledge
Slave Address
The acknowledge bit is a clocked 9th bit that the recipient
uses to handshake receipt of each byte of data (Figure 29).
Thus, each byte transferred effectively requires nine bits.
The master generates the 9th clock pulse, and the recipi-
ent pulls down SDA during the acknowledge clock pulse.
The SDA line is stable low during the high period of the
clock pulse. When the master is transmitting to the slave
device, the slave device generates the acknowledge bit
because the slave device is the recipient. When the slave
device is transmitting to the master, the master generates
the acknowledge bit because the master is the recipient.
The device generates an acknowledge even when the
forward control channel is not active. To prevent acknowl-
edge generation when the forward control channel is not
active, set the I2CLOCACK bit low.
The deserializers have 7-bit long slave addresses. The
bit following a 7-bit slave address is the R/W bit, which is
low for a write command and high for a read command.
The slave address for the deserializer is XX01XXX1 for
read commands and XX01XXX0 for write commands.
See Figure 30.
Bus Reset
2
The device resets the bus with the I C START condition
for reads. When the R/W bit is set to 1, the deserializers
transmit data to the master, thus the master is reading
from the device.
START
CONDITION
CLOCK PULSE FOR
ACKNOWLEDGE
1
2
8
9
SCL
SDA
BY
TRANSMITTER
SDA
BY
RECEIVER
S
Figure 29. Acknowledge
X
0
1
X
X
X
R/W
LSB
SDA
SCL
X
ACK
MSB
Figure 30. Slave Address
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device takes no further action beyond storing the register
address (Figure 31). Any bytes received after the register
address are data bytes. The first data byte goes into the
register selected by the register address, and subsequent
data bytes go into subsequent registers (Figure 32). If
multiple data bytes are transmitted before a STOP con-
dition, these bytes are stored in subsequent registers
because the register addresses autoincrements.
Format for Writing
Writes to the deserializers comprise the transmission of
the slave address with the R/W bit set to zero, followed by
at least one byte of information. The first byte of informa-
tion is the register address or command byte. The register
address determines which register of the device is to be
written by the next byte, if received. If a STOP (P) condi-
tion is detected after the register address is received, the
0 = WRITE
ADDRESS = 0x80
REGISTER ADDRESS = 0x00
REGISTER 0x00 WRITE DATA
S
1
0
0
0
0
0
0
0
A
0
0
0
0
0
0
0
0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
S = START BIT
P = STOP BIT
A = ACK
D_ = DATA BIT
2
Figure 31. Format for I C Write
0 = WRITE
ADDRESS = 0x80
REGISTER ADDRESS = 0x00
S
1
0
0
0
0
0
0
0
A
A
0
0
0
0
0
0
0
0
A
N
S = START BIT
P = STOP BIT
A = ACK
N = NACK
D_ = DATA BIT
REGISTER 0x00 WRITE DATA
REGISTER 0x01 WRITE DATA
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
P
Figure 32. Format for Write to Multiple Registers
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
2
remote side I C setup and hold times should be adjusted
Format for Reading
by setting the I2CSLVSH register settings on both sides.
The deserializers are read using the internally stored
register address as an address pointer, the same way the
stored register address is used as an address pointer for
a write. The pointer autoincrements after each data byte
is read using the same rules as for a write. Thus, a read
is initiated by first configuring the register address by
performing a write (Figure 33). The master can now read
consecutive bytes from the device, with the first data byte
being read from the register address pointed by the previ-
ously written register address. Once the master sends a
NACK, the device stops sending valid data.
2
I C Address Translation
2
The deserializers support I C address translation for up to
two device addresses. Use address translation to assign
unique device addresses to peripherals with limited
2
I C addresses. Source addresses (address to translate
from) are stored in registers 0x18 and 0x1A. Destination
addresses (address to translate to) are stored in registers
0x19 and 0x1B.
In a multilink situation where there are multiple deserial-
izers and/or peripheral devices connected to these serial-
izers, the deserializers support broadcast commands to
control these multiple devices. Select an unused device
address to use as a broadcast device address. Program
all the remote side serializer devices to translate the
broadcast device address (source address stored in reg-
isters 0x0F, 0x11) to the peripherals’ address (destination
address stored in registers 0x10, 0x12). Any commands
sent to the broadcast address (selected unused address)
will be sent to all deserializers and/or peripheral devices
connected to the deserializers whose addresses match
the translated broadcast address.
2
I C Communication with Remote Side Devices
2
The deserializers support I C communication with a
peripheral on the remote side of the communication link
using SCL clock stretching. While multiple masters can
reside on either side of the communication link, arbitration
is not provided. The connected masters need to support
2
SCL clock stretching. The remote side I C bit rate range
2
must be set according to the local side I C bit rate.
Supported remote side bit rates can be found in Table 6.
2
Set the I2CMSTBT (register 0x1C) to set the remote I C
bit rate. If using a bit rate different from 400kbps, local and
0 = WRITE
ADDRESS = 0x80
REGISTER ADDRESS = 0x00
S
1
0
0
0
0
0
0
0
A
0
0
0
0
0
0
0
0
A
S = START BIT
P = STOP BIT
A = ACK
1 = READ
ADDRESS = 0x81
REGISTER 0x00 READ DATA
REPEATED START
N = NACK
D_ = DATA BIT
S
1
0
0
0
0
0
0
1
A
D7
D6
D5
D4
D3
D2
D1
D0
N
P
2
Figure 33. Format for I C Read
2
Table 6. I C Bit Rate Ranges
LOCAL BIT RATE
f > 50kbps
REMOTE BIT RATE RANGE
Up to 1Mbps
I2CMSTBT SETTING
ANY
Up to 110
000
20kbps > f > 50kbps
f < 20kbps
Up to 400kbps
Up to 10kbps
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
GPO/GPI Control
Line Equalizer
GPO on the serializer follows GPI transitions on the dese-
rializer. This GPO/GPI function can be used to transmit
signals such as a frame sync in a surround-view camera
system. The GPI to GPO delay is 0.35ms max. Keep
time between GPI transitions to a minimum 0.35ms. This
includes transitions from the other deserializer in coax
splitter mode. Bit D4 of register 0x06 in the deserializer
stores the GPI input state. GPO is low after power-up.
The µC can set GPO by writing to the SETGPO register
bit. Do not send a logic-low value on the deserializer RX/
SDA input (UART mode) longer than 100µs in either base
or bypass mode to ensure proper GPO/GPI functionality.
The deserializer includes an adjustable line equalizer to
further compensate cable attenuation at high frequencies.
The cable equalizer has 11 selectable levels of com-
pensation from 2.1dB to 13dB (Table 7). To select other
equalization levels, set the corresponding register bits
in the deserializer (0x05 D[3:0]). Use equalization in the
deserializer, together with preemphasis in the serializer, to
create the most reliable link for a given cable.
Spread Spectrum
To reduce the EMI generated by the transitions on
the serial link, the deserializer output is programmable
for spread spectrum. If the serializer, paired with the
MAX9276/MAX9280, has programmable spread spec-
trum, do not enable spread for both at the same time or
their interaction will cancel benefits. The deserializer will
track the serializer spread and will pass the spread to the
deserializer output. The programmable spread-spectrum
amplitudes are ±2%,and ±4% (Table 8).
Table 7. Cable Equalizer Boost Levels
BOOST SETTING
TYPICAL BOOST GAIN (dB)
(0x05 D[3:0])
0000
0001
0010
0011
0100
0101
0110
0111
1000
2.1
2.8
3.4
4.2
5.2
6.2
7
The deserializer includes a sawtooth divider to control the
spread modulation rate. Autodetection of the PCLKOUT
operation range guarantees a spread-spectrum modu-
lation frequency within 20kHz to 40kHz. Additionally,
manual configuration of the sawtooth divider (SDIV: 0x03,
D[5:0]) allows the user to set a modulation frequency
according to the PCLKOUT frequency. When ranges are
manually selected, program the SDIV value for a fixed
modulation frequency around 20kHz.
8.2
9.4
10.7
1001
Power-up default
Manual Programming of the Spread-Spectrum
Divider
The modulation rate relates to the PCLKOUT frequency
as follows:
1010
1011
11.7
13
f
Table 8. Output Spread
PCLKOUT
f
= 1+ DRS
(
)
M
MOD × SDIV
SS
00
01
10
11
SPREAD (%)
No spread spectrum. Power-up default
±2% spread spectrum.
where:
= Modulation frequency
f
M
No spread spectrum
DRS = DRS value (0 or 1)
= PCLKOUT frequency
±4% spread spectrum
f
PCLKOUT
MOD = Modulation coefficient given in Table 9
Table 9. Modulation Coefficients and
Maximum SDIV Settings
SDIV = 5-bit SDIV setting, manually programmed by the µC
To program the SDIV setting, first look up the modulation
coefficient according to the desired bus-width and spread-
spectrum settings. Solve the above equation for SDIV
using the desired pixel clock and modulation frequencies.
If the calculated SDIV value is larger than the maximum
allowed SDIV value in Table 9, set SDIV to the maximum
value.
SPREAD-
SPECTRUM
SETTING (%)
MODULATION
COEFFICIENT
MOD (DECIMAL)
SDIV UPPER
LIMIT (DECIMAL)
4
208
208
15
2
30
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
GMSL
SERIALIZER
MAX9276
MAX9280
OUT+
IN+
IN-
OUT-
OPTIONAL
COMPONENTS
FOR INCREASED
POWER-SUPPLY
REJECTION
MAX9276
MAX9280
IN+
IN-
Figure 34. 2:1 Coax Splitter Connection Diagram
HS/DE. Set HVTRMODE = 0 (D4 of register 0x15) to
disable full periodic tracking. HS/VS/DE tracking can be
turned on in 24-bit and 32-bit modes to track and correct
against bit errors in HS/VS/DE link bits.
GMSL
SERIALIZER
MAX9276
MAX9280
OUT+
Serial Input
IN+
IN-
The device can receive serial data from two kinds of
cable: 100Ω twisted pair and 50Ω coax. (Contact the fac-
tory for devices compatible with 75Ω cables).
OUT-
AVDD
OPTIONAL COMPONENTS FOR
INCREASED POWER-SUPPLY
REJECTION
Coax Splitter Mode
50Ω
In coax mode, OUT+ and OUT- of the serializer are active.
This enables the use as a 1:2 splitter (Figure 34). In coax
mode, connect OUT+ to IN+ of the deserializer. Connect
OUT- to IN- of the second deserializer. Control channel
data is broadcast from the serializer to both deserializers
and their attached peripherals. Assign a unique address
to send control data to one deserializer. Leave all unused
IN_ pins unconnected, or connect them to ground through
50Ω and a capacitor for increased power-supply rejection.
Figure 35. Coax Connection Diagram
Table 10. Configuration Input Map
CX/TP
High
Mid
FUNCTION
Coax+ input. 7-bit device address is XXXXXX0 (bin).
Coax- input. 7-bit device address is XXXXXX1 (bin).
If OUT- is not used, connect OUT- to V
through a 50Ω
DD
Twisted pair input. 7-bit device address is
XXXXXX0 (bin).
resistor (Figure 35). When there are µCs at the serializer,
and at each deserializer, only one µC can communicate
at a time. Disable forward and reverse channel links
according to the communicating deserializer connection
to prevent contention in I C to I C mode. Use ENREVP
or ENREVN register bits to disable/enable the control
channel link. In UART mode, the serializer provides
arbitration of the control channel link.
Low
HS/VS/DE Tracking
2
2
The deserializer has tracking to filter out HS/VS/DE bit or
packet errors. HS/VS/DE tracking is on by default when
the device is in high-bandwidth mode (BWS = open),
and off by default when in 24-bit or 32-bit mode (BWS =
low or high). Set/clear HVTREN (D6 of register 0x15) to
enable/disable HS/VS tracking. Set/clear DETREN (D5 of
register 0x15) to enable/disable DE tracking. By default,
the device uses a partial and full periodic tracking of
Cable Type Configuration Input
CX/TP determine the power-up state of the serial input.
In coax mode, CX/TP also determine which coax input is
active, along with the default device address (Table 10).
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
0x00 for LUTADDR and 0x00 as the number of bytes field
in UART packet, when reading a 256-byte data block.
Color Lookup Tables
The deserializer includes 3 color lookup tables (LUT) to
support automatic translation of RGB pixel values. This
feature can be used for color gamma correction, bright-
ness/contrast or for other purposes. There are 3 lookup
tables, each 8 bits wide and 256 entries deep, enabling a
1 to 1 translation of 8-bit input values to any 8-bit output
value for each color (24-bits total).
LUT Color Translation
After power-up or going out of sleep or power-down
modes, LUT translation is disabled and LUT contents
are unknown. After program and verify operations
are finished, in order to enable LUT translations, set
LUTPROG bit to 0 and set the respective LUT enable bits
(RED_LUT_EN, GRN_LUT_EN, BLU_LUT_EN) to 1 to
enable the desired LUT translation function. Only the
selected colors are translated by the LUT (the other col-
ors are not touched). The µC does not need to fill in all
three color lookup tables if all 3 color translations are not
needed.
Programming and Verifying LUT Data
The µC must set the LUTPROG register bit to 1 before
programming and verifying the tables. To program a LUT,
the µC generates a write packet with register address
set to the assigned register address for respective LUT
(0x7D, 0x7E, or 0x7F). The deserializer writes data in
the packet to the respective LUT starting from the LUT
address location set in LUTADDR register. Successive
bytes in the data packet are written to the next LUT
address location, however each new data packet write
starts from the address location stored in the LUTADDR
register. Use 0x00 for LUTADDR and 0x00 as the number
of bytes field in UART packet, when writing a 256 byte
data-block, because 8-bit wide number of bytes field
cannot normally represent 9-bit wide “256” value. There
After a pixel is deserialized decoded and decrypted (if
necessary) it is segmented into its color components Red,
Green and Blue according to Table 11 and Figure 36. If
LUT translation is enabled, each 8-bit pre-translation color
value is used as address to the respective LUT table to
look up the corresponding (translated) 8-bit color value.
LUT Bit Width
In 32-bit mode and high-bandwidth mode, 24 bits are
available for color data (8 bits per color) and each LUT will
be used for 8-bit to 8-bit color translation. In 24-bit mode,
the deserializer can receive only up to 18-bit color (6 bits
per color). The LUT tables can translate from 6-bit to 6-bit,
using the first 64 locations (0x00 to 0x3F). program the
MSB 2 bits of each LUT value to 00. Alternatively, pro-
gram full 8-bit values to each LUT for 6-bit to 8-bit color
translation.
2
2
is no number of bytes field in I C-to-I C modes.
To readback the contents of an LUT, the µC generates
a read packet with register address set to the assigned
register address for respective LUT (0x7D, 0x7E, or
0x7F). the deserializer outputs read data from the respec-
tive LUT starting from the LUT address location set in
LUT_ADDR register. Similar to the write operation, use
Table 11. Pixel Data Format
DOUT
[5:0]
DOUT
[11:6]
DOUT
[17:12]
DOUT
18
DOUT
19
DOUT
20
DOUT
[22:21]
DOUT
[24:23]
DOUT
[26:25]
R[5:0]
G[5:0]
B[5:0]
HS
VS
DE
R[7:6]
G[7:6]
B[7:6]
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
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32-BIT OR HIGH-
BANDWIDTH MODE
32-BIT OR HIGH-
BANDWIDTH MODE
32-BIT OR HIGH-
BANDWIDTH MODE
R7
R6
G7
G6
B7
B6
24-BIT MODE
0
0
24-BIT MODE
0
0
24-BIT MODE
0
0
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
LSB
LSB
LSB
MSB
MSB
MSB
REDLUTEN
GRNLUTEN
BLULUTEN
ADDR
RED LUT
EN
ADDR
GREEN LUT
ADDR
BLUE LUT
EN
EN
DATA
DATA
DATA
LSB
LSB
LSB
MSB
MSB
MSB
OUTPUT DOUT DOUT
DOUT DOUT DOUT DOUT
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0
DOUT9 DOUT8 DOUT7 DOUT6
PIN
22
21
24
23
11
10
26
25
17
16
15
14
13
12
OUTPUT
SIGNAL
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
Figure 36. LUT Dataflow
4) Repeat steps 2 and 3 for the green LUT, using 0x7E
Recommended LUT Program Procedure
as the register address
1) Write LUTPROG = 1 to register 0x7C. Keep
BLULUTEN = 0, GRNLUTEN = 0, REDLUTEN = 0
(write 0x08 to register 0x7C).
5) Repeat steps 2 and 3 for the blue LUT, using 0x7F as
the register address
2) Write contents of red LUT with a single write packet.
For 24-bit RGB, use 0x7D as register address and
0x00 as number of bytes (UART only) and write 256
bytes. For 18-bit RGB, use 0x7D as register address
and 0x40 as number of bytes (UART only) and write 64
bytes. (Optional: Multiple write packets can be used if
LUTADDR is set before each LUT write packet.)
6a) To finish the program and verify routine, without
enabling the LUT color translation, write LUTPROG =
0 (Write 0x00 to register 0x7C).
6b) To finish the program and verify routine, and start LUT
color translation, write LUTPROG = 0, BLULUTEN =
1, GRNLUTEN = 1, REDLUTEN = 1 (Write 0x07 to
register 0x7C).
3) Read contents of red LUT and verify that they are
correct. Use the same register address and number
of bytes used in the previous step.
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
Table 12. Reverse Control-Channel Modes
2
HIGHIMM BIT OR
SD/HIM PIN SETTING
REVFAST
MAX UART/I C BIT RATE
REVERSE CONTROL-CHANNEL MODE
BIT
(kbps)
Legacy reverse control-channel mode
(compatible with all GMSL devices)
LOW (1)
X
1000
0
High-immunity mode
500
HIGH (1)
1
Fast high-immunity mode
1000
X = Don’t care
Sleep Mode
Table 13. Fast High-Immunity Mode
Requirements
The deserializers have sleep mode to reduce power
consumption. The devices enter or exit sleep mode by a
command from a remote µC using the control channel.
Set the SLEEP bit to 1 to initiate sleep mode. Entering
sleep mode resets the HDCP registers, but not the con-
figuration registers. The deserializer sleeps after serial
link inactivity or 8ms (whichever arrives first) after setting
its SLEEP = 1. See the Link Startup Procedure section
for details on waking up the device for different µC and
starting conditions.
ALLOWED PCLKOUT FREQUENCY
BWS SETTING
(MHz)
Low
High
Open
> 41.66
> 30
> 83.33
Fast high-immunity mode requires DRS = 0
High-Immunity Reverse Control Channel Mode
The deserializer contains a high-immunity reverse con-
trol channel mode, which has increased robustness at
half the bit rate over the standard GMSL reverse control
channel link (Table 12). Connect a 30kΩ resistor to GPO/
HIM on the serializer, and SD/HIM on the deserializer to
use high-immunity mode at power-up. Set the HIGHIMM
bit high in both the serializer and deserializer to enable
high-immunity mode at any time after power-up. Set the
HIGHIMM bit low in both the serializer and deserializer
to use the legacy reverse control channel mode. The
deserializer reverse channel mode is not available for
500µs/1.92ms after the reverse control channel mode is
changed through the serializer/deserializer’s HIGHIMM
bit setting respectively. The user must set SD/HIM and
GPO/HIM or the HIGHIMM bits to the same value for
proper reverse control channel communication.
To wake up from the local side, send an arbitrary control
channel command to deserializer, wait for 5ms for the
chip to power up and then write 0 to SLEEP register bit
to make the wake-up permanent. To wake up from the
remote side, enable serialization. The deserializer will
detect the activity on serial link and then when it locks, it
will automatically set its SLEEP register bit to 0.
Power-Down Mode
The deserializers have a power-down mode which fur-
ther reduces power consumption compared to Sleep
Mode. Set PWDN low to enter power-down mode. In
power-down, the parallel outputs remain high impedance.
Entering power-down resets the device’s registers. Upon
exiting power-down, the state of external pins ADD[2:0],
CX/TP, I2CSEL, SD/HIM, and BWS are latched.
In high-immunity mode, Set HPFTUNE = 00 in the equal-
izer, if the serial bit rate = [PCLKOUT x 30 (BWS = low
or open) or 40 (BWS = high)] is larger than 1Gbps when
BWS is low or high. When BWS = open, set HPFTUNE =
00 when the serial bit rate is larger than 2GBps. In addi-
tion, use 47nF AC-coupling capacitors. Note that legacy
reverse-control channel mode may not function when
using 47nF AC-coupling capacitors.
Configuration Link
The control channel can operate in a low-speed mode
called configuration link in the absence of a clock input.
This allows a microprocessor to program configuration
registers before starting the video link. An internal oscil-
lator provides the clock for the configuration link. Set
CLINKEN = 1 on the serializer to enable configuration
link. Configuration link is active until the video link is
enabled. The video link overrides the configuration link
and attempts to lock when SEREN = 1.
By default, high-immunity mode uses a 500kbps bit rate.
Set REVFAST =1 (D7 in register 0x1A in the serializer and
register 0x11 in the deserializer) in both devices to use a
1Mbps bit rate. Certain limitations apply when using the
fast high-immunity mode (Table 13).
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
after the video link or the configuration link is established.
If the deserializer powers up after the serializer, the con-
trol channel becomes unavailable for 2ms after power-up.
Link Startup Procedure
Table 14 lists the startup procedure for display applica-
tions. Table 15 lists the startup procedure for image-
sensing applications. The control channel is available
Table 14. Startup Procedure for Video-Display Applications
SERIALIZER
NO.
µC
DESERIALIZER
(AUTOSTART ENABLED)
(AUTOSTART DISABLED)
Sets all configuration
Sets all configuration
Sets all configuration
inputs. If any configuration
inputs are available on one
end of the link but not the
other, always connects that
configuration input low.
inputs. If any configuration
inputs are available on one
end of the link but not the
other, always connects that
configuration input low.
inputs. If any configuration
inputs are available on one
end of the link but not the
other, always connects that
configuration input low
—
µC connected to serializer
Powers up and loads default
settings. Establishes video
link when valid PCLK
available
Powers up and loads default
settings. Locks to video link
signal if available.
Powers up and loads default
settings
1
Powers up
Enables serial link by setting
SEREN = 1 or configuration
link by setting SEREN = 0
and CLINKEN = 1 (if valid
PCLK not available) and gets
an acknowledge. Waits for
link to be establish (~3ms)
Establishes configuration or
video link
Locks to configuration or
video link signal
2
3
Writes configuration bits in
the serializer/deserializer and Configuration changed from default settings
gets an acknowledge.
Configuration changed from
default settings
If not already enabled,
sets SEREN = 1, gets an
Establishes video link when valid PCLK available (if not
acknowledge and waits for
Locks to video link signal (if
not already locked)
4
already enabled)
video link to be established
(~3ms)
Begin sending video data to
Video data received and
deserialized
5
Video data serialized and sent across serial link
input
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3.12Gbps GMSL Deserializers
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Table 15. Startup Procedure for Image-Sensing Applications (CDS = High)
SERIALIZER
NO.
µC
DESERIALIZER
(AUTOSTART ENABLED)
(AUTOSTART DISABLED)
Sets all configuration
inputs
—
µC connected to deserializer
Sets all configuration inputs Sets all configuration inputs
Powers up and loads
Powers up and loads
default settings.
Powers up and loads
default settings.
Locks to video link
signal if available.
1
Powers up
default settings. Goes to
Establishes video link when
sleep after 8ms.
valid PCLK available.
Configuration
changed from default
settings
Writes deserializer configuration bits
and gets an acknowledge
2
Wakes up the serializer by sending
dummy packet, and then writing
SLEEP = 0 within 8ms. May not get
an acknowledge (or gets a dummy
acknowledge) if not locked.
3
Wakes up
Writes serializer configuration bits.
May not get an acknowledge (or gets
a dummy acknowledge) if not locked.
4
Configuration changed from default settings
If not already enabled, sets SEREN =
1, gets an acknowledge and waits for
serial link to be established (~3ms)
Locks to video link
signal (if not already
locked)
Establishes video link when valid PCLK available (if not
already enabled)
5
6
Video data received
and deserialized
Begin sending video data to input
Video data serialized and sent across serial link
SLEEP = 1, VIDEO LINK OR CONFIG
LINK NOT LOCKED AFTER 8ms
CONFIG LINK
CONFIG LINK
OPERATING
UNLOCKED
WAKE-UP
SIGNAL
SIGNAL
POWER-ON
IDLE
SERIAL PORT
LOCKING
SLEEP
DETECTED
PROGRAM
REGISTERS
CONFIG LINK
LOCKED
0
SLEEP
VIDEO LINK
LOCKED
VIDEO LINK
UNLOCKED
SERIAL LINK ACTIVITY STOPS OR 8ms ELAPSES AFTER
µC SETS SLEEP = 1
PWDN = HIGH,
POWER-ON
GPI CHANGES FROM
LOW TO HIGH OR
PRBSEN = 0
PRBSEN = 1
SEND GPI TO
POWER-DOWN
VIDEO LINK
OPERATING
VIDEO LINK
PRBS TEST
HIGH TO LOW
PWDN = LOW OR
ALL STATES
OR
POWER-OFF
POWER-OFF
GMSL
SERIALIZER
0
SLEEP
Figure 37. State Diagram
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
every 128 frames. These values are compared internally
(internal comparison mode) or can be compared in the
host µC.
High-Bandwidth Digital Content
Protection (HDCP)
Note: The explanation of HDCP operation in this data
sheet is provided as a guide for general understanding.
Implementation of HDCP in a product must meet the
requirements given in the HDCP System v1.3 Amendment
for GMSL, which is available from DCP.
In addition, the GMSL serializer/deserializer provide
response values for the enhanced link verification.
Enhanced link verification is an optional method of link
verification for faster detection of loss-of-synchronization.
For this option, the GMSL serializer and deserializer
generate 8-bit enhanced link-verification response values
(PJ and PJ’) every 16 frames. The host must detect three
consecutive PJ/PJ’ mismatches before resampling.
HDCP has two main phases of operation: authentication
and the link integrity check. The µC starts authentica-
tion by writing to the START_AUTHENTICATION bit in
the GMSL serializer. The GMSL serializer generates a
64-bit random number. The host µC first reads the 64-bit
random number from the GMSL serializer and writes it
to the deserializer. The µC then reads the GMSL serial-
izer public key selection vector (AKSV) and writes it to
the deserializer. The µC then reads the deserializer KSV
(BKSV) and writes it to the GMSL serializer. The µC
begins checking BKSV against the revocation list. Using
the cipher, the GMSL serializer and deserializer calculate
a 16-bit response value, R0 and R0’, respectively. The
GMSL amendment for HDCP reduces the 100ms mini-
mum wait time allowed for the receiver to generate R0’
(specified in HDCP rev 1.3) to 128 pixel clock cycles in
the GMSL amendment.
Encryption Enable
The GMSL link transfers either encrypted or nonen-
crypted data. To encrypt data, the host µC sets the
encryption enable (ENCRYPTION_ENABLE) bit in both
the GMSL serializer and deserializer. The µC must set
ENCRYPTION_ENABLE in the same VSYNC cycle in
both the GMSL serializer and deserializer (no internal
VSYNC falling edges between the two writes). The same
timing applies when clearing ENCRYPTION_ENABLE to
disable encryption.
Note: ENCRYPTION_ENABLE enables/disables encryp-
tion on the GMSL irrespective of the content. To comply
with HDCP, the µC must not allow content requiring
encryption to cross the GMSL unencrypted.
There are two response-value comparison modes: internal
comparison and µC comparison. Set EN_INT_COMP = 1
to select internal comparison mode. Set EN_INT_COMP
= 0 to select µC comparison mode. In internal compari-
son mode, the µC reads the deserializer response R0’
and writes it to the GMSL serializer. The GMSL serializer
compares R0’ to its internally generated response value
R0, and sets R0_RI_MATCHED. In µC comparison mode,
the µC reads and compares the R0/R0’ values from the
GMSL serializer/deserializer.
The µC must complete the authentication process before
enabling encryption. In addition, encryption must be dis-
abled before starting a new authentication session.
Synchronization of Encryption
The video vertical sync (VSYNC) synchronizes the start
of encryption. Once encryption has started, the GMSL
generates a new encryption key for each frame and each
line, with the internal falling edge of VSYNC and HSYNC.
Rekeying is transparent to data and does not disrupt the
encryption of video or audio data.
During response-value generation and comparison, the
host µC checks for a valid BKSV (having 20 1s and 20
0s is also reported in BKSV_INVALID) and checks BKSV
against the revocation list. If BKSV is not on the list and
the response values match, the host authenticates the
link. If the response values do not match, the µC resam-
ples the response values (as described in HDCP rev 1.3,
Appendix C). If resampling fails, the µC restarts authen-
tication by setting the RESET_HDCP bit in the GMSL
serializer. If BKSV appears on the revocation list, the host
cannot transmit data that requires protection. The host
knows when the link is authenticated and decides when
to output data requiring protection. The µC performs a link
integrity check every 128 frames or every 2s ±0.5s. The
GMSL serializer/deserializer generate response values
Repeater Support
The GMSL serializer/deserializer include features to build
an HDCP repeater. An HDCP repeater receives and
decrypts HDCP content and then encrypts and transmits
on one or more downstream links. A repeater can also use
decrypted HDCP content (e.g., to display on a screen).
To support HDCP repeater-authentication protocol, the
deserializer has a REPEATER register bit. This register
bit must be set to 1 by a µC (most likely on the repeater
module). Both the GMSL serializer and deserializer use
SHA-1 hash-value calculation over the assembled KSV
lists. HDCP GMSL links support a maximum of 15 receiv-
ers (total number including the ones in repeater modules).
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If the total number of downstream receivers exceeds 14,
the µC must set the MAX_DEVS_EXCEEDED register bit
when it assembles the KSV list.
(refer to the HDCP 1.3 Amendment for GMSL for details).
The µC must perform link integrity checks while encryp-
tion is enabled (see Table 17). Any event that indicates
that the deserializer has lost link synchronization should
retrigger authentication. The µC must first write 1 to the
RESET_HDCP bit in the GMSL serializer before starting
a new authentication attempt.
HDCP Authentication Procedures
The GMSL serializer generates a 64-bit random number
exceeding the HDCP requirement. The GMSL serial-
izer/deserializer internal one-time programmable (OTP)
memories contain a unique HDCP keyset programmed at
the factory. The host µC initiates and controls the HDCP
authentication procedure. The GMSL serializer and dese-
rializer generate HDCP authentication response values
for the verification of authentication. Use the following
procedures to authenticate the HDCP GMSL encryption
HDCP Protocol Summary
Table 10, Table 11, and Table 12 list the summaries of the
HDCP protocol. These tables serve as an implementation
guide only. Meet the requirements in the GMSL amend-
ment for HDCP to be in full compliance.
Table 16. Startup, HDCP Authentication, and Normal Operation (Deserializer is Not a
Repeater)—First Part of the HDCP Authentication Protocol
NO.
µC
HDCP GMSL SERIALIZER
HDCP GMSL DESERIALIZER
Powers up waiting for HDCP
authentication.
Powers up waiting for HDCP
authentication.
1
Initial state after power-up.
Makes sure that A/V data not requiring
protection (low-value content) is available at
the GMSL serializer inputs (such as blue or
informative screen). Alternatively, uses the
FORCE_VIDEO and FORCE_AUDIO bits of
the GMSL serializer to mask A/V data at the
input of the GMSL serializer. Starts the link by
writing SEREN = H or link starts automatically
if AUTOS is low.
2
—
—
Starts serialization and transmits Locks to incoming data stream and
3
—
low-value content A/V data.
outputs low-value content A/V data.
Reads the locked bit of the deserializer and
makes sure the link is established.
4
—
—
Combines seed with internally
generated random number. If
no seed provided, only internal
random number is used.
Optionally writes a random-number seed to
the GMSL serializer.
5
6
—
—
If HDCP encryption is required, starts
authentication by writing 1 to the
START_AUTHENTICATION bit of the GMSL
serializer.
Generates (stores) AN, and
resets the
START_AUTHENTICATION bit
to 0.
Reads AN and AKSV from the GMSL serializer
and writes to the deserializer.
Generates R0’ triggered by the µC’s
write of AKSV.
7
8
—
Generates R0, triggered by the
µC’s write of BKSV.
Reads the BKSV and REPEATER bit from
deserializer and writes to the GMSL serializer.
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Table 16. Startup, HDCP Authentication, and Normal Operation (Deserializer is Not a
Repeater)—First Part of the HDCP Authentication Protocol (continued)
NO.
µC
HDCP GMSL SERIALIZER
HDCP GMSL DESERIALIZER
Reads the INVALID_BKSV bit of the GMSL
serializer and continues with authentication
if it is 0. Authentication can be restarted if it
fails (set RESET_HDCP = 1 before restarting
authentication).
9
—
—
Reads R0’ from the deserializer and reads
R0 from the GMSL serializer. If they match,
continues with authentication; otherwise,
retries up to two more times (optionally, GMSL
serializer comparison can be used to detect if
R0/R0’ match). Authentication can be restarted
if it fails (set RESET_HDCP = 1 before
restarting authentication).
10
—
—
Waits for the VSYNC falling edge (internal to
the GMSL serializer) and then sets the
ENCRYPTION_ENABLE bit to 1 in the
deserializer and GMSL serializer (if the FC is
not able to monitor VSYNC, it can utilize the
VSYNC_DET bit in the GMSL serializer).
Encryption enabled after the
next VSYNC falling edge.
Decryption enabled after the next
VSYNC falling edge.
11
Checks that BKSV is not in the Key
Revocation list and continues if it is not.
Authentication can be restarted if it fails.
Note: Revocation list check can start after
BKSV is read in step 8.
12
13
—
—
Starts transmission of A/V content that needs
protection.
Performs HDCP encryption on
high-value content A/V data.
Performs HDCP decryption on high-
value content A/V data.
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Table 17. Link Integrity Check (Normal)—Performed Every 128 Frames After Encryption
is Enabled
NO.
µC
HDCP GMSL SERIALIZER
HDCP GMSL DESERIALIZER
Generates Ri and updates the
RI register every 128 VSYNC
cycles.
Generates Ri’ and updates the RI’
register every 128 VSYNC cycles.
1
—
Continues to encrypt and
transmit A/V data.
Continues to receive, decrypt, and
output A/V data.
2
3
—
Every 128 video frames (VSYNC cycles) or
every 2s.
—
—
4
Reads RI from the GMSL serializer.
Reads RI’ from the deserializer.
—
—
—
—
5
Reads RI again from the GMSL serializer and
makes sure it is stable (matches the previous
RI that it has read from the GMSL serializer). If
RI is not stable, go back to step 5.
6
7
—
—
—
—
If RI matches RI’, the link integrity check is
successful; go back to step 3.
If RI does not match RI’, the link integrity
check fails. After the detection of failure of
link integrity check, the FC makes sure that
A/V data not requiring protection (low-value
content) is available at the GMSL serializer
inputs (such as blue or informative screen).
Alternatively, the FORCE_VIDEO and
FORCE_AUDIO bits of the GMSL serializer
can be used to mask A/V data input of the
GMSL serializer.
8
—
—
Disables encryption and
transmits low-value content A/V
data.
Writes 0 to the ENCRYPTION_ENABLE bit of
the GMSL serializer and deserializer.
Disables decryption and outputs low-
value content A/V data.
9
Restarts authentication by writing 1 to the
RESET_HDCP bit followed by writing 1 to the
START_AUTHENTICATION bit in the GMSL
serializer.
10
—
—
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Table 18. Optional Enhanced Link Integrity Check—Performed Every 16 Frames After
Encryption is Enabled
NO.
µC
HDCP GMSL SERIALIZER
HDCP GMSL DESERIALIZER
Generates PJ and updates the
PJ register every 16 VSYNC
cycles.
Generates PJ’ and updates the PJ’
register every 16 VSYNC cycles.
1
—
Continues to encrypt and
transmit A/V data.
Continues to receive, decrypt, and
output A/V data.
2
3
4
—
Every 16 video frames, reads PJ from the
GMSL serializer and PJ’ from the deserializer.
—
—
—
—
If PJ matches PJ’, the enhanced link integrity
check is successful; go back to step 3.
If there is a mismatch, retry up to two more
times from step 3. Enhanced link integrity
check fails after 3 mismatches. After the
detection of failure of enhanced link integrity
check, the µC makes sure that A/V data not
requiring protection (low-value content) is
available at the GMSL serializer inputs (such
as blue or informative screen). Alternatively,
the FORCE_VIDEO and FORCE_AUDIO bits
of the GMSL serializer can be used to mask
A/V data input of the GMSL serializer.
5
—
—
Disables encryption and
transmits low-value content A/V
data.
Writes 0 to the ENCRYPTION_ENABLE bit of
the GMSL serializer and deserializer.
Disables decryption and outputs low-
value content A/V data.
6
7
Restarts authentication by writing 1 to the
RESET_HDCP bit followed by writing 1 to the
START_AUTHENTICATION bit in the GMSL
serializer.
—
—
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Example Repeater Network—Two µCs
The example shown in Figure 38 has one repeater and two µCs. Table 19 summarizes the authentication operation.
BD-DRIVE
TX_B1
REPEATER
RX_R1
DISPLAY 1
RX_D1
TX_R1
TX_R2
VIDEO
ROUTING
µC_B
DISPLAY 2
RX_D2
MEMORY
WITH SRM
RX_R2
µC_R
VIDEO CONNECTION
CONTROL CONNECTION 1 (µC_B IN BD-DRIVE IS MASTER)
CONTROL CONNECTION 2 (µC_R IN REPEATER IS MASTER)
Figure 38. Example Network with One Repeater and Two µCs (Tx = GMSL Serializer’s, Rx = Deserializer’s)
Table 19. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol
HDCP GMSL
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
HDCP GMSL
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
NO.
µC_B
µC_R
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
All: Power-up waiting for
HDCP authentication.
All: Power-up waiting for
HDCP authentication.
1
Initial state after power-up.
Initial state after power-up.
Writes REPEATER = 1 in
RX_R1. Retries until proper
acknowledge frame received.
Note: This step must be
completed before the first part
of authentication is started
between TX_B1 and RX_R1 by
the µC_B (step 7). For example,
to satisfy this requirement,
RX_R1 can be held at power-
down until µC_R is ready to
write the REPEATER bit, or
µC_B can poll µC_R before
starting authentication.
2
—
—
—
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Table 19. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol (continued)
HDCP GMSL
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
HDCP GMSL
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
NO.
µC_B
µC_R
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
Makes sure that A/V data
not requiring protection (low-
value content) is available at
the TX_B1 inputs (such as
blue or informative screen).
Alternatively, the FORCE_
VIDEO and FORCE_AUDIO
bits of TX_B1 can be used to
mask A/V data input of TX_B1.
Starts the link between TX_B1
and RX_R1 by writing SEREN
= H to TX_B1, or link starts
automatically if AUTOS is low.
TX_B1: Starts
RX_R1: Locks to
serialization and
transmits low-value
content A/V data.
incoming data stream
and outputs low-value
content A/V data.
3
—
Starts all downstream links
by writing SEREN = H to
TX_R1, TX_R2, or links start
automatically if AUTOS of
transmitters are low.
TX_R1, TX_R2: Starts
serialization and
transmits low-value
content A/V data.
RX_D1, RX_D2: Locks
to incoming data stream
and outputs low-value
content A/V data.
4
—
Reads the locked bit of RX_D1
and makes sure the link
Reads the locked bit of RX_R1
and makes sure the link
between TX_B1 and RX_R1 is
established.
between TX_R1 and RX_D1 is
established. Reads the locked
bit of RX_D2 and makes sure
the link between TX_R2 and
RX_D2 is established.
5
—
—
Writes 1 to the
GPIO_0_FUNCTION and
GPIO_1_FUNCTION bits
in RX_R1 to change GPIO
functionality used for HDCP
purpose. Optionally, writes a
random-number seed to TX_R1
and TX_R2.
Optionally, writes a random
number seed to TX_B1.
6
7
—
—
Starts and completes the
TX_B1: According
to commands from
µC_B, generates AN,
computes R0.
RX_R1: According to
commands from µC_B,
computes R0’.
first part of the authentication
protocol between TX_B1, RX_R1
(see steps 6–10 in Table 10).
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Table 19. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol (continued)
HDCP GMSL
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
HDCP GMSL
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
NO.
µC_B
µC_R
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
When GPIO_1 = 1 is detected,
starts and completes the first part TX_R1, TX_R2:
RX_D1, RX_D2:
of the authentication protocol
between the (TX_R1, RX_D1)
and (TX_R2, RX_D2) links (see
steps 6–10 in Table 10).
According to commands According to commands
8
—
from µC_R, generates
AN, computes R0.
from µC_R, computes
R0’.
Waits for the VSYNC falling
edge and then enables
encryption on the (TX_B1,
RX_R1) link. Full authentication
is not complete yet so it makes
sure A/V content that needs
protection is not transmitted.
Since REPEATER = 1 was read
from RX_R1, the second part of
authentication is required.
TX_B1: Encryption
enabled after next
VSYNC falling edge.
RX_R1: Decryption
enabled after next
VSYNC falling edge.
9
—
When GPIO_0 = 1 is detected,
enables encryption on the
(TX_R1, RX_D1) and (TX_R2,
RX_D2) links.
TX_R1, TX_R2:
Encryption enabled
after next VSYNC
falling edge.
RX_D1, RX_D2:
Decryption enabled
after next VSYNC
falling edge.
10
11
—
RX_R1: Control
Blocks control channel
channel from serializer
side (TX_B1) is blocked
after FWDCCEN =
REVCCEN = 0 is
written.
from µC_B side by setting
REVCCEN = FWDCCEN = 0
in RX_R1. Retries until proper
acknowledge frame received.
—
—
Waits for some time to allow
µC_R to make the KSV list
ready in RX_R1. Then polls
(reads) the KSV_LIST_READY
bit of RX_R1 regularly until
proper acknowledge frame is
received and bit is read as 1.
RX_R1: Triggered by
µC_R’s write of BINFO,
calculates hash value
(V’) on the KSV list,
BINFO and the secret-
value M0’.
Writes BKSVs of RX_D1 and
RX_D2 to the KSV list in RX_
R1. Then, calculates and writes
the BINFO register of RX_R1.
12
13
Writes 1 to the KSV_LIST_
READY bit of RX_R1 and then
unblocks the control channel
from the µC_B side by setting
REVCCEN = FWDCCEN = 1 in
RX_R1.
RX_R1: Control channel
from the serializer side
(TX_B1) is unblocked
after FWDCCEN =
REVCCEN = 1 is
written.
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Table 19. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol (continued)
HDCP GMSL
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
HDCP GMSL
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
NO.
µC_B
µC_R
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
Reads the KSV list and BINFO
from RX_R1 and writes them
to TX_B1. If any of the MAX_
DEVS_EXCEEDED or MAX_
CASCADE_EXCEEDED bits
is 1, then authentication fails.
Note: BINFO must be written
after the KSV list.
TX_B1: Triggered by
µC_B’s write of BINFO,
calculates hash value
(V) on the KSV list,
BINFO and the secret-
value M0.
14
15
—
—
—
—
Reads V from TX_B1 and V’
from RX_R1. If they match,
continues with authentication;
otherwise, retries up to two
more times.
—
Searches for each KSV in the
KSV list and BKSV of RX_R1 in
the Key Revocation list.
16
17
18
—
—
—
—
—
—
—
If keys are not revoked,
the second part of the
authentication protocol is
completed.
All: Perform HDCP
encryption on high-
value A/V data.
All: Perform HDCP
decryption on high-
value A/V data.
Starts transmission of A/V
content that needs protection.
Use the following procedure to notify downstream links of
the start of a new authentication request:
Detection and Action Upon New Device
Connection
When a new device is connected to the system, the
device must be authenticated and the device’s KSV
checked against the revocation list. The downstream
µCs can set the NEW_DEV_CONN bit of the upstream
receiver and invoke an interrupt to notify upstream µCs.
1) Host µC begins authentication with the HDCP repeat-
er’s input receiver.
2) When AKSV is written to HDCP repeater’s input
receiver, its AUTH_STARTED bit is automatically set
and its GPIO1 goes high (if GPIO1_FUNCTION is set
to high).
Notification of Start of Authentication and
Enable of Encryption to Downstream Links
HDCP repeaters do not immediately begin authentication
upon startup or detection of a new device, but instead wait
for an authentication request from the upstream transmit-
ter/repeaters.
3) HDCP repeater’s µC waits for a low-to-high transition
on HDCP repeater input receiver’s AUTH_STARTED
bit and/or GPIO1 (if configured) and starts authentica-
tion downstream.
4) HDCP repeater’s µC resets the AUTH_STARTED bit.
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Set GPIO0_FUNCTION to high to have GPIO0 follow the
ENCRYPTION_ENABLE bit of the receiver. The repeater
µC can use this function for notification when encryption
is enabled/disabled by an upstream µC.
applications. However, a µC can reside on each side
simultaneously, and trade off running the control channel.
In this case, each µC can communicate with the serializer
and deserializer and any peripheral devices.
Contention will occur if both µCs attempt to use the
control channel at the same time. It is up to the user
to prevent this contention by implementing a higher
level protocol. In addition, the control channel does not
Applications Information
Self PRBS Test
The serializers include a PRBS pattern generator which
works with bit-error verification in the deserializer. To
run the PRBS test, disable encryption (if used), set
DISHSFILT, DISVSFILT, and DISDEFILT to ‘1’, to disable
glitch filter in the deserializer. Then, set PRBSEN = 1
(0x04, D5) in the serializer and then in the deserializer.
To exit the PRBS test, set PRBSEN = 0 (0x04, D5) in the
deserializer and then in the serializer.
2
provide arbitration between I C masters on both sides of
the link. An acknowledge frame is not generated when
communication fails due to contention. If communication
across the serial link is not required, the µCs can disable
the forward and reverse control channel using the
FWDCCEN and REVCCEN bits (0x04, D[1:0]) in the
serializer/deserializer. Communication across the serial
link is stopped and contention between µCs cannot occur.
Error Checking
As an example of dual µC use in an image-sensing
application, the serializer can be in sleep mode and
waiting for wake-up by µC on the deserializer side. After
wake-up, the serializer-side µC assumes master control
of the serializer’s registers.
The deserializers check the serial link for errors and
store the number of decoding errors in the 8-bit registers
DECERR (0x0D). If a large number of decoding errors
are detected within a short duration (error rate ≥ 1/4), the
deserializers lose lock and stop the error counter. The
deserializers then attempt to relock to the serial data.
DECERR reset upon successful video link lock, suc-
cessful readout of the register (through µC), or whenever
auto error reset is enabled. The deserializers use a sepa-
rate PRBS Register during the internal PRBS test, and
DECERR are reset to 0x00.
Changing the Clock Frequency
It is recommended that the serial link be enabled after
the video clock (f
) and the control-channel
PCLKOUT
clock (f /f ) are stable. When changing the clock
UART I2C
frequency, stop the video clock for 5µs, apply the clock
at the new frequency, then restart the serial link or toggle
SEREN. On-the-fly changes in clock frequency are
possible if the new frequency is immediately stable and
without glitches. The reverse control channel remains
unavailable for 500µs after serial link start or stop. When
using the UART interface, limit on-the-fly changes in
ERR Output
The deserializers have an open-drain ERR output. This
output asserts low whenever the number of decoding
errors exceeds the error thresholds during normal opera-
tion, or when at least 1 PRBS error is detected during
PRBS test. ERR reasserts high whenever DECERR
resets, due to DECERR readout, video link lock, or auto
error reset.
f
to factors of less than 3.5 at a time to ensure
UART
that the device recognizes the UART sync pattern. For
example, when lowering the UART frequency from 1Mbps
to 100kbps, first send data at 333kbps then at 100kbps for
reduction ratios of 3 and 3.333, respectively.
Auto Error Reset
The default method to reset errors is to read the respec-
tive error registers in the deserializers (0x0D and 0x0E).
Auto error reset clears the error counters DECERR and
the ERR output ~1µs after ERR goes low. Auto error reset
is disabled on power-up. Enable auto error reset through
AUTORST (0x06, D5). Auto error reset does not run when
the device is in PRBS test mode.
Fast Detection of Loss of Synchronization
A measure of link quality is the recovery time from loss of
synchronization. The host can be quickly notified of loss-
of-lock by connecting the deserializer’s LOCK output to
the GPI input. If other sources use the GPI input, such as
a touch-screen controller, the µC can implement a routine
to distinguish between interrupts from loss-of-sync and
normal interrupts. Reverse control-channel communica-
tion does not require an active forward link to operate
and accurately tracks the LOCK status of the GMSL link.
LOCK asserts for video link only and not for the configura-
tion link.
Dual µC Control
Usually systems have one microcontroller to run the
control channel, located on the serializer side for display
applications or on the deserializer side for image-sensing
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high level, a pulldown resistor to GND to set a low level, or
open to set a mid level. For digital control, use three-state
logic to drive the 3-level logic input.
Providing a Frame Sync (Camera
Applications)
The GPI/GPO provide a simple solution for camera
applications that require a Frame Sync signal from the
ECU (e.g. surround view systems). Connect the ECU
Frame Sync signal to the GPI input, and connect GPO
output to the camera Frame Sync input. GPI/GPO has
a typical delay of 275µs. Skew between multiple GPI/
GPO channels is typically 115µs. If a lower skew signal
is required, connect the camera’s frame sync input one of
Configuration Blocking
The deserializers can block changes to registers. Set
CFGBLOCK to make registers 0x00 to registers 0x1F as
read only. Once set, the registers remain blocked until the
supplies are removed or until PWDN is low.
Compatibility with Other GMSL Devices
2
the deserializer’s GPIOs and use an I C broadcast write
The deserializers are designed to pair with the MAX9275–
MAX9281 serializers but interoperates with any GMSL
serializers. See the Table 20 for operating limitations
command to change the GPIO output state. This has a
maximum skew of 1.5µs, independent from the used I C
bit rate.
2
Key Memory
Software Programming of the Device
Addresses
Each device has a unique HDCP key set that is stored
in secure nonvolatile memory (NVM). The HDCP key set
consists of forty 56-bit private keys and one 40-bit public
key. The NVM is qualified for automotive applications.
The serializers and deserializers have programmable
device addresses. This allows multiple GMSL devices,
2
along with I C peripherals, to coexist on the same control
HS/VS/DE Inversion
channel. The serializer device address is in register 0x00
of each device, while the deserializer device address is in
register 0x01 of each device. To change a device address,
first write to the device whose address changes (register
0x00 of the serializer for serializer device address change,
or register 0x01 of the deserializer for deserializer device
address change). Then write the same address into the
corresponding register on the other device (register 0x00
of the deserializer for serializer device address change,
or register 0x01 of the serializer for deserializer device
address change).
The deserializer uses an active-high HS, VS, and DE
for encoding and HDCP encryption. Set INVHSYNC,
INVVSYNC, and INVDE in the serializer (registers 0x0D,
0x0E) to invert active-low input signals for use with the
GMSL devices. Set INVHSYNC, INVVSYNC, and INVDE
in the deserializer (register 0x0E) to output active-low
signals for use with downstream devices.
WS/SCK Inversion
The deserializer uses standard polarities for I S. Set
2
INVWS, INVSCK in the serializer (register 0x1B) to invert
opposite polarity signals for use with the GMSL devices.
Set INVWS, INVSCK in the deserializer (register 0x1D) to
output reverse-polarity signals for downstream use.
3-Level Configuration Inputs
CX/TP and BWS are 3-level inputs that control the serial
interface configuration and power-up defaults. Connect
3-level inputs through a pullup resistor to IOVDD to set a
Table 20. MAX9276/MAX9280 Feature Compatibility
MAX9276/MAX9280 FEATURE
HDCP (MAX9280 only)
GMSL SERIALIZER
If feature not supported in serializer, must not be turned on in the MAX9280
If feature not supported in serializer, must only use 24-bit and 32-bit modes
High-bandwidth mode
2
2
2
I C to I C
If feature not supported in serializer, must use UART to I C or UART to UART
If feature not supported in serializer, must connect unused serial output through 200nF and
Coax
50Ω in series to V
and set the reverse control channel amplitude to 100mV.
DD
High-immunity control channel
TDM encoding
If feature not supported in serializer, must use the legacy reverse control channel mode
2
If feature not supported in serializer, must use I S encoding (with 50% WS duty cycle), if
supported
2
2
I S encoding
If feature not supported in serializer must disable I S in the MAX9276/MAX9280
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2
even when the device is not in operation. I C specifies
Table 21. Staggered Output Delay
300ns rise times (30% to 70%) for fast mode, which
is defined for data rates up to 400kbps (see the I C
specifications in the AC Electrical Characteristics table
OUTPUT DELAY RELATIVE
TO DOUT0 (ns)
2
OUTPUT
DISSTAG = 0
DISSTAG = 1
for details). To meet the fast-mode rise-time requirement,
choose the pullup resistors so that rise time t = 0.85
DOUT0–DOUT5,
DOUT21, DOUT22
R
0
0.5
1
0
x R
x C
< 300ns. The waveforms are not
BUS
PULLUP
recognized if the transition time becomes too slow. The
DOUT6–DOUT10,
DOUT23, DOUT24
2
0
0
device supports I C/UART rates up to 1Mbps.
DOUT11–DOUT15,
DOUT25, DOUT26
AC-Coupling
AC-coupling isolates the receiver from DC voltages up
to the voltage rating of the capacitor. Capacitors at the
serializer output and at the deserializer input are needed
for proper link operation and to provide protection if either
end of the cable is shorted to a battery. AC-coupling
blocks low-frequency ground shifts and low-frequency
common-mode noise.
DOUT16–DOUT20,
DOUT27, DOUT28
1.5
0
0
PCLKOUT
0.75
GPIOs
Selection of AC-Coupling Capacitors
The deserializers have two open-drain GPIOs available
when not used for HDCP purposes (see the Notification
of Start of Authentication and Enable of Encryption to
Downstream Links section), GPIO1OUT and GPIO0OUT
(0x06, D3 and D1) set the output state of the GPIOs.
Setting the GPIO output bits to ‘0’ low pulls the output low,
while setting the bits to ‘1’ leaves the output undriven, and
pulled high through internal/external pullup resistors. The
GPIO input buffers are always enabled. The input states
are stored in GPIO1 and GPIO0 (0x06, D2 and D0). Set
GPIO1OUT/GPIO0OUT to 1 when using GPIO1/GPIO0
as an input.
Voltage droop and the digital sum variation (DSV) of
transmitted symbols cause signal transitions to start from
different voltage levels. Because the transition time is fixed,
starting the signal transition from different voltage levels
causes timing jitter. The time constant for an AC-coupled
link needs to be chosen to reduce droop and jitter to an
acceptable level. The RC network for an AC-coupled link
consists of the CML/coax receiver termination resistor
(R ), the CML/coax driver termination resistor (R ),
TR
TD
and the series AC-coupling capacitors (C). The RC
time constant for four equal-value series capacitors
is (C x (R
+ R ))/4. R
and R
are required to
TR
TD
TR
TD
Staggered Parallel Outputs
match the transmission line impedance (usually 100Ω
differential, 50Ω single ended). This leaves the capacitor
selection to change the system time constant. Use at
0.22μF (using legacy reverse control channel), 47nF
(using high-immunity reverse control channel), or larger
high-frequency surface-mount ceramic capacitors, with
sufficient voltage rating to withstand a short to battery, to
pass the lower speed reverse control-channel signal. Use
capacitors with a case size less than 3.2mm x 1.6mm to
have lower parasitic effects to the high-speed signal.
The deserializers stagger the parallel data outputs to
reduce EMI and noise. Staggering outputs also reduces
the power-supply transient requirements. By default,
the deserializers stagger outputs according to Table 21.
Disable output staggering through the DISSTAG bit (0x06,
D7).
Internal Input Pulldowns
The control and configuration inputs (except 3-level
inputs) include a pulldown resistor to GND. External pull-
down resistors are not needed.
Power-Supply Circuits and Bypassing
The deserializers use an AVDD and DVDD of 3.0V to
3.6V. All single-ended inputs and outputs except for the
serial input derive power from an IOVDD of 1.7V to 3.6V,
which scale with IOVDD. Proper voltage-supply bypass-
ing is essential for high-frequency circuit stability.
2
Choosing I C/UART Pullup Resistors
2
I C and UART open-drain lines require a pullup resistor
to provide a logic-high level. There are tradeoffs between
power dissipation and speed, and a compromise may
be required when choosing pullup resistor values. Every
device connected to the bus introduces some capacitance
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Power-Supply Table
Cables and Connectors
Power-supply currents shown in the DC Electrical
Characteristics table is the sum of the currents from
AVDD, DVDD, and IOVDD. IOVDD is measured at
Interconnect for CML typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Coax cables typically have a characteristic
impedance of 50Ω, contact the factory for 75Ω operation).
Table 24 lists the suggested cables and connectors used
in the GMSL link.
V
= 3.6V. If using a different IOVDD voltage, the
IOVDD
IOVDD worst-case supply current will vary according to
Table 22. HDCP operation (MAX9280 only) draws addi-
tional current. This is shown in Table 23.
Table 22. IOVDD Current Simulation Results
IOVDD SUPPLY VOLTAGE
IOVDD WORST-CASE SUPPLY CURRENT
1.9V
4.4
3.3V*
7.9
3.6V
8.6
C = 5pF
L
BWS = low,
= 16.6MHz
f
PCLKOUT
C = 10pF
6.4
12.4
14.5
23.1
25.6
40.7
38.7
60.3
18.2
28.9
45
13.5
15.8
25.2
27.9
44.4
42.2
65.8
19.8
31.5
49
L
C = 5pF
8
L
BWS = low,
= 33.3MHz
f
PCLKOUT
C = 10pF
13.2
14.9
23.4
21.6
34.8
10.2
16.6
25.1
40.4
L
C = 5pF
L
BWS = low,
= 66.6MHz
f
PCLKOUT
C = 10pF
L
mA
C = 5pF
L
BWS = low,
= 104MHz
f
PCLKOUT
C = 10pF
L
C = 5pF
L
BWS = mid,
= 36.6MHz
f
PCLKOUT
C = 10pF
L
C = 5pF
L
BWS = mid,
= 104MHz
f
PCLKOUT
C = 10pF
70.2
76.5
L
Table 23. Additional Supply Current from HDCP (MAX9280 Only)
PCLK
(MHz)
MAXIMUM HDCP CURRENT
(mA)
16.6
33.3
36.6
66.6
104
6
9
9
12
18
Table 24. Suggested Connectors and Cables for GMSL
VENDOR
Rosenberger
Rosenberger
Nissei
CONNECTOR
59S2AX-400A5-Y
D4S10A-40ML5-Z
GT11L-2S
CABLE
TYPE
Coax
STP
RG174
Dacar 538
F-2WME AWG28
A-BW-Lxxxxx
STP
JAE
MX38-FF
STP
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Board Layout
R
D
Separate LVCMOS logic signals and CML/coax high-
speed signals to prevent crosstalk. Use a four-layer PCB
with separate layers for power, ground, CML/coax, and
LVCMOS logic signals. Layout PCB traces close to each
other for a 100Ω differential characteristic impedance for
STP. The trace dimensions depend on the type of trace
used (microstrip or stripline). Note that two 50Ω PCB
traces do not have 100Ω differential impedance when
brought close together—the impedance goes down when
the traces are brought closer. Use a 50Ω trace for the
single-ended output when driving coax.
1MΩ
1.5kΩ
CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
100pF
S
STORAGE
CAPACITOR
SOURCE
Figure 39. Human Body Model ESD Test Circuit
Route the PCB traces for differential CML channel in par-
allel to maintain the differential characteristic impedance.
Avoid vias. Keep PCB traces that make up a differential
pair equal length to avoid skew within the differential pair.
R
330Ω
D
CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR
RESISTANCE
ESD Protection
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
ESD tolerance is rated for Human Body Model, IEC
61000-4-2, and ISO 10605. The ISO 10605 and IEC
61000-4-2 standards specify ESD tolerance for electronic
systems. The serial link inputs are rated for ISO 10605
ESD protection and IEC 61000-4-2 ESD protection. All
pins are tested for the Human Body Model. The Human
150pF
SOURCE
Figure 40. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Body Model discharge components are C = 100pF and
S
R
= 1.5kΩ (Figure 39). The IEC 61000-4-2 discharge
D
components are C = 150pF and R = 330Ω (Figure 40).
S
D
R
D
The ISO 10605 discharge components are C = 330pF
2kΩ
S
and R = 2kΩ (Figure 41).
D
CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
330pF
SOURCE
Figure 41. ISO 10605 Contact Discharge ESD Test Circuit
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3.12Gbps GMSL Deserializers
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Table 25. Register Table
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
Serializer device address (power-up default value
XX00XX0
D[7:1]
D0
SERID
—
XXXXXXX
0
depends on latched address pin level)
0x00
Reserved
0
Deserializer device address (power-up default
value depends on latched address pin level).
D[7:1]
DESID
XXXXXXX
XX01XXX
0x01
0
Normal operation
D0
CFGBLOCK
0
1
Registers 0x00 to 0x1F are read only
No spread spectrum.
00
01
10
11
±2% spread spectrum
No spread spectrum
D[7:6]
SS
00
±4% spread spectrum
WS, SCK configured as output (deserializer
sourced clock)
0
D5
D4
AUDIOMODE
AUDIOEN
PRNG
0
1
WS, SCK configured as input (system sourced
clock)
1
2
0
Disable I S/TDM channel
0x02
2
1
Enable I S/TDM channel
00
01
10
11
00
01
10
11
12.5MHz to 25MHz pixel clock
25MHz to 50MHz pixel clock
50MHz to 104MHz pixel clock
Automatically detect the pixel clock range
0.5 to 1Gbps serial data rate
1 to 2Gbps serial data rate
D[3:2]
11
D[1:0]
D[7:6]
SRNG
11
2 to 3.12Gbps serial data rate
Automatically detect serial data rate
Calibrate spread modulation rate only once after
locking
00
01
10
11
Calibrate spread modulation rate every 2ms after
locking
AUTOFM
00
Calibrate spread modulation rate every 16ms after
locking
0x03
Calibrate spread modulation rate every 256ms
after locking
D5
—
0
Reserved
0
00000
Auto calibrate sawtooth divider
Manual SDIV setting. See the Manual
Programming of the Spread-Spectrum Divider
section.
D[4:0]
SDIV
00000
XXXXX
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Table 25. Register Table (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
0
LOCK output is low
LOCK output is high
0
D7
LOCKED
(Read only)
1
Enable outputs (power-up default value depends
on ENABLE pin value at power-up)
0
D6
D5
D4
OUTENB
PRBSEN
SLEEP
0, 1
0
Disable outputs (power-up default value depends
on ENABLE pin value at power-up)
Disable PRBS test
Enable PRBS test
1
0
1
Normal mode (power-up default value depends on
MS pin value at power-up)
0
0, 1
0x04
Activate sleep mode (power-up default value
depends on MS pin value at power-up)
1
2
00
01
Local control channel uses I C when I2CSEL = 0
D[3:2]
D1
INTTYPE
Local control channel uses UART when I2CSEL = 0
Local control channel disabled
01
1
10, 11
0
Disable reverse control channel to serializer (sending)
Enable reverse control channel to serializer (sending)
REVCCEN
1
Disable forward control channel from serializer
(receiving)
0
1
0
1
D0
D7
FWDCCEN
1
Enable forward control channel from serializer
(receiving)
2
I C conversion sends the register address when
2
converting UART to I C
I2CMETHOD
0
2
Disable sending of I C register address when
2
converting UART to I C (command-byte-only mode)
00
01
7.5MHz equalizer highpass filter cutoff frequency
3.75MHz equalizer highpass filter cutoff frequency
2.5MHz equalizer highpass filter cutoff frequency
1.87MHz equalizer highpass filter cutoff frequency
Enable equalizer
D[6:5]
D4
HPFTUNE
PDEQ
01
10
11
0
0
1
Disable equalizer
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
11XX
2.1dB equalizer boost gain
2.8dB equalizer boost gain
0x05
3.4dB equalizer boost gain
4.2dB equalizer boost gain
5.2dB equalizer boost gain
6.2dB equalizer boost gain
D[3:0]
EQTUNE
7dB equalizer boost gain
1001
8.2dB equalizer boost gain
9.4dB equalizer boost gain
10.7dB equalizer boost gain. Power-up default
11.7dB equalizer boost gain
13dB equalizer boost gain
Do not use
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Table 25. Register Table (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
0
Enable staggered outputs
D7
DISSTAG
0
1
Disable staggered outputs
Do not automatically reset error registers and
outputs
0
1
0
1
D6
D5
AUTORST
DISGPI
0
Automatically reset DECERR register 1µs after
ERR asserts
Enable GPI to GPO signal transmission to
serializer
0
Disable GPI to GPO signal transmission to
serializer
0x06
0
GPI input is low
GPI input is high
Set GPIO1 to low
Set GPIO1 to high
GPIO1 input is low
GPIO1 input is high
Set GPIO0 to low
Set GPIO0 to high
GPIO0 input is low
GPIO0 input is high
Reserved
0
D4
D3
D2
D1
D0
GPIIN
(Read only)
1
0
GPIO1OUT
GPIO1IN
1
1
0
0
(Read only)
1
0
GPIO0OUT
GPIO0IN
1
1
0
0
(Read only)
1
0x07
0x08
D[7:0]
D[7:3]
—
—
01010100
01010100
00110
00110
Reserved
0
Enable DE glitch filter
Disable DE glitch filter
Enable VS glitch filter
Disable VS glitch filter
Enable HS glitch filter
Disable HS glitch filter
Reserved
D2
D1
D0
DISDEFILT
DISVSFILT
DISHSFILT
0
0
0
1
0
1
0
1
0x09
0x0A
0x0B
0x0C
D[7:0]
D[7:0]
D[7:0]
D[7:0]
—
—
11001000
00010XXX
00100000
11001000
00010XXX
00100000
00000000
Reserved
—
Reserved
ERRTHR
XXXXXXXX Error threshold for decoding errors.
00000000
(Read only)
0x0D
0x0E
D[7:0]
D[7:0]
DECERR
XXXXXXXX Decoding error counter
00000000
(Read only)
PRBSERR
XXXXXXXX PRBS error counter
0x0F
0x10
D[7:0]
D[7:0]
—
—
XXXXXXXX Reserved
XXXXXXXX Reserved
(Read only)
(Read only)
High-immunity reverse channel mode uses
500kbps bit rate
0
D7
REVFAST
—
0
0x11
High-immunity reverse channel mode uses 1Mbps
bit rate
1
D[6:0]
0100010
Reserved
0100010
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Table 25. Register Table (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
0
MCLK derived from PCLKOUT. See Table 5.
D7
MCLKSRC
0
1
MCLK derived from internal oscillator
0x12
0000000
MCLK disabled
0000000
D[6:0]
D[7:0]
D7
MCLKDIV
—
XXXXXXX
MCLK divider
0x13
0X000000
Reserved
0X000000
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
No VS inversion at the output
Invert VS at the output
INVVSYNC
No HS inversion at the output
Invert HS at the output
D6
D5
D4
D3
D2
D1
D0
INVHSYNC
INVDE
DRS
0
0
0
0
0
0
0
No DE inversion at the output
Invert DE at the output
High data rate mode
Low data rate mode
0x14
Normal parallel output driver current
Boosted parallel output driver current
Enable remote wake-up
DCS
DISRWAKE
ES
Disable remote wake-up
Output data valid on rising edge of PCLKOUT
Output data valid on falling edge of PCLKOUT
Drive INTOUT low
INTOUT
Drive INTOUT high
INTOUT pin output controlled by INTOUT bit above
D7
D6
AUTOINT
HVTREN
1
Writes to any AVINFO bytes sets INTOUT to high.
Reads to any AVINFO bytes sets INTOUT to low
1
0
1
0
1
Disable HS/VS tracking (power-up default value
depends on state of BWS input value at power-up)
0, 1
Enable HS/VS tracking (power-up default value
depends on state of BWS input value at power-up)
Disable DE tracking (power-up default value
depends on state of BWS input value at power-up)
0x15
D5
DETREN
0, 1
Enable DE tracking (power-up default value
depends on state of BWS input value at power-up)
0
1
Partial periodic HS/VS and DE tracking
Partial and full periodic HS/VS and DE tracking
Reserved
D4
D[3:2]
D1
HVTRMODE
—
1
00
0
00
0
MCLK output operates normally
WS is output from MCLK (MCLK mirrors WS)
MCLK output on DOUT28/CNTL2
MCLK output on CNTL0/ADD0
MCLKWS
1
0
D0
MCLKPIN
0
1
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Table 25. Register Table (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
Legacy reverse control channel mode (power-up
default value depends on SD/HIM at power-up)
0
D7
HIGHIMM
0, 1
High-immunity reverse control channel mode
(power-up default value depends on SD/HIM at
power-up)
0x16
1
D[6:0]
D[7:0]
D[7:1]
D0
—
—
1011010
Reserved
Reserved
1011010
0x17
0x18
000XXXXX
000XXXXX
2
I2CSRCA
—
XXXXXXX
I C Address translator source A
0000000
0
Reserved
0
2
D[7:1]
D0
I2CDSTA
—
XXXXXXX
I C Address translator destination A
0000000
0x19
0x1A
0x1B
0
Reserved
0
2
D[7:1]
D0
I2CSRCB
—
XXXXXXX
I C Address translator source B
0000000
0
XXXXXXX
0
Reserved
0
0000000
0
2
D[7:1]
D0
I2CDSTB
—
I C Address translator destination B
Reserved
Acknowledge not generated when forward
channel is not available
0
D7
I2CLOCACK
I2CSLVSH
1
2
2
I C to I C-slave generates local acknowledge
1
when forward channel is not available
2
00
01
352ns/117ns I C setup/hold time
2
469ns/234ns I C setup/hold time
D[6:5]
01
2
10
938ns/352ns I C setup/hold time
2
11
1046ns/469ns I C setup/hold time
2
2
000
001
010
011
100
101
110
111
00
8.47kbps (typ) I C to I C-Master bit-rate setting
2
2
28.3kbps (typ) I C to I C-Master bit-rate setting
0x1C
2
2
84.7kbps (typ) I C to I C-Master bit-rate setting
2
2
105kbps (typ) I C to I C-Master bit-rate setting
D[4:2]
D[1:0]
I2CMSTBT
I2CSLVTO
101
2
2
173kbps (typ) I C to I C-Master bit-rate setting
2
2
339kbps (typ) I C to I C-Master bit-rate setting
2
2
533kbps (typ) I C to I C-Master bit-rate setting
2
2
837kbps (typ) I C to I C-Master bit-rate setting
2
2
64µs (typ) I C to I C-Slave remote timeout
2
2
01
256µs (typ) I C to I C-Slave remote timeout
10
2
2
10
1024µs (typ) I C to I C-Slave remote timeout
2
2
11
No I C to I C-Slave remote timeout
Reserved
D[7:3]
—
00000
00000
0
Audio FIFO repeats last audio word when FIFO is
empty
0
D2
AUDUFBEH
1
0
1
0
1
Audio FIFO outputs all zeroes when FIFO is empty
Do not invert SCK at output
Invert SCK at output
0x1D
D1
INVSCK
INVWS
0
0
Do not invert WS at output
Invert WS at output
D0
Maxim Integrated
│ 65
www.maximintegrated.com
MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
Table 25. Register Table (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
00100X10
000
FUNCTION
Device identifier
00100X10
0x1E
D[7:0]
ID
(MAX9276 = 0x22)
(Read only)
(MAX9280 = 0x26)
000
(Read only)
D[7:5]
D4
—
Reserved
0x1F
0
1
Not HDCP capable (MAX9276)
(Read only)
CAPS
HDCP capable (MAX9280)
D[3:0]
D[7:0]
D[7:0]
REVISION
AVINFO
—
XXXX
Device revision
(Read only)
All zeroes
0x40 to 0x59
0x77
XXXXXXXX Video/Audio format/status/information bytes
XXXXXXXX
(Read only)
Audio FIFO last overflow/underflow period
XXXXXXXX
0x78
D[7:0]
D7
AUDOUPER
AUDOU
—
(Read only)
(Read only)
(AUDIOMODE = 1 only)
0
Audio FIFO is in underflow (AUDIOMODE = 1 only)
Audio FIFO is in overflow (AUDIOMODE = 1 only)
1
0x79
0x7B
0000XXX
(Read only)
D[6:0]
0000XXX
Reserved
D[7:0]
D[7:4]
LUTADDR
—
XXXXXXXX LUT start address for write and read
00000000
0000
0000
Reserved
0
1
0
1
0
1
0
1
Disable LUT write and read
Enable LUT write and read
Disable blue LUT
Enable blue LUT
D3
D2
D1
D0
LUTPROG
BLULUTEN
GRNLUTEN
REDLUTEN
0
0
0
0
0x7C
Disable green LUT
Enable green LUT
Disable red LUT
Enable red LUT
0x7D
0x7E
D[7:0]
D[7:0]
D[7:0]
REDLUT
GREENLUT
BLUELUT
XXXXXXXX Red LUT value (see Table 11)
XXXXXXXX Green LUT value (see Table 11)
XXXXXXXX Blue LUT value (see Table 11)
00000000
00000000
00000000
0x7F
X = Don’t care
Maxim Integrated
│ 66
www.maximintegrated.com
MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
Table 26. HDCP Register Table (MAX9280 Only)
REGISTER
ADDRESS
SIZE
(Bytes)
READ/
WRITE
DEFAULT VALUE
(hex)
NAME
FUNCTION
0X80 to 0x84
0X85 to 0x86
0X87
5
2
1
8
5
BKSV
RI’
Read only
Read only
Read only
Read/write
Read/write
HDCP receiver KSV
(Read only)
(Read only)
Link verification response
Enhanced link verification response
Session random number
PJ’
(Read only)
0X88 to 0x8F
0X90 to 0x94
AN
0x0000000000000000
0x0000000000
AKSV
HDCP transmitter KSV
D7 = PD_HDCP
1 = Power down HDCP circuits
0 = HDCP circuits normal
D[6:4] = Reserved
D3 = GPIO1_FUNCTION
1 = GPIO1 mirrors AUTH_STARTED
0 = normal GPIO1 operation
D2 = GPIO0_FUNCTION
0x95
1
BCTRL
Read/write
1 = GPIO0 mirrors ENCRYPTION_ENABLE
0 = normal GPIO0 operation
0x00
D1 = AUTH_STARTED
1 = Authentication started (triggered by write
to AKSV)
0 = Authentication not started
D0 = ENCRYPTION_ENABLE
1 = Enable encryption
0 = Disable encryption
D[7:2] = Reserved
D1 = NEW_DEV_CONN
1 = Set to 1 if a new connected device is
detected
0 = Set to 0 if no new device is connected
0x96
1
BSTATUS
Read/write
0x00
0x00
D0 = KSV_LIST_READY
1 = Set to 1 if KSV list and BINFO is ready
0 = Set to 0 if KSV list or BINFO is not ready
D[7:1] = Reserved
D0 = REPEATER
1 = Set to one if device is a repeater
0 = Set to zero if device is not a repeater
0x97
1
BCAPS
—
Read/write
Read only
0x0000000000000000
(Read only)
0x98 to 0x9F
8
Reserved
0XA0 to 0xA3
0XA4 to 0xA7
0XA8 to 0xAB
0XAC to 0xAF
0XB0 to 0xB3
4
4
4
4
4
V’.H0
V’.H1
V’.H2
V’.H3
V’.H4
Read/write
Read/write
Read/write
Read/write
Read/write
H0 part of SHA-1 hash value
H1 part of SHA-1 hash value
H2 part of SHA-1 hash value
H3 part of SHA-1 hash value
H4 part of SHA-1 hash value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Maxim Integrated
│ 67
www.maximintegrated.com
MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
Table 26. HDCP Register Table (MAX9280 Only) (continued)
REGISTER
ADDRESS
SIZE
(Bytes)
READ/
WRITE
DEFAULT VALUE
(hex)
NAME
FUNCTION
D[15:12] = Reserved
D11 = MAX_CASCADE_EXCEEDED
1 = Set to one if more than seven cascaded
devices attached
0 = Set to zero if seven or fewer cascaded
devices attached
D[10:8] = DEPTH
Depth of cascaded devices
0XB4 to 0xB5
2
BINFO
Read/write
0x0000
D7 = MAX_DEVS_EXCEEDED
1 = Set to one if more than 14 devices
attached
0 = Set to zero if 14 or fewer devices
attached
D[6:0] = DEVICE_COUNT
Number of devices attached
0xB6
1
GPMEM
—
Read/write
Read only
General-purpose memory byte
Reserved
0x00
0xB7 to 0xB9
3
0x000000
List of KSVs downstream repeaters and
receivers (maximum of 14 devices)
0xBA to 0xFF
70
KSV_LIST
Read/write
All zero
Maxim Integrated
│ 68
www.maximintegrated.com
MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
Typical Application Circuit
PCLK
RGB
PCLKOUT
DOUT(26:0)
I2CSEL
PCLK
PCLKIN
RGBHV
DIN(26:0)
DISPLAY
45.3kΩ
4.99kΩ
45.3kΩ
4.99kΩ
CNTL0/ADD0
CDS/CNTL3
GPU
CNTL3/ADD1
INTOUT/ADD2
LMN1
LMN0
MAX9275
MAX9279
MAX9276
MAX9280
ECU
TO PERIPHERALS
INT
RX/SDA
TX
RX
TX/SCL
RX/SDA
TX/SCL
OUT+
OUT-
IN+
IN-
UART
SCL
SDA
LOCK
LFLT
LFLT
INT
IMS
GPO/HIM
MS/CNTLO
MAX9850
49.9kΩ
49.9kΩ
CONF3
CONF2
CONF0
CONF1
WS
SCK
SD/HIM
WS
SCK
SD
WS
SCK
SD
WS
AUDIO
SCK
SD
CX/TP
DOUT28/MCLK
MCLK
NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS.
VIDEO-DISPLAY APPLICATION
Package Information
Ordering Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PIN-
PACKAGE
PART
TEMP RANGE
HDCP
MAX9276GTN+
-40°C to +105°C 56 TQFN-EP*
-40°C to +105°C 56 TQFN-EP*
NO
NO
MAX9276GTN/V+
MAX9276GGN/VY+ -40°C to +105°C 56 QFND-EP* NO
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
MAX9280GTN+
-40°C to +105°C 56 TQFN-EP* YES**
-40°C to +105°C 56 TQFN-EP* YES**
MAX9280GTN/V+
56 TQFN-EP
56 QFND-EP
T5688+2
21-0135
90-0046
90-0423
/V denotes an automotive qualified product.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
G5688Y+1
21-0704
**HDCP parts require registration with Digital Content
Protection, LLC..
Chip Information
PROCESS: CMOS
Maxim Integrated
│ 69
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MAX9276/MAX9280
3.12Gbps GMSL Deserializers
for Coax or STP Input and Parallel Output
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
3/13
Initial release
—
1, 7, 9, 13, 17, 21,
Fixed typos, clarified functions, added new simplified diagram and Figure 2a,
deleted Table 1 renumbering remaining tables, added QFND package, and
removed future product designations from Ordering Information table
25–30, 32, 33,
36–38, 43–50,
52–63, 65–73
1
11/15
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2015 Maxim Integrated Products, Inc.
│ 70
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