MAX9400 [MAXIM]
Quad Differential LVECL/LVPECL Buffer/Receivers; 四路差分LVECL / LVPECL缓冲器/接收器
| 型号： | MAX9400 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Quad Differential LVECL/LVPECL Buffer/Receivers |
| 文件： | 总14页 (文件大小：331K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2223; Rev 1; 1/02
Quad Differential LVECL/LVPECL
Buffer/Receivers
General Description
Features
ꢀ 400mV Differential Output at 3.0GHz Data Rate
ꢀ 335ps Propagation Delay in Asynchronous Mode
The MAX9400/MAX9402/MAX9403/MAX9405 are
extremely fast, low-skew quad LVECL/ECL or LVPECL/
PECL buffer/receivers designed for high-speed data
and clock driver applications. These devices feature an
ultra-low propagation delay of 335ps and channel-to-
channel skew of 16ps in asynchronous mode with
86mA supply current.
ꢀ 8ps Channel-to-Channel Skew in Synchronous
Mode
ꢀ Integrated 50Ω Outputs (MAX9402/MAX9405)
ꢀ Integrated 100Ω Inputs (MAX9403/MAX9405)
ꢀ Synchronous/Asynchronous Operation
The four channels can be operated synchronously with
an external clock, or in asynchronous mode determined
by the state of the SEL input. An enable input provides
the ability to force all the outputs to a differential low
state.
Ordering Information
A variety of input and output terminations are offered for
maximum design flexibility. The MAX9400 has open
inputs and open emitter outputs. The MAX9402 has
open inputs and 50Ω series outputs. The MAX9403 has
100Ω differential input impedance and open emitter
outputs. The MAX9405 has 100Ω differential input
impedance and 50Ω series outputs.
TEMP
RANGE
PIN-
DATA
PART
OUTPUT
PACKAGE INPUT
MAX9400EHJ -40°C to +85°C 32 TQFP
MAX9400EGJ* -40°C to +85°C 32 QFN
MAX9402EHJ -40°C to +85°C 32 TQFP
MAX9402EGJ* -40°C to +85°C 32 QFN
MAX9403EHJ -40°C to +85°C 32 TQFP
MAX9403EGJ* -40°C to +85°C 32 QFN
MAX9405EHJ -40°C to +85°C 32 TQFP
MAX9405EGJ* -40°C to +85°C 32 QFN
Open
Open
Open
Open
100Ω
100Ω
100Ω
100Ω
Open
Open
50Ω
These devices operate with a supply voltage of (V
EE
-
CC
50Ω
V
) = 2.375V to 5.5V, and are specified for operation
Open
Open
50Ω
from -40°C to +85°C. These devices are offered in
space-saving 32-pin 5mm ✕ 5mm TQFP and 32-lead
5mm ✕ 5mm QFN packages.
50Ω
*Future product—contact factory for availability.
Applications
Data and Clock Driver and Buffer
Central Office Backplane Clock Distribution
DSLAM Backplane
Pin Configurations
TOP VIEW
Base Station
32 31 30 29 28 27 26 25
ATE
V
1
2
3
4
5
6
7
8
24
23
V
CC
CC
OUT1
SEL
SEL
CLK
CLK
EN
22 OUT1
21
20
V
EE
V
EE
MAX9400
MAX9402
MAX9403
MAX9405
Functional Diagram appears at end of data sheet.
19 OUT2
18 OUT2
EN
V
17 V
CC
CC
9
10 11 12 13 14 15 16
TQFP (5mm x 5mm)
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Quad Differential LVECL/LVPECL
Buffer/Receivers
ABSOLUTE MAXIMUM RATINGS
V
to V ................................................................-0.3V to +6V
Junction-to-Ambient Thermal Resistance with
CC
EE
Inputs to V ...............................................-0.3V to (V
+ 0.3V)
500LFPM Airflow
EE
CC
Differential Input Voltage ....................................................... 3V
Continuous Output Current.................................................50mA
Surge Output Current........................................................100mA
32-Pin 5mm x 5mm TQFP.........................................+73°C/W
Junction-to-Case Thermal Resistance
32-Pin 5mm x 5mm TQFP.........................................+25°C/W
32-Lead 5mm x 5mm QFN .........................................+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection
Continuous Power Dissipation (T = +70°C)
A
32-Pin 5mm x 5mm TQFP
(derate 9.5mW/°C above +70°C).................................761mW
32-Lead 5mm x 5mm QFN
(derate 21.3mW/°C above +70°C)...................................1.7W
Junction-to-Ambient Thermal Resistance in Still Air
32-Pin 5mm x 5mm TQFP........................................+105°C/W
32-Lead 5mm x 5mm QFN ........................................+47°C/W
Human Body Model (Inputs and Outputs) ........................2kV
Soldering Temperature (10s)...........................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
- V = 2.375V to 5.5V, MAX9400/MAX9403 outputs terminated with 50Ω 1ꢀ to V
- 2.0V. Typical values are at V
- V
=
EE
CC
EE
CC
CC
3.3V, V
= V
- 0.9V, V
= V
- 1.7V, T = +25°C, unless otherwise noted.) (Notes 1, 2, and 3)
IHD
CC
ILD
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUTS (IN_, IN_, CLK, CLK, EN, EN, SEL, SEL)
V
+
1.4
EE
Differential Input High Voltage
Differential Input Low Voltage
V
Figure 1
Figure 1
V
V
V
IHD
CC
V
-
CC
V
V
EE
ILD
0.2
V
V
-
CC
V
V
- V < +3.0V
0.2
0.2
-10
CC
CC
EE
Differential Input Voltage
Input Current
V
Figure 1
EE
V
ID
- V ≥ +3.0V
EE
3.0
MAX9400/
MAX9402
EN, EN, SEL, SEL , IN_, IN_,
CLK, or CLK = V or V
25
IHD
ILD
I
, I
IH IL
µA
MAX9403/
MAX9405
EN, EN, SEL, SEL, CLK, or
CLK = V or V
-10
86
25
IHD
ILD
Differential Input Resistance
R
MAX9403/MAX9405
114
Ω
IN
OUTPUTS (OUT_, OUT_)
V
V
-
OH
Differential Output Voltage
Figure 1
Figure 1
600
660
mV
V
OL
V
-
V
-
V
1.1
-
CC
CC
CC
Output Common-Mode Voltage
V
OCM
1.5
1.25
Internal Current Source
Output Impedance
POWER SUPPLY
I
MAX9402/MAX9405, Figure 2
MAX9402/MAX9405, Figure 2
6.5
40
8.3
50
10
60
mA
SINK
R
Ω
OUT
MAX9402/MAX9405
MAX9400/MAX9403
150
86
180
118
Supply Current
I
EE
mA
2
_______________________________________________________________________________________
Quad Differential LVECL/LVPECL
Buffer/Receivers
AC ELECTRICAL CHARACTERISTICS
(V
- V = 2.375V to 5.5V, outputs terminated with 50Ω 1ꢀ to V
- 2.0V, enabled, CLK = 3.2GHz, f = 1.6GHz, input transition
CC IN
CC
EE
time = 125ps (20ꢀ to 80ꢀ), V
= V + 1.2V to V , V
= V to V
- 0.2V, V
- V
= 0.2V to smaller of |V - V | or 3V,
CC EE
IHD
EE
CC ILD
EE
CC
IHD
ILD
unless otherwise noted. Typical values are at V
noted.) (Notes 1, 4)
- V = 3.3V, V
= V
- 0.9V, V
= V 1.7V, T = +25°C, unless otherwise
CC A
CC
EE
IHD
CC
ILD
PARAMETER
SYMBOL
CONDITIONS
MIN
237
237
397
397
TYP
335
335
475
475
MAX
437
437
597
597
UNITS
MAX9400/MAX9403
MAX9402/MAX9405
MAX9400/MAX9403
MAX9402/MAX9405
IN-to-OUT Differential
Propagation Delay
t
t
PLH1
PHL1
SEL = high, Figure 3
SEL = low, Figure 4
ps
CLK-to-OUT Differential
Propagation Delay
t
t
PLH2
PHL2
ps
ps
ps
IN-to-OUT Channel-to-Channel
Skew (Note 5)
t
t
SEL = high
SEL = low
16
8
80
55
SKD1
SKD2
CLK-to-OUT Channel-to-
Channel Skew (Note 5)
Maximum Clock Frequency
Maximum Data Frequency
f
V
V
-V ≥ 500mV, SEL = low
OH OL
3.0
2
GHz
GHZ
CLK(MAX)
f
-V ≥ 400mV, SEL = high
OH OL
IN(MAX)
SEL = low, f
= 3.0GHz clock, f = 1.5GHz
0.64
0.74
1.3
1.5
CLK
IN
Added Random Jitter (Note 6)
t
RJ
ps
(RMS)
SEL = high, f = 2GHz
IN
SEL = low, f
= 3.0GHz, IN_ = 3.0Gbps
CLK
17
40
30
55
223 - 1 PRBS pattern
Added Deterministic Jitter
(Note 6)
t
DJ
ps
(P-P)
SEL = high, IN = 2.0Gbps 223 - 1 PRBS
pattern
IN-to-CLK Setup Time
CLK-to-IN Hold Time
Output Rise Time
t
Figure 4
Figure 4
Figure 3
Figure 3
80
80
ps
ps
ps
ps
S
t
H
t
80
80
120
120
R
Output Fall Time
t
F
Propagation Delay Temperature
Coefficient
∆t
∆T
/
PD
0.2
1
ps/°C
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters are production tested at +25°C. DC limits are guaranteed by design and characterization over the full oper-
ating temperature range.
Note 4: Guaranteed by design and characterization. Limits are set to 6 sigma.
Note 5: Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 6: Device jitter added to the input signal.
_______________________________________________________________________________________
3
Quad Differential LVECL/LVPECL
Buffer/Receivers
Typical Operating Characteristics
(V
- V = 3.3V, MAX9400, outputs terminated with 50Ω 1ꢀ to V
- 2.0V, enabled, SEL = high, CLK = 2.0GHz, f = 1.0GHz,
CC IN
CC
EE
input transition time = 125ps (20ꢀ to 80ꢀ), V
= V
- 1.0V, V
= V - 1.5V, T = +25°C, unless otherwise noted.)
CC A
IHD
CC
ILD
SUPPLY CURRENT (I
vs. TEMPERATURE
)
OUTPUT AMPLITUDE (V - V )
OH OL
OUTPUT RISE/FALL
vs. TEMPERATURE
EE
vs. IN_ FREQUENCY
95
90
85
80
75
70
1000
100
90
80
70
60
800
600
400
200
0
t
R
t
F
-40
-15
10
35
60
85
0
500 1000 1500 2000 2500 3000 3500
IN_ FREQUENCY (MHz)
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
CLK-TO-OUT PROPAGATION DELAY
vs. TEMPERATURE
IN-TO-OUT PROPAGATION DELAY
vs. TEMPERATURE
355
350
345
340
335
330
520
500
480
460
440
t
PLH2
t
PLH
t
PHL2
t
PHL
325
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
Quad Differential LVECL/LVPECL
Buffer/Receivers
Pin Description
PIN
NAME
FUNCTION
1, 8,11,
17, 24, 30
Positive Supply Voltage. Bypass V
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
to V with 0.1µF and 0.01µF ceramic capacitors. Place the
CC EE
V
CC
Noninverting Differential Select Input. Setting SEL = high and SEL = low (differential high) enables all four
channels to operate asynchronously. Setting SEL = low and SEL = high (differential low) enables all four
channels to operate in synchronous mode.
2
SEL
3
4
SEL
Inverting Differential Select Input
CLK
Noninverting Differential Clock Input
Inverting Differential Clock Input. A rising edge on CLK (and falling on CLK) transfers data from the inputs
to the outputs when SEL = low.
5
6
CLK
Noninverting Differential Output Enable Input. Setting EN = high and EN = low (differential high) enables
the outputs. Setting EN = low and EN = high (differential low) drives outputs low.
EN
7
EN
IN3
Inverting Differential Output Enable Input
Noninverting Differential Input 3
Inverting Differential Input 3
9
10
12
13
IN3
OUT3
OUT3
Inverting Differential Output 3
Noninverting Differential Output 3
14, 20,
21, 27
V
Negative Supply Voltage
EE
15
16
18
19
22
23
25
26
28
29
31
32
—
IN2
IN2
Noninverting Differential Input 2
Inverting Differential Input 2
OUT2
OUT2
OUT1
OUT1
IN1
Inverting Differential Output 2
Noninverting Differential Output 2
Noninverting Differential Output 1
Inverting Differential Output 1
Inverting Differential Input 1
IN1
Noninverting Differential Input 1
Noninverting Differential Output 0
Inverting Differential Output 0
Inverting Differential Input 0
OUT0
OUT0
IN0
IN0
Noninverting Differential Input 0
EP
Exposed Paddle (MAX940_EGJ only). Connected to V internally. See package dimensions.
EE
_______________________________________________________________________________________
5
Quad Differential LVECL/LVPECL
Buffer/Receivers
The CLK signal is ignored in this mode. In asynchro-
nous mode, the CLK signal should be set to either a
logic low or high state to minimize noise coupling.
Detailed Description
The MAX9400/MAX9402/MAX9403/MAX9405 are
extremely fast, low-skew quad LVECL/ECL or LVPECL/
PECL buffer/receivers designed for high-speed data
and clock driver applications. The devices feature an
ultra-low propagation delay of 335ps and channel-to-
channel skew of 16ps in asynchronous mode with an
86mA supply current.
Synchronous Operation
Setting SEL = low and SEL = high enables all four
channels to operate in synchronous mode. In this
mode, buffered inputs are clocked into flip-flops simul-
taneously on the rising edge of the differential clock
input (CLK and CLK).
The four channels can be operated synchronously with
an external clock, or in asynchronous mode, determined
by the state of the SEL input. An enable input provides
the ability to force all the outputs to a differential low state.
Differential Signal Input Limit
The maximum signal magnitude of the differential
inputs is V
- V or 3V, whichever is less.
EE
CC
A variety of input and output terminations are offered
for maximum design flexibility. The MAX9400 has open
inputs and open-emitter outputs. The MAX9402 has
open inputs and 50Ω series outputs. The MAX9403 has
100Ω differential input impedance and open-emitter
outputs. The MAX9405 has 100Ω differential input
impedance and 50Ω series outputs.
Applications Information
Input Bias
Unused inputs should be biased or driven as shown in
Figure 5. This avoids noise coupling that might cause
toggling at the unused outputs.
Output Termination
Supply Voltage
The MAX9400/MAX9402/MAX9403/MAX9405 are de-
signed for operation with a single supply. Using a single
Terminate open-emitter outputs (MAX9400/MAX9403)
through 50Ω to V
- 2V or use an equivalent Thevenin
CC
termination. Terminate both outputs and use identical
termination on each for the lowest output-to-output
skew. When a single-ended signal is taken from a dif-
ferential output, terminate both outputs. For example, if
OUT_ is used as a single-ended output, terminate both
OUT_ and OUT_.
negative supply of V = -2.375V to -5.5V (V = ground)
EE
CC
yields LVECL/ECL-compatible input and output levels.
Using a single positive supply of V
EE
levels.
= 2.375V to 5.5V
CC
(V = ground) yields LVPECL/PECL input and output
Data Inputs
Ensure that the output currents do not exceed the cur-
rent limits as specified in the Absolute Maximum
Ratings table. Under all operating conditions, the
device’s total thermal limits should be observed.
The MAX9400/MAX9402 have open inputs and require
external termination. The MAX9403/MAX9405 have inte-
grated 100Ω differential input termination resistors from
IN_ to IN_, reducing external component count.
Power-Supply Bypassing
Adequate power-supply bypassing is necessary to
maximize the performance and noise immunity. Bypass
Outputs
The MAX9402/MAX9405 have internal 50Ω series out-
put termination resistors and 8mA internal pulldown
current sources. Using integrated resistors reduces
external component count.
V
CC
to V with high-frequency surface-mount ceramic
EE
0.1µF and 0.01µF capacitors as close to the device as
possible with the 0.01µF capacitor closest to the device
pins. Use multiple bypass vias for connection to mini-
mize inductance.
The MAX9400/MAX9403 have open-emitter outputs. An
external termination is required. See the Output
Termination section.
Circuit Board Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9400/MAX9402/MAX9403/MAX9405.
Connect each of the inputs and outputs to a 50Ω char-
acteristic impedance trace. Avoid discontinuities in dif-
ferential impedance and maximize common-mode
noise immunity by maintaining the distance between
differential traces and avoid sharp corners. Minimize
the number of vias to prevent impedance discontinu-
ities. Reduce reflections by maintaining the 50Ω char-
Enable
Setting EN = high and EN = low enables the device.
Setting EN = low and EN = high forces the outputs to a
differential low, and all changes on CLK, SEL, and IN_
are ignored.
Asynchronous Operation
Setting SEL = high and SEL = low enables the four
channels to operate independently as buffer/receivers.
6
_______________________________________________________________________________________
Quad Differential LVECL/LVPECL
Buffer/Receivers
acteristic impedance through connectors and across
cables. Minimize skew by matching the electrical
length of the traces.
Chip Information
TRANSISTOR COUNT: 713
PROCESS: Bipolar
V
CC
V
IHD
(MAX)
V
CC
V
V
V
= 0V
ID
ID
V
V
OH
V
V
(MAX)
(MIN)
ILD
V - V
OH OL
V
OCM
IHD
OL
V = 0V
ID
ID
V
EE
V
EE
V
ILD
(MIN)
INPUT VOLTAGE DEFINITION
OUTPUT VOLTAGE DEFINITION
Figure 1. Input and Output Voltage Definitions
IN_
IN_
100kΩ
IN_
IN_
MAX9420/MAX9421
MAX9422/MAX9423
V
CC
V
CC
50Ω
50Ω
OUT_
OUT_
OUT_
OUT_
8mA
8mA
V
EE
MAX9420/MAX9422
MAX9421/MAX9423
Figure 2. Input and Output Configurations
_______________________________________________________________________________________
7
Quad Differential LVECL/LVPECL
Buffer/Receivers
IN_
V
- V
ILD
IHD
IN_
t
t
PHL1
PLH1
OUT_
OUT_
V
- V
OH
OH
OL
OL
V
V
- V
- V
80%
80%
20%
20%
OH
OL
DIFFERENTIAL OUTPUT
WAVEFORM
OUT_ - OUT_
t
t
F
R
SEL = HIGH
EN = HIGH
Figure 3. IN-to-OUT Propagation Delay and Transition Timing Diagram
CLK
V
- V
ILD
IHD
CLK
t
t
t
H
H
S
IN_
IN_
V
- V
ILD
IHD
t
t
PHL2
PLH2
OUT_
OUT_
V
- V
ILD
IHD
SEL = LOW
EN = HIGH
Figure 4. CLK-to-OUT Propagation Delay Timing Diagram
8
_______________________________________________________________________________________
Quad Differential LVECL/LVPECL
Buffer/Receivers
V
V
CC
CC
IN_
100Ω
IN_
IN_
IN_
OUT_
OUT_
OUT_
OUT_
100Ω
1kΩ
1/4 MAX9400/MAX9402
1kΩ
1/4 MAX9403/MAX9405
V
V
EE
EE
Figure 5. Input Bias Circuits for Unused Inputs
Pin Configurations (continued)
TOP VIEW
*
*
V
1
2
3
4
5
6
7
8
24
V
CC
CC
SEL
SEL
CLK
CLK
EN
23 OUT1
22 OUT1
MAX9400
MAX9402
MAX9403
MAX9405
21
20
V
V
EE
EE
19 OUT2
18 OUT2
*EXPOSED PADDLE
EN
V
17
V
CC
CC
*
*
QFN-EP*
*EXPOSED PADDLE AND CORNER PINS ARE CONNECTED TO V
.
EE
_______________________________________________________________________________________
9
Quad Differential LVECL/LVPECL
Buffer/Receivers
Functional Diagram
IN0
IN0
1
OUT0
OUT0
D
D
Q
Q
0
CK
CK
IN1
IN1
1
0
OUT1
OUT1
D
Q
Q
D
CK
CK
IN2
IN2
1
0
OUT2
OUT2
D
Q
Q
D
CK
CK
IN3
IN3
1
0
OUT3
OUT3
D
Q
Q
D
CK
CK
CLK
CLK
SEL
SEL
EN
EN
10 ______________________________________________________________________________________
Quad Differential LVECL/LVPECL
Buffer/Receivers
Package Information
______________________________________________________________________________________ 11
Quad Differential LVECL/LVPECL
Buffer/Receivers
Package Information (continued)
12 ______________________________________________________________________________________
Quad Differential LVECL/LVPECL
Buffer/Receivers
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.
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