MAX9424EGJ [MAXIM]
Lowest Jitter Quad PECL-to-ECL Differential Translators; 最低的抖动四路PECL到ECL差分转换器
| 型号： | MAX9424EGJ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Lowest Jitter Quad PECL-to-ECL Differential Translators |
| 文件： | 总11页 (文件大小：346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2390; Rev 0; 4/02
Lowest Jitter Quad PECL-to-ECL
Differential Translators
General Description
Features
The MAX9424–MAX9427 high-speed, low-skew quad
PECL-to-ECL translators are designed for high-speed
data and clock driver applications. These devices feature
ꢀ 0.24ps RMS Added Random Jitter
ꢀ 10ps Channel-to-Channel Skew in Synchronous
Mode
an ultra-low 0.24ps
random jitter and channel-to-
(RMS)
channel skew is less than 90ps in asynchronous mode.
ꢀ Guaranteed 500mV Differential Output at 3GHz
Clock Frequency
The four channels can be operated synchronously with
an external clock, or in asynchronous mode determined
by the state of the SEL input. An enable input provides
the ability to force all the outputs to a differential low state.
ꢀ 420ps Propagation Delay in Asynchronous Mode
ꢀ Functionally Compatible with
SK4426 (MAX9424)
The parts differ from one another by their input and out-
put termination options. The input options are an open
input or an internal differential 100Ω termination. The
output options are an open-emitter output or a series
50Ω termination. See Ordering Information.
The MAX9424–MAX9427 operate from a positive voltage
supply of +2.375V to +5.5V, and a negative supply volt-
age of -2.375V to -5.5V and operate across the extended
temperature range of -40°C to +85°C. They are offered in
32-pin 5mm x 5mm TQFP and space-saving 5mm x 5mm
QFN packages.
SK4430 (MAX9425)
SK4436 (MAX9426)
SK4440 (MAX9427)
ꢀ Integrated 50Ω Outputs (MAX9425/MAX9427)
ꢀ Integrated 100Ω Inputs (MAX9426/MAX9427)
ꢀ Synchronous/Asynchronous Operation
Ordering Information
INPUT OUTPUT
(IN_, (OUT_,
TEMP
RANGE
PIN-
PACKAGE
PART
Applications
IN_)
OUT_)
Open
Open
50Ω
Data and Clock Driver and Buffer
MAX9424EHJ -40°C to +85°C 32 TQFP
MAX9424EGJ* -40°C to +85°C 32 QFN
MAX9425EHJ -40°C to +85°C 32 TQFP
MAX9425EGJ* -40°C to +85°C 32 QFN
MAX9426EHJ -40°C to +85°C 32 TQFP
MAX9426EGJ* -40°C to +85°C 32 QFN
MAX9427EHJ -40°C to +85°C 32 TQFP
MAX9427EGJ* -40°C to +85°C 32 QFN
Open
Open
Open
Open
100Ω
100Ω
100Ω
100Ω
Central Office Backplane Clock Distribution
DSLAM Backplane
Base Station
ATE
50Ω
Open
Open
50Ω
50Ω
*Future product—contact factory for availability.
Pin Configurations
TOP VIEW
TOP VIEW
32 31 30 29 28 27 26 25
*
*
V
1
2
3
4
5
6
7
8
24
V
GG
V
1
2
3
4
5
6
7
8
24
V
CC
CC
GG
SEL
SEL
CLK
CLK
EN
23 OUT1
22 OUT1
SEL
SEL
CLK
CLK
EN
23 OUT1
22 OUT1
MAX9424
MAX9425
MAX9426
MAX9427
21
20
V
V
EE
EE
21
20
V
EE
V
EE
MAX9424
MAX9425
MAX9426
MAX9427
19 OUT2
18 OUT2
19 OUT2
18 OUT2
EN
EN
V
CC
17
V
GG
V
17 V
GG
CC
*
*
9
10 11 12 13 14 15 16
QFN
TQFP (5mm x 5mm)
NOTE: CORNER PINS ARE CONNECTED TO V
.
GG
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Lowest Jitter Quad PECL-to-ECL
Differential Translators
ABSOLUTE MAXIMUM RATINGS
V
V
to V ............................................................-0.3V to +6.0V
Junction-to-Ambient Thermal Resistance with
500LFPM Airflow
CC
GG
GG
to V .............................................................-0.3V to +6.0V
EE
Input Pins to V ........................................-0.3V to (V + 0.3V)
32-Pin 5mm x 5mm TQFP..........................................+73°C/W
Junction-to-Case Thermal Resistance
GG
CC
Differential Input Voltage..............................|V
- V | or 3.0V,
CC
GG
whichever is less
Continuous Output Current.................................................50mA
Surge Output Current........................................................100mA
32-Pin 5mm x 5mm TQFP..........................................+25°C/W
32-Pin 5mm x 5mm QFN..............................................+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection
Human Body Model (all input pins) ............................... 500V
Human Body Model (all output pins) ............................... 2ꢀV
Soldering Temperature (10s)...........................................+300°C
Continuous Power Dissipation (T = +70°C)
32-Pin 5mm x 5mm TQFP
A
(derate 9.5mW/°C above +70°C).................................761mW
32-Pin 5mm x 5mm QFN
(derate 21.3mW/°C above +70°C)...................................1.7W
Junction-to-Ambient Thermal Resistance in Still Air
32-Pin 5mm x 5mm TQFP........................................+105°C/W
32-Pin 5mm x 5mm QFN............................................+47°C/W
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
- V
= 2.375V to 5.5V, V
- V
= 2.375V to 5.5V, MAX9424/MAX9426 outputs terminated with 50Ω to V
- 2.0V,
GG
- V = 3.3V, V
CC
GG
GG
EE
MAX9425/MAX9427 not externally terminated, T = -40°C to +85°C. Typical values are at V
- V
= 3.3V, V
A
CC
GG
GG EE IHD
= V
- 0.9V, V
= V - 1.7V, T = +25°C, unless otherwise noted.) (Notes 1, 2, and 3)
CC A
CC
ILD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUTS (IN_, IN_, CLK, CLK, EN, EN, SEL, SEL)
V
+
GG
1.4
Differential Input High Voltage
Differential Input Low Voltage
V
Figure 1
Figure 1
V
V
V
IHD
CC
V
-
CC
V
V
GG
ILD
0.2
V
V
GG
3.0
-
CC
V
V
- V
- V
< 3.0V
0.2
0.2
-10
CC
CC
GG
Differential Input Voltage
Input Current
V
Figure 1
V
ID
≥ 3.0V
GG
MAX9424/ EN, EN, SEL, SEL, IN_, IN_, CLK
MAX9425 or CLK = V or V
MAX9426/ EN, EN, SEL, SEL, CLK, or CLK
MAX9427 = V or V
25
25
IHD
ILD
I
, I
IH IL
µA
-10
86
IHD
ILD
Differential Input Resistance
(IN_, IN_)
R
MAX9426/MAX9427
100
635
114
Ω
IN
OUTPUTS (OUT_, OUT_)
Differential Output Voltage
V
- V
Figure 1
Figure 1
600
mV
V
OH
OL
V
-
V
-
V
-
GG
GG
GG
Output Common-Mode Voltage
V
OCM
1.50
1.25
1.05
Output Impedance
R
MAX9425/MAX9427
MAX9425/MAX9427
40
6
50
8
60
10
Ω
OUT
Internal Current Source
POWER SUPPLY
I
mA
SINK
Positive Supply Current
I
(Note 4)
16
27
mA
mA
CC
MAX9424/MAX9426 (Note 4)
MAX9425/MAX9427 (Note 4)
100
172
130
230
Negative Supply Current
I
EE
2
_______________________________________________________________________________________
Lowest Jitter Quad PECL-to-ECL
Differential Translators
AC ELECTRICAL CHARACTERISTICS
(V
- V
= 2.375V to 5.5V, V
- V = 2.375V to 5.5V, outputs terminated with 50Ω to V
- 2.0V, EN = V , EN = V , f
ILD CLK
≤
CC
GG
GG
EE
GG
IHD
3.0GHz, f ≤ 1.5GHz, input transition time = 125ps (20% to 80%), V
= V
+ 1.4V to V , V
= V
to V
- 0.2V, V
- V
IN
IHD
GG
CC ILD
GG
CC
CC
IHD
ILD
= 0.2V to smallest of |V
- V | or 3.0V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
- V
= 3.3V, V
CC
GG
A
GG
GG
- V = 3.3V, V
= V
- 0.9V, V
= V - 1.7V, T = +25°C, unless otherwise noted.) (Notes 1 and 5)
CC A
EE
IHD
CC
ILD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IN_ to OUT_ Differential
Propagation Delay
CLK to OUT_ Differential
Propagation Delay
t
t
t
t
Figure 3, SEL = high, asynchronous
operation
PLH1
PHL1
PLH2
PHL2
300
420
570
ps
Figure 4, SEL = low, synchronous operation
460
580
730
ps
SEL = high, asynchronous operation
(Note 6)
OUT_ to OUT_ Sꢀew
OUT_ to OUT_ Sꢀew
t
t
38
10
90
70
ps
ps
SKD1
SKD2
SEL = low, synchronous operation (Note 6)
MAX9424/MAX9426, V
SEL = low
MAX9425/MAX9427, V
SEL = low
MAX9424/MAX9426, V
SEL = high
MAX9425/MAX9427, V
SEL = high
- V ≥ 500mV,
OL
OH
OH
OH
OH
Maximum Clocꢀ Frequency
f
3.0
2.0
GHz
GHz
CLK(MAX)
- V ≥ 300mV,
OL
- V ≥ 400mV,
OL
Maximum Data Frequency
Added Random Jitter
f
IN(MAX)
- V ≥ 250mV,
OL
SEL = low, f
= 3.0GHz clocꢀ, f
=
IN
CLK
0.24
0.3
27
0.8
0.8
80
1.5GHz (Note 7)
t
ps
(RMS)
RJ
SEL = high, f = 2.0GHz (Note 7)
IN
SEL = low, f
= 3.0GHz, IN_ = 3.0Gbps
CLK
223 - 1 PRBS pattern (Note 7)
SEL = high, IN_ = 2.0Gbps 223 - 1 PRBS
pattern (Note 7)
Added Deterministic Jitter
t
ps
(P-P)
DJ
20
80
IN_ to CLK Setup Time
CLK to IN_ Hold Time
Output Rise Time
t
Figure 4
Figure 4
Figure 3
Figure 3
80
80
ps
ps
ps
ps
S
t
H
t
89
87
120
120
R
Output Fall Time
t
F
Propagation Delay Temperature
Coefficient
∆t /∆T
PD
0.2
1
ps/°C
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters are production tested at +25°C. DC limits are guaranteed by design and characterization over the full
operating temperature range.
Note 4: All outputs open, all inputs biased differential high or low except V , V , and V
.
EE
CC GG
Note 5: Guaranteed by design and characterization, and are not production tested. Limits are set to 6 sigma.
Note 6: Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 7: Device jitter added to the input signal.
_______________________________________________________________________________________
3
Lowest Jitter Quad PECL-to-ECL
Differential Translators
Typical Operating Characteristics
(MAX9424: V
input transition time = 125ps (20% to 80%), V
- V
= 3.3V, V
- V = 3.3V, outputs terminated with 50Ω to V
- 2.0V, enabled, f
= 3.0GHz, f = 1.5GHz,
CLK IN
CC
GG
GG
EE
GG
= V
- 0.9V, V
= V - 1.7V, T = +25°C, unless otherwise noted.)
CC A
IHD
CC
ILD
OUTPUT AMPLITUDE (V - V
OH
)
OL
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
vs. IN_ FREQUENCY
SUPPLY CURRENT vs. TEMPERATURE
650
94
92
90
88
86
84
100
I
EE
600
550
500
450
400
350
SEL = HIGH
FALL TIME
RISE TIME
75
50
25
0
INPUTS BIASED
DIFFERENTIALLY HIGH OR
LOW, OUTPUTS OPEN
I
CC
0
0.5
1.0
1.5
2.0
2.5
3.0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
IN_ FREQUENCY (GHz)
TEMPERATURE (°C)
TEMPERATURE (°C)
IN-TO-OUT PROPAGATION DELAY
vs. TEMPERATURE
CLK-TO-OUT PROPAGATION DELAY
vs. TEMPERATURE
420
410
400
390
380
630
620
610
600
590
580
570
t
PHL1
t
,
PLH2
t
PHL2
t
PLH1
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
Lowest Jitter Quad PECL-to-ECL
Differential Translators
Pin Description
PIN
NAME
FUNCTION
Positive Supply Voltage. Bypass V
to V
with 0.1µF and 0.01µF ceramic capacitors. Place the
GG
CC
1, 8
V
CC
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
Noninverting Differential Select Input. Setting SEL = 1 and SEL = 0 enables all four channels to
operate independently. Setting SEL = 0 and SEL = 1 enables all four channels to be synchronized to
CLK.
2
SEL
3
4
5
SEL
CLK
CLK
Inverting Differential Select Input
Noninverting Differential Clock Input
Inverting Differential Clock Input
Noninverting Differential Output Enable Input. Setting EN = 1 and EN = 0 enables all four outputs.
Setting EN = 0 and EN = 1 disables all four outputs.
6
EN
7
9
EN
IN3
IN3
Inverting Differential Output Enable Input
Noninverting Differential Input 3
Inverting Differential Input 3
10
11, 17, 24,
V
Ground Reference
GG
30
12
OUT3
Inverting Differential Output 3
13
OUT3
Noninverting Differential Output 3
Negative Supply Voltage. Bypass from V to V
the capacitors as close to the device as possible with the smaller value capacitor closest to the
device.
with 0.1µF and 0.01µF ceramic capacitors. Place
GG
EE
14, 20, 21,
27
V
EE
15
16
18
19
22
23
25
26
28
29
31
32
IN2
IN2
Noninverting Differential Input 2
Inverting Differential Input 2
Inverting Differential Output 2
Noninverting Differential Output 2
Noninverting Differential Output 1
Inverting Differential Output 1
Inverting Differential Input 1
Noninverting Differential Input 1
Noninverting Differential Output 0
Inverting Differential Output 0
Inverting Differential Input 0
Noninverting Differential Input 0
OUT2
OUT2
OUT1
OUT1
IN1
IN1
OUT0
OUT0
IN0
IN0
_______________________________________________________________________________________
5
Lowest Jitter Quad PECL-to-ECL
Differential Translators
Functional Diagram
V
V
V
EE
14, 20,
21, 27
CC
GG
11, 17,
24, 30
1, 8
V
CC
32
31
IN0
IN0
1
0
V
CC
28
29
V
V
GG
OUT0
OUT0
D
D
Q
Q
CK
CK
V
EE
CC
26
25
IN1
IN1
1
0
V
CC
22
23
V
GG
CC
OUT1
OUT1
D
Q
Q
D
CK
CK
V
EE
V
15
16
IN2
IN2
1
0
V
CC
19
18
V
V
GG
OUT2
OUT2
D
Q
Q
D
CK
CK
V
EE
CC
9
IN3
IN3
1
0
10
V
CC
13
12
V
V
GG
OUT3
OUT3
D
Q
Q
D
CK
CK
V
EE
CC
4
5
CLK
CLK
2
3
MAX9424
MAX9425
MAX9426
MAX9427
SEL
SEL
6
7
EN
EN
V
GG
6
_______________________________________________________________________________________
Lowest Jitter Quad PECL-to-ECL
Differential Translators
V
CC
V
IHD
(MAX)
V
GG
V
V
V
V
= 0
ID
ID
V
V
OH
OL
V
V
(MAX)
(MIN)
ILD
V
- V
OH OL
V
OCM
IHD
= 0
ID
ID
V
V
GG
V
(MIN)
EE
ILD
INPUT VOLTAGE DEFINITION
(PECL)
OUTPUT VOLTAGE DEFINITION
(ECL)
Figure 1. Input and Output Voltage Definitions
IN_
IN_
100kΩ
IN_
IN_
MAX9424/MAX9425
MAX9426/MAX9427
V
GG
V
GG
50Ω
50Ω
OUT_
OUT_
OUT_
OUT_
8mA
8mA
V
EE
MAX9424/MAX9426
MAX9425/MAX9427
Figure 2. Input and Output Configurations
Supply Voltages
These devices require a positive voltage supply (con-
nect to V ), a negative voltage supply (connect to
Detailed Description
The MAX9424–MAX9427 high-speed, low-sꢀew PECL-to-
ECL differential translators are designed for high-speed
data and clocꢀ driver applications. These devices trans-
late up to four PECL signals to ECL signals.
CC
V
), and a ground reference (connect to V ). V
is
CC
EE
GG
independent of V and therefore the supply voltages
EE
do not need to be symmetrical. The PECL input volt-
The four channels can be operated synchronously with
an external clocꢀ, or in asynchronous mode, determined
by the state of the SEL input. An enable input provides
the ability to force all the outputs to a differential low state.
ages are referenced to V , and the ECL output volt-
CC
ages are referenced to V
.
GG
Data Inputs and Outputs
The input and output structures are shown in Figure 2.
The open inputs of the MAX9424/MAX9425 require
external termination, whereas the MAX9426/MAX9427
have integrated 100Ω differential input termination
resistors between IN_ and IN_.
A variety of input and output terminations are offered
for maximum design flexibility. The MAX9424 has open
inputs and open-emitter outputs. The MAX9425 has
open inputs and 50Ω series outputs. The MAX9426 has
100Ω differential input impedance and open-emitter
outputs. The MAX9427 has 100Ω differential input
impedance and 50Ω series outputs.
_______________________________________________________________________________________
7
Lowest Jitter Quad PECL-to-ECL
Differential Translators
IN_
V
- V
ILD
IHD
IN_
t
t
PHL1
PLH1
OUT_
OUT_
V
- V
OH
OH
OL
OL
V
V
- V
- V
80%
80%
20%
20%
OH
OL
DIFFERENTIAL OUTPUT
WAVEFORM
OUT_ - OUT_
t
t
F
R
SEL = HIGH
EN = HIGH
Figure 3. IN to OUT Propagation Delay and Transition Timing Diagram
CLK
V
IHD
- V
ILD
CLK
t
H
t
S
t
H
IN_
IN_
V
IHD
- V
ILD
t
t
PHL2
PLH2
OUT_
OUT_
V
IHD
- V
ILD
SEL = LOW
EN = HIGH
Figure 4. CLK to OUT Propagation Delay Timing Diagram
The MAX9425/MAX9427 have internal 50Ω series-out-
put termination resistors and 8mA internal pulldown
current sources, removing the need for external termi-
nation. The MAX9424/MAX9426 have open-emitter out-
puts, which require external termination (see the Output
Termination section).
Asynchronous Operation
Setting SEL = high and SEL = low enables the four chan-
nels to operate independently. The clocꢀ signal is
ignored in this mode. When asynchronous mode is
selected, drive or bias the CLK and CLK inputs. Biasing
the clocꢀ inputs properly is shown in Figure 5. This pre-
vents the unused clocꢀ inputs from toggling, which elimi-
nates unnecessary switching noise.
Enable
Setting EN = high and EN = low enables the device.
Alternatively, setting EN = low and EN = high forces the
outputs to a differential low; all changes on CLK, SEL,
and IN_ are ignored.
8
_______________________________________________________________________________________
Lowest Jitter Quad PECL-to-ECL
Differential Translators
V
V
CC
CC
IN_
100Ω
IN_
IN_
IN_
OUT_
OUT_
OUT_
OUT_
100Ω
1kΩ
1/4 MAX9424/MAX9425
1kΩ
1/4 MAX9426/MAX9427
V
GG
V
GG
Figure 5. Input Bias Circuits for Unused Inputs
Synchronous Operation
Setting SEL = low and SEL = high enables all four
channels to operate in synchronous mode where the
buffered inputs are clocꢀed out simultaneously on the
rising edge of the differential clocꢀ input (CLK and
CLK). To have the input signals clocꢀed out on the
falling edge, swap the clocꢀ lines.
Power-Supply Bypassing
Typically, V
is directly connected to ground. Bypass
GG
pin to V
each V
with high-frequency surface-mount
CC
GG
ceramic 0.01µF capacitors. Place these capacitors as
close to the device as possible. Use the same bypass
capacitor configuration between each V pin and V
.
EE
GG
In high-frequency, high-noise environments, add a 0.1µF
capacitor in parallel with each 0.01µF capacitor.
Differential Signal Input
The maximum input signal magnitude for each of the
Use multiple vias when connecting the bypass capaci-
tors to V
(ground). This reduces trace inductance,
GG
devices is V
- V
or 3.0V, whichever is less. This
GG
CC
lowering power-supply bounce when drawing high
transient currents.
includes IN_, IN_, CLK, CLK, SEL, SEL, EN and EN.
Applications Information
Circuit Board Traces
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reduc-
ing signal reflections and sꢀew, and increasing com-
mon-mode noise immunity.
Input Bias
Bias any unused inputs as shown in Figure 5. This
avoids noise coupling that can cause toggling of the
unused outputs.
Output Termination
Signal reflections are caused by discontinuities in the
50Ω characteristic impedance of the traces. Avoid dis-
continuities by maintaining the distance between differ-
ential traces, not using sharp corners, and using vias.
Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal sꢀew
is accomplished by matching the electrical length of
the differential traces.
Terminate the open-emitter outputs (MAX9424/
MAX9426) through 50Ω to V
- 2V or use equivalent
GG
Thevenin terminations. Terminate both outputs of a dif-
ferential pair and use identical termination on each for
the lowest output-to-output sꢀew. When a single-ended
signal is taꢀen from a differential output, terminate both
outputs. For example, if OUT0 is used as a single-
ended output, terminate both OUT0 and OUT0.
Chip Information
TRANSISTOR COUNT: 882
Ensure that output currents do not exceed the current
limits as specified in the Absolute Maximum Ratings.
Under all operating conditions, the device’s total ther-
mal limits should be observed.
PROCESS: Bipolar
_______________________________________________________________________________________
9
Lowest Jitter Quad PECL-to-ECL
Differential Translators
Package Information
(The pacꢀage drawing(s) in this data sheet may not reflect the most current specifications. For the latest pacꢀage outline information,
go to www.maxim-ic.com/packages.)
10 ______________________________________________________________________________________
Lowest Jitter Quad PECL-to-ECL
Differential Translators
Package Information (continued)
(The pacꢀage drawing(s) in this data sheet may not reflect the most current specifications. For the latest pacꢀage outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2002 Maxim Integrated Products
Printed USA
is a registered trademarꢀ of Maxim Integrated Products.
相关型号：
MAX9424EGJ-T
PECL to ECL Translator, 4 Func, Complementary Output, BIPolar, CQCC32, 5 X 5 MM, 0.90 MM HEIGHT, QFN-32
MAXIM
MAX9425EGJ-T
PECL to ECL Translator, 4 Func, Complementary Output, BIPolar, CQCC32, 5 X 5 MM, 0.90 MM HEIGHT, QFN-32
MAXIM
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