MAX9491EUD-T [MAXIM]
Clock Generator, 200MHz, CMOS, PDSO14, 4.40 MM, MO-153AB-1, TSSOP-14;
| 型号： | MAX9491EUD-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Clock Generator, 200MHz, CMOS, PDSO14, 4.40 MM, MO-153AB-1, TSSOP-14 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总11页 (文件大小：290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3942; Rev 0; 1/06
Factory-Programmable, Single PLL
Clock Generator
General Description
Features
The MAX9491 multipurpose clock generator is ideal for
communication applications. It offers a factory-program-
mable PLL output that can be set to almost any frequency,
ranging from 4MHz to 200MHz. The MAX9491 uses a
one-time-programmable (OTP) ROM to program the PLL
output. The MAX9491 also features an integrated volt-
age-controlled crystal oscillator (VCXO) that is tuned by a
DC voltage. The VCXO output is used as the PLL input.
The VCXO has a wide 200ppm (typ) tuning range. The
OTP on the MAX9491 is factory preset, based upon the
customer request. Contact the factory for samples with
preferred frequencies.
♦ 5MHz to 35MHz for Crystal-Clock Reference
♦ 5MHz to 50MHz for a Driver Clock Reference
♦ One Fractional-N PLL with Buffered Output
♦ 4MHz to 200MHz Output Frequency Range
♦ Low RMS Jitter PLL (< 13ps) at 197 MHz
♦ Integrated VCXO with 200ppꢀ ꢁuning Range
♦ Available in 14-Pin ꢁSSOP and 20-Pin ꢁQFN
Packages
♦ +3.3V Supply
The device operates from a 3.3V supply and is speci-
fied over the -40°C to +85°C extended temperature
range. The MAX9491 is available in 14-pin TSSOP and
20-pin TQFN (5mm x 5mm) packages.
♦ -40°C to +85°C ꢁeꢀperature Range
Ordering Information
Applications
Telecommunications
Data Networking Systems
Home Entertainment Centers
SOHO
PIN-
PACKAGE
PKG
CODE
PARꢁ
ꢁEMP RANGE
MAX9491ETP
-40°C to +85°C 20 TQFN-EP** T2055-5
-40°C to +85°C 14 TSSOP U14-2
MAX9491EUD*
*Future product—contact factory for availability.
**EP = Exposed pad.
Pin Configurations
TOP VIEW
15 14 13 12 11
TOP VIEW
X1
I.C.
I.C.
1
2
3
4
5
6
7
14 X2
13 PD
V
16
10 GND
DD
X2 17
X1 18
I.C. 19
I.C. 20
9
8
7
6
I.C.
I.C.
I.C.
I.C.
12
V
DD
MAX9491
V
11 GND
10 I.C.
DD
TUNE
GND
MAX9491
9
8
GND
I.C.
1
2
3
4
5
CLK_OUT
ꢁSSOP
ꢁQFN (5ꢀꢀ x 5ꢀꢀ)
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Factory Programmable Single PLL
Clock Generator
ABSOLUꢁE MAXIMUM RAꢁINGS
V
V
to GND...........................................................-0.3V to +4.0V
Continuous Power Dissipation (T = +70°C)
A
DD
DDA
to AGND ......................................................-0.3V to +4.0V
20-Lead TQFN (derate 21.3mW/°C above +70°C)....2758mW
14-Pin TSSOP (derate 9.1mW/°C above +70°C) ......796.8mW
Storage Temperature Range.............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Lead Temperature (soldering, 10s) .................................+300°C
All Other Pins to GND ..................................-0.3V to V
Short-Circuit Duration
(all LVCMOS outputs)..............................................Continuous
ESD Protection (Human Body Model).................................. 2kV
+ 0.3V
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECꢁRICAL CHARACꢁERISꢁICS
(V
= V
= +3.0V to +3.6V and T = -40°C to +85°C. Typical values at V
= V
= 3.3V, T = +25°C, unless otherwise noted.)
DDA A
DD
DDA
A
DD
(Note 1)
PARAMEꢁER
SYMBOL
CONDIꢁIONS
MIN
ꢁYP
MAX
UNIꢁS
LVCMOS INPUꢁS (PD, X1 as a reference INPUꢁ CLK)
Input High Level
V
2.0
0
V
V
IH
DD
Input Low Level
V
0.8
20
V
IL
High-Level Input Current
Low-Level Input Current
CLOCK OUꢁPUꢁ (CLK_OUꢁ)
I
V
V
= V
= 0
µA
µA
IH
IN
IN
DD
I
-20
IL
V
0.6
-
DD
Output High Level
V
I
I
= -4mA
= 4mA
V
V
OH
OH
Output Low Level
V
0.4
OL
OL
POWER SUPPLIES
Digital Power-Supply Voltage
Analog Power-Supply Voltage
V
3.0
3.0
3.6
3.6
V
V
DD
V
DDA
Total Current for Digital and
Analog Supplies
f
= 45MHz, no load
OUT
= 13MHz
I
10
60
mA
µA
DC
f
IN
Power-Down Current
I
2
PD = low
DC
2
_______________________________________________________________________________________
Factory Programmable Single PLL
Clock Generator
AC ELECꢁRICAL CHARACꢁERISꢁICS
(V
= V
= +3.0V to +3.6V, C = 10pF and T = -40°C to +85°C. Typical values are at V
= V
= 3.3V, T = +25°C, unless
DDA A
DD
DDA
L
A
DD
otherwise noted.) (Note 2)
PARAMEꢁER
SYMBOL
CONDIꢁIONS
MIN
ꢁYP
MAX
UNIꢁS
OUꢁPUꢁ CLOCK (CLK_OUꢁ)
Minimum Frequency Range
Maximum Frequency Range
f
= 5MHz to 50MHz
4
IN
f
MHz
ns
OUT
C < 5pF
133
200
1.5
L
20% to 80% of V , f
f
= 80MHz,
= 80MHz,
DD OUT
Clock Rise Time
t
R
= 13MHz
IN
80% to 20% of V , f
f
DD OUT
Clock Fall Time
Duty Cycle
t
1.3
50
ns
%
F
= 13MHz
IN
f
= 45MHz, f = 13MHz
44
56
OUT
IN
f
f
f
= 45MHz, f = 13MHz
14
22
13
OUT
OUT
OUT
IN
ps
RMS
Output Period Jitter
J
= 80MHz, f = 13MHz
IN
P
= 197MHz, f = 13MHz
IN
PD from low to high, f
= 45MHz,
OUT
Soft Power-On Time
t
t
1
ms
ms
PO2
PO1
f
IN
= 13MHz, see Figure 2
Hard Power-On Time
VCXO CLOCK
See Figure 2
15
Crystal Frequency
Crystal Accuracy
f
27
30
MHz
ppm
XTL
Tuning Voltage Range
VCXO Tuning Range
V
Z
0
3
V
TUNE
TUNE
V
V
= 0 to 3V, C = C = 4pF
150
200
95
ppm
TUNE
TUNE
1
2
TUNE Input Impedance
Output CLK Accuracy
kΩ
= 1.5V, C = C = 4pF
50
ppm
1
2
Note 1: All parameters are tested at T = +25°C. Specifications over temperature are guaranteed by design and characterization.
A
Note 2: Guaranteed by design and characterization; limits are set at 6 sigma.
_______________________________________________________________________________________
3
Factory Programmable Single PLL
Clock Generator
Typical Operating Characteristics
(V
= V
= +3.3V, T = +25°C, f = 13MHz clock, C = 10pF, 27MHz, unless otherwise noted.)
DDA A IN L
DD
SUPPLY CURRENT vs. TEMPERATURE
RISE TIME vs. TEMPERATURE
FALL TIME vs. TEMPERATURE
13
2.2
1.8
1.4
1.0
0.6
0.2
2.2
1.8
1.4
1.0
0.6
0.2
f
f
= 13MHz
= 45MHz
f
f
= 13MHz
= 45MHz
f
f
= 13MHz
IN
= 45MHz
OUT
IN
OUT
IN
OUT
12
11
10
9
8
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
JITTER vs. TEMPERATURE
JITTER vs. TEMPERATURE
JITTER vs. TEMPERATURE
40
35
40
32
24
16
8
40
30
f
f
= 13MHz
f
f
= 13MHz
f
f
= 27MHz
IN
IN
IN
= 80MHz
= 45MHz
= 197MHz
OUT
OUT
OUT
30
25
20
15
10
5
20
10
0
0
0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
TYPICAL CLK_OUT WAVEFORM AT 197MHz
TYPICAL CLK_OUT WAVEFORM AT 45MHz
TYPICAL CLK_OUT WAVEFORM AT 80MHz
V
= V
= 3.0V
DDA
V
= V
= 3.0V
V
= V
= 3.0V
DDA
DD
DD
DDA
DD
CLK1
CLK1
CLK1
1V/div
1V/div
1V/div
4ns/div
4ns/div
4ns/div
4
_______________________________________________________________________________________
Factory Programmable Single PLL
Clock Generator
Typical Operating Characteristics (continued)
(V
= V
= +3.3V, T = +25°C, f = 13MHz clock, C = 10pF, 27MHz, unless otherwise noted.)
DDA A IN L
DD
VCXO ACCURACY vs. VCXO TUNING RANGE
DUTY CYCLE vs. OUTPUT FREQUENCY
100
80
60
40
20
0
300
f
f
= 27MHz
f
= 13MHz
IN
IN
= 45MHz
OUT
6pF
200
100
0
4pF
5pF
-100
-200
-300
0
0.5
1.0
1.5
2.0
2.5
3.0
45
50
55
60
65
70
75
80
VCXO TUNING RANGE (V)
FREQUENCY (MHz)
45MHz OUTPUT
80MHz OUTPUT
10dB/REF = 0dBm
RBW = 3kHz
10dB/REF = 0dBm
RBW = 3kHz
VBW = 3kHz
VBW = 3kHz
ATN = 20dB
ATN = 20dB
CENTER = 45MHz
SPAN = 2MHz
CENTER = 80MHz
SPAN = 2MHz
_______________________________________________________________________________________
5
Factory Programmable Single PLL
Clock Generator
Typical Operating Circuit/Block Diagram
+3.3V
+3.3V
0.1µF
0.1µF x 3
V
V
V
V
DD
DD
DD
DDA
X1
MAX9491
OR REFERENCE
INPUT
C1
VCXO
C2
X2
PLL
OTP
TUNE
CLK_OUT
PD
AGND
GND
Pin Description
PIN
NAME
FUNCꢁION
ꢁQFN
ꢁSSOP
VCXO Tune Voltage Input. If using a reference clock input or VCXO is not used,
connect TUNE to V
1
5
TUNE
.
DD
2
—
—
V
Analog Power Supply. Bypass to GND with a 0.1µF capacitor.
DDA
3
4, 10, 11
5
AGND
GND
Analog Ground
Ground
6, 9, 11
7
CLK_OUT Output Clock. Internally pulled down.
I.C. Internally Connected. Leave unconnected for normal operation.
6–9, 14, 19, 20
12, 13, 16
2, 3, 8, 10
4, 12
V
Power Supply. Bypass to GND with a 0.1µF capacitor.
DD
Active-Low Power-Down Input. Pull high for normal operation. Drive PD low to place
MAX9491 in power-down mode. Internally pulled down.
15
13
PD
17
18
EP
14
1
X2
X1
EP
Crystal Connection 2. Leave unconnected if using a reference clock.
Crystal Connection 1 or Reference Clock Input
—
Exposed Paddle (TQFN Only). Connect EP to GND or leave unconnected.
shuts down the PLL. CLK_OUT has an 80kΩ (typ) inter-
nal pulldown resistor.
Detailed Description
The MAX9491 features a programmable fractional-N
PLL, so frequencies between 4MHz to 200MHz can be
generated. The device provides a buffered PLL clock
output. The crystal input frequency can be between
5MHz and 35MHz, and the clock input between 5MHz
and 50MHz. The internal VCXO has a fine-tuning range
of 200ppm.
Voltage-Controlled Crystal Oscillator
(VCXO)
The MAX9491’s internal VCXO produces a reference
clock for the PLL used to generate the CLK_OUT. The
oscillator uses a crystal as the base frequency refer-
ence and has a voltage-controlled tuning input for micro
adjustment in a 200ppm range. The tuning voltage,
Power-Down
Driving PD low places the MAX9491 in power-down
mode. PD then sets CLK_OUT to high impedance and
V
TUNE
, can vary from 0 to 3V as shown in Figure 1. The
crystal should be AT-cut and oscillate on its fundamen-
tal mode with 30ppm. The crystal shunt capacitor
6
_______________________________________________________________________________________
Factory Programmable Single PLL
Clock Generator
should be less than 10pF, including board parasitic
with an internal POR signal and can be disabled by PD.
When VCXO is not used, connect TUNE to V
capacitance. To achieve up to 200ppm pullability, make
sure the crystal-loading capacitance is less than 14pF.
The VCXO is a free-running oscillator. It starts oscillating
.
DD
Applications Information
Using an Input Clock as the Reference
When an input clock is used as the reference, connect
the input clock to X1, leave X2 unconnected, and connect
TUNE to V
.
DD
27.0405
+150ppm
27.00
Crystal Selection
When using a crystal with the MAX9491’s internal oscil-
lator, connect the crystal to X1 and X2. Choose an AT-
cut crystal that oscillates on its fundamental mode with
30ppm and loading capacitance less than 14pF. To
achieve a wide VCXO tuning range, select a crystal
with motional capacitance greater than 7fF and con-
nect 6pF or less shunt capacitors at both X1 and X2 to
ground. When the VCXO is used as an oscillator, select
both shunt capacitors to approximately 13pF. The opti-
mal shunt capacitors for achieving minimum frequency
offset can be determined experimentally.
-150ppm
26.99595
0
3V
V
TUNE
Figure 1. VCXO Tuning Range for a 27MHz Crystal
V
DD
2.2V
t
CLK_IN
PD
CLK_OUT
t
t
PO2
PO1
Figure 2. PLL Settling Time
_______________________________________________________________________________________
7
Factory Programmable Single PLL
Clock Generator
Board Layout Considerations and
Chip Information
Bypassing
PROCESS: CMOS
The MAX9491’s high-frequency oscillator requires
proper layout to ensure stability. For best performance,
place components as close as possible to the device.
Digital or AC transient signals on GND can create noise
at the clock output. Return GND to the highest quality
ground available. Bypass each V
and V
with a
DDA
DD
0.1µF capacitor, placed as close as possible to the
device. Careful PC board ground layout minimizes
crosstalk between the output and digital inputs.
8
_______________________________________________________________________________________
Factory Programmable Single PLL
Clock Generator
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.ꢀaxiꢀ-ic.coꢀ/packages.)
PACKAGE OUTLINE, TSSOP 4.40mm BODY
1
21-0066
G
1
_______________________________________________________________________________________
9
Factory Programmable Single PLL
Clock Generator
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.ꢀaxiꢀ-ic.coꢀ/packages.)
D2
D
b
0.10 M
C A B
C
L
D2/2
D/2
k
L
MARKING
AAAAA
E/2
E2/2
C
(NE-1) X
e
L
E2
E
PIN # 1 I.D.
0.35x45°
DETAIL A
e/2
PIN # 1
I.D.
e
(ND-1) X
e
DETAIL B
e
L
C
L
C
L
L1
L
L
e
e
0.10
C
A
0.08
C
C
A3
A1
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
1
-DRAWING NOT TO SCALE-
I
21-0140
2
10 ______________________________________________________________________________________
Factory Programmable Single PLL
Clock Generator
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.ꢀaxiꢀ-ic.coꢀ/packages.)
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
PKG.
16L 5x5
20L 5x5
28L 5x5
32L 5x5
40L 5x5
L
DOWN
BONDS
ALLOWED
D2
E2
exceptions
PKG.
SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
CODES
±0.15
MIN. NOM. MAX. MIN. NOM. MAX.
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
A
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80
0.02 0.05 0.02 0.05 0.02 0.05 0.02 0.05 0.02 0.05
0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF.
T1655-2
T1655-3
YES
NO
NO
**
**
**
**
A1
0
0
0
0
0
A3
b
T1655N-1 3.00 3.10 3.20 3.00 3.10 3.20
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
T2055-3
T2055-4
T2055-5
T2855-3
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
YES
NO
D
E
**
YES
3.15 3.25 3.35 3.15 3.25 3.35 0.40
e
0.80 BSC.
0.25
0.65 BSC.
0.25
0.50 BSC.
0.25
0.50 BSC.
0.25
0.40 BSC.
3.15 3.25 3.35 3.15 3.25 3.35
YES
YES
NO
**
**
**
k
-
-
-
-
-
-
-
-
0.25 0.35 0.45
T2855-4
T2855-5
2.60 2.70 2.80 2.60 2.70 2.80
2.60 2.70 2.80 2.60 2.70 2.80
3.15 3.25 3.35 3.15 3.25 3.35
L
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60
L1
-
-
-
-
-
-
-
-
-
-
-
-
0.30 0.40 0.50
NO
YES
YES
T2855-6
T2855-7
**
**
N
ND
NE
16
4
4
20
5
5
28
7
7
32
8
8
40
10
10
2.80
2.60 2.70
2.60 2.70 2.80
T2855-8
3.15 3.25 3.35 3.15 3.25 3.35 0.40
WHHB
WHHC
WHHD-1
WHHD-2
-----
JEDEC
T2855N-1 3.15 3.25 3.35 3.15 3.25 3.35
NO
YES
NO
YES
NO
**
**
**
**
**
**
3.20
3.00 3.10 3.20
T3255-3
T3255-4
T3255-5
3.00 3.10
3.00 3.10 3.20 3.00 3.10 3.20
3.20
NOTES:
3.00 3.10
3.00 3.10 3.20
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
T3255N-1 3.00 3.10 3.20 3.00 3.10 3.20
T4055-1 3.20 3.30 3.40 3.20 3.30 3.40
YES
**SEE COMMON DIMENSIONS TABLE
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE
OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1
IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN
0.25 mm AND 0.30 mm FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR
T2855-3 AND T2855-6.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", ±0.05.
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
2
-DRAWING NOT TO SCALE-
21-0140
I
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2006 Maxim Integrated Products
Springer
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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